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synopGMAC_Dev.h
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1 /* ===================================================================================
2  * Copyright (c) <2009> Synopsys, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a copy of
5  * this software annotated with this license and associated documentation files
6  * (the "Software"), to deal in the Software without restriction, including without
7  * limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the Software is
9  * furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in all
12  * copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
15  * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
16  * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
17  * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
18  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
19  * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20  *
21  * =================================================================================== */
22 
23 /**\file
24  * This file defines the function prototypes for the Synopsys GMAC device and the
25  * Marvell 88E1011/88E1011S integrated 10/100/1000 Gigabit Ethernet Transceiver.
26  * Since the phy register mapping are standardised, the phy register map and the
27  * bit definitions remain the same for other phy as well.
28  * This also defines some of the Ethernet related parmeters.
29  * \internal
30  * -----------------------------REVISION HISTORY------------------------------------
31  * Synopsys 01/Aug/2007 Created
32  */
33 
34 
35 #ifndef SYNOP_GMAC_DEV_H
36 #define SYNOP_GMAC_DEV_H 1
37 
38 #include "synopGMAC_plat.h"
39 
40 #define GMAC_CNT 1
41 
42 /*SynopGMAC can support up to 32 phys*/
43 
44 enum GMACPhyBase {
45  PHY0 = 0, //The device can support 32 phys, but we use first phy only
46  PHY1 = 1,
47  PHY31 = 31,
48 };
49 
50 #define DEFAULT_PHY_BASE PHY1 //We use First Phy
51 
52 #define GMAC0MappedAddr EMAC_BASE //0x40012000
53 #define GMAC1MappedAddr EMAC_BASE
54 #define MACBASE 0x0000 // The Mac Base address offset is 0x0000
55 #define DMABASE 0x1000 // Dma base address starts with an offset 0x1000
56 
57 
58 #define TRANSMIT_DESC_SIZE 8//256 //Tx Descriptors needed in the Descriptor pool/queue
59 #define RECEIVE_DESC_SIZE 16//256 //Rx Descriptors needed in the Descriptor pool/queue
60 
61 #define ETHERNET_HEADER 14 //6 byte Dest addr, 6 byte Src addr, 2 byte length/type
62 #define ETHERNET_CRC 4 //Ethernet CRC
63 #define ETHERNET_EXTRA 2 //Only God knows about this?????
64 #define ETHERNET_PACKET_COPY 250 // Maximum length when received data is copied on to a new skb
65 #define ETHERNET_PACKET_EXTRA 18 // Preallocated length for the rx packets is MTU + ETHERNET_PACKET_EXTRA
66 #define VLAN_TAG 4 //optional 802.1q VLAN Tag
67 #define MIN_ETHERNET_PAYLOAD 46 //Minimum Ethernet payload size
68 #define MAX_ETHERNET_PAYLOAD 1500 //Maximum Ethernet payload size
69 #define JUMBO_FRAME_PAYLOAD 9000 //Jumbo frame payload size
70 
71 #define TX_BUF_SIZE ETHERNET_HEADER + ETHERNET_CRC + MAX_ETHERNET_PAYLOAD + VLAN_TAG
72 
73 
74 // This is the IP's phy address. This is unique address for every MAC in the universe
75 #define DEFAULT_MAC0_ADDRESS {0x00, 0x55, 0x7B, 0xB5, 0x7D, 0xF7}
76 #define DEFAULT_MAC1_ADDRESS {0x00, 0x55, 0x7B, 0xB5, 0x7D, 0xF8}
77 /*
78 DMA Descriptor Structure
79 The structure is common for both receive and transmit descriptors
80 The descriptor is of 4 words, but our structrue contains 6 words where
81 last two words are to hold the virtual address of the network buffer pointers
82 for driver's use
83 From the GMAC core release 3.50a onwards, the Enhanced Descriptor structure got changed.
84 The descriptor (both transmit and receive) are of 8 words each rather the 4 words of normal
85 descriptor structure.
86 Whenever IEEE 1588 Timestamping is enabled TX/RX DESC6 provides the lower 32 bits of Timestamp value and
87  TX/RX DESC7 provides the upper 32 bits of Timestamp value
88 In addition to this whenever extended status bit is set (RX DESC0 bit 0), RX DESC4 contains the extended status information
89 */
90 
91 #define MODULO_INTERRUPT 1 // if it is set to 1, interrupt is available for all the descriptors or else interrupt is available only for
92 // descriptor whose index%MODULO_INTERRUPT is zero
93 typedef struct DmaDescStruct {
94  u32 status; /* Status */
95  u32 length; /* Buffer 1 and Buffer 2 length */
96  u32 buffer1; /* Network Buffer 1 pointer (Dma-able) */
97  u32 buffer2; /* Network Buffer 2 pointer or next descriptor pointer (Dma-able)in chain structure */
98  /* This data below is used only by driver */
99  u32 extstatus; /* Extended status of a Rx Descriptor */
100  u32 reserved1; /* Reserved word */
101  u32 timestamplow; /* Lower 32 bits of the 64 bit timestamp value */
102  u32 timestamphigh; /* Higher 32 bits of the 64 bit timestamp value */
103  //u32 data1; /* This holds virtual address of buffer1, not used by DMA */
104  //u32 data2; /* This holds virtual address of buffer2, not used by DMA */
105 } DmaDesc;
106 
107 enum DescMode {
108  RINGMODE = 0x00000001,
109  CHAINMODE = 0x00000002,
110 };
111 
112 enum BufferMode {
113  SINGLEBUF = 0x00000001,
114  DUALBUF = 0x00000002,
115 };
116 
117 typedef u32 * dma_addr_t;
118 
119 /* synopGMAC device data */
120 
121 struct sk_buff {
122  unsigned char data[2048];
123  unsigned int len;
124  unsigned int volatile rdy;
125 };
126 
127 struct net_device_stats {
128  u32 tx_bytes;
129  u32 tx_packets;
130  u32 tx_errors;
131  u32 tx_aborted_errors;
132  u32 tx_carrier_errors;
133  u32 tx_ip_header_errors;
134  u32 tx_ip_payload_errors;
135  u32 collisions;
136  u32 rx_bytes;
137  u32 rx_packets;
138  u32 rx_errors;
139  u32 rx_crc_errors;
140  u32 rx_frame_errors;
141  u32 rx_length_errors;
142  u32 rx_dropped;
143  u32 rx_over_errors;
144  u32 rx_ip_header_errors;
145  u32 rx_ip_payload_errors;
146  volatile u32 ts_int;
147 };
148 
149 typedef struct synopGMACDeviceStruct {
150  u64 MacBase; /* base address of MAC registers */
151  u64 DmaBase; /* base address of DMA registers */
152  u64 PhyBase; /* PHY device address on MII interface */
153  u64 Version; /* Gmac Revision version */
154 
155 
156  /*dma_addr_t*/ DmaDesc *TxDescDma; /* Dma-able address of first tx descriptor either in ring or chain mode, this is used by the GMAC device*/
157  /*dma_addr_t*/ DmaDesc *RxDescDma; /* Dma-albe address of first rx descriptor either in ring or chain mode, this is used by the GMAC device*/
158  DmaDesc *TxDesc; /* start address of TX descriptors ring or chain, this is used by the driver */
159  DmaDesc *RxDesc; /* start address of RX descriptors ring or chain, this is used by the driver */
160 
161  u32 BusyTxDesc; /* Number of Tx Descriptors owned by DMA at any given time*/
162  u32 BusyRxDesc; /* Number of Rx Descriptors owned by DMA at any given time*/
163 
164  u32 RxDescCount; /* number of rx descriptors in the tx descriptor queue/pool */
165  u32 TxDescCount; /* number of tx descriptors in the rx descriptor queue/pool */
166 
167  u32 TxBusy; /* index of the tx descriptor owned by DMA, is obtained by synopGMAC_get_tx_qptr() */
168  u32 TxNext; /* index of the tx descriptor next available with driver, given to DMA by synopGMAC_set_tx_qptr() */
169  u32 RxBusy; /* index of the rx descriptor owned by DMA, obtained by synopGMAC_get_rx_qptr() */
170  u32 RxNext; /* index of the rx descriptor next available with driver, given to DMA by synopGMAC_set_rx_qptr() */
171 
172  DmaDesc * TxBusyDesc; /* Tx Descriptor address corresponding to the index TxBusy */
173  DmaDesc * TxNextDesc; /* Tx Descriptor address corresponding to the index TxNext */
174  DmaDesc * RxBusyDesc; /* Rx Descriptor address corresponding to the index TxBusy */
175  DmaDesc * RxNextDesc; /* Rx Descriptor address corresponding to the index RxNext */
176 
177 
178  /*Phy related stuff*/
179  u32 ClockDivMdc; /* Clock divider value programmed in the hardware */
180  /* The status of the link */
181  u32 LinkState; /* Link status as reported by the Marvel Phy */
182  u32 DuplexMode; /* Duplex mode of the Phy */
183  u32 Speed; /* Speed of the Phy */
184  u32 LoopBackMode; /* Loopback status of the Phy */
185  u32 Intf;
186  struct net_device_stats synopGMACNetStats;
187 
188  u32 tx_sec;
189  u32 tx_subsec;
190  u32 rx_sec;
191  u32 rx_subsec;
192 
193  u32 GMAC_Power_down;
194 
195 } synopGMACdevice;
196 
197 
198 /* Below is "88E1011/88E1011S Integrated 10/100/1000 Gigabit Ethernet Transceiver"
199  * Register and their layouts. This Phy has been used in the Dot Aster GMAC Phy daughter.
200  * Since the Phy register map is standard, this map hardly changes to a different Ppy
201  */
202 
203 enum MiiRegisters {
204  PHY_CONTROL_REG = 0x0000, /*Control Register*/
205  PHY_STATUS_REG = 0x0001, /*Status Register */
206  PHY_ID_HI_REG = 0x0002, /*PHY Identifier High Register*/
207  PHY_ID_LOW_REG = 0x0003, /*PHY Identifier High Register*/
208  PHY_AN_ADV_REG = 0x0004, /*Auto-Negotiation Advertisement Register*/
209  PHY_LNK_PART_ABl_REG = 0x0005, /*Link Partner Ability Register (Base Page)*/
210  PHY_AN_EXP_REG = 0x0006, /*Auto-Negotiation Expansion Register*/
211  PHY_AN_NXT_PAGE_TX_REG = 0x0007, /*Next Page Transmit Register*/
212  PHY_LNK_PART_NXT_PAGE_REG = 0x0008, /*Link Partner Next Page Register*/
213  PHY_1000BT_CTRL_REG = 0x0009, /*1000BASE-T Control Register*/
214  PHY_1000BT_STATUS_REG = 0x000a, /*1000BASE-T Status Register*/
215  PHY_SPECIFIC_CTRL_REG = 0x0010, /*Phy specific control register*/
216  PHY_SPECIFIC_STATUS_REG = 0x0011, /*Phy specific status register*/
217  PHY_INTERRUPT_ENABLE_REG = 0x0012, /*Phy interrupt enable register*/
218  PHY_INTERRUPT_STATUS_REG = 0x0013, /*Phy interrupt status register*/
219  PHY_EXT_PHY_SPC_CTRL = 0x0014, /*Extended Phy specific control*/
220  PHY_RX_ERR_COUNTER = 0x0015, /*Receive Error Counter*/
221  PHY_EXT_ADDR_CBL_DIAG = 0x0016, /*Extended address for cable diagnostic register*/
222  PHY_LED_CONTROL = 0x0018, /*LED Control*/
223  PHY_MAN_LED_OVERIDE = 0x0019, /*Manual LED override register*/
224  PHY_EXT_PHY_SPC_CTRL2 = 0x001a, /*Extended Phy specific control 2*/
225  PHY_EXT_PHY_SPC_STATUS = 0x001b, /*Extended Phy specific status*/
226  PHY_CBL_DIAG_REG = 0x001c, /*Cable diagnostic registers*/
227 };
228 
229 
230 /* This is Control register layout. Control register is of 16 bit wide.
231 */
232 
233 enum Mii_GEN_CTRL {
234  /* Description bits R/W default value */
235  Mii_reset = 0x8000,
236  Mii_Speed_10 = 0x0000, /* 10 Mbps 6:13 RW */
237  Mii_Speed_100 = 0x2000, /* 100 Mbps 6:13 RW */
238  Mii_Speed_1000 = 0x0040, /* 1000 Mbit/s 6:13 RW */
239 
240  Mii_Duplex = 0x0100, /* Full Duplex mode 8 RW */
241 
242  Mii_Manual_Master_Config = 0x0800, /* Manual Master Config 11 RW */
243 
244  Mii_Loopback = 0x4000, /* Enable Loop back 14 RW */
245  Mii_NoLoopback = 0x0000, /* Enable Loop back 14 RW */
246 };
247 
248 enum Mii_Phy_Status {
249  Mii_phy_status_speed_10 = 0x0000,
250  Mii_phy_status_speed_100 = 0x4000,
251  Mii_phy_status_speed_1000 = 0x8000,
252 
253  Mii_phy_status_full_duplex = 0x2000,
254  Mii_phy_status_half_duplex = 0x0000,
255 
256  Mii_phy_status_link_up = 0x0400,
257 };
258 /* This is Status register layout. Status register is of 16 bit wide.
259 */
260 enum Mii_GEN_STATUS {
261  Mii_AutoNegCmplt = 0x0020, /* Autonegotiation completed 5 RW */
262  Mii_Link = 0x0004, /* Link status 2 RW */
263 };
264 
265 enum Mii_Link_Status {
266  LINKDOWN = 0,
267  LINKUP = 1,
268 };
269 
270 enum Mii_Duplex_Mode {
271  HALFDUPLEX = 1,
272  FULLDUPLEX = 2,
273 };
274 enum Mii_Link_Speed {
275  SPEED10 = 1,
276  SPEED100 = 2,
277  SPEED1000 = 3,
278 };
279 
280 enum Mii_Loop_Back {
281  NOLOOPBACK = 0,
282  LOOPBACK = 1,
283 };
284 
285 
286 
287 /**********************************************************
288  * GMAC registers Map
289  * For Pci based system address is BARx + GmacRegisterBase
290  * For any other system translation is done accordingly
291  **********************************************************/
292 enum GmacRegisters {
293  GmacConfig = 0x0000, /* Mac config Register */
294  GmacFrameFilter = 0x0004, /* Mac frame filtering controls */
295  GmacHashHigh = 0x0008, /* Multi-cast hash table high */
296  GmacHashLow = 0x000C, /* Multi-cast hash table low */
297  GmacGmiiAddr = 0x0010, /* GMII address Register(ext. Phy) */
298  GmacGmiiData = 0x0014, /* GMII data Register(ext. Phy) */
299  GmacFlowControl = 0x0018, /* Flow control Register */
300  GmacVlan = 0x001C, /* VLAN tag Register (IEEE 802.1Q) */
301 
302  GmacVersion = 0x0020, /* GMAC Core Version Register */
303  GmacDebug = 0x0024, /* GMAC Debug Register */
304  GmacWakeupAddr = 0x0028, /* GMAC wake-up frame filter adrress reg */
305  GmacPmtCtrlStatus = 0x002C, /* PMT control and status register */
306 
307 
308  GmacLPICtrlSts = 0x0030, /* LPI (low power idle) Control and Status Register */
309  GmacLPITimerCtrl = 0x0034, /* LPI timer control register */
310 
311 
312  GmacInterruptStatus = 0x0038, /* Mac Interrupt ststus register */
313  GmacInterruptMask = 0x003C, /* Mac Interrupt Mask register */
314 
315  GmacAddr0High = 0x0040, /* Mac address0 high Register */
316  GmacAddr0Low = 0x0044, /* Mac address0 low Register */
317  GmacAddr1High = 0x0048, /* Mac address1 high Register */
318  GmacAddr1Low = 0x004C, /* Mac address1 low Register */
319  GmacAddr2High = 0x0050, /* Mac address2 high Register */
320  GmacAddr2Low = 0x0054, /* Mac address2 low Register */
321  GmacAddr3High = 0x0058, /* Mac address3 high Register */
322  GmacAddr3Low = 0x005C, /* Mac address3 low Register */
323  GmacAddr4High = 0x0060, /* Mac address4 high Register */
324  GmacAddr4Low = 0x0064, /* Mac address4 low Register */
325  GmacAddr5High = 0x0068, /* Mac address5 high Register */
326  GmacAddr5Low = 0x006C, /* Mac address5 low Register */
327  GmacAddr6High = 0x0070, /* Mac address6 high Register */
328  GmacAddr6Low = 0x0074, /* Mac address6 low Register */
329  GmacAddr7High = 0x0078, /* Mac address7 high Register */
330  GmacAddr7Low = 0x007C, /* Mac address7 low Register */
331  GmacAddr8High = 0x0080, /* Mac address8 high Register */
332  GmacAddr8Low = 0x0084, /* Mac address8 low Register */
333  GmacAddr9High = 0x0088, /* Mac address9 high Register */
334  GmacAddr9Low = 0x008C, /* Mac address9 low Register */
335  GmacAddr10High = 0x0090, /* Mac address10 high Register */
336  GmacAddr10Low = 0x0094, /* Mac address10 low Register */
337  GmacAddr11High = 0x0098, /* Mac address11 high Register */
338  GmacAddr11Low = 0x009C, /* Mac address11 low Register */
339  GmacAddr12High = 0x00A0, /* Mac address12 high Register */
340  GmacAddr12Low = 0x00A4, /* Mac address12 low Register */
341  GmacAddr13High = 0x00A8, /* Mac address13 high Register */
342  GmacAddr13Low = 0x00AC, /* Mac address13 low Register */
343  GmacAddr14High = 0x00B0, /* Mac address14 high Register */
344  GmacAddr14Low = 0x00B4, /* Mac address14 low Register */
345  GmacAddr15High = 0x00B8, /* Mac address15 high Register */
346  GmacAddr15Low = 0x00BC, /* Mac address15 low Register */
347  GmacRgmiiCtrlSts = 0x00D8, /*SGMII_RGMII_SMII_Control_Status Register */
348  GmacVLANIncRep = 0x0584,
349  /*Time Stamp Register Map*/
350  GmacTSControl = 0x0700, /* Controls the Timestamp update logic : only when IEEE 1588 time stamping is enabled in corekit */
351 
352  GmacTSSubSecIncr = 0x0704, /* 8 bit value by which sub second register is incremented : only when IEEE 1588 time stamping without external timestamp input */
353 
354  GmacTSHigh = 0x0708, /* 32 bit seconds(MS) : only when IEEE 1588 time stamping without external timestamp input */
355  GmacTSLow = 0x070C, /* 32 bit nano seconds(MS) : only when IEEE 1588 time stamping without external timestamp input */
356 
357  GmacTSHighUpdate = 0x0710, /* 32 bit seconds(MS) to be written/added/subtracted : only when IEEE 1588 time stamping without external timestamp input */
358  GmacTSLowUpdate = 0x0714, /* 32 bit nano seconds(MS) to be writeen/added/subtracted : only when IEEE 1588 time stamping without external timestamp input */
359 
360  GmacTSAddend = 0x0718, /* Used by Software to readjust the clock frequency linearly : only when IEEE 1588 time stamping without external timestamp input */
361 
362  GmacTSTargetTimeHigh = 0x071C, /* 32 bit seconds(MS) to be compared with system time : only when IEEE 1588 time stamping without external timestamp input */
363  GmacTSTargetTimeLow = 0x0720, /* 32 bit nano seconds(MS) to be compared with system time : only when IEEE 1588 time stamping without external timestamp input */
364 
365  GmacTSHighWord = 0x0724, /* Time Stamp Higher Word Register (Version 2 only); only lower 16 bits are valid */
366  //GmacTSHighWordUpdate = 0x072C, /* Time Stamp Higher Word Update Register (Version 2 only); only lower 16 bits are valid */
367 
368  GmacTSStatus = 0x0728, /* Time Stamp Status Register */
369  GmacPPSCtrl = 0x072C, /* PPS Control Register */
370  GmacPPSInt = 0x0760, /* PPS0 Interval Register */
371  GmacPPSWidth = 0x0764, /* PPS0 Width Register */
372 };
373 
374 /**********************************************************
375  * GMAC Network interface registers
376  * This explains the Register's Layout
377 
378  * FES is Read only by default and is enabled only when Tx
379  * Config Parameter is enabled for RGMII/SGMII interface
380  * during CoreKit Config.
381 
382  * DM is Read only with value 1'b1 in Full duplex only Config
383  **********************************************************/
384 
385 /* GmacConfig = 0x0000, Mac config Register Layout */
386 enum GmacConfigReg {
387  /* Bit description Bits R/W Reset value */
388 
389  GmacSrcAddrInsRpl = 0x70000000,
390  GmacSrcAddrIns = 0x20000000,
391  GmacSrcAddrRpl = 0x30000000,
392  GmacWatchdog = 0x00800000,
393  GmacWatchdogDisable = 0x00800000, /* (WD)Disable watchdog timer on Rx 23 RW */
394  GmacWatchdogEnable = 0x00000000, /* Enable watchdog timer 0 */
395 
396  GmacJabber = 0x00400000,
397  GmacJabberDisable = 0x00400000, /* (JD)Disable jabber timer on Tx 22 RW */
398  GmacJabberEnable = 0x00000000, /* Enable jabber timer 0 */
399 
400  GmacFrameBurst = 0x00200000,
401  GmacFrameBurstEnable = 0x00200000, /* (BE)Enable frame bursting during Tx 21 RW */
402  GmacFrameBurstDisable = 0x00000000, /* Disable frame bursting 0 */
403 
404  GmacJumboFrame = 0x00100000,
405  GmacJumboFrameEnable = 0x00100000, /* (JE)Enable jumbo frame for Tx 20 RW */
406  GmacJumboFrameDisable = 0x00000000, /* Disable jumbo frame 0 */
407 
408  GmacInterFrameGap7 = 0x000E0000, /* (IFG) Config7 - 40 bit times 19:17 RW */
409  GmacInterFrameGap6 = 0x000C0000, /* (IFG) Config6 - 48 bit times */
410  GmacInterFrameGap5 = 0x000A0000, /* (IFG) Config5 - 56 bit times */
411  GmacInterFrameGap4 = 0x00080000, /* (IFG) Config4 - 64 bit times */
412  GmacInterFrameGap3 = 0x00040000, /* (IFG) Config3 - 72 bit times */
413  GmacInterFrameGap2 = 0x00020000, /* (IFG) Config2 - 80 bit times */
414  GmacInterFrameGap1 = 0x00010000, /* (IFG) Config1 - 88 bit times */
415  GmacInterFrameGap0 = 0x00000000, /* (IFG) Config0 - 96 bit times 000 */
416 
417  GmacDisableCrs = 0x00010000,
418  GmacMiiGmii = 0x00008000,
419  GmacSelectMii = 0x00008000, /* (PS)Port Select-MII mode 15 RW */
420  GmacSelectGmii = 0x00000000, /* GMII mode 0 */
421 
422  GmacFESpeed100 = 0x00004000, /*(FES)Fast Ethernet speed 100Mbps 14 RW */
423  GmacFESpeed10 = 0x00000000, /* 10Mbps 0 */
424 
425  GmacRxOwn = 0x00002000,
426  GmacDisableRxOwn = 0x00002000, /* (DO)Disable receive own packets 13 RW */
427  GmacEnableRxOwn = 0x00000000, /* Enable receive own packets 0 */
428 
429  GmacLoopback = 0x00001000,
430  GmacLoopbackOn = 0x00001000, /* (LM)Loopback mode for GMII/MII 12 RW */
431  GmacLoopbackOff = 0x00000000, /* Normal mode 0 */
432 
433  GmacDuplex = 0x00000800,
434  GmacFullDuplex = 0x00000800, /* (DM)Full duplex mode 11 RW */
435  GmacHalfDuplex = 0x00000000, /* Half duplex mode 0 */
436 
437  GmacRxIpcOffload = 0x00000400, /*IPC checksum offload 10 RW 0 */
438 
439  GmacRetry = 0x00000200,
440  GmacRetryDisable = 0x00000200, /* (DR)Disable Retry 9 RW */
441  GmacRetryEnable = 0x00000000, /* Enable retransmission as per BL 0 */
442 
443  GmacLinkUp = 0x00000100, /* (LUD)Link UP 8 RW */
444  GmacLinkDown = 0x00000100, /* Link Down 0 */
445 
446  GmacPadCrcStrip = 0x00000080,
447  GmacPadCrcStripEnable = 0x00000080, /* (ACS) Automatic Pad/Crc strip enable 7 RW */
448  GmacPadCrcStripDisable = 0x00000000, /* Automatic Pad/Crc stripping disable 0 */
449 
450  GmacBackoffLimit = 0x00000060,
451  GmacBackoffLimit3 = 0x00000060, /* (BL)Back-off limit in HD mode 6:5 RW */
452  GmacBackoffLimit2 = 0x00000040, /* */
453  GmacBackoffLimit1 = 0x00000020, /* */
454  GmacBackoffLimit0 = 0x00000000, /* 00 */
455 
456  GmacDeferralCheck = 0x00000010,
457  GmacDeferralCheckEnable = 0x00000010, /* (DC)Deferral check enable in HD mode 4 RW */
458  GmacDeferralCheckDisable = 0x00000000, /* Deferral check disable 0 */
459 
460  GmacTx = 0x00000008,
461  GmacTxEnable = 0x00000008, /* (TE)Transmitter enable 3 RW */
462  GmacTxDisable = 0x00000000, /* Transmitter disable 0 */
463 
464  GmacRx = 0x00000004,
465  GmacRxEnable = 0x00000004, /* (RE)Receiver enable 2 RW */
466  GmacRxDisable = 0x00000000, /* Receiver disable 0 */
467 };
468 
469 /* GmacFrameFilter = 0x0004, Mac frame filtering controls Register Layout*/
470 enum GmacFrameFilterReg {
471  GmacFilter = 0x80000000,
472  GmacFilterOff = 0x80000000, /* (RA)Receive all incoming packets 31 RW */
473  GmacFilterOn = 0x00000000, /* Receive filtered packets only 0 */
474  GmacVlanTagFilter = 0x00010000, /*VLAN tag filter enable 16 RW 0 */
475  GmacHashPerfectFilter = 0x00000400, /*Hash or Perfect Filter enable 10 RW 0 */
476 
477  GmacSrcAddrFilter = 0x00000200,
478  GmacSrcAddrFilterEnable = 0x00000200, /* (SAF)Source Address Filter enable 9 RW */
479  GmacSrcAddrFilterDisable = 0x00000000, /* 0 */
480 
481  GmacSrcInvaAddrFilter = 0x00000100,
482  GmacSrcInvAddrFilterEn = 0x00000100, /* (SAIF)Inv Src Addr Filter enable 8 RW */
483  GmacSrcInvAddrFilterDis = 0x00000000, /* 0 */
484 
485  GmacPassControl = 0x000000C0,
486  GmacPassControl3 = 0x000000C0, /* (PCS)Forwards ctrl frms that pass AF 7:6 RW */
487  GmacPassControl2 = 0x00000080, /* Forwards all control frames */
488  GmacPassControl1 = 0x00000040, /* Does not pass control frames */
489  GmacPassControl0 = 0x00000000, /* Does not pass control frames 00 */
490 
491  GmacBroadcast = 0x00000020,
492  GmacBroadcastDisable = 0x00000020, /* (DBF)Disable Rx of broadcast frames 5 RW */
493  GmacBroadcastEnable = 0x00000000, /* Enable broadcast frames 0 */
494 
495  GmacMulticastFilter = 0x00000010,
496  GmacMulticastFilterOff = 0x00000010, /* (PM) Pass all multicast packets 4 RW */
497  GmacMulticastFilterOn = 0x00000000, /* Pass filtered multicast packets 0 */
498 
499  GmacDestAddrFilter = 0x00000008,
500  GmacDestAddrFilterInv = 0x00000008, /* (DAIF)Inverse filtering for DA 3 RW */
501  GmacDestAddrFilterNor = 0x00000000, /* Normal filtering for DA 0 */
502 
503  GmacMcastHashFilter = 0x00000004,
504  GmacMcastHashFilterOn = 0x00000004, /* (HMC)perfom multicast hash filtering 2 RW */
505  GmacMcastHashFilterOff = 0x00000000, /* perfect filtering only 0 */
506 
507  GmacUcastHashFilter = 0x00000002,
508  GmacUcastHashFilterOn = 0x00000002, /* (HUC)Unicast Hash filtering only 1 RW */
509  GmacUcastHashFilterOff = 0x00000000, /* perfect filtering only 0 */
510 
511  GmacPromiscuousMode = 0x00000001,
512  GmacPromiscuousModeOn = 0x00000001, /* Receive all frames 0 RW */
513  GmacPromiscuousModeOff = 0x00000000, /* Receive filtered packets only 0 */
514 };
515 
516 
517 /*GmacGmiiAddr = 0x0010, GMII address Register(ext. Phy) Layout */
518 enum GmacGmiiAddrReg {
519  GmiiDevMask = 0x0000F800, /* (PA)GMII device address 15:11 RW 0x00 */
520  GmiiDevShift = 11,
521 
522  GmiiRegMask = 0x000007C0, /* (GR)GMII register in selected Phy 10:6 RW 0x00 */
523  GmiiRegShift = 6,
524 
525  GmiiCsrClkMask = 0x0000001C, /*CSR Clock bit Mask 4:2 */
526  GmiiCsrClk5 = 0x00000014, /* (CR)CSR Clock Range 250-300 MHz 4:2 RW 000 */
527  GmiiCsrClk4 = 0x00000010, /* 150-250 MHz */
528  GmiiCsrClk3 = 0x0000000C, /* 35-60 MHz */
529  GmiiCsrClk2 = 0x00000008, /* 20-35 MHz */
530  GmiiCsrClk1 = 0x00000004, /* 100-150 MHz */
531  GmiiCsrClk0 = 0x00000000, /* 60-100 MHz */
532 
533  GmiiWrite = 0x00000002, /* (GW)Write to register 1 RW */
534  GmiiRead = 0x00000000, /* Read from register 0 */
535 
536  GmiiBusy = 0x00000001, /* (GB)GMII interface is busy 0 RW 0 */
537 };
538 
539 enum GmacVlanTagReg {
540  GmacEnableSVlan = 0x00040000, /* (ESVL) Enabe S-Vlan */
541  GmacVlanInvMatch = 0x00020000, /* (VTIM) VLAN tag inverse match enable */
542  GmacEnable12BitComp = 0x00010000, /* (ETV) Enable 12-bit VLAN tag comparision */
543  GmacVlanTagMsk = 0x0000FFFF /* (VL) VLAN tag */
544 
545 };
546 
547 
548 enum GmacLPICtrlStsReg {
549  GmacLPITxAuto = 0x00080000,
550  GmacLPIPhyStsEn = 0x00040000,
551  GmacLPIPhySts = 0x00020000,
552  GmacLPIEn = 0x00010000,
553  GmacRxLPISts = 0x00000200,
554  GmacTxLPISts = 0x00000100,
555  GmacRxLPIExit = 0x00000008,
556  GmacRxLPIEnter = 0x00000004,
557  GmacTxLPIExit = 0x00000002,
558  GmacTxLPIEnter = 0x00000001,
559 };
560 
561 enum GmacLPITimerCtrlReg {
562  GmacLPILinkStableTimerMsk = 0x03FF0000,
563  GmacLPITxWaitTimerMsk = 0x0000FFFF,
564 };
565 
566 
567 /* GmacGmiiData = 0x0014, GMII data Register(ext. Phy) Layout */
568 enum GmacGmiiDataReg {
569  GmiiDataMask = 0x0000FFFF, /* (GD)GMII Data 15:0 RW 0x0000 */
570 };
571 
572 
573 /*GmacFlowControl = 0x0018, Flow control Register Layout */
574 enum GmacFlowControlReg {
575  GmacPauseTimeMask = 0xFFFF0000, /* (PT) PAUSE TIME field in the control frame 31:16 RW 0x0000 */
576  GmacPauseTimeShift = 16,
577 
578  GmacPauseLowThresh = 0x00000030,
579  GmacPauseLowThresh3 = 0x00000030, /* (PLT)thresh for pause tmr 256 slot time 5:4 RW */
580  GmacPauseLowThresh2 = 0x00000020, /* 144 slot time */
581  GmacPauseLowThresh1 = 0x00000010, /* 28 slot time */
582  GmacPauseLowThresh0 = 0x00000000, /* 4 slot time 000 */
583 
584  GmacUnicastPauseFrame = 0x00000008,
585  GmacUnicastPauseFrameOn = 0x00000008, /* (UP)Detect pause frame with unicast addr. 3 RW */
586  GmacUnicastPauseFrameOff = 0x00000000, /* Detect only pause frame with multicast addr. 0 */
587 
588  GmacRxFlowControl = 0x00000004,
589  GmacRxFlowControlEnable = 0x00000004, /* (RFE)Enable Rx flow control 2 RW */
590  GmacRxFlowControlDisable = 0x00000000, /* Disable Rx flow control 0 */
591 
592  GmacTxFlowControl = 0x00000002,
593  GmacTxFlowControlEnable = 0x00000002, /* (TFE)Enable Tx flow control 1 RW */
594  GmacTxFlowControlDisable = 0x00000000, /* Disable flow control 0 */
595 
596  GmacFlowControlBackPressure= 0x00000001,
597  GmacSendPauseFrame = 0x00000001, /* (FCB/PBA)send pause frm/Apply back pressure 0 RW 0 */
598 };
599 
600 
601 enum GmacVLANIncRepReg {
602  GmacSVLAN = 0x00080000,
603  GmacCVLAN = 0x00000000,
604  GmacVLP = 0x00040000,
605  GmacVLANNoACT = 0x00000000,
606  GmacVLANDel = 0x00010000,
607  GmacVLANIns = 0x00020000,
608  GmacVLANRep = 0x00030000,
609  GmacVLANMsk = 0x0000FFFF
610 
611 };
612 
613 /* GmacInterruptStatus = 0x0038, Mac Interrupt ststus register */
614 enum GmacInterruptStatusBitDefinition {
615  GmacLPIIntSts = 0x00000400, /* set if int generated due to TS (Read Time Stamp Status Register to know details)*/
616  GmacTSIntSts = 0x00000200, /* set if int generated due to TS (Read Time Stamp Status Register to know details)*/
617  GmacMmcRxChksumOffload = 0x00000080, /* set if int generated in MMC RX CHECKSUM OFFLOAD int register */
618  GmacMmcTxIntSts = 0x00000040, /* set if int generated in MMC TX Int register */
619  GmacMmcRxIntSts = 0x00000020, /* set if int generated in MMC RX Int register */
620  GmacMmcIntSts = 0x00000010, /* set if any of the above bit [7:5] is set */
621  GmacPmtIntSts = 0x00000008, /* set whenver magic pkt/wake-on-lan frame is received */
622  GmacPcsAnComplete = 0x00000004, /* set when AN is complete in TBI/RTBI/SGMIII phy interface */
623  GmacPcsLnkStsChange = 0x00000002, /* set if any lnk status change in TBI/RTBI/SGMII interface */
624  GmacRgmiiIntSts = 0x00000001, /* set if any change in lnk status of RGMII interface */
625 
626 };
627 
628 /* GmacInterruptMask = 0x003C, Mac Interrupt Mask register */
629 enum GmacInterruptMaskBitDefinition {
630  GmacTSIntMask = 0x00000200, /* when set disables the time stamp interrupt generation */
631  GmacPmtIntMask = 0x00000008, /* when set Disables the assertion of PMT interrupt */
632  GmacPcsAnIntMask = 0x00000004, /* When set disables the assertion of PCS AN complete interrupt */
633  GmacPcsLnkStsIntMask = 0x00000002, /* when set disables the assertion of PCS lnk status change interrupt */
634  GmacRgmiiIntMask = 0x00000001, /* when set disables the assertion of RGMII int */
635 };
636 
637 /**********************************************************
638  * GMAC DMA registers
639  * For Pci based system address is BARx + GmaDmaBase
640  * For any other system translation is done accordingly
641  **********************************************************/
642 
643 enum DmaRegisters {
644  DmaBusMode = 0x0000, /* CSR0 - Bus Mode Register */
645  DmaTxPollDemand = 0x0004, /* CSR1 - Transmit Poll Demand Register */
646  DmaRxPollDemand = 0x0008, /* CSR2 - Receive Poll Demand Register */
647  DmaRxBaseAddr = 0x000C, /* CSR3 - Receive Descriptor list base address */
648  DmaTxBaseAddr = 0x0010, /* CSR4 - Transmit Descriptor list base address */
649  DmaStatus = 0x0014, /* CSR5 - Dma status Register */
650  DmaControl = 0x0018, /* CSR6 - Dma Operation Mode Register */
651  DmaInterrupt = 0x001C, /* CSR7 - Interrupt enable */
652  DmaMissedFr = 0x0020, /* CSR8 - Missed Frame & Buffer overflow Counter */
653  DmaTxCurrDesc = 0x0048, /* - Current host Tx Desc Register */
654  DmaRxCurrDesc = 0x004C, /* - Current host Rx Desc Register */
655  DmaTxCurrAddr = 0x0050, /* CSR20 - Current host transmit buffer address */
656  DmaRxCurrAddr = 0x0054, /* CSR21 - Current host receive buffer address */
657 
658 
659 };
660 
661 /**********************************************************
662  * DMA Engine registers Layout
663  **********************************************************/
664 
665 /*DmaBusMode = 0x0000, CSR0 - Bus Mode */
666 enum DmaBusModeReg {
667  /* Bit description Bits R/W Reset value */
668 
669  DmaFixedBurstEnable = 0x00010000, /* (FB)Fixed Burst SINGLE, INCR4, INCR8 or INCR16 16 RW */
670  DmaFixedBurstDisable = 0x00000000, /* SINGLE, INCR 0 */
671 
672  DmaTxPriorityRatio11 = 0x00000000, /* (PR)TX:RX DMA priority ratio 1:1 15:14 RW 00 */
673  DmaTxPriorityRatio21 = 0x00004000, /* (PR)TX:RX DMA priority ratio 2:1 */
674  DmaTxPriorityRatio31 = 0x00008000, /* (PR)TX:RX DMA priority ratio 3:1 */
675  DmaTxPriorityRatio41 = 0x0000C000, /* (PR)TX:RX DMA priority ratio 4:1 */
676 
677  DmaBurstLengthx8 = 0x01000000, /* When set mutiplies the PBL by 8 24 RW 0 */
678 
679  DmaBurstLength256 = 0x01002000, /*(DmaBurstLengthx8 | DmaBurstLength32) = 256 [24]:13:8 */
680  DmaBurstLength128 = 0x01001000, /*(DmaBurstLengthx8 | DmaBurstLength16) = 128 [24]:13:8 */
681  DmaBurstLength64 = 0x01000800, /*(DmaBurstLengthx8 | DmaBurstLength8) = 64 [24]:13:8 */
682  DmaBurstLength32 = 0x00002000, /* (PBL) programmable Dma burst length = 32 13:8 RW */
683  DmaBurstLength16 = 0x00001000, /* Dma burst length = 16 */
684  DmaBurstLength8 = 0x00000800, /* Dma burst length = 8 */
685  DmaBurstLength4 = 0x00000400, /* Dma burst length = 4 */
686  DmaBurstLength2 = 0x00000200, /* Dma burst length = 2 */
687  DmaBurstLength1 = 0x00000100, /* Dma burst length = 1 */
688  DmaBurstLength0 = 0x00000000, /* Dma burst length = 0 0x00 */
689 
690  DmaDescriptor8Words = 0x00000080, /* Enh Descriptor works 1=> 8 word descriptor 7 0 */
691  DmaDescriptor4Words = 0x00000000, /* Enh Descriptor works 0=> 4 word descriptor 7 0 */
692 
693  DmaDescriptorSkip16 = 0x00000040, /* (DSL)Descriptor skip length (no.of dwords) 6:2 RW */
694  DmaDescriptorSkip8 = 0x00000020, /* between two unchained descriptors */
695  DmaDescriptorSkip4 = 0x00000010, /* */
696  DmaDescriptorSkip2 = 0x00000008, /* */
697  DmaDescriptorSkip1 = 0x00000004, /* */
698  DmaDescriptorSkip0 = 0x00000000, /* 0x00 */
699 
700  DmaArbitRr = 0x00000000, /* (DA) DMA RR arbitration 1 RW 0 */
701  DmaArbitPr = 0x00000002, /* Rx has priority over Tx */
702 
703  DmaResetOn = 0x00000001, /* (SWR)Software Reset DMA engine 0 RW */
704  DmaResetOff = 0x00000000, /* 0 */
705 };
706 
707 
708 /*DmaStatus = 0x0014, CSR5 - Dma status Register */
709 enum DmaStatusReg {
710  /*Bit 28 27 and 26 indicate whether the interrupt due to PMT GMACMMC or GMAC LINE Remaining bits are DMA interrupts*/
711 
712 
713  GmacLPIIntr = 0x40000000, /* GMC LPI interrupt 31 RO 0 */
714 
715 
716  GmacPmtIntr = 0x10000000, /* (GPI)Gmac subsystem interrupt 28 RO 0 */
717  GmacMmcIntr = 0x08000000, /* (GMI)Gmac MMC subsystem interrupt 27 RO 0 */
718  GmacLineIntfIntr = 0x04000000, /* Line interface interrupt 26 RO 0 */
719 
720  DmaErrorBit2 = 0x02000000, /* (EB)Error bits 0-data buffer, 1-desc. access 25 RO 0 */
721  DmaErrorBit1 = 0x01000000, /* (EB)Error bits 0-write trnsf, 1-read transfr 24 RO 0 */
722  DmaErrorBit0 = 0x00800000, /* (EB)Error bits 0-Rx DMA, 1-Tx DMA 23 RO 0 */
723 
724  DmaTxState = 0x00700000, /* (TS)Transmit process state 22:20 RO */
725  DmaTxStopped = 0x00000000, /* Stopped - Reset or Stop Tx Command issued 000 */
726  DmaTxFetching = 0x00100000, /* Running - fetching the Tx descriptor */
727  DmaTxWaiting = 0x00200000, /* Running - waiting for status */
728  DmaTxReading = 0x00300000, /* Running - reading the data from host memory */
729  DmaTxSuspended = 0x00600000, /* Suspended - Tx Descriptor unavailabe */
730  DmaTxClosing = 0x00700000, /* Running - closing Rx descriptor */
731 
732  DmaRxState = 0x000E0000, /* (RS)Receive process state 19:17 RO */
733  DmaRxStopped = 0x00000000, /* Stopped - Reset or Stop Rx Command issued 000 */
734  DmaRxFetching = 0x00020000, /* Running - fetching the Rx descriptor */
735  DmaRxWaiting = 0x00060000, /* Running - waiting for packet */
736  DmaRxSuspended = 0x00080000, /* Suspended - Rx Descriptor unavailable */
737  DmaRxClosing = 0x000A0000, /* Running - closing descriptor */
738  DmaRxQueuing = 0x000E0000, /* Running - queuing the recieve frame into host memory */
739 
740  DmaIntNormal = 0x00010000, /* (NIS)Normal interrupt summary 16 RW 0 */
741  DmaIntAbnormal = 0x00008000, /* (AIS)Abnormal interrupt summary 15 RW 0 */
742 
743  DmaIntEarlyRx = 0x00004000, /* Early receive interrupt (Normal) RW 0 */
744  DmaIntBusError = 0x00002000, /* Fatal bus error (Abnormal) RW 0 */
745  DmaIntEarlyTx = 0x00000400, /* Early transmit interrupt (Abnormal) RW 0 */
746  DmaIntRxWdogTO = 0x00000200, /* Receive Watchdog Timeout (Abnormal) RW 0 */
747  DmaIntRxStopped = 0x00000100, /* Receive process stopped (Abnormal) RW 0 */
748  DmaIntRxNoBuffer = 0x00000080, /* Receive buffer unavailable (Abnormal) RW 0 */
749  DmaIntRxCompleted = 0x00000040, /* Completion of frame reception (Normal) RW 0 */
750  DmaIntTxUnderflow = 0x00000020, /* Transmit underflow (Abnormal) RW 0 */
751  DmaIntRcvOverflow = 0x00000010, /* Receive Buffer overflow interrupt RW 0 */
752  DmaIntTxJabberTO = 0x00000008, /* Transmit Jabber Timeout (Abnormal) RW 0 */
753  DmaIntTxNoBuffer = 0x00000004, /* Transmit buffer unavailable (Normal) RW 0 */
754  DmaIntTxStopped = 0x00000002, /* Transmit process stopped (Abnormal) RW 0 */
755  DmaIntTxCompleted = 0x00000001, /* Transmit completed (Normal) RW 0 */
756 };
757 
758 /*DmaControl = 0x0018, CSR6 - Dma Operation Mode Register */
759 enum DmaControlReg {
760  DmaDisableDropTcpCs = 0x04000000, /* (DT) Dis. drop. of tcp/ip CS error frames 26 RW 0 */
761 
762  DmaStoreAndForward = 0x00200000, /* (SF)Store and forward 21 RW 0 */
763  DmaFlushTxFifo = 0x00100000, /* (FTF)Tx FIFO controller is reset to default 20 RW 0 */
764 
765  DmaTxThreshCtrl = 0x0001C000, /* (TTC)Controls thre Threh of MTL tx Fifo 16:14 RW */
766  DmaTxThreshCtrl16 = 0x0001C000, /* (TTC)Controls thre Threh of MTL tx Fifo 16 16:14 RW */
767  DmaTxThreshCtrl24 = 0x00018000, /* (TTC)Controls thre Threh of MTL tx Fifo 24 16:14 RW */
768  DmaTxThreshCtrl32 = 0x00014000, /* (TTC)Controls thre Threh of MTL tx Fifo 32 16:14 RW */
769  DmaTxThreshCtrl40 = 0x00010000, /* (TTC)Controls thre Threh of MTL tx Fifo 40 16:14 RW */
770  DmaTxThreshCtrl256 = 0x0000c000, /* (TTC)Controls thre Threh of MTL tx Fifo 256 16:14 RW */
771  DmaTxThreshCtrl192 = 0x00008000, /* (TTC)Controls thre Threh of MTL tx Fifo 192 16:14 RW */
772  DmaTxThreshCtrl128 = 0x00004000, /* (TTC)Controls thre Threh of MTL tx Fifo 128 16:14 RW */
773  DmaTxThreshCtrl64 = 0x00000000, /* (TTC)Controls thre Threh of MTL tx Fifo 64 16:14 RW 000 */
774 
775  DmaTxStart = 0x00002000, /* (ST)Start/Stop transmission 13 RW 0 */
776 
777  DmaRxFlowCtrlDeact = 0x00401800, /* (RFD)Rx flow control deact. threhold [22]:12:11 RW */
778  DmaRxFlowCtrlDeact1K = 0x00000000, /* (RFD)Rx flow control deact. threhold (1kbytes) [22]:12:11 RW 00 */
779  DmaRxFlowCtrlDeact2K = 0x00000800, /* (RFD)Rx flow control deact. threhold (2kbytes) [22]:12:11 RW */
780  DmaRxFlowCtrlDeact3K = 0x00001000, /* (RFD)Rx flow control deact. threhold (3kbytes) [22]:12:11 RW */
781  DmaRxFlowCtrlDeact4K = 0x00001800, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */
782  DmaRxFlowCtrlDeact5K = 0x00400000, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */
783  DmaRxFlowCtrlDeact6K = 0x00400800, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */
784  DmaRxFlowCtrlDeact7K = 0x00401000, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */
785 
786  DmaRxFlowCtrlAct = 0x00800600, /* (RFA)Rx flow control Act. threhold [23]:10:09 RW */
787  DmaRxFlowCtrlAct1K = 0x00000000, /* (RFA)Rx flow control Act. threhold (1kbytes) [23]:10:09 RW 00 */
788  DmaRxFlowCtrlAct2K = 0x00000200, /* (RFA)Rx flow control Act. threhold (2kbytes) [23]:10:09 RW */
789  DmaRxFlowCtrlAct3K = 0x00000400, /* (RFA)Rx flow control Act. threhold (3kbytes) [23]:10:09 RW */
790  DmaRxFlowCtrlAct4K = 0x00000300, /* (RFA)Rx flow control Act. threhold (4kbytes) [23]:10:09 RW */
791  DmaRxFlowCtrlAct5K = 0x00800000, /* (RFA)Rx flow control Act. threhold (5kbytes) [23]:10:09 RW */
792  DmaRxFlowCtrlAct6K = 0x00800200, /* (RFA)Rx flow control Act. threhold (6kbytes) [23]:10:09 RW */
793  DmaRxFlowCtrlAct7K = 0x00800400, /* (RFA)Rx flow control Act. threhold (7kbytes) [23]:10:09 RW */
794 
795  DmaRxThreshCtrl = 0x00000018, /* (RTC)Controls thre Threh of MTL rx Fifo 4:3 RW */
796  DmaRxThreshCtrl64 = 0x00000000, /* (RTC)Controls thre Threh of MTL tx Fifo 64 4:3 RW */
797  DmaRxThreshCtrl32 = 0x00000008, /* (RTC)Controls thre Threh of MTL tx Fifo 32 4:3 RW */
798  DmaRxThreshCtrl96 = 0x00000010, /* (RTC)Controls thre Threh of MTL tx Fifo 96 4:3 RW */
799  DmaRxThreshCtrl128 = 0x00000018, /* (RTC)Controls thre Threh of MTL tx Fifo 128 4:3 RW */
800 
801  DmaEnHwFlowCtrl = 0x00000100, /* (EFC)Enable HW flow control 8 RW */
802  DmaDisHwFlowCtrl = 0x00000000, /* Disable HW flow control 0 */
803 
804  DmaFwdErrorFrames = 0x00000080, /* (FEF)Forward error frames 7 RW 0 */
805  DmaFwdUnderSzFrames = 0x00000040, /* (FUF)Forward undersize frames 6 RW 0 */
806  DmaTxSecondFrame = 0x00000004, /* (OSF)Operate on second frame 4 RW 0 */
807  DmaRxStart = 0x00000002, /* (SR)Start/Stop reception 1 RW 0 */
808 };
809 
810 
811 /*DmaInterrupt = 0x001C, CSR7 - Interrupt enable Register Layout */
812 enum DmaInterruptReg {
813  DmaIeNormal = DmaIntNormal , /* Normal interrupt enable RW 0 */
814  DmaIeAbnormal = DmaIntAbnormal , /* Abnormal interrupt enable RW 0 */
815 
816  DmaIeEarlyRx = DmaIntEarlyRx , /* Early receive interrupt enable RW 0 */
817  DmaIeBusError = DmaIntBusError , /* Fatal bus error enable RW 0 */
818  DmaIeEarlyTx = DmaIntEarlyTx , /* Early transmit interrupt enable RW 0 */
819  DmaIeRxWdogTO = DmaIntRxWdogTO , /* Receive Watchdog Timeout enable RW 0 */
820  DmaIeRxStopped = DmaIntRxStopped , /* Receive process stopped enable RW 0 */
821  DmaIeRxNoBuffer = DmaIntRxNoBuffer , /* Receive buffer unavailable enable RW 0 */
822  DmaIeRxCompleted = DmaIntRxCompleted, /* Completion of frame reception enable RW 0 */
823  DmaIeTxUnderflow = DmaIntTxUnderflow, /* Transmit underflow enable RW 0 */
824 
825  DmaIeRxOverflow = DmaIntRcvOverflow, /* Receive Buffer overflow interrupt RW 0 */
826  DmaIeTxJabberTO = DmaIntTxJabberTO , /* Transmit Jabber Timeout enable RW 0 */
827  DmaIeTxNoBuffer = DmaIntTxNoBuffer , /* Transmit buffer unavailable enable RW 0 */
828  DmaIeTxStopped = DmaIntTxStopped , /* Transmit process stopped enable RW 0 */
829  DmaIeTxCompleted = DmaIntTxCompleted, /* Transmit completed enable RW 0 */
830 };
831 
832 
833 /**********************************************************
834  * DMA Engine descriptors
835  **********************************************************/
836 
837 /*
838 **********Enhanced Descritpor structure to support 8K buffer per buffer ****************************
839 
840 DmaRxBaseAddr = 0x000C, CSR3 - Receive Descriptor list base address
841 DmaRxBaseAddr is the pointer to the first Rx Descriptors. the Descriptor format in Little endian with a
842 32 bit Data bus is as shown below
843 
844 Similarly
845 DmaTxBaseAddr = 0x0010, CSR4 - Transmit Descriptor list base address
846 DmaTxBaseAddr is the pointer to the first Rx Descriptors. the Descriptor format in Little endian with a
847 32 bit Data bus is as shown below
848  --------------------------------------------------------------------------
849  RDES0 |OWN (31)| Status |
850  --------------------------------------------------------------------------
851  RDES1 | Ctrl | Res | Byte Count Buffer 2 | Ctrl | Res | Byte Count Buffer 1 |
852  --------------------------------------------------------------------------
853  RDES2 | Buffer 1 Address |
854  --------------------------------------------------------------------------
855  RDES3 | Buffer 2 Address / Next Descriptor Address |
856  --------------------------------------------------------------------------
857 
858  --------------------------------------------------------------------------
859  TDES0 |OWN (31)| Ctrl | Res | Ctrl | Res | Status |
860  --------------------------------------------------------------------------
861  TDES1 | Res | Byte Count Buffer 2 | Res | Byte Count Buffer 1 |
862  --------------------------------------------------------------------------
863  TDES2 | Buffer 1 Address |
864  --------------------------------------------------------------------------
865  TDES3 | Buffer 2 Address / Next Descriptor Address |
866  --------------------------------------------------------------------------
867 
868 */
869 
870 enum DmaDescriptorStatus /* status word of DMA descriptor */
871 {
872 
873  DescOwnByDma = 0x80000000, /* (OWN)Descriptor is owned by DMA engine 31 RW */
874 
875  DescDAFilterFail = 0x40000000, /* (AFM)Rx - DA Filter Fail for the rx frame 30 */
876 
877  DescFrameLengthMask = 0x3FFF0000, /* (FL)Receive descriptor frame length 29:16 */
878  DescFrameLengthShift = 16,
879 
880  DescError = 0x00008000, /* (ES)Error summary bit - OR of the follo. bits: 15 */
881  /* DE || OE || IPC || LC || RWT || RE || CE */
882  DescRxTruncated = 0x00004000, /* (DE)Rx - no more descriptors for receive frame 14 */
883  DescSAFilterFail = 0x00002000, /* (SAF)Rx - SA Filter Fail for the received frame 13 */
884  DescRxLengthError = 0x00001000, /* (LE)Rx - frm size not matching with len field 12 */
885  DescRxDamaged = 0x00000800, /* (OE)Rx - frm was damaged due to buffer overflow 11 */
886  DescRxVLANTag = 0x00000400, /* (VLAN)Rx - received frame is a VLAN frame 10 */
887  DescRxFirst = 0x00000200, /* (FS)Rx - first descriptor of the frame 9 */
888  DescRxLast = 0x00000100, /* (LS)Rx - last descriptor of the frame 8 */
889  DescRxLongFrame = 0x00000080, /* (Giant Frame)Rx - frame is longer than 1518/1522 7 */
890  DescRxTSAvailable = 0x00000080, /* Share bit with (Giant Frame)Rx 7 */
891  DescRxCollision = 0x00000040, /* (LC)Rx - late collision occurred during reception 6 */
892  DescRxFrameEther = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */
893  DescRxWatchdog = 0x00000010, /* (RWT)Rx - watchdog timer expired during reception 4 */
894  DescRxMiiError = 0x00000008, /* (RE)Rx - error reported by MII interface 3 */
895  DescRxDribbling = 0x00000004, /* (DE)Rx - frame contains non int multiple of 8 bits 2 */
896  DescRxCrc = 0x00000002, /* (CE)Rx - CRC error 1 */
897 // DescRxMacMatch = 0x00000001, /* (RX MAC Address) Rx mac address reg(1 to 15)match 0 */
898 
899  DescRxEXTsts = 0x00000001, /* Extended Status Available (RDES4) 0 */
900 
901  DescTxIntEnable = 0x40000000, /* (IC)Tx - interrupt on completion 30 */
902  DescTxLast = 0x20000000, /* (LS)Tx - Last segment of the frame 29 */
903  DescTxFirst = 0x10000000, /* (FS)Tx - First segment of the frame 28 */
904  DescTxDisableCrc = 0x08000000, /* (DC)Tx - Add CRC disabled (first segment only) 27 */
905  DescTxDisablePadd = 0x04000000, /* (DP)disable padding, added by - reyaz 26 */
906  DescTxTSEnable = 0x02000000, /* (TTSE) Transmit Timestamp Enable 25 */
907  DescTxCrcReplacement = 0x01000000, /* (CRCR) CRC Replacement Control 24 */
908  DescTxCisMask = 0x00c00000, /* Tx checksum offloading control mask 23:22 */
909  DescTxCisBypass = 0x00000000, /* Checksum bypass */
910  DescTxCisIpv4HdrCs = 0x00400000, /* IPv4 header checksum */
911  DescTxCisTcpOnlyCs = 0x00800000, /* TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present */
912  DescTxCisTcpPseudoCs = 0x00c00000, /* TCP/UDP/ICMP checksum fully in hardware including pseudo header */
913 
914  TxDescEndOfRing = 0x00200000, /* (TER)End of descriptors ring 21 */
915  TxDescChain = 0x00100000, /* (TCH)Second buffer address is chain address 20 */
916 
917  DescRxChkBit0 = 0x00000001, /*() Rx - Rx Payload Checksum Error 0 */
918  DescRxChkBit7 = 0x00000080, /* (IPC CS ERROR)Rx - Ipv4 header checksum error 7 */
919  DescRxChkBit5 = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */
920 
921  DescRxTSavail = 0x00000080, /* Time stamp available 7 */
922  DescRxFrameType = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */
923  DescTxTSStatus = 0x00020000, /* (TTSS) Transmit Timestamp Status 17 */
924  DescTxIpv4ChkError = 0x00010000, /* (IHE) Tx Ip header error 16 */
925  DescTxTimeout = 0x00004000, /* (JT)Tx - Transmit jabber timeout 14 */
926  DescTxFrameFlushed = 0x00002000, /* (FF)Tx - DMA/MTL flushed the frame due to SW flush 13 */
927  DescTxPayChkError = 0x00001000, /* (PCE) Tx Payload checksum Error 12 */
928  DescTxLostCarrier = 0x00000800, /* (LC)Tx - carrier lost during tramsmission 11 */
929  DescTxNoCarrier = 0x00000400, /* (NC)Tx - no carrier signal from the tranceiver 10 */
930  DescTxLateCollision = 0x00000200, /* (LC)Tx - transmission aborted due to collision 9 */
931  DescTxExcCollisions = 0x00000100, /* (EC)Tx - transmission aborted after 16 collisions 8 */
932  DescTxVLANFrame = 0x00000080, /* (VF)Tx - VLAN-type frame 7 */
933 
934  DescTxCollMask = 0x00000078, /* (CC)Tx - Collision count 6:3 */
935  DescTxCollShift = 3,
936 
937  DescTxExcDeferral = 0x00000004, /* (ED)Tx - excessive deferral 2 */
938  DescTxUnderflow = 0x00000002, /* (UF)Tx - late data arrival from the memory 1 */
939  DescTxDeferred = 0x00000001, /* (DB)Tx - frame transmision deferred 0 */
940 
941  /*
942  This explains the RDES1/TDES1 bits layout
943  --------------------------------------------------------------------
944  RDES1/TDES1 | Control Bits | Byte Count Buffer 2 | Byte Count Buffer 1 |
945  --------------------------------------------------------------------
946 
947  */
948 // DmaDescriptorLength length word of DMA descriptor
949 
950 
951  RxDisIntCompl = 0x80000000, /* (Disable Rx int on completion) 31 */
952  RxDescEndOfRing = 0x00008000, /* (TER)End of descriptors ring 15 */
953  RxDescChain = 0x00004000, /* (TCH)Second buffer address is chain address 14 */
954 
955 
956  DescSize2Mask = 0x1FFF0000, /* (TBS2) Buffer 2 size 28:16 */
957  DescSize2Shift = 16,
958  DescSize1Mask = 0x00001FFF, /* (TBS1) Buffer 1 size 12:0 */
959  DescSize1Shift = 0,
960 
961 
962  /*
963  This explains the RDES4 Extended Status bits layout
964  --------------------------------------------------------------------
965  RDES4 | Extended Status |
966  --------------------------------------------------------------------
967  */
968 
969  DescRxPtpAvail = 0x00004000, /* PTP snapshot available 14 */
970  DescRxPtpVer = 0x00002000, /* When set indicates IEEE1584 Version 2 (else Ver1) 13 */
971  DescRxPtpFrameType = 0x00001000, /* PTP frame type Indicates PTP sent over ethernet 12 */
972  DescRxPtpMessageType = 0x00000F00, /* Message Type 11:8 */
973  DescRxPtpNo = 0x00000000, /* 0000 => No PTP message received */
974  DescRxPtpSync = 0x00000100, /* 0001 => Sync (all clock types) received */
975  DescRxPtpFollowUp = 0x00000200, /* 0010 => Follow_Up (all clock types) received */
976  DescRxPtpDelayReq = 0x00000300, /* 0011 => Delay_Req (all clock types) received */
977  DescRxPtpDelayResp = 0x00000400, /* 0100 => Delay_Resp (all clock types) received */
978  DescRxPtpPdelayReq = 0x00000500, /* 0101 => Pdelay_Req (in P to P tras clk) or Announce in Ord and Bound clk */
979  DescRxPtpPdelayResp = 0x00000600, /* 0110 => Pdealy_Resp(in P to P trans clk) or Management in Ord and Bound clk */
980  DescRxPtpPdelayRespFP = 0x00000700, /* 0111 => Pdealy_Resp_Follow_Up (in P to P trans clk) or Signaling in Ord and Bound clk */
981  DescRxPtpIPV6 = 0x00000080, /* Received Packet is in IPV6 Packet 7 */
982  DescRxPtpIPV4 = 0x00000040, /* Received Packet is in IPV4 Packet 6 */
983 
984  DescRxChkSumBypass = 0x00000020, /* When set indicates checksum offload engine 5
985  is bypassed */
986  DescRxIpPayloadError = 0x00000010, /* When set indicates 16bit IP payload CS is in error 4 */
987  DescRxIpHeaderError = 0x00000008, /* When set indicates 16bit IPV4 header CS is in 3
988  error or IP datagram version is not consistent
989  with Ethernet type value */
990  DescRxIpPayloadType = 0x00000007, /* Indicate the type of payload encapsulated 2:0
991  in IPdatagram processed by COE (Rx) */
992  DescRxIpPayloadUnknown= 0x00000000, /* Unknown or didnot process IP payload */
993  DescRxIpPayloadUDP = 0x00000001, /* UDP */
994  DescRxIpPayloadTCP = 0x00000002, /* TCP */
995  DescRxIpPayloadICMP = 0x00000003, /* ICMP */
996 
997 };
998 
999 
1000 // Rx Descriptor COE type2 encoding
1001 enum RxDescCOEEncode {
1002  RxLenLT600 = 0, /* Bit(5:7:0)=>0 IEEE 802.3 type frame Length field is Lessthan 0x0600 */
1003  RxIpHdrPayLoadChkBypass = 1, /* Bit(5:7:0)=>1 Payload & Ip header checksum bypassed (unsuppported payload) */
1004  RxIpHdrPayLoadRes = 2, /* Bit(5:7:0)=>2 Reserved */
1005  RxChkBypass = 3, /* Bit(5:7:0)=>3 Neither IPv4 nor IPV6. So checksum bypassed */
1006  RxNoChkError = 4, /* Bit(5:7:0)=>4 No IPv4/IPv6 Checksum error detected */
1007  RxPayLoadChkError = 5, /* Bit(5:7:0)=>5 Payload checksum error detected for Ipv4/Ipv6 frames */
1008  RxIpHdrChkError = 6, /* Bit(5:7:0)=>6 Ip header checksum error detected for Ipv4 frames */
1009  RxIpHdrPayLoadChkError = 7, /* Bit(5:7:0)=>7 Payload & Ip header checksum error detected for Ipv4/Ipv6 frames */
1010 };
1011 
1012 /**********************************************************
1013  * DMA engine interrupt handling functions
1014  **********************************************************/
1015 
1016 enum synopGMACDmaIntEnum /* Intrerrupt types */
1017 {
1018  synopGMACDmaRxNormal = 0x01, /* normal receiver interrupt */
1019  synopGMACDmaRxAbnormal = 0x02, /* abnormal receiver interrupt */
1020  synopGMACDmaRxStopped = 0x04, /* receiver stopped */
1021  synopGMACDmaTxNormal = 0x08, /* normal transmitter interrupt */
1022  synopGMACDmaTxAbnormal = 0x10, /* abnormal transmitter interrupt */
1023  synopGMACDmaTxStopped = 0x20, /* transmitter stopped */
1024  synopGMACDmaError = 0x80, /* Dma engine error */
1025 
1026 };
1027 
1028 
1029 /**********************************************************
1030  * Initial register values
1031  **********************************************************/
1032 enum InitialRegisters {
1033  /* Full-duplex mode with perfect filter on */
1034  GmacConfigInitFdx1000 = GmacWatchdogEnable | GmacJabberEnable | GmacFrameBurstEnable | GmacJumboFrameDisable
1035  | GmacSelectGmii | GmacEnableRxOwn | GmacLoopbackOff
1036  | GmacFullDuplex | GmacRetryEnable | GmacPadCrcStripDisable
1037  | GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable,
1038 
1039  /* Full-duplex mode with perfect filter on */
1040  GmacConfigInitFdx110 = GmacWatchdogEnable | GmacJabberEnable | GmacFrameBurstEnable | GmacJumboFrameDisable
1041  | GmacSelectMii | GmacEnableRxOwn | GmacLoopbackOff
1042  | GmacFullDuplex | GmacRetryEnable | GmacPadCrcStripDisable
1043  | GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable,
1044 
1045  /* Full-duplex mode */
1046  // CHANGED: Pass control config, dest addr filter normal, added source address filter, multicast & unicast
1047  // Hash filter.
1048  /* = GmacFilterOff | GmacPassControlOff | GmacBroadcastEnable */
1049  GmacFrameFilterInitFdx = GmacFilterOn | GmacPassControl0 | GmacBroadcastEnable | GmacSrcAddrFilterDisable
1050  | GmacMulticastFilterOn | GmacDestAddrFilterNor | GmacMcastHashFilterOff
1051  | GmacPromiscuousModeOff | GmacUcastHashFilterOff,
1052 
1053  /* Full-duplex mode */
1054  GmacFlowControlInitFdx = GmacUnicastPauseFrameOff | GmacRxFlowControlEnable | GmacTxFlowControlEnable,
1055 
1056  /* Full-duplex mode */
1057  GmacGmiiAddrInitFdx = GmiiCsrClk2,
1058 
1059 
1060  /* Half-duplex mode with perfect filter on */
1061  // CHANGED: Removed Endian configuration, added single bit config for PAD/CRC strip,
1062  /*| GmacSelectMii | GmacLittleEndian | GmacDisableRxOwn | GmacLoopbackOff*/
1063  GmacConfigInitHdx1000 = GmacWatchdogEnable | GmacJabberEnable | GmacFrameBurstEnable | GmacJumboFrameDisable
1064  | GmacSelectGmii | GmacDisableRxOwn | GmacLoopbackOff
1065  | GmacHalfDuplex | GmacRetryEnable | GmacPadCrcStripDisable
1066  | GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable,
1067 
1068  /* Half-duplex mode with perfect filter on */
1069  GmacConfigInitHdx110 = GmacWatchdogEnable | GmacJabberEnable | GmacFrameBurstEnable | GmacJumboFrameDisable
1070  | GmacSelectMii | GmacDisableRxOwn | GmacLoopbackOff
1071  | GmacHalfDuplex | GmacRetryEnable | GmacPadCrcStripDisable
1072  | GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable,
1073 
1074  /* Half-duplex mode */
1075  GmacFrameFilterInitHdx = GmacFilterOn | GmacPassControl0 | GmacBroadcastEnable | GmacSrcAddrFilterDisable
1076  | GmacMulticastFilterOn | GmacDestAddrFilterNor | GmacMcastHashFilterOff
1077  | GmacUcastHashFilterOff| GmacPromiscuousModeOff,
1078 
1079  /* Half-duplex mode */
1080  GmacFlowControlInitHdx = GmacUnicastPauseFrameOff | GmacRxFlowControlDisable | GmacTxFlowControlDisable,
1081 
1082  /* Half-duplex mode */
1083  GmacGmiiAddrInitHdx = GmiiCsrClk2,
1084 
1085 
1086 
1087  /**********************************************
1088  *DMA configurations
1089  **********************************************/
1090 
1091  DmaBusModeInit = DmaFixedBurstEnable | DmaBurstLength8 | DmaDescriptorSkip2 | DmaResetOff,
1092 // DmaBusModeInit = DmaFixedBurstEnable | DmaBurstLength8 | DmaDescriptorSkip4 | DmaResetOff,
1093 
1094  /* 1000 Mb/s mode */
1095  DmaControlInit1000 = DmaStoreAndForward,// | DmaTxSecondFrame ,
1096 
1097  /* 100 Mb/s mode */
1098  DmaControlInit100 = DmaStoreAndForward,
1099 
1100  /* 10 Mb/s mode */
1101  DmaControlInit10 = DmaStoreAndForward,
1102 
1103  /* Interrupt groups */
1104  DmaIntErrorMask = DmaIntBusError, /* Error */
1105  DmaIntRxAbnMask = DmaIntRxNoBuffer, /* receiver abnormal interrupt */
1106  DmaIntRxNormMask = DmaIntRxCompleted, /* receiver normal interrupt */
1107  DmaIntRxStoppedMask = DmaIntRxStopped, /* receiver stopped */
1108  DmaIntTxAbnMask = DmaIntTxUnderflow, /* transmitter abnormal interrupt */
1109  DmaIntTxNormMask = DmaIntTxCompleted, /* transmitter normal interrupt */
1110  DmaIntTxStoppedMask = DmaIntTxStopped, /* transmitter stopped */
1111 
1112  DmaIntEnable = DmaIeNormal | DmaIeAbnormal | DmaIntErrorMask
1113  | DmaIntRxAbnMask | DmaIntRxNormMask | DmaIntRxStoppedMask
1114  | DmaIntTxAbnMask | DmaIntTxNormMask | DmaIntTxStoppedMask,
1115  DmaIntDisable = 0,
1116 };
1117 
1118 
1119 
1120 
1121 /**********************************************************
1122  * Power Management (PMT) Block
1123  **********************************************************/
1124 
1125 /**
1126  * PMT supports the reception of network (remote) wake-up frames and Magic packet frames.
1127  * It generates interrupts for wake-up frames and Magic packets received by GMAC.
1128  * PMT sits in Rx path and is enabled with remote wake-up frame enable and Magic packet enable.
1129  * These enable are in PMT control and Status register and are programmed by apllication.
1130  *
1131  * When power down mode is enabled in PMT, all rx frames are dropped by the core. Core comes
1132  * out of power down mode only when either Magic packe tor a Remote wake-up frame is received
1133  * and the corresponding detection is enabled.
1134  *
1135  * Driver need not be modified to support this feature. Only Api to put the device in to power
1136  * down mode is sufficient
1137  */
1138 
1139 #define WAKEUP_REG_LENGTH 8 /*This is the reg length for wake up register configuration*/
1140 
1141 enum GmacPmtCtrlStatusBitDefinition {
1142  GmacPmtFrmFilterPtrReset = 0x80000000, /* when set remote wake-up frame filter register pointer to 3'b000 */
1143  GmacPmtGlobalUnicast = 0x00000200, /* When set enables any unicast packet to be a wake-up frame */
1144  GmacPmtWakeupFrameReceived = 0x00000040, /* Wake up frame received */
1145  GmacPmtMagicPktReceived = 0x00000020, /* Magic Packet received */
1146  GmacPmtWakeupFrameEnable = 0x00000004, /* Wake-up frame enable */
1147  GmacPmtMagicPktEnable = 0x00000002, /* Magic packet enable */
1148  GmacPmtPowerDown = 0x00000001, /* Power Down */
1149 };
1150 
1151 
1152 
1153 
1154 /**********************************************************
1155  * IEEE 1588-2008 Precision Time Protocol (PTP) Support
1156  **********************************************************/
1157 enum PTPMessageType {
1158  SYNC = 0x0,
1159  Delay_Req = 0x1,
1160  Pdelay_Req = 0x2,
1161  Pdelay_Resp = 0x3,
1162  Follow_up = 0x8,
1163  Delay_Resp = 0x9,
1164  Pdelay_Resp_Follow_Up = 0xA,
1165  Announce = 0xB,
1166  Signaling = 0xC,
1167  Management = 0xD,
1168 };
1169 
1170 
1171 
1172 typedef struct TimeStampStruct {
1173  u32 TSversion; /* PTP Version 1 or PTP version2 */
1174  u32 TSmessagetype; /* Message type associated with this time stamp */
1175 
1176  u16 TShighest16; /* Highest 16 bit time stamp value, Valid onley when ADV_TIME_HIGH_WORD configured in corekit */
1177  u32 TSupper32; /* Most significant 32 bit time stamp value */
1178  u32 TSlower32; /* Least Significat 32 bit time stamp value */
1179 
1180 } TimeStamp;
1181 
1182 
1183 /**
1184  * IEEE 1588-2008 is the optional module to support Ethernet frame time stamping.
1185  * Sixty four (+16) bit time stamps are given in each frames transmit and receive status.
1186  * The driver assumes the following
1187  * 1. "IEEE 1588 Time Stamping" "TIME_STAMPING"is ENABLED in corekit
1188  * 2. "IEEE 1588 External Time Stamp Input Enable" "EXT_TIME_STAMPING" is DISABLED in corekit
1189  * 3. "IEEE 1588 Advanced Time Stamp support" "ADV_TIME_STAMPING" is ENABLED in corekit
1190  * 4. "IEEE 1588 Higher Word Register Enable" "ADV_TIME_HIGH_WORD" is ENABLED in corekit
1191  */
1192 
1193 /* GmacTSControl = 0x0700, Controls the Timestamp update logic : only when IEEE 1588 time stamping is enabled in corekit */
1194 enum GmacTSControlReg {
1195  GmacTSENMACADDR = 0x00040000, /* Enable Mac Addr for PTP filtering 18 RW 0 */
1196 
1197  GmacTSCLKTYPE = 0x00030000, /* Select the type of clock node 17:16 RW 00 */
1198  /*
1199  TSCLKTYPE TSMSTRENA TSEVNTENA Messages for wihich TS snapshot is taken
1200  00/01 X 0 SYNC, FOLLOW_UP, DELAY_REQ, DELAY_RESP
1201  00/01 1 0 DELAY_REQ
1202  00/01 0 1 SYNC
1203  10 NA 0 SYNC, FOLLOW_UP, DELAY_REQ, DELAY_RESP
1204  10 NA 1 SYNC, FOLLOW_UP
1205  11 NA 0 SYNC, FOLLOW_UP, DELAY_REQ, DELAY_RESP, PDELAY_REQ, PDELAY_RESP
1206  11 NA 1 SYNC, PDELAY_REQ, PDELAY_RESP
1207  */
1208  GmacTSOrdClk = 0x00000000, /* 00=> Ordinary clock*/
1209  GmacTSBouClk = 0x00010000, /* 01=> Boundary clock*/
1210  GmacTSEtoEClk = 0x00020000, /* 10=> End-to-End transparent clock*/
1211  GmacTSPtoPClk = 0x00030000, /* 11=> P-to-P transparent clock*/
1212 
1213  GmacTSMSTRENA = 0x00008000, /* Ena TS Snapshot for Master Messages 15 RW 0 */
1214  GmacTSEVNTENA = 0x00004000, /* Ena TS Snapshot for Event Messages 14 RW 0 */
1215  GmacTSIPV4ENA = 0x00002000, /* Ena TS snapshot for IPv4 13 RW 1 */
1216  GmacTSIPV6ENA = 0x00001000, /* Ena TS snapshot for IPv6 12 RW 0 */
1217  GmacTSIPENA = 0x00000800, /* Ena TS snapshot for PTP over E'net 11 RW 0 */
1218  GmacTSVER2ENA = 0x00000400, /* Ena PTP snooping for version 2 10 RW 0 */
1219 
1220  GmacTSCTRLSSR = 0x00000200, /* Digital or Binary Rollover 9 RW 0 */
1221 
1222  GmacTSENALL = 0x00000100, /* Enable TS fro all frames (Ver2 only) 8 RW 0 */
1223 
1224  GmacTSADDREG = 0x00000020, /* Addend Register Update 5 RW_SC 0 */
1225  GmacTSUPDT = 0x00000008, /* Time Stamp Update 3 RW_SC 0 */
1226  GmacTSINT = 0x00000004, /* Time Atamp Initialize 2 RW_SC 0 */
1227 
1228  GmacTSTRIG = 0x00000010, /* Time stamp interrupt Trigger Enable 4 RW_SC 0 */
1229 
1230  GmacTSCFUPDT = 0x00000002, /* Time Stamp Fine/Coarse 1 RW 0 */
1231  GmacTSCUPDTCoarse = 0x00000000, /* 0=> Time Stamp update method is coarse */
1232  GmacTSCUPDTFine = 0x00000002, /* 1=> Time Stamp update method is fine */
1233 
1234  GmacTSENA = 0x00000001, /* Time Stamp Enable 0 RW 0 */
1235 };
1236 
1237 
1238 /* GmacTSSubSecIncr = 0x0704, 8 bit value by which sub second register is incremented : only when IEEE 1588 time stamping without external timestamp input */
1239 enum GmacTSSubSecIncrReg {
1240  GmacSSINCMsk = 0x000000FF, /* Only Lower 8 bits are valid bits 7:0 RW 00 */
1241 };
1242 
1243 /* GmacTSLow = 0x070C, Indicates whether the timestamp low count is positive or negative; for Adv timestamp it is always zero */
1244 enum GmacTSSign {
1245  GmacTSSign = 0x80000000, /* PSNT 31 RW 0 */
1246  GmacTSPositive = 0x00000000,
1247  GmacTSNegative = 0x80000000,
1248 };
1249 
1250 /*GmacTargetTimeLow = 0x0718, 32 bit nano seconds(MS) to be compared with system time : only when IEEE 1588 time stamping without external timestamp input */
1251 enum GmacTSLowReg {
1252  GmacTSDecThr = 0x3B9AC9FF, /*when TSCTRLSSR is set the max value for GmacTargetTimeLowReg and GmacTimeStampLow register is 0x3B9AC9FF at 1ns precision */
1253 };
1254 
1255 /* GmacTSHighWord = 0x0724, Time Stamp Higher Word Register (Version 2 only); only lower 16 bits are valid */
1256 enum GmacTSHighWordReg {
1257  GmacTSHighWordMask = 0x0000FFFF, /* Time Stamp Higher work register has only lower 16 bits valid */
1258 };
1259 /*GmacTSStatus = 0x0728, Time Stamp Status Register */
1260 enum GmacTSStatusReg {
1261  GmacTSTargTimeReached = 0x00000002, /* Time Stamp Target Time Reached 1 RO 0 */
1262  GmacTSSecondsOverflow = 0x00000001, /* Time Stamp Seconds Overflow 0 RO 0 */
1263 };
1264 
1265 
1266 /**********************************************************
1267  * Time stamp related functions
1268  **********************************************************/
1269 void synopGMAC_TS_enable(synopGMACdevice *gmacdev);
1270 void synopGMAC_TS_disable(synopGMACdevice *gmacdev);
1271 
1272 void synopGMAC_TS_int_enable(synopGMACdevice *gmacdev);
1273 void synopGMAC_TS_int_disable(synopGMACdevice *gmacdev);
1274 
1275 void synopGMAC_TS_mac_addr_filt_enable(synopGMACdevice *gmacdev);
1276 void synopGMAC_TS_mac_addr_filt_disable(synopGMACdevice *gmacdev);
1277 void synopGMAC_TS_set_clk_type(synopGMACdevice *gmacdev, u32 clk_type);
1278 void synopGMAC_TS_master_enable(synopGMACdevice *gmacdev); // Only for Ordinary clock and Boundary clock and "Advanced Time Stamp"
1279 void synopGMAC_TS_master_disable(synopGMACdevice *gmacdev); // Only for Ordinary clock and Boundary clock and "Advanced Time Stamp"
1280 void synopGMAC_TS_event_enable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp"
1281 void synopGMAC_TS_event_disable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp"
1282 void synopGMAC_TS_IPV4_enable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp"
1283 void synopGMAC_TS_IPV4_disable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp"
1284 void synopGMAC_TS_IPV6_enable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp"
1285 void synopGMAC_TS_IPV6_disable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp"
1286 void synopGMAC_TS_ptp_over_ethernet_enable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp"
1287 void synopGMAC_TS_ptp_over_ethernet_disable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp"
1288 void synopGMAC_TS_pkt_snoop_ver2(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp"
1289 void synopGMAC_TS_pkt_snoop_ver1(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp"
1290 
1291 void synopGMAC_TS_digital_rollover_enable(synopGMACdevice *gmacdev);
1292 void synopGMAC_TS_binary_rollover_enable(synopGMACdevice *gmacdev);
1293 void synopGMAC_TS_all_frames_enable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp"
1294 void synopGMAC_TS_all_frames_disable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp"
1295 
1296 s32 synopGMAC_TS_addend_update(synopGMACdevice *gmacdev, u32 addend_value);
1297 s32 synopGMAC_TS_timestamp_update(synopGMACdevice *gmacdev, u32 high_value, u32 low_value);
1298 s32 synopGMAC_TS_timestamp_init(synopGMACdevice *gmacdev, u32 high_value, u32 low_value);
1299 
1300 void synopGMAC_TS_coarse_update(synopGMACdevice *gmacdev); // Only if "fine correction" enabled
1301 void synopGMAC_TS_fine_update(synopGMACdevice *gmacdev); // Only if "fine correction" enabled
1302 
1303 void synopGMAC_TS_subsecond_init(synopGMACdevice *gmacdev, u32 sub_sec_inc_val); // Update should happen making use of subsecond mask
1304 void synopGMAC_TS_read_timestamp(synopGMACdevice *gmacdev, u16 * higher_sec_val,
1305  u32 * sec_val, u32 * sub_sec_val); // Reads the timestamp low,high and higher(Ver2) registers in the the struct pointer; readonly contents
1306 void synopGMAC_TS_load_target_timestamp(synopGMACdevice *gmacdev, u32 sec_val, u32 sub_sec_val); //Loads the timestamp target register with the values provided
1307 
1308 void synopGMAC_TS_load_timestamp_higher_val(synopGMACdevice *gmacdev, u32 higher_sec_val);
1309 void synopGMAC_TS_read_timestamp_higher_val(synopGMACdevice *gmacdev, u16 * higher_sec_val);
1310 void synopGMAC_TS_read_target_timestamp(synopGMACdevice *gmacdev, u32 * sec_val, u32 * sub_sec_val); //Read the target time stamp register contents
1311 
1312 
1313 /**********************************************************
1314  * Common functions
1315  **********************************************************/
1316 s32 synopGMAC_set_mdc_clk_div(synopGMACdevice *gmacdev,u32 clk_div_val);
1317 u32 synopGMAC_get_mdc_clk_div(synopGMACdevice *gmacdev);
1318 s32 synopGMAC_read_phy_reg(u32 *RegBase,u32 PhyBase, u32 RegOffset, u16 * data);
1319 s32 synopGMAC_write_phy_reg(u32 *RegBase, u32 PhyBase, u32 RegOffset, u16 data);
1320 s32 synopGMAC_phy_loopback(synopGMACdevice *gmacdev, bool loopback);
1321 s32 synopGMAC_read_version (synopGMACdevice * gmacdev) ;
1322 s32 synopGMAC_reset (synopGMACdevice * gmacdev );
1323 s32 synopGMAC_reset_nocheck (synopGMACdevice * gmacdev );
1324 s32 synopGMAC_dma_bus_mode_init(synopGMACdevice * gmacdev, u32 init_value );
1325 s32 synopGMAC_dma_control_init(synopGMACdevice * gmacdev, u32 init_value);
1326 void synopGMAC_wd_enable(synopGMACdevice * gmacdev);
1327 void synopGMAC_wd_disable(synopGMACdevice * gmacdev);
1328 void synopGMAC_jab_enable(synopGMACdevice * gmacdev);
1329 void synopGMAC_jab_disable(synopGMACdevice * gmacdev);
1330 void synopGMAC_frame_burst_enable(synopGMACdevice * gmacdev);
1331 void synopGMAC_frame_burst_disable(synopGMACdevice * gmacdev);
1332 void synopGMAC_jumbo_frame_enable(synopGMACdevice * gmacdev);
1333 void synopGMAC_jumbo_frame_disable(synopGMACdevice * gmacdev);
1334 void synopGMAC_select_gmii(synopGMACdevice * gmacdev);
1335 void synopGMAC_select_mii(synopGMACdevice * gmacdev);
1336 void synopGMAC_rx_own_enable(synopGMACdevice * gmacdev);
1337 void synopGMAC_rx_own_disable(synopGMACdevice * gmacdev);
1338 void synopGMAC_loopback_on(synopGMACdevice * gmacdev);
1339 void synopGMAC_loopback_off(synopGMACdevice * gmacdev);
1340 void synopGMAC_set_full_duplex(synopGMACdevice * gmacdev);
1341 void synopGMAC_set_half_duplex(synopGMACdevice * gmacdev);
1342 void synopGMAC_retry_enable(synopGMACdevice * gmacdev);
1343 void synopGMAC_retry_disable(synopGMACdevice * gmacdev);
1344 void synopGMAC_pad_crc_strip_enable(synopGMACdevice * gmacdev);
1345 void synopGMAC_pad_crc_strip_disable(synopGMACdevice * gmacdev);
1346 void synopGMAC_back_off_limit(synopGMACdevice * gmacdev, u32 value);
1347 void synopGMAC_deferral_check_enable(synopGMACdevice * gmacdev);
1348 void synopGMAC_deferral_check_disable(synopGMACdevice * gmacdev);
1349 void synopGMAC_rx_enable(synopGMACdevice * gmacdev);
1350 void synopGMAC_rx_disable(synopGMACdevice * gmacdev);
1351 void synopGMAC_tx_enable(synopGMACdevice * gmacdev);
1352 void synopGMAC_tx_disable(synopGMACdevice * gmacdev);
1353 void synopGMAC_frame_filter_enable(synopGMACdevice * gmacdev);
1354 void synopGMAC_frame_filter_disable(synopGMACdevice * gmacdev);
1355 void synopGMAC_write_hash_table_high(synopGMACdevice * gmacdev, u32 data);
1356 void synopGMAC_write_hash_table_low(synopGMACdevice * gmacdev, u32 data);
1357 void synopGMAC_hash_perfect_filter_enable(synopGMACdevice * gmacdev);
1358 void synopGMAC_Hash_filter_only_enable(synopGMACdevice * gmacdev);
1359 void synopGMAC_src_addr_filter_enable(synopGMACdevice * gmacdev);
1360 void synopGMAC_src_addr_filter_disable(synopGMACdevice * gmacdev);
1361 void synopGMAC_dst_addr_filter_inverse(synopGMACdevice * gmacdev);
1362 void synopGMAC_dst_addr_filter_normal(synopGMACdevice * gmacdev);
1363 void synopGMAC_set_pass_control(synopGMACdevice * gmacdev,u32 passcontrol);
1364 void synopGMAC_broadcast_enable(synopGMACdevice * gmacdev);
1365 void synopGMAC_broadcast_disable(synopGMACdevice * gmacdev);
1366 void synopGMAC_multicast_enable(synopGMACdevice * gmacdev);
1367 void synopGMAC_multicast_disable(synopGMACdevice * gmacdev);
1368 void synopGMAC_multicast_hash_filter_enable(synopGMACdevice * gmacdev);
1369 void synopGMAC_multicast_hash_filter_disable(synopGMACdevice * gmacdev);
1370 void synopGMAC_promisc_enable(synopGMACdevice * gmacdev);
1371 void synopGMAC_promisc_disable(synopGMACdevice * gmacdev);
1372 void synopGMAC_unicast_hash_filter_enable(synopGMACdevice * gmacdev);
1373 void synopGMAC_unicast_hash_filter_disable(synopGMACdevice * gmacdev);
1374 void synopGMAC_unicast_pause_frame_detect_enable(synopGMACdevice * gmacdev);
1375 void synopGMAC_unicast_pause_frame_detect_disable(synopGMACdevice * gmacdev);
1376 void synopGMAC_rx_flow_control_enable(synopGMACdevice * gmacdev);
1377 void synopGMAC_rx_flow_control_disable(synopGMACdevice * gmacdev);
1378 void synopGMAC_tx_flow_control_enable(synopGMACdevice * gmacdev);
1379 void synopGMAC_tx_flow_control_disable(synopGMACdevice * gmacdev);
1380 void synopGMAC_tx_activate_flow_control(synopGMACdevice * gmacdev);
1381 void synopGMAC_tx_deactivate_flow_control(synopGMACdevice * gmacdev);
1382 void synopGMAC_pause_control(synopGMACdevice *gmacdev);
1383 s32 synopGMAC_mac_init(synopGMACdevice * gmacdev);
1384 s32 synopGMAC_check_phy_init (synopGMACdevice * gmacdev);
1385 s32 synopGMAC_set_mac_addr(synopGMACdevice *gmacdev, u32 MacHigh, u32 MacLow, u8 *MacAddr);
1386 s32 synopGMAC_get_mac_addr(synopGMACdevice *gmacdev, u32 MacHigh, u32 MacLow, u8 *MacAddr);
1387 s32 synopGMAC_attach (synopGMACdevice * gmacdev, u32 macBase, u32 dmaBase, u32 phyBase);
1388 void synopGMAC_rx_desc_init_ring(DmaDesc *desc, bool last_ring_desc);
1389 void synopGMAC_tx_desc_init_ring(DmaDesc *desc, bool last_ring_desc);
1390 void synopGMAC_rx_desc_init_chain(DmaDesc * desc);
1391 void synopGMAC_tx_desc_init_chain(DmaDesc * desc);
1392 s32 synopGMAC_init_tx_rx_desc_queue(synopGMACdevice *gmacdev);
1393 void synopGMAC_init_rx_desc_base(synopGMACdevice *gmacdev);
1394 void synopGMAC_init_tx_desc_base(synopGMACdevice *gmacdev);
1395 void synopGMAC_set_owner_dma(DmaDesc *desc);
1396 void synopGMAC_set_desc_sof(DmaDesc *desc);
1397 void synopGMAC_set_desc_eof(DmaDesc *desc);
1398 bool synopGMAC_is_sof_in_rx_desc(DmaDesc *desc);
1399 bool synopGMAC_is_eof_in_rx_desc(DmaDesc *desc);
1400 bool synopGMAC_is_da_filter_failed(DmaDesc *desc);
1401 bool synopGMAC_is_sa_filter_failed(DmaDesc *desc);
1402 bool synopGMAC_is_desc_owned_by_dma(DmaDesc *desc);
1403 u32 synopGMAC_get_rx_desc_frame_length(u32 status);
1404 bool synopGMAC_is_desc_valid(u32 status);
1405 bool synopGMAC_is_desc_empty(DmaDesc *desc);
1406 bool synopGMAC_is_rx_desc_valid(u32 status);
1407 bool synopGMAC_is_tx_aborted(u32 status);
1408 bool synopGMAC_is_tx_carrier_error(u32 status);
1409 u32 synopGMAC_get_tx_collision_count(u32 status);
1410 u32 synopGMAC_is_exc_tx_collisions(u32 status);
1411 bool synopGMAC_is_rx_frame_damaged(u32 status);
1412 bool synopGMAC_is_rx_frame_collision(u32 status);
1413 bool synopGMAC_is_rx_crc(u32 status);
1414 bool synopGMAC_is_frame_dribbling_errors(u32 status);
1415 bool synopGMAC_is_rx_frame_length_errors(u32 status);
1416 bool synopGMAC_is_last_rx_desc(synopGMACdevice * gmacdev,DmaDesc *desc);
1417 bool synopGMAC_is_last_tx_desc(synopGMACdevice * gmacdev,DmaDesc *desc);
1418 bool synopGMAC_is_rx_desc_chained(DmaDesc * desc);
1419 bool synopGMAC_is_tx_desc_chained(DmaDesc * desc);
1420 void synopGMAC_get_desc_data(DmaDesc * desc, u32 * Status, u32 * Buffer1, u32 * Length1, u32 * Data1);
1421 
1422 s32 synopGMAC_get_tx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u32 * Data1, u32 * Ext_Status, u32 * Time_Stamp_High, u32 * Time_Stamp_low);
1423 
1424 s32 synopGMAC_set_tx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u32 Data1, u32 offload_needed, u32 ts);
1425 s32 synopGMAC_set_rx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u32 Data1);
1426 
1427 s32 synopGMAC_get_rx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u32 * Data1, u32 * Ext_Status, u32 * Time_Stamp_High, u32 * Time_Stamp_low);
1428 
1429 void synopGMAC_clear_interrupt(synopGMACdevice *gmacdev);
1430 u32 synopGMAC_get_interrupt_type(synopGMACdevice *gmacdev);
1431 u32 synopGMAC_get_interrupt_mask(synopGMACdevice *gmacdev);
1432 void synopGMAC_enable_interrupt(synopGMACdevice *gmacdev, u32 interrupts);
1433 void synopGMAC_disable_interrupt_all(synopGMACdevice *gmacdev);
1434 void synopGMAC_disable_interrupt(synopGMACdevice *gmacdev, u32 interrupts);
1435 void synopGMAC_enable_dma_rx(synopGMACdevice * gmacdev);
1436 void synopGMAC_enable_dma_tx(synopGMACdevice * gmacdev);
1437 void synopGMAC_resume_dma_tx(synopGMACdevice * gmacdev);
1438 void synopGMAC_resume_dma_rx(synopGMACdevice * gmacdev);
1439 void synopGMAC_take_desc_ownership(DmaDesc * desc);
1440 void synopGMAC_take_desc_ownership_rx(synopGMACdevice * gmacdev);
1441 void synopGMAC_take_desc_ownership_tx(synopGMACdevice * gmacdev);
1442 void synopGMAC_disable_dma_tx(synopGMACdevice * gmacdev);
1443 void synopGMAC_disable_dma_rx(synopGMACdevice * gmacdev);
1444 /******Following APIs are valid only for Enhanced Descriptor from 3.50a release onwards*******/
1445 bool synopGMAC_is_ext_status(synopGMACdevice *gmacdev,u32 status);
1446 bool synopGMAC_ES_is_IP_header_error(synopGMACdevice *gmacdev,u32 ext_status);
1447 bool synopGMAC_ES_is_rx_checksum_bypassed(synopGMACdevice *gmacdev,u32 ext_status);
1448 bool synopGMAC_ES_is_IP_payload_error(synopGMACdevice *gmacdev,u32 ext_status);
1449 /*******************PMT APIs***************************************/
1450 void synopGMAC_pmt_int_enable(synopGMACdevice *gmacdev);
1451 void synopGMAC_pmt_int_disable(synopGMACdevice *gmacdev);
1452 void synopGMAC_power_down_enable(synopGMACdevice *gmacdev);
1453 void synopGMAC_power_down_disable(synopGMACdevice *gmacdev);
1454 void synopGMAC_enable_pmt_interrupt(synopGMACdevice *gmacdev);
1455 void synopGMAC_disable_pmt_interrupt(synopGMACdevice *gmacdev);
1456 void synopGMAC_magic_packet_enable(synopGMACdevice *gmacdev);
1457 void synopGMAC_magic_packet_disable(synopGMACdevice *gmacdev);
1458 void synopGMAC_wakeup_frame_enable(synopGMACdevice *gmacdev);
1459 void synopGMAC_pmt_unicast_enable(synopGMACdevice *gmacdev);
1460 bool synopGMAC_is_magic_packet_received(synopGMACdevice *gmacdev);
1461 bool synopGMAC_is_wakeup_frame_received(synopGMACdevice *gmacdev);
1462 void synopGMAC_write_wakeup_frame_register(synopGMACdevice *gmacdev, u32 * filter_contents);
1463 
1464 /*******************Ip checksum offloading APIs***************************************/
1465 void synopGMAC_enable_rx_chksum_offload(synopGMACdevice *gmacdev);
1466 void synopGMAC_disable_rx_chksum_offload(synopGMACdevice *gmacdev);
1467 void synopGMAC_rx_tcpip_chksum_drop_enable(synopGMACdevice *gmacdev);
1468 void synopGMAC_rx_tcpip_chksum_drop_disable(synopGMACdevice *gmacdev);
1469 u32 synopGMAC_is_rx_checksum_error(synopGMACdevice *gmacdev, u32 status);
1470 bool synopGMAC_is_tx_ipv4header_checksum_error(synopGMACdevice *gmacdev, u32 status);
1471 bool synopGMAC_is_tx_payload_checksum_error(synopGMACdevice *gmacdev, u32 status);
1472 void synopGMAC_tx_checksum_offload_bypass(synopGMACdevice *gmacdev, DmaDesc *desc);
1473 void synopGMAC_tx_checksum_offload_ipv4hdr(synopGMACdevice *gmacdev, DmaDesc *desc);
1474 void synopGMAC_tx_checksum_offload_tcponly(synopGMACdevice *gmacdev, DmaDesc *desc);
1475 void synopGMAC_tx_checksum_offload_tcp_pseudo(synopGMACdevice *gmacdev, DmaDesc *desc);
1476 
1477 
1478 // For testing --ya
1479 void synopGMAC_src_addr_insert_enable(synopGMACdevice * gmacdev);
1480 void synopGMAC_src_addr_insert_disable(synopGMACdevice * gmacdev);
1481 void synopGMAC_src_addr_replace_enable(synopGMACdevice * gmacdev);
1482 void synopGMAC_src_addr_replace_disable(synopGMACdevice * gmacdev);
1483 
1484 void synopGMAC_svlan_insertion_enable(synopGMACdevice * gmacdev, u16 vlantag);
1485 void synopGMAC_cvlan_insertion_enable(synopGMACdevice * gmacdev, u16 vlantag);
1486 void synopGMAC_svlan_replace_enable(synopGMACdevice * gmacdev, u16 vlantag);
1487 void synopGMAC_cvlan_replace_enable(synopGMACdevice * gmacdev, u16 vlantag);
1488 void synopGMAC_vlan_deletion_enable(synopGMACdevice * gmacdev);
1489 void synopGMAC_vlan_no_act_enable(synopGMACdevice * gmacdev);
1490 
1491 void synopGMAC_set_crc_replacement(synopGMACdevice * gmacdev);
1492 void synopGMAC_clr_crc_replacement(synopGMACdevice * gmacdev);
1493 
1494 void synopGMAC_enable_under_size_pkt(synopGMACdevice * gmacdev);
1495 void synopGMAC_disable_under_size_pkt(synopGMACdevice * gmacdev);
1496 
1497 void synopGMAC_enable_crc_err_pkt(synopGMACdevice * gmacdev);
1498 void synopGMAC_disable_crc_err_pkt(synopGMACdevice * gmacdev);
1499 
1500 #endif /* End of file */
s32
signed int s32
Define 32-bit signed data type.
Definition: synopGMAC_plat.h:55
GmacTSControlReg
GmacTSControlReg
IEEE 1588-2008 is the optional module to support Ethernet frame time stamping.
Definition: synopGMAC_Dev.h:1194
u8
unsigned char u8
Define 8-bit unsigned data type.
Definition: synopGMAC_plat.h:52
sk_buff
Definition: synopGMAC_Dev.h:121
u16
unsigned short u16
Define 16-bit unsigned data type.
Definition: synopGMAC_plat.h:53
net_device_stats
Definition: synopGMAC_Dev.h:127
u32
unsigned int u32
Define 32-bit unsigned data type.
Definition: synopGMAC_plat.h:54
synopGMAC_plat.h
This file serves as the wrapper for the platform/OS dependent functions It is needed to modify these ...
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