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10 years, 5 months ago.
How critical is the length of the PCB-traces from mbed to an RJ45 connector?
Hi, I am designing a PCB that contains an mbed board and it needs to communicate via ethernet. I have read that the trace-length on the PCB may be critical, that they need to be the same length for RD-, RD+, TX- and TX+ Has anybody experience with this, and how criticial it actually is?
Furthermore I would like to drive the 2 LED's on the connector, and I found this code on the forum:
/* driving Ethernet Jack LED's */ define FIO1PIN (*(unsigned long*)0x2009C034UL) DigitalOut Green(p30), Yellow(p29); leds are on pins 29 and 30 Green = !(FIO1PIN&(1<<25)); link Yellow= !(FIO1PIN&(1<<26));speed
Anyone tried this?
Regards, Willem Braat
3 Answers
10 years, 5 months ago.
I belive that the track length is not too critical, as long as there is simmilar length, impeadance, capacitance,
You should be OK, as I did get mine to work,
But It took some tinkering, and the MBED uses a slightly different PHY chip to mine.
Hope that helps
Ceri
10 years, 5 months ago.
Hi Cleri, thanks for the quick answer.
The data on my traces are:
RD+ 14.164mm RD- 12.458mm TD+ 19.565mm TD- 15.434mm
Would this be ok?
Regards, WIllem
10 years, 5 months ago.
There are several Rules that you should keep in mind when routing Ethernet traces on your PCB. Shorter is better. Usually the rules say you should have not more than 25mm of traces between the magnetic module and the RJ45-jack. If you have an RJ45-jack with integrated magnetics, this does not directly apply. On the other hand, you definately must have the PHY as close as possible to the magnetics. I'd say if you stay below 20mm you should be OK. Single trace impedance should be lower than 50 Ohm and the differential impedance should be 100 Ohm. Depending on your pcb layer-stack, 0.25mm trace with and trace seperation should result in something around 100 Ohm impedance. There are a lot of free calculators on the web, if your layout-software can not directly calculate the track impedances. The lenght-difference should be as small as possible too. I usually define a rule so the two traces of a pair stay within 2.54mm of eachother, but that is just my guess as i have not seen the allowable difference specified in a datasheet. You could calculate the allowed difference in lenght by using the timing requirements, but for now, i've managed just fine with my 2.54mm guess. From my experience with ethernet traces and components the most critical part of the layout always was the (R)MII-Interface to the PHY and the PHY-clock (usually 25MHz). They seem to give a lot more EMC-problems compared to the differential ethernet-signals. If you have the room, it's always wise to put some serial resistors (33 Ohm usually is enough) in these interfaces (near the signal source) to have some way to control and improve signal integrity.
This code works for the mbed 1768 (without the typo's). It basically reads two gpio pins which are connected to the PHY and copies the inverse to two digital io pins called green and yellow which have been named after the colours of the leds in the magjack to which they are connected. Depending on whether the leds are connected to Vcc or gnd you need to invert or not.
posted by Ad van der Weiden 07 Mar 2014Hi Ad, sorry for my ignorance, but what does & stand for? Regards, Willem
posted by Willem Braat 03 May 2014