Wilson Tang / max14724

8:4 Matrix Multiplexer

Fork of max14661 by Maxim Integrated

This is an untested driver for the MAX14724.

max14724.cpp@10:5a3720e6e017, 2015-04-27 (annotated)

Committer:
wt8008
Date:
Mon Apr 27 17:24:52 2015 +0000
Revision:
10:5a3720e6e017
Initial Import

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wt8008 10:5a3720e6e017 1 /******************************************************************//**
wt8008 10:5a3720e6e017 2 * @file max14724.cpp
wt8008 10:5a3720e6e017 3 *
wt8008 10:5a3720e6e017 4 * @author Wilson Tang
wt8008 10:5a3720e6e017 5 *
wt8008 10:5a3720e6e017 6 * @version 1.0
wt8008 10:5a3720e6e017 7 *
wt8008 10:5a3720e6e017 8 * Started: 22APR15
wt8008 10:5a3720e6e017 9 *
wt8008 10:5a3720e6e017 10 * Updated:
wt8008 10:5a3720e6e017 11 *
wt8008 10:5a3720e6e017 12 * @brief Source file for MAX14724 class
wt8008 10:5a3720e6e017 13 *
wt8008 10:5a3720e6e017 14 * http://www.maximintegrated.com/max14724
wt8008 10:5a3720e6e017 15 *
wt8008 10:5a3720e6e017 16 ***********************************************************************
wt8008 10:5a3720e6e017 17 *
wt8008 10:5a3720e6e017 18 * @copyright
wt8008 10:5a3720e6e017 19 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
wt8008 10:5a3720e6e017 20 *
wt8008 10:5a3720e6e017 21 * Permission is hereby granted, free of charge, to any person obtaining a
wt8008 10:5a3720e6e017 22 * copy of this software and associated documentation files (the "Software"),
wt8008 10:5a3720e6e017 23 * to deal in the Software without restriction, including without limitation
wt8008 10:5a3720e6e017 24 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
wt8008 10:5a3720e6e017 25 * and/or sell copies of the Software, and to permit persons to whom the
wt8008 10:5a3720e6e017 26 * Software is furnished to do so, subject to the following conditions:
wt8008 10:5a3720e6e017 27 *
wt8008 10:5a3720e6e017 28 * The above copyright notice and this permission notice shall be included
wt8008 10:5a3720e6e017 29 * in all copies or substantial portions of the Software.
wt8008 10:5a3720e6e017 30 *
wt8008 10:5a3720e6e017 31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
wt8008 10:5a3720e6e017 32 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
wt8008 10:5a3720e6e017 33 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
wt8008 10:5a3720e6e017 34 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
wt8008 10:5a3720e6e017 35 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
wt8008 10:5a3720e6e017 36 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
wt8008 10:5a3720e6e017 37 * OTHER DEALINGS IN THE SOFTWARE.
wt8008 10:5a3720e6e017 38 *
wt8008 10:5a3720e6e017 39 * Except as contained in this notice, the name of Maxim Integrated
wt8008 10:5a3720e6e017 40 * Products, Inc. shall not be used except as stated in the Maxim Integrated
wt8008 10:5a3720e6e017 41 * Products, Inc. Branding Policy.
wt8008 10:5a3720e6e017 42 *
wt8008 10:5a3720e6e017 43 * The mere transfer of this software does not imply any licenses
wt8008 10:5a3720e6e017 44 * of trade secrets, proprietary technology, copyrights, patents,
wt8008 10:5a3720e6e017 45 * trademarks, maskwork rights, or any other form of intellectual
wt8008 10:5a3720e6e017 46 * property whatsoever. Maxim Integrated Products, Inc. retains all
wt8008 10:5a3720e6e017 47 * ownership rights.
wt8008 10:5a3720e6e017 48 **********************************************************************/
wt8008 10:5a3720e6e017 49
wt8008 10:5a3720e6e017 50
wt8008 10:5a3720e6e017 51 #include "max14724.h"
wt8008 10:5a3720e6e017 52
wt8008 10:5a3720e6e017 53
wt8008 10:5a3720e6e017 54 /**********************************************************//**
wt8008 10:5a3720e6e017 55 * Constructor for Max14724 Class
wt8008 10:5a3720e6e017 56 *
wt8008 10:5a3720e6e017 57 * On Entry:
wt8008 10:5a3720e6e017 58 * @param[in] sda - sda pin of I2C bus
wt8008 10:5a3720e6e017 59 * @param[in] scl - scl pin of I2C bus
wt8008 10:5a3720e6e017 60 * @param[in] i2c_adrs - 7-bit slave address of MAX14724
wt8008 10:5a3720e6e017 61 *
wt8008 10:5a3720e6e017 62 * On Exit:
wt8008 10:5a3720e6e017 63 * @return none
wt8008 10:5a3720e6e017 64 *
wt8008 10:5a3720e6e017 65 * Example:
wt8008 10:5a3720e6e017 66 * @code
wt8008 10:5a3720e6e017 67 *
wt8008 10:5a3720e6e017 68 * //declare mux object
wt8008 10:5a3720e6e017 69 * Max14724 mux(D14, D15, MAX14724_I2C_ADRS0);
wt8008 10:5a3720e6e017 70 *
wt8008 10:5a3720e6e017 71 * @endcode
wt8008 10:5a3720e6e017 72 **************************************************************/
wt8008 10:5a3720e6e017 73 Max14724::Max14724(PinName sda, PinName scl, max14724_i2c_adrs_t i2c_adrs) :
wt8008 10:5a3720e6e017 74 I2C(sda, scl)
wt8008 10:5a3720e6e017 75 {
wt8008 10:5a3720e6e017 76 w_adrs = (i2c_adrs << 1);
wt8008 10:5a3720e6e017 77 r_adrs = (w_adrs | 0x01);
wt8008 10:5a3720e6e017 78 }
wt8008 10:5a3720e6e017 79
wt8008 10:5a3720e6e017 80
wt8008 10:5a3720e6e017 81 /******************************************************************//**
wt8008 10:5a3720e6e017 82 * Writes given commands to CMD_A, CMD_B, CMD_C, and CMD_D
wt8008 10:5a3720e6e017 83 *
wt8008 10:5a3720e6e017 84 * On Entry:
wt8008 10:5a3720e6e017 85 * @param[in] cmdA - command for CMD_A
wt8008 10:5a3720e6e017 86 * @param[in] cmdB - command for CMD_B
wt8008 10:5a3720e6e017 87 * @param[in] cmdC - command for CMD_C
wt8008 10:5a3720e6e017 88 * @param[in] cmdD - command for CMD_D
wt8008 10:5a3720e6e017 89 *
wt8008 10:5a3720e6e017 90 * On Exit:
wt8008 10:5a3720e6e017 91 * @return return value = 0 on success, non-0 on failure
wt8008 10:5a3720e6e017 92 *
wt8008 10:5a3720e6e017 93 * Example:
wt8008 10:5a3720e6e017 94 * @code
wt8008 10:5a3720e6e017 95 *
wt8008 10:5a3720e6e017 96 * //declare mux object
wt8008 10:5a3720e6e017 97 * Max14724 mux(D14, D15, MAX14724_I2C_ADRS0);
wt8008 10:5a3720e6e017 98 *
wt8008 10:5a3720e6e017 99 * uint16_t rtn_val;
wt8008 10:5a3720e6e017 100 *
wt8008 10:5a3720e6e017 101 * rtn_val = mux.wrt_cmd_registers(DISABLE_BANK, DISABLE_BANK, DISABLE_BANK, DISABLE_BANK);
wt8008 10:5a3720e6e017 102 *
wt8008 10:5a3720e6e017 103 * @endcode
wt8008 10:5a3720e6e017 104 **********************************************************************/
wt8008 10:5a3720e6e017 105 uint16_t Max14724::wrt_cmd_registers(max14724_cmds_t cmdA, max14724_cmds_t cmdB, max14724_cmds_t cmdC, max14724_cmds_t cmdD)
wt8008 10:5a3720e6e017 106 {
wt8008 10:5a3720e6e017 107 uint8_t data[3];
wt8008 10:5a3720e6e017 108 uint8_t data_length = 0;
wt8008 10:5a3720e6e017 109 uint16_t rtn_val = 1;
wt8008 10:5a3720e6e017 110
wt8008 10:5a3720e6e017 111 //build packet
wt8008 10:5a3720e6e017 112 data[data_length++] = CMD0;
wt8008 10:5a3720e6e017 113 data[data_length++] = (cmdB & 0x0F) << 4 | (cmdA & 0x0F);
wt8008 10:5a3720e6e017 114 data[data_length++] = (cmdD & 0x0F) << 4 | (cmdC & 0x0F);
wt8008 10:5a3720e6e017 115
wt8008 10:5a3720e6e017 116 rtn_val = write(w_adrs,(const char*) data, data_length);
wt8008 10:5a3720e6e017 117
wt8008 10:5a3720e6e017 118 return(rtn_val);
wt8008 10:5a3720e6e017 119 }
wt8008 10:5a3720e6e017 120
wt8008 10:5a3720e6e017 121
wt8008 10:5a3720e6e017 122 /******************************************************************//**
wt8008 10:5a3720e6e017 123 * Writes bankA, bankB, bankC, and bankD to coresponding shadow registers
wt8008 10:5a3720e6e017 124 *
wt8008 10:5a3720e6e017 125 * On Entry:
wt8008 10:5a3720e6e017 126 * @param[in] bankA - binary representation of switch states
wt8008 10:5a3720e6e017 127 * @param[in] bankB - binary representation of switch states
wt8008 10:5a3720e6e017 128 * @param[in] bankC - binary representation of switch states
wt8008 10:5a3720e6e017 129 * @param[in] bankD - binary representation of switch states
wt8008 10:5a3720e6e017 130 *
wt8008 10:5a3720e6e017 131 * On Exit:
wt8008 10:5a3720e6e017 132 * @return return value = 0 on success, non-0 on failure
wt8008 10:5a3720e6e017 133 *
wt8008 10:5a3720e6e017 134 * Example:
wt8008 10:5a3720e6e017 135 * @code
wt8008 10:5a3720e6e017 136 *
wt8008 10:5a3720e6e017 137 * //declare mux object
wt8008 10:5a3720e6e017 138 * Max14724 mux(D14, D15, MAX14724_I2C_ADRS0);
wt8008 10:5a3720e6e017 139 *
wt8008 10:5a3720e6e017 140 * uint16_t bankA = (SW03 | SW02); //example only
wt8008 10:5a3720e6e017 141 * uint16_t bankB = (SW05 | SW04);
wt8008 10:5a3720e6e017 142 * uint16_t bankC = SW07;
wt8008 10:5a3720e6e017 143 * uint16_t bankD = SW08;
wt8008 10:5a3720e6e017 144 * uint16_t rtn_val;
wt8008 10:5a3720e6e017 145 *
wt8008 10:5a3720e6e017 146 * //wite shadow registers
wt8008 10:5a3720e6e017 147 * rtn_val = mux.wrt_shadow_registers(bankA, bankB, bankC, bankD);
wt8008 10:5a3720e6e017 148 *
wt8008 10:5a3720e6e017 149 * @endcode
wt8008 10:5a3720e6e017 150 **********************************************************************/
wt8008 10:5a3720e6e017 151 uint16_t Max14724::wrt_shadow_registers(uint8_t bankA, uint8_t bankB, uint8_t bankC, uint8_t bankD)
wt8008 10:5a3720e6e017 152 {
wt8008 10:5a3720e6e017 153 uint8_t data[5];
wt8008 10:5a3720e6e017 154 uint8_t data_length = 0;
wt8008 10:5a3720e6e017 155 uint16_t rtn_val = 1;
wt8008 10:5a3720e6e017 156
wt8008 10:5a3720e6e017 157 data[data_length++] = SHDW0;
wt8008 10:5a3720e6e017 158 data[data_length++] = (bankA & 0x00FF);
wt8008 10:5a3720e6e017 159 data[data_length++] = (bankB & 0x00FF);
wt8008 10:5a3720e6e017 160 data[data_length++] = (bankC & 0x00FF);
wt8008 10:5a3720e6e017 161 data[data_length++] = (bankD & 0x00FF);
wt8008 10:5a3720e6e017 162
wt8008 10:5a3720e6e017 163 rtn_val = write(w_adrs,(const char*) data, data_length);
wt8008 10:5a3720e6e017 164
wt8008 10:5a3720e6e017 165 return(rtn_val);
wt8008 10:5a3720e6e017 166 }
wt8008 10:5a3720e6e017 167
wt8008 10:5a3720e6e017 168
wt8008 10:5a3720e6e017 169 /******************************************************************//**
wt8008 10:5a3720e6e017 170 * Writes bankA, bankB, bankC, and bankD to coresponding shadow registers
wt8008 10:5a3720e6e017 171 *
wt8008 10:5a3720e6e017 172 * On Entry:
wt8008 10:5a3720e6e017 173 * @param[in] bankA - binary representation of switch states
wt8008 10:5a3720e6e017 174 * @param[in] bankB - binary representation of switch states
wt8008 10:5a3720e6e017 175 * @param[in] bankC - binary representation of switch states
wt8008 10:5a3720e6e017 176 * @param[in] bankD - binary representation of switch states
wt8008 10:5a3720e6e017 177 *
wt8008 10:5a3720e6e017 178 * On Exit:
wt8008 10:5a3720e6e017 179 * @return return value = 0 on success, non-0 on failure
wt8008 10:5a3720e6e017 180 *
wt8008 10:5a3720e6e017 181 * Example:
wt8008 10:5a3720e6e017 182 * @code
wt8008 10:5a3720e6e017 183 *
wt8008 10:5a3720e6e017 184 * //declare mux object
wt8008 10:5a3720e6e017 185 * Max14724 mux(D14, D15, MAX14724_I2C_ADRS0);
wt8008 10:5a3720e6e017 186 *
wt8008 10:5a3720e6e017 187 * uint8_t bankA = (SW03 | SW02); //example only
wt8008 10:5a3720e6e017 188 * uint8_t bankB = (SW05 | SW04);
wt8008 10:5a3720e6e017 189 * uint8_t bankC = SW07;
wt8008 10:5a3720e6e017 190 * uint8_t bankD = SW08;
wt8008 10:5a3720e6e017 191 * uint16_t rtn_val;
wt8008 10:5a3720e6e017 192 *
wt8008 10:5a3720e6e017 193 * //wite shadow registers
wt8008 10:5a3720e6e017 194 * rtn_val = mux.wrt_shadow_registers(bankA, bankB, bankC, bankD);
wt8008 10:5a3720e6e017 195 *
wt8008 10:5a3720e6e017 196 * @endcode
wt8008 10:5a3720e6e017 197 **********************************************************************/
wt8008 10:5a3720e6e017 198 uint16_t Max14724::wrt_dir_registers(uint8_t bankA, uint8_t bankB, uint8_t bankC, uint8_t bankD)
wt8008 10:5a3720e6e017 199 {
wt8008 10:5a3720e6e017 200 uint8_t data[5];
wt8008 10:5a3720e6e017 201 uint8_t data_length = 0;
wt8008 10:5a3720e6e017 202 uint16_t rtn_val = 1;
wt8008 10:5a3720e6e017 203
wt8008 10:5a3720e6e017 204 data[data_length++] = DIR0;
wt8008 10:5a3720e6e017 205 data[data_length++] = (bankA & 0x00FF);
wt8008 10:5a3720e6e017 206 data[data_length++] = (bankB & 0x00FF);
wt8008 10:5a3720e6e017 207 data[data_length++] = (bankC & 0x00FF);
wt8008 10:5a3720e6e017 208 data[data_length++] = (bankD & 0x00FF);
wt8008 10:5a3720e6e017 209
wt8008 10:5a3720e6e017 210 rtn_val = write(w_adrs,(const char*) data, data_length);
wt8008 10:5a3720e6e017 211
wt8008 10:5a3720e6e017 212 return(rtn_val);
wt8008 10:5a3720e6e017 213 }
wt8008 10:5a3720e6e017 214
wt8008 10:5a3720e6e017 215
wt8008 10:5a3720e6e017 216 /******************************************************************//**
wt8008 10:5a3720e6e017 217 * Writes bankA, bankB, bankC, and bankD to coresponding shadow register and then
wt8008 10:5a3720e6e017 218 * issues copy command for both banks
wt8008 10:5a3720e6e017 219 *
wt8008 10:5a3720e6e017 220 * On Entry:
wt8008 10:5a3720e6e017 221 * @param[in] bankA - binary representation of switch states
wt8008 10:5a3720e6e017 222 * @param[in] bankB - binary representation of switch states
wt8008 10:5a3720e6e017 223 * @param[in] bankC - binary representation of switch states
wt8008 10:5a3720e6e017 224 * @param[in] bankD - binary representation of switch states
wt8008 10:5a3720e6e017 225 *
wt8008 10:5a3720e6e017 226 * On Exit:
wt8008 10:5a3720e6e017 227 * @return return value = 0 on success, non-0 on failure
wt8008 10:5a3720e6e017 228 *
wt8008 10:5a3720e6e017 229 * Example:
wt8008 10:5a3720e6e017 230 * @code
wt8008 10:5a3720e6e017 231 *
wt8008 10:5a3720e6e017 232 * //declare mux object
wt8008 10:5a3720e6e017 233 * Max14724 mux(D14, D15, MAX14724_I2C_ADRS0);
wt8008 10:5a3720e6e017 234 *
wt8008 10:5a3720e6e017 235 * uint16_t bankA = (SW12 | SW02); //example only
wt8008 10:5a3720e6e017 236 * uint16_t bankB = (SW11 | SW01);
wt8008 10:5a3720e6e017 237 * uint16_t bankC = SW07;
wt8008 10:5a3720e6e017 238 * uint16_t bankD = SW08;
wt8008 10:5a3720e6e017 239 * uint16_t rtn_val;
wt8008 10:5a3720e6e017 240 *
wt8008 10:5a3720e6e017 241 * //wite shadow registers
wt8008 10:5a3720e6e017 242 * rtn_val = mux.set_switches(bankA, bankB, bankC, bankD);
wt8008 10:5a3720e6e017 243 *
wt8008 10:5a3720e6e017 244 * @endcode
wt8008 10:5a3720e6e017 245 **********************************************************************/
wt8008 10:5a3720e6e017 246 uint16_t Max14724::set_switches(uint8_t bankA, uint8_t bankB, uint8_t bankC, uint8_t bankD)
wt8008 10:5a3720e6e017 247 {
wt8008 10:5a3720e6e017 248 uint8_t data[7];
wt8008 10:5a3720e6e017 249 uint8_t data_length = 0;
wt8008 10:5a3720e6e017 250 uint16_t rtn_val = 1;
wt8008 10:5a3720e6e017 251
wt8008 10:5a3720e6e017 252 data[data_length++] = SHDW0;
wt8008 10:5a3720e6e017 253 data[data_length++] = (bankA & 0x00FF);
wt8008 10:5a3720e6e017 254 data[data_length++] = (bankB & 0x00FF);
wt8008 10:5a3720e6e017 255 data[data_length++] = (bankC & 0x00FF);
wt8008 10:5a3720e6e017 256 data[data_length++] = (bankD & 0x00FF);
wt8008 10:5a3720e6e017 257 data[data_length++] = ((COPY_SHADOW << 4) | COPY_SHADOW);
wt8008 10:5a3720e6e017 258 data[data_length++] = ((COPY_SHADOW << 4) | COPY_SHADOW);
wt8008 10:5a3720e6e017 259
wt8008 10:5a3720e6e017 260 rtn_val = write(w_adrs,(const char*) data, data_length);
wt8008 10:5a3720e6e017 261
wt8008 10:5a3720e6e017 262 return(rtn_val);
wt8008 10:5a3720e6e017 263 }
wt8008 10:5a3720e6e017 264
wt8008 10:5a3720e6e017 265
wt8008 10:5a3720e6e017 266 /**********************************************************//**
wt8008 10:5a3720e6e017 267 * Reads data from direct access registers starting at DIR0 and
wt8008 10:5a3720e6e017 268 * stores it in byte array pointed at by 'data'
wt8008 10:5a3720e6e017 269 *
wt8008 10:5a3720e6e017 270 * On Entry:
wt8008 10:5a3720e6e017 271 * @param[in] data - pointer to byte array for storing data
wt8008 10:5a3720e6e017 272 *
wt8008 10:5a3720e6e017 273 * On Exit:
wt8008 10:5a3720e6e017 274 * @param[out] data - data buffer now contains data read
wt8008 10:5a3720e6e017 275 * from dir registers
wt8008 10:5a3720e6e017 276 * @return return value = 0 on success, non-0 on failure
wt8008 10:5a3720e6e017 277 *
wt8008 10:5a3720e6e017 278 * Example:
wt8008 10:5a3720e6e017 279 * @code
wt8008 10:5a3720e6e017 280 *
wt8008 10:5a3720e6e017 281 * //declare mux object
wt8008 10:5a3720e6e017 282 * Max14724 mux(D14, D15, MAX14724_I2C_ADRS0);
wt8008 10:5a3720e6e017 283 *
wt8008 10:5a3720e6e017 284 * uint16_t rtn_val;
wt8008 10:5a3720e6e017 285 * uint8_t data[4];
wt8008 10:5a3720e6e017 286 *
wt8008 10:5a3720e6e017 287 * //read direct access registers
wt8008 10:5a3720e6e017 288 * rtn_val = mux.rd_dir_registers(data);
wt8008 10:5a3720e6e017 289 *
wt8008 10:5a3720e6e017 290 * @endcode
wt8008 10:5a3720e6e017 291 **********************************************************************/
wt8008 10:5a3720e6e017 292 uint16_t Max14724::rd_dir_registers(uint8_t* data)
wt8008 10:5a3720e6e017 293 {
wt8008 10:5a3720e6e017 294 uint16_t rtn_val = 1;
wt8008 10:5a3720e6e017 295
wt8008 10:5a3720e6e017 296 data[0] = DIR0;
wt8008 10:5a3720e6e017 297
wt8008 10:5a3720e6e017 298 rtn_val = write(w_adrs,(const char*) data, 1);
wt8008 10:5a3720e6e017 299
wt8008 10:5a3720e6e017 300 if(!rtn_val) {
wt8008 10:5a3720e6e017 301 rtn_val = read(r_adrs,(char*) data, 4);
wt8008 10:5a3720e6e017 302 }
wt8008 10:5a3720e6e017 303
wt8008 10:5a3720e6e017 304 return(rtn_val);
wt8008 10:5a3720e6e017 305 }
wt8008 10:5a3720e6e017 306
wt8008 10:5a3720e6e017 307
wt8008 10:5a3720e6e017 308 /**********************************************************//**
wt8008 10:5a3720e6e017 309 * Reads data from shadow registers starting at SHDW0 and stores
wt8008 10:5a3720e6e017 310 * it in byte array pointed at by 'data'
wt8008 10:5a3720e6e017 311 *
wt8008 10:5a3720e6e017 312 * On Entry:
wt8008 10:5a3720e6e017 313 * @param[in] data - pointer to byte array for storing data
wt8008 10:5a3720e6e017 314 *
wt8008 10:5a3720e6e017 315 * On Exit:
wt8008 10:5a3720e6e017 316 * @param[out] data - data buffer now contains data read
wt8008 10:5a3720e6e017 317 * from shadow registers
wt8008 10:5a3720e6e017 318 * @return return value = 0 on success, non-0 on failure
wt8008 10:5a3720e6e017 319 *
wt8008 10:5a3720e6e017 320 * Example:
wt8008 10:5a3720e6e017 321 * @code
wt8008 10:5a3720e6e017 322 *
wt8008 10:5a3720e6e017 323 * //declare mux object
wt8008 10:5a3720e6e017 324 * Max14724 mux(D14, D15, MAX14724_I2C_ADRS0);
wt8008 10:5a3720e6e017 325 *
wt8008 10:5a3720e6e017 326 * uint16_t rtn_val;
wt8008 10:5a3720e6e017 327 * uint8_t data[4];
wt8008 10:5a3720e6e017 328 *
wt8008 10:5a3720e6e017 329 * //read shadow registers
wt8008 10:5a3720e6e017 330 * rtn_val = mux.rd_shadow_registers(data);
wt8008 10:5a3720e6e017 331 *
wt8008 10:5a3720e6e017 332 * @endcode
wt8008 10:5a3720e6e017 333 **************************************************************/
wt8008 10:5a3720e6e017 334 uint16_t Max14724::rd_shadow_registers(uint8_t* data)
wt8008 10:5a3720e6e017 335 {
wt8008 10:5a3720e6e017 336 uint16_t rtn_val = 1;
wt8008 10:5a3720e6e017 337
wt8008 10:5a3720e6e017 338 data[0] = SHDW0;
wt8008 10:5a3720e6e017 339
wt8008 10:5a3720e6e017 340 rtn_val = write(w_adrs,(const char*) data, 1);
wt8008 10:5a3720e6e017 341
wt8008 10:5a3720e6e017 342 if(!rtn_val) {
wt8008 10:5a3720e6e017 343 rtn_val = read(r_adrs,(char*) data, 4);
wt8008 10:5a3720e6e017 344 }
wt8008 10:5a3720e6e017 345
wt8008 10:5a3720e6e017 346 return(rtn_val);
wt8008 10:5a3720e6e017 347 }