mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_SDT32620B/TOOLCHAIN_ARM_STD/spix_regs.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 167:84c0a372a020 1 /*******************************************************************************
AnnaBridge 167:84c0a372a020 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
AnnaBridge 167:84c0a372a020 3 *
AnnaBridge 167:84c0a372a020 4 * Permission is hereby granted, free of charge, to any person obtaining a
AnnaBridge 167:84c0a372a020 5 * copy of this software and associated documentation files (the "Software"),
AnnaBridge 167:84c0a372a020 6 * to deal in the Software without restriction, including without limitation
AnnaBridge 167:84c0a372a020 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
AnnaBridge 167:84c0a372a020 8 * and/or sell copies of the Software, and to permit persons to whom the
AnnaBridge 167:84c0a372a020 9 * Software is furnished to do so, subject to the following conditions:
AnnaBridge 167:84c0a372a020 10 *
AnnaBridge 167:84c0a372a020 11 * The above copyright notice and this permission notice shall be included
AnnaBridge 167:84c0a372a020 12 * in all copies or substantial portions of the Software.
AnnaBridge 167:84c0a372a020 13 *
AnnaBridge 167:84c0a372a020 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
AnnaBridge 167:84c0a372a020 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
AnnaBridge 167:84c0a372a020 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
AnnaBridge 167:84c0a372a020 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
AnnaBridge 167:84c0a372a020 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
AnnaBridge 167:84c0a372a020 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
AnnaBridge 167:84c0a372a020 20 * OTHER DEALINGS IN THE SOFTWARE.
AnnaBridge 167:84c0a372a020 21 *
AnnaBridge 167:84c0a372a020 22 * Except as contained in this notice, the name of Maxim Integrated
AnnaBridge 167:84c0a372a020 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
AnnaBridge 167:84c0a372a020 24 * Products, Inc. Branding Policy.
AnnaBridge 167:84c0a372a020 25 *
AnnaBridge 167:84c0a372a020 26 * The mere transfer of this software does not imply any licenses
AnnaBridge 167:84c0a372a020 27 * of trade secrets, proprietary technology, copyrights, patents,
AnnaBridge 167:84c0a372a020 28 * trademarks, maskwork rights, or any other form of intellectual
AnnaBridge 167:84c0a372a020 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
AnnaBridge 167:84c0a372a020 30 * ownership rights.
AnnaBridge 167:84c0a372a020 31 *
AnnaBridge 167:84c0a372a020 32 * $Date: 2016-03-11 11:46:37 -0600 (Fri, 11 Mar 2016) $
AnnaBridge 167:84c0a372a020 33 * $Revision: 21839 $
AnnaBridge 167:84c0a372a020 34 *
AnnaBridge 167:84c0a372a020 35 ******************************************************************************/
AnnaBridge 167:84c0a372a020 36
AnnaBridge 167:84c0a372a020 37 #ifndef _MXC_SPIX_REGS_H_
AnnaBridge 167:84c0a372a020 38 #define _MXC_SPIX_REGS_H_
AnnaBridge 167:84c0a372a020 39
AnnaBridge 167:84c0a372a020 40 #ifdef __cplusplus
AnnaBridge 167:84c0a372a020 41 extern "C" {
AnnaBridge 167:84c0a372a020 42 #endif
AnnaBridge 167:84c0a372a020 43
AnnaBridge 167:84c0a372a020 44 #include <stdint.h>
AnnaBridge 167:84c0a372a020 45
AnnaBridge 167:84c0a372a020 46 /*
AnnaBridge 167:84c0a372a020 47 If types are not defined elsewhere (CMSIS) define them here
AnnaBridge 167:84c0a372a020 48 */
AnnaBridge 167:84c0a372a020 49 #ifndef __IO
AnnaBridge 167:84c0a372a020 50 #define __IO volatile
AnnaBridge 167:84c0a372a020 51 #endif
AnnaBridge 167:84c0a372a020 52 #ifndef __I
AnnaBridge 167:84c0a372a020 53 #define __I volatile const
AnnaBridge 167:84c0a372a020 54 #endif
AnnaBridge 167:84c0a372a020 55 #ifndef __O
AnnaBridge 167:84c0a372a020 56 #define __O volatile
AnnaBridge 167:84c0a372a020 57 #endif
AnnaBridge 167:84c0a372a020 58 #ifndef __RO
AnnaBridge 167:84c0a372a020 59 #define __RO volatile const
AnnaBridge 167:84c0a372a020 60 #endif
AnnaBridge 167:84c0a372a020 61
AnnaBridge 167:84c0a372a020 62
AnnaBridge 167:84c0a372a020 63 /*
AnnaBridge 167:84c0a372a020 64 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
AnnaBridge 167:84c0a372a020 65 access to each register in module.
AnnaBridge 167:84c0a372a020 66 */
AnnaBridge 167:84c0a372a020 67
AnnaBridge 167:84c0a372a020 68 /* Offset Register Description
AnnaBridge 167:84c0a372a020 69 ============= ============================================================================ */
AnnaBridge 167:84c0a372a020 70 typedef struct {
AnnaBridge 167:84c0a372a020 71 __IO uint32_t master_cfg; /* 0x0000 SPIX Master Configuration */
AnnaBridge 167:84c0a372a020 72 __IO uint32_t fetch_ctrl; /* 0x0004 SPIX Fetch Control */
AnnaBridge 167:84c0a372a020 73 __IO uint32_t mode_ctrl; /* 0x0008 SPIX Mode Control */
AnnaBridge 167:84c0a372a020 74 __IO uint32_t mode_data; /* 0x000C SPIX Mode Data */
AnnaBridge 167:84c0a372a020 75 __IO uint32_t sck_fb_ctrl; /* 0x0010 SPIX SCK_FB Control Register */
AnnaBridge 167:84c0a372a020 76 } mxc_spix_regs_t;
AnnaBridge 167:84c0a372a020 77
AnnaBridge 167:84c0a372a020 78
AnnaBridge 167:84c0a372a020 79 /*
AnnaBridge 167:84c0a372a020 80 Register offsets for module SPIX.
AnnaBridge 167:84c0a372a020 81 */
AnnaBridge 167:84c0a372a020 82
AnnaBridge 167:84c0a372a020 83 #define MXC_R_SPIX_OFFS_MASTER_CFG ((uint32_t)0x00000000UL)
AnnaBridge 167:84c0a372a020 84 #define MXC_R_SPIX_OFFS_FETCH_CTRL ((uint32_t)0x00000004UL)
AnnaBridge 167:84c0a372a020 85 #define MXC_R_SPIX_OFFS_MODE_CTRL ((uint32_t)0x00000008UL)
AnnaBridge 167:84c0a372a020 86 #define MXC_R_SPIX_OFFS_MODE_DATA ((uint32_t)0x0000000CUL)
AnnaBridge 167:84c0a372a020 87 #define MXC_R_SPIX_OFFS_SCK_FB_CTRL ((uint32_t)0x00000010UL)
AnnaBridge 167:84c0a372a020 88
AnnaBridge 167:84c0a372a020 89
AnnaBridge 167:84c0a372a020 90 /*
AnnaBridge 167:84c0a372a020 91 Field positions and masks for module SPIX.
AnnaBridge 167:84c0a372a020 92 */
AnnaBridge 167:84c0a372a020 93
AnnaBridge 167:84c0a372a020 94 #define MXC_F_SPIX_MASTER_CFG_SPI_MODE_POS 0
AnnaBridge 167:84c0a372a020 95 #define MXC_F_SPIX_MASTER_CFG_SPI_MODE ((uint32_t)(0x00000003UL << MXC_F_SPIX_MASTER_CFG_SPI_MODE_POS))
AnnaBridge 167:84c0a372a020 96 #define MXC_F_SPIX_MASTER_CFG_SS_ACT_LO_POS 2
AnnaBridge 167:84c0a372a020 97 #define MXC_F_SPIX_MASTER_CFG_SS_ACT_LO ((uint32_t)(0x00000001UL << MXC_F_SPIX_MASTER_CFG_SS_ACT_LO_POS))
AnnaBridge 167:84c0a372a020 98 #define MXC_F_SPIX_MASTER_CFG_ALT_TIMING_EN_POS 3
AnnaBridge 167:84c0a372a020 99 #define MXC_F_SPIX_MASTER_CFG_ALT_TIMING_EN ((uint32_t)(0x00000001UL << MXC_F_SPIX_MASTER_CFG_ALT_TIMING_EN_POS))
AnnaBridge 167:84c0a372a020 100 #define MXC_F_SPIX_MASTER_CFG_SLAVE_SEL_POS 4
AnnaBridge 167:84c0a372a020 101 #define MXC_F_SPIX_MASTER_CFG_SLAVE_SEL ((uint32_t)(0x00000007UL << MXC_F_SPIX_MASTER_CFG_SLAVE_SEL_POS))
AnnaBridge 167:84c0a372a020 102 #define MXC_F_SPIX_MASTER_CFG_SCK_LO_CLK_POS 8
AnnaBridge 167:84c0a372a020 103 #define MXC_F_SPIX_MASTER_CFG_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MASTER_CFG_SCK_LO_CLK_POS))
AnnaBridge 167:84c0a372a020 104 #define MXC_F_SPIX_MASTER_CFG_SCK_HI_CLK_POS 12
AnnaBridge 167:84c0a372a020 105 #define MXC_F_SPIX_MASTER_CFG_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MASTER_CFG_SCK_HI_CLK_POS))
AnnaBridge 167:84c0a372a020 106 #define MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS 16
AnnaBridge 167:84c0a372a020 107 #define MXC_F_SPIX_MASTER_CFG_ACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS))
AnnaBridge 167:84c0a372a020 108 #define MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS 18
AnnaBridge 167:84c0a372a020 109 #define MXC_F_SPIX_MASTER_CFG_INACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS))
AnnaBridge 167:84c0a372a020 110 #define MXC_F_SPIX_MASTER_CFG_ALT_SCK_LO_CLK_POS 20
AnnaBridge 167:84c0a372a020 111 #define MXC_F_SPIX_MASTER_CFG_ALT_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MASTER_CFG_ALT_SCK_LO_CLK_POS))
AnnaBridge 167:84c0a372a020 112 #define MXC_F_SPIX_MASTER_CFG_ALT_SCK_HI_CLK_POS 24
AnnaBridge 167:84c0a372a020 113 #define MXC_F_SPIX_MASTER_CFG_ALT_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MASTER_CFG_ALT_SCK_HI_CLK_POS))
AnnaBridge 167:84c0a372a020 114 #define MXC_F_SPIX_MASTER_CFG_SDIO_SAMPLE_POINT_POS 28
AnnaBridge 167:84c0a372a020 115 #define MXC_F_SPIX_MASTER_CFG_SDIO_SAMPLE_POINT ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MASTER_CFG_SDIO_SAMPLE_POINT_POS))
AnnaBridge 167:84c0a372a020 116
AnnaBridge 167:84c0a372a020 117 #define MXC_F_SPIX_FETCH_CTRL_CMD_VALUE_POS 0
AnnaBridge 167:84c0a372a020 118 #define MXC_F_SPIX_FETCH_CTRL_CMD_VALUE ((uint32_t)(0x000000FFUL << MXC_F_SPIX_FETCH_CTRL_CMD_VALUE_POS))
AnnaBridge 167:84c0a372a020 119 #define MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH_POS 8
AnnaBridge 167:84c0a372a020 120 #define MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH ((uint32_t)(0x00000003UL << MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH_POS))
AnnaBridge 167:84c0a372a020 121 #define MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH_POS 10
AnnaBridge 167:84c0a372a020 122 #define MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH ((uint32_t)(0x00000003UL << MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH_POS))
AnnaBridge 167:84c0a372a020 123 #define MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH_POS 12
AnnaBridge 167:84c0a372a020 124 #define MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH ((uint32_t)(0x00000003UL << MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH_POS))
AnnaBridge 167:84c0a372a020 125 #define MXC_F_SPIX_FETCH_CTRL_FOUR_BYTE_ADDR_POS 16
AnnaBridge 167:84c0a372a020 126 #define MXC_F_SPIX_FETCH_CTRL_FOUR_BYTE_ADDR ((uint32_t)(0x00000001UL << MXC_F_SPIX_FETCH_CTRL_FOUR_BYTE_ADDR_POS))
AnnaBridge 167:84c0a372a020 127
AnnaBridge 167:84c0a372a020 128 #define MXC_F_SPIX_MODE_CTRL_MODE_CLOCKS_POS 0
AnnaBridge 167:84c0a372a020 129 #define MXC_F_SPIX_MODE_CTRL_MODE_CLOCKS ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MODE_CTRL_MODE_CLOCKS_POS))
AnnaBridge 167:84c0a372a020 130 #define MXC_F_SPIX_MODE_CTRL_NO_CMD_MODE_POS 8
AnnaBridge 167:84c0a372a020 131 #define MXC_F_SPIX_MODE_CTRL_NO_CMD_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIX_MODE_CTRL_NO_CMD_MODE_POS))
AnnaBridge 167:84c0a372a020 132
AnnaBridge 167:84c0a372a020 133 #define MXC_F_SPIX_MODE_DATA_MODE_DATA_BITS_POS 0
AnnaBridge 167:84c0a372a020 134 #define MXC_F_SPIX_MODE_DATA_MODE_DATA_BITS ((uint32_t)(0x0000FFFFUL << MXC_F_SPIX_MODE_DATA_MODE_DATA_BITS_POS))
AnnaBridge 167:84c0a372a020 135 #define MXC_F_SPIX_MODE_DATA_MODE_DATA_OE_POS 16
AnnaBridge 167:84c0a372a020 136 #define MXC_F_SPIX_MODE_DATA_MODE_DATA_OE ((uint32_t)(0x0000FFFFUL << MXC_F_SPIX_MODE_DATA_MODE_DATA_OE_POS))
AnnaBridge 167:84c0a372a020 137
AnnaBridge 167:84c0a372a020 138 #define MXC_F_SPIX_SCK_FB_CTRL_ENABLE_SCK_FB_MODE_POS 0
AnnaBridge 167:84c0a372a020 139 #define MXC_F_SPIX_SCK_FB_CTRL_ENABLE_SCK_FB_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIX_SCK_FB_CTRL_ENABLE_SCK_FB_MODE_POS))
AnnaBridge 167:84c0a372a020 140 #define MXC_F_SPIX_SCK_FB_CTRL_INVERT_SCK_FB_CLK_POS 1
AnnaBridge 167:84c0a372a020 141 #define MXC_F_SPIX_SCK_FB_CTRL_INVERT_SCK_FB_CLK ((uint32_t)(0x00000001UL << MXC_F_SPIX_SCK_FB_CTRL_INVERT_SCK_FB_CLK_POS))
AnnaBridge 167:84c0a372a020 142
AnnaBridge 167:84c0a372a020 143 #if(MXC_SPIX_REV == 0)
AnnaBridge 167:84c0a372a020 144 #define MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS_POS 4
AnnaBridge 167:84c0a372a020 145 #define MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS ((uint32_t)(0x0000003FUL << MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS_POS))
AnnaBridge 167:84c0a372a020 146 #define MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS_NO_CMD_POS 12
AnnaBridge 167:84c0a372a020 147 #define MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS_NO_CMD ((uint32_t)(0x0000003FUL << MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS_NO_CMD_POS))
AnnaBridge 167:84c0a372a020 148 #endif
AnnaBridge 167:84c0a372a020 149
AnnaBridge 167:84c0a372a020 150
AnnaBridge 167:84c0a372a020 151 /*
AnnaBridge 167:84c0a372a020 152 Field values and shifted values for module SPIX.
AnnaBridge 167:84c0a372a020 153 */
AnnaBridge 167:84c0a372a020 154
AnnaBridge 167:84c0a372a020 155 #define MXC_V_SPIX_MASTER_CFG_SPI_MODE_SCK_HI_SAMPLE_RISING ((uint32_t)(0x00000000UL))
AnnaBridge 167:84c0a372a020 156 #define MXC_V_SPIX_MASTER_CFG_SPI_MODE_SCK_LO_SAMPLE_FALLING ((uint32_t)(0x00000003UL))
AnnaBridge 167:84c0a372a020 157
AnnaBridge 167:84c0a372a020 158 #define MXC_S_SPIX_MASTER_CFG_SPI_MODE_SCK_HI_SAMPLE_RISING ((uint32_t)(MXC_V_SPIX_MASTER_CFG_SPI_MODE_SCK_HI_SAMPLE_RISING << MXC_F_SPIX_MASTER_CFG_SPI_MODE_POS))
AnnaBridge 167:84c0a372a020 159 #define MXC_S_SPIX_MASTER_CFG_SPI_MODE_SCK_LO_SAMPLE_FALLING ((uint32_t)(MXC_V_SPIX_MASTER_CFG_SPI_MODE_SCK_LO_SAMPLE_FALLING << MXC_F_SPIX_MASTER_CFG_SPI_MODE_POS))
AnnaBridge 167:84c0a372a020 160
AnnaBridge 167:84c0a372a020 161 #define MXC_V_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_HIGH ((uint32_t)(0x00000000UL))
AnnaBridge 167:84c0a372a020 162 #define MXC_V_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_LOW ((uint32_t)(0x00000001UL))
AnnaBridge 167:84c0a372a020 163
AnnaBridge 167:84c0a372a020 164 #define MXC_S_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_HIGH ((uint32_t)(MXC_V_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_HIGH << MXC_F_SPIX_MASTER_CFG_SS_ACT_LO_POS))
AnnaBridge 167:84c0a372a020 165 #define MXC_S_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_LOW ((uint32_t)(MXC_V_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_LOW << MXC_F_SPIX_MASTER_CFG_SS_ACT_LO_POS))
AnnaBridge 167:84c0a372a020 166
AnnaBridge 167:84c0a372a020 167 #define MXC_V_SPIX_MASTER_CFG_ALT_TIMING_EN_DISABLED ((uint32_t)(0x00000000UL))
AnnaBridge 167:84c0a372a020 168 #define MXC_V_SPIX_MASTER_CFG_ALT_TIMING_EN_ENABLED_AS_NEEDED ((uint32_t)(0x00000001UL))
AnnaBridge 167:84c0a372a020 169
AnnaBridge 167:84c0a372a020 170 #define MXC_S_SPIX_MASTER_CFG_ALT_TIMING_EN_DISABLED ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ALT_TIMING_EN_DISABLED << MXC_F_SPIX_MASTER_CFG_ALT_TIMING_EN_POS))
AnnaBridge 167:84c0a372a020 171 #define MXC_S_SPIX_MASTER_CFG_ALT_TIMING_EN_ENABLED_AS_NEEDED ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ALT_TIMING_EN_ENABLED_AS_NEEDED << MXC_F_SPIX_MASTER_CFG_ALT_TIMING_EN_POS))
AnnaBridge 167:84c0a372a020 172
AnnaBridge 167:84c0a372a020 173 #define MXC_V_SPIX_MASTER_CFG_ACT_DELAY_OFF ((uint32_t)(0x00000000UL))
AnnaBridge 167:84c0a372a020 174 #define MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(0x00000001UL))
AnnaBridge 167:84c0a372a020 175 #define MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(0x00000002UL))
AnnaBridge 167:84c0a372a020 176 #define MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(0x00000003UL))
AnnaBridge 167:84c0a372a020 177
AnnaBridge 167:84c0a372a020 178 #define MXC_S_SPIX_MASTER_CFG_ACT_DELAY_OFF ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ACT_DELAY_OFF << MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS))
AnnaBridge 167:84c0a372a020 179 #define MXC_S_SPIX_MASTER_CFG_ACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_2_MOD_CLK << MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS))
AnnaBridge 167:84c0a372a020 180 #define MXC_S_SPIX_MASTER_CFG_ACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_4_MOD_CLK << MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS))
AnnaBridge 167:84c0a372a020 181 #define MXC_S_SPIX_MASTER_CFG_ACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_8_MOD_CLK << MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS))
AnnaBridge 167:84c0a372a020 182
AnnaBridge 167:84c0a372a020 183 #define MXC_V_SPIX_MASTER_CFG_INACT_DELAY_OFF ((uint32_t)(0x00000000UL))
AnnaBridge 167:84c0a372a020 184 #define MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(0x00000001UL))
AnnaBridge 167:84c0a372a020 185 #define MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(0x00000002UL))
AnnaBridge 167:84c0a372a020 186 #define MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(0x00000003UL))
AnnaBridge 167:84c0a372a020 187
AnnaBridge 167:84c0a372a020 188 #define MXC_S_SPIX_MASTER_CFG_INACT_DELAY_OFF ((uint32_t)(MXC_V_SPIX_MASTER_CFG_INACT_DELAY_OFF << MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS))
AnnaBridge 167:84c0a372a020 189 #define MXC_S_SPIX_MASTER_CFG_INACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_2_MOD_CLK << MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS))
AnnaBridge 167:84c0a372a020 190 #define MXC_S_SPIX_MASTER_CFG_INACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_4_MOD_CLK << MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS))
AnnaBridge 167:84c0a372a020 191 #define MXC_S_SPIX_MASTER_CFG_INACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_8_MOD_CLK << MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS))
AnnaBridge 167:84c0a372a020 192
AnnaBridge 167:84c0a372a020 193 #define MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_SINGLE ((uint32_t)(0x00000000UL))
AnnaBridge 167:84c0a372a020 194 #define MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_DUAL_IO ((uint32_t)(0x00000001UL))
AnnaBridge 167:84c0a372a020 195 #define MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_QUAD_IO ((uint32_t)(0x00000002UL))
AnnaBridge 167:84c0a372a020 196
AnnaBridge 167:84c0a372a020 197 #define MXC_S_SPIX_FETCH_CTRL_CMD_WIDTH_SINGLE ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_SINGLE << MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH_POS))
AnnaBridge 167:84c0a372a020 198 #define MXC_S_SPIX_FETCH_CTRL_CMD_WIDTH_DUAL_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_DUAL_IO << MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH_POS))
AnnaBridge 167:84c0a372a020 199 #define MXC_S_SPIX_FETCH_CTRL_CMD_WIDTH_QUAD_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_QUAD_IO << MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH_POS))
AnnaBridge 167:84c0a372a020 200
AnnaBridge 167:84c0a372a020 201 #define MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_SINGLE ((uint32_t)(0x00000000UL))
AnnaBridge 167:84c0a372a020 202 #define MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_DUAL_IO ((uint32_t)(0x00000001UL))
AnnaBridge 167:84c0a372a020 203 #define MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_QUAD_IO ((uint32_t)(0x00000002UL))
AnnaBridge 167:84c0a372a020 204
AnnaBridge 167:84c0a372a020 205 #define MXC_S_SPIX_FETCH_CTRL_ADDR_WIDTH_SINGLE ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_SINGLE << MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH_POS))
AnnaBridge 167:84c0a372a020 206 #define MXC_S_SPIX_FETCH_CTRL_ADDR_WIDTH_DUAL_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_DUAL_IO << MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH_POS))
AnnaBridge 167:84c0a372a020 207 #define MXC_S_SPIX_FETCH_CTRL_ADDR_WIDTH_QUAD_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_QUAD_IO << MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH_POS))
AnnaBridge 167:84c0a372a020 208
AnnaBridge 167:84c0a372a020 209 #define MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_SINGLE ((uint32_t)(0x00000000UL))
AnnaBridge 167:84c0a372a020 210 #define MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_DUAL_IO ((uint32_t)(0x00000001UL))
AnnaBridge 167:84c0a372a020 211 #define MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_QUAD_IO ((uint32_t)(0x00000002UL))
AnnaBridge 167:84c0a372a020 212
AnnaBridge 167:84c0a372a020 213 #define MXC_S_SPIX_FETCH_CTRL_DATA_WIDTH_SINGLE ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_SINGLE << MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH_POS))
AnnaBridge 167:84c0a372a020 214 #define MXC_S_SPIX_FETCH_CTRL_DATA_WIDTH_DUAL_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_DUAL_IO << MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH_POS))
AnnaBridge 167:84c0a372a020 215 #define MXC_S_SPIX_FETCH_CTRL_DATA_WIDTH_QUAD_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_QUAD_IO << MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH_POS))
AnnaBridge 167:84c0a372a020 216
AnnaBridge 167:84c0a372a020 217
AnnaBridge 167:84c0a372a020 218
AnnaBridge 167:84c0a372a020 219 #ifdef __cplusplus
AnnaBridge 167:84c0a372a020 220 }
AnnaBridge 167:84c0a372a020 221 #endif
AnnaBridge 167:84c0a372a020 222
AnnaBridge 167:84c0a372a020 223 #endif /* _MXC_SPIX_REGS_H_ */
AnnaBridge 167:84c0a372a020 224