The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 167:84c0a372a020 1 /*******************************************************************************
AnnaBridge 167:84c0a372a020 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
AnnaBridge 167:84c0a372a020 3 *
AnnaBridge 167:84c0a372a020 4 * Permission is hereby granted, free of charge, to any person obtaining a
AnnaBridge 167:84c0a372a020 5 * copy of this software and associated documentation files (the "Software"),
AnnaBridge 167:84c0a372a020 6 * to deal in the Software without restriction, including without limitation
AnnaBridge 167:84c0a372a020 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
AnnaBridge 167:84c0a372a020 8 * and/or sell copies of the Software, and to permit persons to whom the
AnnaBridge 167:84c0a372a020 9 * Software is furnished to do so, subject to the following conditions:
AnnaBridge 167:84c0a372a020 10 *
AnnaBridge 167:84c0a372a020 11 * The above copyright notice and this permission notice shall be included
AnnaBridge 167:84c0a372a020 12 * in all copies or substantial portions of the Software.
AnnaBridge 167:84c0a372a020 13 *
AnnaBridge 167:84c0a372a020 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
AnnaBridge 167:84c0a372a020 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
AnnaBridge 167:84c0a372a020 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
AnnaBridge 167:84c0a372a020 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
AnnaBridge 167:84c0a372a020 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
AnnaBridge 167:84c0a372a020 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
AnnaBridge 167:84c0a372a020 20 * OTHER DEALINGS IN THE SOFTWARE.
AnnaBridge 167:84c0a372a020 21 *
AnnaBridge 167:84c0a372a020 22 * Except as contained in this notice, the name of Maxim Integrated
AnnaBridge 167:84c0a372a020 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
AnnaBridge 167:84c0a372a020 24 * Products, Inc. Branding Policy.
AnnaBridge 167:84c0a372a020 25 *
AnnaBridge 167:84c0a372a020 26 * The mere transfer of this software does not imply any licenses
AnnaBridge 167:84c0a372a020 27 * of trade secrets, proprietary technology, copyrights, patents,
AnnaBridge 167:84c0a372a020 28 * trademarks, maskwork rights, or any other form of intellectual
AnnaBridge 167:84c0a372a020 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
AnnaBridge 167:84c0a372a020 30 * ownership rights.
AnnaBridge 167:84c0a372a020 31 *
AnnaBridge 167:84c0a372a020 32 * $Date: 2016-04-27 09:12:38 -0700 (Wed, 27 Apr 2016) $
AnnaBridge 167:84c0a372a020 33 * $Revision: 22537 $
AnnaBridge 167:84c0a372a020 34 *
AnnaBridge 167:84c0a372a020 35 ******************************************************************************/
AnnaBridge 167:84c0a372a020 36
AnnaBridge 167:84c0a372a020 37 #ifndef _MAX32620_H_
AnnaBridge 167:84c0a372a020 38 #define _MAX32620_H_
AnnaBridge 167:84c0a372a020 39
AnnaBridge 167:84c0a372a020 40 #include <stdint.h>
AnnaBridge 167:84c0a372a020 41
AnnaBridge 167:84c0a372a020 42 #ifndef FALSE
AnnaBridge 167:84c0a372a020 43 #define FALSE (0)
AnnaBridge 167:84c0a372a020 44 #endif
AnnaBridge 167:84c0a372a020 45
AnnaBridge 167:84c0a372a020 46 #ifndef TRUE
AnnaBridge 167:84c0a372a020 47 #define TRUE (1)
AnnaBridge 167:84c0a372a020 48 #endif
AnnaBridge 167:84c0a372a020 49
AnnaBridge 167:84c0a372a020 50 /* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */
AnnaBridge 167:84c0a372a020 51 #if defined ( __GNUC__ )
AnnaBridge 167:84c0a372a020 52 #define __weak __attribute__((weak))
AnnaBridge 167:84c0a372a020 53
AnnaBridge 167:84c0a372a020 54 #elif defined ( __CC_ARM)
AnnaBridge 167:84c0a372a020 55
AnnaBridge 167:84c0a372a020 56 #define inline __inline
AnnaBridge 167:84c0a372a020 57 #pragma anon_unions
AnnaBridge 167:84c0a372a020 58
AnnaBridge 167:84c0a372a020 59 #endif
AnnaBridge 167:84c0a372a020 60
AnnaBridge 167:84c0a372a020 61 typedef enum {
AnnaBridge 167:84c0a372a020 62 NonMaskableInt_IRQn = -14,
AnnaBridge 167:84c0a372a020 63 HardFault_IRQn = -13,
AnnaBridge 167:84c0a372a020 64 MemoryManagement_IRQn = -12,
AnnaBridge 167:84c0a372a020 65 BusFault_IRQn = -11,
AnnaBridge 167:84c0a372a020 66 UsageFault_IRQn = -10,
AnnaBridge 167:84c0a372a020 67 SVCall_IRQn = -5,
AnnaBridge 167:84c0a372a020 68 DebugMonitor_IRQn = -4,
AnnaBridge 167:84c0a372a020 69 PendSV_IRQn = -2,
AnnaBridge 167:84c0a372a020 70 SysTick_IRQn = -1,
AnnaBridge 167:84c0a372a020 71
AnnaBridge 167:84c0a372a020 72 /* Device-specific interrupt sources (external to ARM core) */
AnnaBridge 167:84c0a372a020 73 /* table entry number */
AnnaBridge 167:84c0a372a020 74 /* |||| */
AnnaBridge 167:84c0a372a020 75 /* |||| table offset address */
AnnaBridge 167:84c0a372a020 76 /* vvvv vvvvvv */
AnnaBridge 167:84c0a372a020 77
AnnaBridge 167:84c0a372a020 78 CLKMAN_IRQn = 0, /* 0x10 0x0040 CLKMAN */
AnnaBridge 167:84c0a372a020 79 PWRMAN_IRQn, /* 0x11 0x0044 PWRMAN */
AnnaBridge 167:84c0a372a020 80 FLC_IRQn, /* 0x12 0x0048 Flash Controller */
AnnaBridge 167:84c0a372a020 81 RTC0_IRQn, /* 0x13 0x004C RTC Counter match with Compare 0 */
AnnaBridge 167:84c0a372a020 82 RTC1_IRQn, /* 0x14 0x0050 RTC Counter match with Compare 1 */
AnnaBridge 167:84c0a372a020 83 RTC2_IRQn, /* 0x15 0x0054 RTC Prescaler interval compare match */
AnnaBridge 167:84c0a372a020 84 RTC3_IRQn, /* 0x16 0x0058 RTC Overflow */
AnnaBridge 167:84c0a372a020 85 PMU_IRQn, /* 0x17 0x005C Peripheral Management Unit (PMU/DMA) */
AnnaBridge 167:84c0a372a020 86 USB_IRQn, /* 0x18 0x0060 USB */
AnnaBridge 167:84c0a372a020 87 AES_IRQn, /* 0x19 0x0064 AES */
AnnaBridge 167:84c0a372a020 88 MAA_IRQn, /* 0x1A 0x0068 MAA */
AnnaBridge 167:84c0a372a020 89 WDT0_IRQn, /* 0x1B 0x006C Watchdog 0 timeout */
AnnaBridge 167:84c0a372a020 90 WDT0_P_IRQn, /* 0x1C 0x0070 Watchdog 0 pre-window (fed too early) */
AnnaBridge 167:84c0a372a020 91 WDT1_IRQn, /* 0x1D 0x0074 Watchdog 1 timeout */
AnnaBridge 167:84c0a372a020 92 WDT1_P_IRQn, /* 0x1E 0x0078 Watchdog 1 pre-window (fed too early) */
AnnaBridge 167:84c0a372a020 93 GPIO_P0_IRQn, /* 0x1F 0x007C GPIO Port 0 */
AnnaBridge 167:84c0a372a020 94 GPIO_P1_IRQn, /* 0x20 0x0080 GPIO Port 1 */
AnnaBridge 167:84c0a372a020 95 GPIO_P2_IRQn, /* 0x21 0x0084 GPIO Port 2 */
AnnaBridge 167:84c0a372a020 96 GPIO_P3_IRQn, /* 0x22 0x0088 GPIO Port 3 */
AnnaBridge 167:84c0a372a020 97 GPIO_P4_IRQn, /* 0x23 0x008C GPIO Port 4 */
AnnaBridge 167:84c0a372a020 98 GPIO_P5_IRQn, /* 0x24 0x0090 GPIO Port 5 */
AnnaBridge 167:84c0a372a020 99 GPIO_P6_IRQn, /* 0x25 0x0094 GPIO Port 6 */
AnnaBridge 167:84c0a372a020 100 TMR0_0_IRQn, /* 0x26 0x0098 Timer 0 (32-bit, 16-bit #0) */
AnnaBridge 167:84c0a372a020 101 TMR0_1_IRQn, /* 0x27 0x009C Timer 0 (16-bit #1) */
AnnaBridge 167:84c0a372a020 102 TMR1_0_IRQn, /* 0x28 0x00A0 Timer 1 (32-bit, 16-bit #0) */
AnnaBridge 167:84c0a372a020 103 TMR1_1_IRQn, /* 0x29 0x00A4 Timer 1 (16-bit #1) */
AnnaBridge 167:84c0a372a020 104 TMR2_0_IRQn, /* 0x2A 0x00A8 Timer 2 (32-bit, 16-bit #0) */
AnnaBridge 167:84c0a372a020 105 TMR2_1_IRQn, /* 0x2B 0x00AC Timer 2 (16-bit #1) */
AnnaBridge 167:84c0a372a020 106 TMR3_0_IRQn, /* 0x2C 0x00B0 Timer 3 (32-bit, 16-bit #0) */
AnnaBridge 167:84c0a372a020 107 TMR3_1_IRQn, /* 0x2D 0x00B4 Timer 3 (16-bit #1) */
AnnaBridge 167:84c0a372a020 108 TMR4_0_IRQn, /* 0x2E 0x00B8 Timer 4 (32-bit, 16-bit #0) */
AnnaBridge 167:84c0a372a020 109 TMR4_1_IRQn, /* 0x2F 0x00BC Timer 4 (16-bit #1) */
AnnaBridge 167:84c0a372a020 110 TMR5_0_IRQn, /* 0x30 0x00C0 Timer 5 (32-bit, 16-bit #0) */
AnnaBridge 167:84c0a372a020 111 TMR5_1_IRQn, /* 0x31 0x00C4 Timer 5 (16-bit #1) */
AnnaBridge 167:84c0a372a020 112 UART0_IRQn, /* 0x32 0x00C8 UART 0 */
AnnaBridge 167:84c0a372a020 113 UART1_IRQn, /* 0x33 0x00CC UART 1 */
AnnaBridge 167:84c0a372a020 114 UART2_IRQn, /* 0x34 0x00D0 UART 2 */
AnnaBridge 167:84c0a372a020 115 UART3_IRQn, /* 0x35 0x00D4 UART 3 */
AnnaBridge 167:84c0a372a020 116 PT_IRQn, /* 0x36 0x00D8 Pulse Trains */
AnnaBridge 167:84c0a372a020 117 I2CM0_IRQn, /* 0x37 0x00DC I2C Master 0 */
AnnaBridge 167:84c0a372a020 118 I2CM1_IRQn, /* 0x38 0x00E0 I2C Master 1 */
AnnaBridge 167:84c0a372a020 119 I2CM2_IRQn, /* 0x39 0x00E4 I2C Master 2 */
AnnaBridge 167:84c0a372a020 120 I2CS_IRQn, /* 0x3A 0x00E8 I2C Slave */
AnnaBridge 167:84c0a372a020 121 SPIM0_IRQn, /* 0x3B 0x00EC SPI Master 0 */
AnnaBridge 167:84c0a372a020 122 SPIM1_IRQn, /* 0x3C 0x00F0 SPI Master 1 */
AnnaBridge 167:84c0a372a020 123 SPIM2_IRQn, /* 0x3D 0x00F4 SPI Master 2 */
AnnaBridge 167:84c0a372a020 124 SPIB_IRQn, /* 0x3E 0x00F8 SPI Bridge */
AnnaBridge 167:84c0a372a020 125 OWM_IRQn, /* 0x3F 0x00FC 1-Wire Master */
AnnaBridge 167:84c0a372a020 126 AFE_IRQn, /* 0x40 0x0100 Analog Front End, ADC */
AnnaBridge 167:84c0a372a020 127 SPIS_IRQn, /* 0x41 0x0104 SPI Slave */
AnnaBridge 167:84c0a372a020 128 GPIO_P7_IRQn, /* 0x42 0x0108 GPIO Port 7 */
AnnaBridge 167:84c0a372a020 129 GPIO_P8_IRQn, /* 0x43 0x010C GPIO Port 8 */
AnnaBridge 167:84c0a372a020 130 MXC_IRQ_EXT_COUNT,
AnnaBridge 167:84c0a372a020 131 } IRQn_Type;
AnnaBridge 167:84c0a372a020 132
AnnaBridge 167:84c0a372a020 133 #define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16)
AnnaBridge 167:84c0a372a020 134
AnnaBridge 167:84c0a372a020 135
AnnaBridge 167:84c0a372a020 136 /* ================================================================================ */
AnnaBridge 167:84c0a372a020 137 /* ================ Processor and Core Peripheral Section ================ */
AnnaBridge 167:84c0a372a020 138 /* ================================================================================ */
AnnaBridge 167:84c0a372a020 139
AnnaBridge 167:84c0a372a020 140 /* ---------------------- Configuration of the Cortex-M Processor and Core Peripherals ---------------------- */
AnnaBridge 167:84c0a372a020 141 #define __CM4_REV 0x0100 /*!< Cortex-M4 Core Revision */
AnnaBridge 167:84c0a372a020 142 #define __MPU_PRESENT 0 /*!< MPU present or not */
AnnaBridge 167:84c0a372a020 143 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
AnnaBridge 167:84c0a372a020 144 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
AnnaBridge 167:84c0a372a020 145 #define __FPU_PRESENT 1 /*!< FPU present or not */
AnnaBridge 167:84c0a372a020 146
AnnaBridge 167:84c0a372a020 147 #include <core_cm4.h> /*!< Cortex-M4 processor and core peripherals */
AnnaBridge 167:84c0a372a020 148 #include "system_max32620.h" /*!< System Header */
AnnaBridge 167:84c0a372a020 149
AnnaBridge 167:84c0a372a020 150
AnnaBridge 167:84c0a372a020 151 /* ================================================================================ */
AnnaBridge 167:84c0a372a020 152 /* ================== Device Specific Memory Section ================== */
AnnaBridge 167:84c0a372a020 153 /* ================================================================================ */
AnnaBridge 167:84c0a372a020 154
AnnaBridge 167:84c0a372a020 155 #define MXC_FLASH_MEM_BASE 0x00000000UL
AnnaBridge 167:84c0a372a020 156 #define MXC_FLASH_PAGE_SIZE 0x00002000UL
AnnaBridge 167:84c0a372a020 157 #define MXC_FLASH_FULL_MEM_SIZE 0x00200000UL
AnnaBridge 167:84c0a372a020 158 #define MXC_SYS_MEM_BASE 0x20000000UL
AnnaBridge 167:84c0a372a020 159 #define MXC_SRAM_FULL_MEM_SIZE 0x00040000UL
AnnaBridge 167:84c0a372a020 160 #define MXC_EXT_FLASH_MEM_BASE 0x10000000UL
AnnaBridge 167:84c0a372a020 161
AnnaBridge 167:84c0a372a020 162 /* ================================================================================ */
AnnaBridge 167:84c0a372a020 163 /* ================ Device Specific Peripheral Section ================ */
AnnaBridge 167:84c0a372a020 164 /* ================================================================================ */
AnnaBridge 167:84c0a372a020 165
AnnaBridge 167:84c0a372a020 166
AnnaBridge 167:84c0a372a020 167 /*
AnnaBridge 167:84c0a372a020 168 Base addresses and configuration settings for all MAX32620 peripheral modules.
AnnaBridge 167:84c0a372a020 169 */
AnnaBridge 167:84c0a372a020 170
AnnaBridge 167:84c0a372a020 171
AnnaBridge 167:84c0a372a020 172 /*******************************************************************************/
AnnaBridge 167:84c0a372a020 173 /* System Manager Settings */
AnnaBridge 167:84c0a372a020 174
AnnaBridge 167:84c0a372a020 175 #define MXC_BASE_SYSMAN ((uint32_t)0x40000000UL)
AnnaBridge 167:84c0a372a020 176 #define MXC_SYSMAN ((mxc_sysman_regs_t *)MXC_BASE_SYSMAN)
AnnaBridge 167:84c0a372a020 177
AnnaBridge 167:84c0a372a020 178
AnnaBridge 167:84c0a372a020 179
AnnaBridge 167:84c0a372a020 180 /*******************************************************************************/
AnnaBridge 167:84c0a372a020 181 /* System Clock Manager */
AnnaBridge 167:84c0a372a020 182
AnnaBridge 167:84c0a372a020 183 #define MXC_BASE_CLKMAN ((uint32_t)0x40000400UL)
AnnaBridge 167:84c0a372a020 184 #define MXC_CLKMAN ((mxc_clkman_regs_t *)MXC_BASE_CLKMAN)
AnnaBridge 167:84c0a372a020 185
AnnaBridge 167:84c0a372a020 186
AnnaBridge 167:84c0a372a020 187
AnnaBridge 167:84c0a372a020 188 /*******************************************************************************/
AnnaBridge 167:84c0a372a020 189 /* System Power Manager */
AnnaBridge 167:84c0a372a020 190
AnnaBridge 167:84c0a372a020 191 #define MXC_BASE_PWRMAN ((uint32_t)0x40000800UL)
AnnaBridge 167:84c0a372a020 192 #define MXC_PWRMAN ((mxc_pwrman_regs_t *)MXC_BASE_PWRMAN)
AnnaBridge 167:84c0a372a020 193
AnnaBridge 167:84c0a372a020 194
AnnaBridge 167:84c0a372a020 195
AnnaBridge 167:84c0a372a020 196 /*******************************************************************************/
AnnaBridge 167:84c0a372a020 197 /* Real Time Clock */
AnnaBridge 167:84c0a372a020 198
AnnaBridge 167:84c0a372a020 199 #define MXC_BASE_RTCTMR ((uint32_t)0x40000A00UL)
AnnaBridge 167:84c0a372a020 200 #define MXC_RTCTMR ((mxc_rtctmr_regs_t *)MXC_BASE_RTCTMR)
AnnaBridge 167:84c0a372a020 201 #define MXC_BASE_RTCCFG ((uint32_t)0x40000A70UL)
AnnaBridge 167:84c0a372a020 202 #define MXC_RTCCFG ((mxc_rtccfg_regs_t *)MXC_BASE_RTCCFG)
AnnaBridge 167:84c0a372a020 203
AnnaBridge 167:84c0a372a020 204 #define MXC_RTCTMR_GET_IRQ(i) (IRQn_Type)(i == 0 ? RTC0_IRQn : \
AnnaBridge 167:84c0a372a020 205 i == 1 ? RTC1_IRQn : \
AnnaBridge 167:84c0a372a020 206 i == 2 ? RTC2_IRQn : \
AnnaBridge 167:84c0a372a020 207 i == 3 ? RTC3_IRQn : 0)
AnnaBridge 167:84c0a372a020 208
AnnaBridge 167:84c0a372a020 209
AnnaBridge 167:84c0a372a020 210
AnnaBridge 167:84c0a372a020 211 /*******************************************************************************/
AnnaBridge 167:84c0a372a020 212 /* Power Sequencer */
AnnaBridge 167:84c0a372a020 213
AnnaBridge 167:84c0a372a020 214 #define MXC_BASE_PWRSEQ ((uint32_t)0x40000A30UL)
AnnaBridge 167:84c0a372a020 215 #define MXC_PWRSEQ ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ)
AnnaBridge 167:84c0a372a020 216
AnnaBridge 167:84c0a372a020 217
AnnaBridge 167:84c0a372a020 218
AnnaBridge 167:84c0a372a020 219 /*******************************************************************************/
AnnaBridge 167:84c0a372a020 220 /* System I/O Manager */
AnnaBridge 167:84c0a372a020 221
AnnaBridge 167:84c0a372a020 222 #define MXC_BASE_IOMAN ((uint32_t)0x40000C00UL)
AnnaBridge 167:84c0a372a020 223 #define MXC_IOMAN ((mxc_ioman_regs_t *)MXC_BASE_IOMAN)
AnnaBridge 167:84c0a372a020 224
AnnaBridge 167:84c0a372a020 225
AnnaBridge 167:84c0a372a020 226
AnnaBridge 167:84c0a372a020 227 /*******************************************************************************/
AnnaBridge 167:84c0a372a020 228 /* Shadow Trim Registers */
AnnaBridge 167:84c0a372a020 229
AnnaBridge 167:84c0a372a020 230 #define MXC_BASE_TRIM ((uint32_t)0x40001000UL)
AnnaBridge 167:84c0a372a020 231 #define MXC_TRIM ((mxc_trim_regs_t *)MXC_BASE_TRIM)
AnnaBridge 167:84c0a372a020 232
AnnaBridge 167:84c0a372a020 233
AnnaBridge 167:84c0a372a020 234
AnnaBridge 167:84c0a372a020 235 /*******************************************************************************/
AnnaBridge 167:84c0a372a020 236 /* Flash Controller */
AnnaBridge 167:84c0a372a020 237
AnnaBridge 167:84c0a372a020 238 #define MXC_BASE_FLC ((uint32_t)0x40002000UL)
AnnaBridge 167:84c0a372a020 239 #define MXC_FLC ((mxc_flc_regs_t *)MXC_BASE_FLC)
AnnaBridge 167:84c0a372a020 240
AnnaBridge 167:84c0a372a020 241 #define MXC_FLC_PAGE_SIZE_SHIFT (13)
AnnaBridge 167:84c0a372a020 242 #define MXC_FLC_PAGE_SIZE (1 << MXC_FLC_PAGE_SIZE_SHIFT)
AnnaBridge 167:84c0a372a020 243 #define MXC_FLC_PAGE_ERASE_MSK ((~(1 << (MXC_FLC_PAGE_SIZE_SHIFT - 1))) >> MXC_FLC_PAGE_SIZE_SHIFT) << MXC_FLC_PAGE_SIZE_SHIFT
AnnaBridge 167:84c0a372a020 244
AnnaBridge 167:84c0a372a020 245
AnnaBridge 167:84c0a372a020 246
AnnaBridge 167:84c0a372a020 247 /*******************************************************************************/
AnnaBridge 167:84c0a372a020 248 /* Instruction Cache */
AnnaBridge 167:84c0a372a020 249
AnnaBridge 167:84c0a372a020 250 #define MXC_BASE_ICC ((uint32_t)0x40003000UL)
AnnaBridge 167:84c0a372a020 251 #define MXC_ICC ((mxc_icc_regs_t *)MXC_BASE_ICC)
AnnaBridge 167:84c0a372a020 252
AnnaBridge 167:84c0a372a020 253
AnnaBridge 167:84c0a372a020 254
AnnaBridge 167:84c0a372a020 255 /*******************************************************************************/
AnnaBridge 167:84c0a372a020 256 /* SPI XIP Interface */
AnnaBridge 167:84c0a372a020 257
AnnaBridge 167:84c0a372a020 258 #define MXC_BASE_SPIX ((uint32_t)0x40004000UL)
AnnaBridge 167:84c0a372a020 259 #define MXC_SPIX ((mxc_spix_regs_t *)MXC_BASE_SPIX)
AnnaBridge 167:84c0a372a020 260
AnnaBridge 167:84c0a372a020 261
AnnaBridge 167:84c0a372a020 262
AnnaBridge 167:84c0a372a020 263 /*******************************************************************************/
AnnaBridge 167:84c0a372a020 264 /* Peripheral Management Unit */
AnnaBridge 167:84c0a372a020 265
AnnaBridge 167:84c0a372a020 266 #define MXC_CFG_PMU_CHANNELS (6)
AnnaBridge 167:84c0a372a020 267
AnnaBridge 167:84c0a372a020 268 #define MXC_BASE_PMU0 ((uint32_t)0x40005000UL)
AnnaBridge 167:84c0a372a020 269 #define MXC_PMU0 ((mxc_pmu_regs_t *)MXC_BASE_PMU0)
AnnaBridge 167:84c0a372a020 270 #define MXC_BASE_PMU1 ((uint32_t)0x40005020UL)
AnnaBridge 167:84c0a372a020 271 #define MXC_PMU1 ((mxc_pmu_regs_t *)MXC_BASE_PMU1)
AnnaBridge 167:84c0a372a020 272 #define MXC_BASE_PMU2 ((uint32_t)0x40005040UL)
AnnaBridge 167:84c0a372a020 273 #define MXC_PMU2 ((mxc_pmu_regs_t *)MXC_BASE_PMU2)
AnnaBridge 167:84c0a372a020 274 #define MXC_BASE_PMU3 ((uint32_t)0x40005060UL)
AnnaBridge 167:84c0a372a020 275 #define MXC_PMU3 ((mxc_pmu_regs_t *)MXC_BASE_PMU3)
AnnaBridge 167:84c0a372a020 276 #define MXC_BASE_PMU4 ((uint32_t)0x40005080UL)
AnnaBridge 167:84c0a372a020 277 #define MXC_PMU4 ((mxc_pmu_regs_t *)MXC_BASE_PMU4)
AnnaBridge 167:84c0a372a020 278 #define MXC_BASE_PMU5 ((uint32_t)0x400050A0UL)
AnnaBridge 167:84c0a372a020 279 #define MXC_PMU5 ((mxc_pmu_regs_t *)MXC_BASE_PMU5)
AnnaBridge 167:84c0a372a020 280
AnnaBridge 167:84c0a372a020 281 #define MXC_PMU_GET_BASE(i) ((i) == 0 ? MXC_BASE_PMU0 : \
AnnaBridge 167:84c0a372a020 282 (i) == 1 ? MXC_BASE_PMU1 : \
AnnaBridge 167:84c0a372a020 283 (i) == 2 ? MXC_BASE_PMU2 : \
AnnaBridge 167:84c0a372a020 284 (i) == 3 ? MXC_BASE_PMU3 : \
AnnaBridge 167:84c0a372a020 285 (i) == 4 ? MXC_BASE_PMU4 : \
AnnaBridge 167:84c0a372a020 286 (i) == 5 ? MXC_BASE_PMU5 : 0)
AnnaBridge 167:84c0a372a020 287
AnnaBridge 167:84c0a372a020 288 #define MXC_PMU_GET_PMU(i) ((i) == 0 ? MXC_PMU0 : \
AnnaBridge 167:84c0a372a020 289 (i) == 1 ? MXC_PMU1 : \
AnnaBridge 167:84c0a372a020 290 (i) == 2 ? MXC_PMU2 : \
AnnaBridge 167:84c0a372a020 291 (i) == 3 ? MXC_PMU3 : \
AnnaBridge 167:84c0a372a020 292 (i) == 4 ? MXC_PMU4 : \
AnnaBridge 167:84c0a372a020 293 (i) == 5 ? MXC_PMU5 : 0)
AnnaBridge 167:84c0a372a020 294
AnnaBridge 167:84c0a372a020 295 #define MXC_PMU_GET_IDX(p) ((p) == MXC_PMU0 ? 0 : \
AnnaBridge 167:84c0a372a020 296 (p) == MXC_PMU1 ? 1 : \
AnnaBridge 167:84c0a372a020 297 (p) == MXC_PMU2 ? 2 : \
AnnaBridge 167:84c0a372a020 298 (p) == MXC_PMU3 ? 3 : \
AnnaBridge 167:84c0a372a020 299 (p) == MXC_PMU4 ? 4 : \
AnnaBridge 167:84c0a372a020 300 (p) == MXC_PMU5 ? 5 : -1)
AnnaBridge 167:84c0a372a020 301
AnnaBridge 167:84c0a372a020 302 /*******************************************************************************/
AnnaBridge 167:84c0a372a020 303 /* USB Device Controller */
AnnaBridge 167:84c0a372a020 304
AnnaBridge 167:84c0a372a020 305 #define MXC_BASE_USB ((uint32_t)0x40100000UL)
AnnaBridge 167:84c0a372a020 306 #define MXC_USB ((mxc_usb_regs_t *)MXC_BASE_USB)
AnnaBridge 167:84c0a372a020 307
AnnaBridge 167:84c0a372a020 308 #define MXC_USB_MAX_PACKET (64)
AnnaBridge 167:84c0a372a020 309 #define MXC_USB_NUM_EP (8)
AnnaBridge 167:84c0a372a020 310
AnnaBridge 167:84c0a372a020 311
AnnaBridge 167:84c0a372a020 312
AnnaBridge 167:84c0a372a020 313 /*******************************************************************************/
AnnaBridge 167:84c0a372a020 314 /* CRC-16/CRC-32 Engine */
AnnaBridge 167:84c0a372a020 315
AnnaBridge 167:84c0a372a020 316 #define MXC_BASE_CRC ((uint32_t)0x40006000UL)
AnnaBridge 167:84c0a372a020 317 #define MXC_CRC ((mxc_crc_regs_t *)MXC_BASE_CRC)
AnnaBridge 167:84c0a372a020 318 #define MXC_BASE_CRC_DATA ((uint32_t)0x40101000UL)
AnnaBridge 167:84c0a372a020 319 #define MXC_CRC_DATA ((mxc_crc_data_regs_t *)MXC_BASE_CRC_DATA)
AnnaBridge 167:84c0a372a020 320
AnnaBridge 167:84c0a372a020 321 /*******************************************************************************/
AnnaBridge 167:84c0a372a020 322 /* Pseudo-random number generator (PRNG) */
AnnaBridge 167:84c0a372a020 323
AnnaBridge 167:84c0a372a020 324 #define MXC_BASE_PRNG ((uint32_t)0x40007000UL)
AnnaBridge 167:84c0a372a020 325 #define MXC_PRNG ((mxc_prng_regs_t *)MXC_BASE_PRNG)
AnnaBridge 167:84c0a372a020 326
AnnaBridge 167:84c0a372a020 327 /*******************************************************************************/
AnnaBridge 167:84c0a372a020 328 /* AES Cryptographic Engine */
AnnaBridge 167:84c0a372a020 329
AnnaBridge 167:84c0a372a020 330 #define MXC_BASE_AES ((uint32_t)0x40007400UL)
AnnaBridge 167:84c0a372a020 331 #define MXC_AES ((mxc_aes_regs_t *)MXC_BASE_AES)
AnnaBridge 167:84c0a372a020 332 #define MXC_BASE_AES_MEM ((uint32_t)0x40102000UL)
AnnaBridge 167:84c0a372a020 333 #define MXC_AES_MEM ((mxc_aes_mem_regs_t *)MXC_BASE_AES_MEM)
AnnaBridge 167:84c0a372a020 334
AnnaBridge 167:84c0a372a020 335 /*******************************************************************************/
AnnaBridge 167:84c0a372a020 336 /* MAA Cryptographic Engine */
AnnaBridge 167:84c0a372a020 337
AnnaBridge 167:84c0a372a020 338 #define MXC_BASE_MAA ((uint32_t)0x40007800UL)
AnnaBridge 167:84c0a372a020 339 #define MXC_MAA ((mxc_maa_regs_t *)MXC_BASE_MAA)
AnnaBridge 167:84c0a372a020 340 #define MXC_BASE_MAA_MEM ((uint32_t)0x40102800UL)
AnnaBridge 167:84c0a372a020 341 #define MXC_MAA_MEM ((mxc_maa_mem_regs_t *)MXC_BASE_MAA_MEM)
AnnaBridge 167:84c0a372a020 342
AnnaBridge 167:84c0a372a020 343 /*******************************************************************************/
AnnaBridge 167:84c0a372a020 344 /* Trust Protection Unit (TPU) */
AnnaBridge 167:84c0a372a020 345
AnnaBridge 167:84c0a372a020 346 #define MXC_BASE_TPU ((uint32_t)0x40007000UL)
AnnaBridge 167:84c0a372a020 347 #define MXC_TPU ((mxc_tpu_regs_t *)MXC_BASE_TPU)
AnnaBridge 167:84c0a372a020 348 #define MXC_BASE_TPU_TSR ((uint32_t)0x40007C00UL)
AnnaBridge 167:84c0a372a020 349 #define MXC_TPU_TSR ((mxc_tpu_tsr_regs_t *)MXC_BASE_TPU_TSR)
AnnaBridge 167:84c0a372a020 350
AnnaBridge 167:84c0a372a020 351 /*******************************************************************************/
AnnaBridge 167:84c0a372a020 352 /* Watchdog Timers */
AnnaBridge 167:84c0a372a020 353
AnnaBridge 167:84c0a372a020 354 #define MXC_CFG_WDT_INSTANCES (2)
AnnaBridge 167:84c0a372a020 355
AnnaBridge 167:84c0a372a020 356 #define MXC_BASE_WDT0 ((uint32_t)0x40008000UL)
AnnaBridge 167:84c0a372a020 357 #define MXC_WDT0 ((mxc_wdt_regs_t *)MXC_BASE_WDT0)
AnnaBridge 167:84c0a372a020 358 #define MXC_BASE_WDT1 ((uint32_t)0x40009000UL)
AnnaBridge 167:84c0a372a020 359 #define MXC_WDT1 ((mxc_wdt_regs_t *)MXC_BASE_WDT1)
AnnaBridge 167:84c0a372a020 360
AnnaBridge 167:84c0a372a020 361 #define MXC_WDT_GET_IRQ(i) (IRQn_Type)((i) == 0 ? WDT0_IRQn : \
AnnaBridge 167:84c0a372a020 362 (i) == 1 ? WDT1_IRQn : 0)
AnnaBridge 167:84c0a372a020 363
AnnaBridge 167:84c0a372a020 364 #define MXC_WDT_GET_IRQ_P(i) (IRQn_Type)((i) == 0 ? WDT0_P_IRQn : \
AnnaBridge 167:84c0a372a020 365 (i) == 1 ? WDT1_P_IRQn : 0)
AnnaBridge 167:84c0a372a020 366
AnnaBridge 167:84c0a372a020 367 #define MXC_WDT_GET_BASE(i) ((i) == 0 ? MXC_BASE_WDT0 : \
AnnaBridge 167:84c0a372a020 368 (i) == 1 ? MXC_BASE_WDT1 : 0)
AnnaBridge 167:84c0a372a020 369
AnnaBridge 167:84c0a372a020 370 #define MXC_WDT_GET_WDT(i) ((i) == 0 ? MXC_WDT0 : \
AnnaBridge 167:84c0a372a020 371 (i) == 1 ? MXC_WDT1 : 0)
AnnaBridge 167:84c0a372a020 372
AnnaBridge 167:84c0a372a020 373 #define MXC_WDT_GET_IDX(i) ((i) == MXC_WDT0 ? 0: \
AnnaBridge 167:84c0a372a020 374 (i) == MXC_WDT1 ? 1: -1)
AnnaBridge 167:84c0a372a020 375
AnnaBridge 167:84c0a372a020 376
AnnaBridge 167:84c0a372a020 377 /*******************************************************************************/
AnnaBridge 167:84c0a372a020 378 /* Always-On Watchdog Timer */
AnnaBridge 167:84c0a372a020 379
AnnaBridge 167:84c0a372a020 380 #define MXC_BASE_WDT2 ((uint32_t)0x40007C60UL)
AnnaBridge 167:84c0a372a020 381 #define MXC_WDT2 ((mxc_wdt2_regs_t *)MXC_BASE_WDT2)
AnnaBridge 167:84c0a372a020 382
AnnaBridge 167:84c0a372a020 383
AnnaBridge 167:84c0a372a020 384
AnnaBridge 167:84c0a372a020 385 /*******************************************************************************/
AnnaBridge 167:84c0a372a020 386 /* General Purpose I/O Ports (GPIO) */
AnnaBridge 167:84c0a372a020 387
AnnaBridge 167:84c0a372a020 388 #define MXC_GPIO_NUM_PORTS (7)
AnnaBridge 167:84c0a372a020 389 #define MXC_GPIO_MAX_PINS_PER_PORT (8)
AnnaBridge 167:84c0a372a020 390
AnnaBridge 167:84c0a372a020 391 #define MXC_BASE_GPIO ((uint32_t)0x4000A000UL)
AnnaBridge 167:84c0a372a020 392 #define MXC_GPIO ((mxc_gpio_regs_t *)MXC_BASE_GPIO)
AnnaBridge 167:84c0a372a020 393
AnnaBridge 167:84c0a372a020 394 #define MXC_GPIO_GET_IRQ(i) (IRQn_Type)((i) == 0 ? GPIO_P0_IRQn : \
AnnaBridge 167:84c0a372a020 395 (i) == 1 ? GPIO_P1_IRQn : \
AnnaBridge 167:84c0a372a020 396 (i) == 2 ? GPIO_P2_IRQn : \
AnnaBridge 167:84c0a372a020 397 (i) == 3 ? GPIO_P3_IRQn : \
AnnaBridge 167:84c0a372a020 398 (i) == 4 ? GPIO_P4_IRQn : \
AnnaBridge 167:84c0a372a020 399 (i) == 5 ? GPIO_P5_IRQn : \
AnnaBridge 167:84c0a372a020 400 (i) == 6 ? GPIO_P6_IRQn : \
AnnaBridge 167:84c0a372a020 401 (i) == 7 ? GPIO_P7_IRQn : \
AnnaBridge 167:84c0a372a020 402 (i) == 8 ? GPIO_P8_IRQn : 0)
AnnaBridge 167:84c0a372a020 403
AnnaBridge 167:84c0a372a020 404
AnnaBridge 167:84c0a372a020 405
AnnaBridge 167:84c0a372a020 406 /*******************************************************************************/
AnnaBridge 167:84c0a372a020 407 /* 16/32 bit Timer/Counters */
AnnaBridge 167:84c0a372a020 408
AnnaBridge 167:84c0a372a020 409 #define MXC_CFG_TMR_INSTANCES (6)
AnnaBridge 167:84c0a372a020 410
AnnaBridge 167:84c0a372a020 411 #define MXC_BASE_TMR0 ((uint32_t)0x4000B000UL)
AnnaBridge 167:84c0a372a020 412 #define MXC_TMR0 ((mxc_tmr_regs_t *)MXC_BASE_TMR0)
AnnaBridge 167:84c0a372a020 413 #define MXC_BASE_TMR1 ((uint32_t)0x4000C000UL)
AnnaBridge 167:84c0a372a020 414 #define MXC_TMR1 ((mxc_tmr_regs_t *)MXC_BASE_TMR1)
AnnaBridge 167:84c0a372a020 415 #define MXC_BASE_TMR2 ((uint32_t)0x4000D000UL)
AnnaBridge 167:84c0a372a020 416 #define MXC_TMR2 ((mxc_tmr_regs_t *)MXC_BASE_TMR2)
AnnaBridge 167:84c0a372a020 417 #define MXC_BASE_TMR3 ((uint32_t)0x4000E000UL)
AnnaBridge 167:84c0a372a020 418 #define MXC_TMR3 ((mxc_tmr_regs_t *)MXC_BASE_TMR3)
AnnaBridge 167:84c0a372a020 419 #define MXC_BASE_TMR4 ((uint32_t)0x4000F000UL)
AnnaBridge 167:84c0a372a020 420 #define MXC_TMR4 ((mxc_tmr_regs_t *)MXC_BASE_TMR4)
AnnaBridge 167:84c0a372a020 421 #define MXC_BASE_TMR5 ((uint32_t)0x40010000UL)
AnnaBridge 167:84c0a372a020 422 #define MXC_TMR5 ((mxc_tmr_regs_t *)MXC_BASE_TMR5)
AnnaBridge 167:84c0a372a020 423
AnnaBridge 167:84c0a372a020 424 #define MXC_TMR_GET_IRQ_32(i) (IRQn_Type)((i) == 0 ? TMR0_0_IRQn : \
AnnaBridge 167:84c0a372a020 425 (i) == 1 ? TMR1_0_IRQn : \
AnnaBridge 167:84c0a372a020 426 (i) == 2 ? TMR2_0_IRQn : \
AnnaBridge 167:84c0a372a020 427 (i) == 3 ? TMR3_0_IRQn : \
AnnaBridge 167:84c0a372a020 428 (i) == 4 ? TMR4_0_IRQn : \
AnnaBridge 167:84c0a372a020 429 (i) == 5 ? TMR5_0_IRQn : 0)
AnnaBridge 167:84c0a372a020 430
AnnaBridge 167:84c0a372a020 431 #define MXC_TMR_GET_IRQ_16(i) (IRQn_Type)((i) == 0 ? TMR0_0_IRQn : \
AnnaBridge 167:84c0a372a020 432 (i) == 1 ? TMR1_0_IRQn : \
AnnaBridge 167:84c0a372a020 433 (i) == 2 ? TMR2_0_IRQn : \
AnnaBridge 167:84c0a372a020 434 (i) == 3 ? TMR3_0_IRQn : \
AnnaBridge 167:84c0a372a020 435 (i) == 4 ? TMR4_0_IRQn : \
AnnaBridge 167:84c0a372a020 436 (i) == 5 ? TMR5_0_IRQn : \
AnnaBridge 167:84c0a372a020 437 (i) == 6 ? TMR0_1_IRQn : \
AnnaBridge 167:84c0a372a020 438 (i) == 7 ? TMR1_1_IRQn : \
AnnaBridge 167:84c0a372a020 439 (i) == 8 ? TMR2_1_IRQn : \
AnnaBridge 167:84c0a372a020 440 (i) == 9 ? TMR3_1_IRQn : \
AnnaBridge 167:84c0a372a020 441 (i) == 10 ? TMR4_1_IRQn : \
AnnaBridge 167:84c0a372a020 442 (i) == 11 ? TMR5_1_IRQn : 0)
AnnaBridge 167:84c0a372a020 443
AnnaBridge 167:84c0a372a020 444 #define MXC_TMR_GET_BASE(i) ((i) == 0 ? MXC_BASE_TMR0 : \
AnnaBridge 167:84c0a372a020 445 (i) == 1 ? MXC_BASE_TMR1 : \
AnnaBridge 167:84c0a372a020 446 (i) == 2 ? MXC_BASE_TMR2 : \
AnnaBridge 167:84c0a372a020 447 (i) == 3 ? MXC_BASE_TMR3 : \
AnnaBridge 167:84c0a372a020 448 (i) == 4 ? MXC_BASE_TMR4 : \
AnnaBridge 167:84c0a372a020 449 (i) == 5 ? MXC_BASE_TMR5 : 0)
AnnaBridge 167:84c0a372a020 450
AnnaBridge 167:84c0a372a020 451 #define MXC_TMR_GET_TMR(i) ((i) == 0 ? MXC_TMR0 : \
AnnaBridge 167:84c0a372a020 452 (i) == 1 ? MXC_TMR1 : \
AnnaBridge 167:84c0a372a020 453 (i) == 2 ? MXC_TMR2 : \
AnnaBridge 167:84c0a372a020 454 (i) == 3 ? MXC_TMR3 : \
AnnaBridge 167:84c0a372a020 455 (i) == 4 ? MXC_TMR4 : \
AnnaBridge 167:84c0a372a020 456 (i) == 5 ? MXC_TMR5 : 0)
AnnaBridge 167:84c0a372a020 457
AnnaBridge 167:84c0a372a020 458 #define MXC_TMR_GET_IDX(p) ((p) == MXC_TMR0 ? 0 : \
AnnaBridge 167:84c0a372a020 459 (p) == MXC_TMR1 ? 1 : \
AnnaBridge 167:84c0a372a020 460 (p) == MXC_TMR2 ? 2 : \
AnnaBridge 167:84c0a372a020 461 (p) == MXC_TMR3 ? 3 : \
AnnaBridge 167:84c0a372a020 462 (p) == MXC_TMR4 ? 4 : \
AnnaBridge 167:84c0a372a020 463 (p) == MXC_TMR5 ? 5 : -1)
AnnaBridge 167:84c0a372a020 464
AnnaBridge 167:84c0a372a020 465
AnnaBridge 167:84c0a372a020 466
AnnaBridge 167:84c0a372a020 467
AnnaBridge 167:84c0a372a020 468 /*******************************************************************************/
AnnaBridge 167:84c0a372a020 469 /* Pulse Train Generation */
AnnaBridge 167:84c0a372a020 470
AnnaBridge 167:84c0a372a020 471 #define MXC_CFG_PT_INSTANCES (16)
AnnaBridge 167:84c0a372a020 472
AnnaBridge 167:84c0a372a020 473 #define MXC_BASE_PTG ((uint32_t)0x40011000UL)
AnnaBridge 167:84c0a372a020 474 #define MXC_PTG ((mxc_ptg_regs_t *)MXC_BASE_PTG)
AnnaBridge 167:84c0a372a020 475 #define MXC_BASE_PT0 ((uint32_t)0x40011020UL)
AnnaBridge 167:84c0a372a020 476 #define MXC_PT0 ((mxc_pt_regs_t *)MXC_BASE_PT0)
AnnaBridge 167:84c0a372a020 477 #define MXC_BASE_PT1 ((uint32_t)0x40011040UL)
AnnaBridge 167:84c0a372a020 478 #define MXC_PT1 ((mxc_pt_regs_t *)MXC_BASE_PT1)
AnnaBridge 167:84c0a372a020 479 #define MXC_BASE_PT2 ((uint32_t)0x40011060UL)
AnnaBridge 167:84c0a372a020 480 #define MXC_PT2 ((mxc_pt_regs_t *)MXC_BASE_PT2)
AnnaBridge 167:84c0a372a020 481 #define MXC_BASE_PT3 ((uint32_t)0x40011080UL)
AnnaBridge 167:84c0a372a020 482 #define MXC_PT3 ((mxc_pt_regs_t *)MXC_BASE_PT3)
AnnaBridge 167:84c0a372a020 483 #define MXC_BASE_PT4 ((uint32_t)0x400110A0UL)
AnnaBridge 167:84c0a372a020 484 #define MXC_PT4 ((mxc_pt_regs_t *)MXC_BASE_PT4)
AnnaBridge 167:84c0a372a020 485 #define MXC_BASE_PT5 ((uint32_t)0x400110C0UL)
AnnaBridge 167:84c0a372a020 486 #define MXC_PT5 ((mxc_pt_regs_t *)MXC_BASE_PT5)
AnnaBridge 167:84c0a372a020 487 #define MXC_BASE_PT6 ((uint32_t)0x400110E0UL)
AnnaBridge 167:84c0a372a020 488 #define MXC_PT6 ((mxc_pt_regs_t *)MXC_BASE_PT6)
AnnaBridge 167:84c0a372a020 489 #define MXC_BASE_PT7 ((uint32_t)0x40011100UL)
AnnaBridge 167:84c0a372a020 490 #define MXC_PT7 ((mxc_pt_regs_t *)MXC_BASE_PT7)
AnnaBridge 167:84c0a372a020 491 #define MXC_BASE_PT8 ((uint32_t)0x40011120UL)
AnnaBridge 167:84c0a372a020 492 #define MXC_PT8 ((mxc_pt_regs_t *)MXC_BASE_PT8)
AnnaBridge 167:84c0a372a020 493 #define MXC_BASE_PT9 ((uint32_t)0x40011140UL)
AnnaBridge 167:84c0a372a020 494 #define MXC_PT9 ((mxc_pt_regs_t *)MXC_BASE_PT9)
AnnaBridge 167:84c0a372a020 495 #define MXC_BASE_PT10 ((uint32_t)0x40011160UL)
AnnaBridge 167:84c0a372a020 496 #define MXC_PT10 ((mxc_pt_regs_t *)MXC_BASE_PT10)
AnnaBridge 167:84c0a372a020 497 #define MXC_BASE_PT11 ((uint32_t)0x40011180UL)
AnnaBridge 167:84c0a372a020 498 #define MXC_PT11 ((mxc_pt_regs_t *)MXC_BASE_PT11)
AnnaBridge 167:84c0a372a020 499 #define MXC_BASE_PT12 ((uint32_t)0x400111A0UL)
AnnaBridge 167:84c0a372a020 500 #define MXC_PT12 ((mxc_pt_regs_t *)MXC_BASE_PT12)
AnnaBridge 167:84c0a372a020 501 #define MXC_BASE_PT13 ((uint32_t)0x400111C0UL)
AnnaBridge 167:84c0a372a020 502 #define MXC_PT13 ((mxc_pt_regs_t *)MXC_BASE_PT13)
AnnaBridge 167:84c0a372a020 503 #define MXC_BASE_PT14 ((uint32_t)0x400111E0UL)
AnnaBridge 167:84c0a372a020 504 #define MXC_PT14 ((mxc_pt_regs_t *)MXC_BASE_PT14)
AnnaBridge 167:84c0a372a020 505 #define MXC_BASE_PT15 ((uint32_t)0x40011200UL)
AnnaBridge 167:84c0a372a020 506 #define MXC_PT15 ((mxc_pt_regs_t *)MXC_BASE_PT15)
AnnaBridge 167:84c0a372a020 507
AnnaBridge 167:84c0a372a020 508 #define MXC_PT_GET_BASE(i) ((i) == 0 ? MXC_BASE_PT0 : \
AnnaBridge 167:84c0a372a020 509 (i) == 1 ? MXC_BASE_PT1 : \
AnnaBridge 167:84c0a372a020 510 (i) == 2 ? MXC_BASE_PT2 : \
AnnaBridge 167:84c0a372a020 511 (i) == 3 ? MXC_BASE_PT3 : \
AnnaBridge 167:84c0a372a020 512 (i) == 4 ? MXC_BASE_PT4 : \
AnnaBridge 167:84c0a372a020 513 (i) == 5 ? MXC_BASE_PT5 : \
AnnaBridge 167:84c0a372a020 514 (i) == 6 ? MXC_BASE_PT6 : \
AnnaBridge 167:84c0a372a020 515 (i) == 7 ? MXC_BASE_PT7 : \
AnnaBridge 167:84c0a372a020 516 (i) == 8 ? MXC_BASE_PT8 : \
AnnaBridge 167:84c0a372a020 517 (i) == 9 ? MXC_BASE_PT9 : \
AnnaBridge 167:84c0a372a020 518 (i) == 10 ? MXC_BASE_PT10 : \
AnnaBridge 167:84c0a372a020 519 (i) == 11 ? MXC_BASE_PT11 : \
AnnaBridge 167:84c0a372a020 520 (i) == 12 ? MXC_BASE_PT12 : \
AnnaBridge 167:84c0a372a020 521 (i) == 13 ? MXC_BASE_PT13 : \
AnnaBridge 167:84c0a372a020 522 (i) == 14 ? MXC_BASE_PT14 : \
AnnaBridge 167:84c0a372a020 523 (i) == 15 ? MXC_BASE_PT15 : 0)
AnnaBridge 167:84c0a372a020 524
AnnaBridge 167:84c0a372a020 525 #define MXC_PT_GET_PT(i) ((i) == 0 ? MXC_PT0 : \
AnnaBridge 167:84c0a372a020 526 (i) == 1 ? MXC_PT1 : \
AnnaBridge 167:84c0a372a020 527 (i) == 2 ? MXC_PT2 : \
AnnaBridge 167:84c0a372a020 528 (i) == 3 ? MXC_PT3 : \
AnnaBridge 167:84c0a372a020 529 (i) == 4 ? MXC_PT4 : \
AnnaBridge 167:84c0a372a020 530 (i) == 5 ? MXC_PT5 : \
AnnaBridge 167:84c0a372a020 531 (i) == 6 ? MXC_PT6 : \
AnnaBridge 167:84c0a372a020 532 (i) == 7 ? MXC_PT7 : \
AnnaBridge 167:84c0a372a020 533 (i) == 8 ? MXC_PT8 : \
AnnaBridge 167:84c0a372a020 534 (i) == 9 ? MXC_PT9 : \
AnnaBridge 167:84c0a372a020 535 (i) == 10 ? MXC_PT10 : \
AnnaBridge 167:84c0a372a020 536 (i) == 11 ? MXC_PT11 : \
AnnaBridge 167:84c0a372a020 537 (i) == 12 ? MXC_PT12 : \
AnnaBridge 167:84c0a372a020 538 (i) == 13 ? MXC_PT13 : \
AnnaBridge 167:84c0a372a020 539 (i) == 14 ? MXC_PT14 : \
AnnaBridge 167:84c0a372a020 540 (i) == 15 ? MXC_PT15 : 0)
AnnaBridge 167:84c0a372a020 541
AnnaBridge 167:84c0a372a020 542 #define MXC_PT_GET_IDX(p) ((p) == MXC_PT0 ? 0 : \
AnnaBridge 167:84c0a372a020 543 (p) == MXC_PT1 ? 1 : \
AnnaBridge 167:84c0a372a020 544 (p) == MXC_PT2 ? 2 : \
AnnaBridge 167:84c0a372a020 545 (p) == MXC_PT3 ? 3 : \
AnnaBridge 167:84c0a372a020 546 (p) == MXC_PT4 ? 4 : \
AnnaBridge 167:84c0a372a020 547 (p) == MXC_PT5 ? 5 : \
AnnaBridge 167:84c0a372a020 548 (p) == MXC_PT6 ? 6 : \
AnnaBridge 167:84c0a372a020 549 (p) == MXC_PT7 ? 7 : \
AnnaBridge 167:84c0a372a020 550 (p) == MXC_PT8 ? 8 : \
AnnaBridge 167:84c0a372a020 551 (p) == MXC_PT9 ? 9 : \
AnnaBridge 167:84c0a372a020 552 (p) == MXC_PT10 ? 10 : \
AnnaBridge 167:84c0a372a020 553 (p) == MXC_PT11 ? 11 : \
AnnaBridge 167:84c0a372a020 554 (p) == MXC_PT12 ? 12 : \
AnnaBridge 167:84c0a372a020 555 (p) == MXC_PT13 ? 13 : \
AnnaBridge 167:84c0a372a020 556 (p) == MXC_PT14 ? 14 : \
AnnaBridge 167:84c0a372a020 557 (p) == MXC_PT15 ? 15 : -1)
AnnaBridge 167:84c0a372a020 558
AnnaBridge 167:84c0a372a020 559
AnnaBridge 167:84c0a372a020 560
AnnaBridge 167:84c0a372a020 561 /*******************************************************************************/
AnnaBridge 167:84c0a372a020 562 /* UART / Serial Port Interface */
AnnaBridge 167:84c0a372a020 563
AnnaBridge 167:84c0a372a020 564 #define MXC_CFG_UART_INSTANCES (4)
AnnaBridge 167:84c0a372a020 565 #define MXC_UART_FIFO_DEPTH (32)
AnnaBridge 167:84c0a372a020 566
AnnaBridge 167:84c0a372a020 567 #define MXC_BASE_UART0 ((uint32_t)0x40012000UL)
AnnaBridge 167:84c0a372a020 568 #define MXC_UART0 ((mxc_uart_regs_t *)MXC_BASE_UART0)
AnnaBridge 167:84c0a372a020 569 #define MXC_BASE_UART1 ((uint32_t)0x40013000UL)
AnnaBridge 167:84c0a372a020 570 #define MXC_UART1 ((mxc_uart_regs_t *)MXC_BASE_UART1)
AnnaBridge 167:84c0a372a020 571 #define MXC_BASE_UART2 ((uint32_t)0x40014000UL)
AnnaBridge 167:84c0a372a020 572 #define MXC_UART2 ((mxc_uart_regs_t *)MXC_BASE_UART2)
AnnaBridge 167:84c0a372a020 573 #define MXC_BASE_UART3 ((uint32_t)0x40015000UL)
AnnaBridge 167:84c0a372a020 574 #define MXC_UART3 ((mxc_uart_regs_t *)MXC_BASE_UART3)
AnnaBridge 167:84c0a372a020 575 #define MXC_BASE_UART0_FIFO ((uint32_t)0x40103000UL)
AnnaBridge 167:84c0a372a020 576 #define MXC_UART0_FIFO ((mxc_uart_fifo_regs_t *)MXC_BASE_UART0_FIFO)
AnnaBridge 167:84c0a372a020 577 #define MXC_BASE_UART1_FIFO ((uint32_t)0x40104000UL)
AnnaBridge 167:84c0a372a020 578 #define MXC_UART1_FIFO ((mxc_uart_fifo_regs_t *)MXC_BASE_UART1_FIFO)
AnnaBridge 167:84c0a372a020 579 #define MXC_BASE_UART2_FIFO ((uint32_t)0x40105000UL)
AnnaBridge 167:84c0a372a020 580 #define MXC_UART2_FIFO ((mxc_uart_fifo_regs_t *)MXC_BASE_UART2_FIFO)
AnnaBridge 167:84c0a372a020 581 #define MXC_BASE_UART3_FIFO ((uint32_t)0x40106000UL)
AnnaBridge 167:84c0a372a020 582 #define MXC_UART3_FIFO ((mxc_uart_fifo_regs_t *)MXC_BASE_UART3_FIFO)
AnnaBridge 167:84c0a372a020 583
AnnaBridge 167:84c0a372a020 584 #define MXC_UART_GET_IRQ(i) (IRQn_Type)((i) == 0 ? UART0_IRQn : \
AnnaBridge 167:84c0a372a020 585 (i) == 1 ? UART1_IRQn : \
AnnaBridge 167:84c0a372a020 586 (i) == 2 ? UART2_IRQn : \
AnnaBridge 167:84c0a372a020 587 (i) == 3 ? UART3_IRQn : 0)
AnnaBridge 167:84c0a372a020 588
AnnaBridge 167:84c0a372a020 589 #define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0 : \
AnnaBridge 167:84c0a372a020 590 (i) == 1 ? MXC_BASE_UART1 : \
AnnaBridge 167:84c0a372a020 591 (i) == 2 ? MXC_BASE_UART2 : \
AnnaBridge 167:84c0a372a020 592 (i) == 3 ? MXC_BASE_UART3 : 0)
AnnaBridge 167:84c0a372a020 593
AnnaBridge 167:84c0a372a020 594 #define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : \
AnnaBridge 167:84c0a372a020 595 (i) == 1 ? MXC_UART1 : \
AnnaBridge 167:84c0a372a020 596 (i) == 2 ? MXC_UART2 : \
AnnaBridge 167:84c0a372a020 597 (i) == 3 ? MXC_UART3 : 0)
AnnaBridge 167:84c0a372a020 598
AnnaBridge 167:84c0a372a020 599 #define MXC_UART_GET_IDX(p) ((p) == MXC_UART0 ? 0 : \
AnnaBridge 167:84c0a372a020 600 (p) == MXC_UART1 ? 1 : \
AnnaBridge 167:84c0a372a020 601 (p) == MXC_UART2 ? 2 : \
AnnaBridge 167:84c0a372a020 602 (p) == MXC_UART3 ? 3 : -1)
AnnaBridge 167:84c0a372a020 603
AnnaBridge 167:84c0a372a020 604 #define MXC_UART_GET_BASE_FIFO(i) ((i) == 0 ? MXC_BASE_UART0_FIFO : \
AnnaBridge 167:84c0a372a020 605 (i) == 1 ? MXC_BASE_UART1_FIFO : \
AnnaBridge 167:84c0a372a020 606 (i) == 2 ? MXC_BASE_UART2_FIFO : \
AnnaBridge 167:84c0a372a020 607 (i) == 3 ? MXC_BASE_UART3_FIFO : 0)
AnnaBridge 167:84c0a372a020 608
AnnaBridge 167:84c0a372a020 609 #define MXC_UART_GET_FIFO(i) ((i) == 0 ? MXC_UART0_FIFO : \
AnnaBridge 167:84c0a372a020 610 (i) == 1 ? MXC_UART1_FIFO : \
AnnaBridge 167:84c0a372a020 611 (i) == 2 ? MXC_UART2_FIFO : \
AnnaBridge 167:84c0a372a020 612 (i) == 3 ? MXC_UART3_FIFO : 0)
AnnaBridge 167:84c0a372a020 613
AnnaBridge 167:84c0a372a020 614
AnnaBridge 167:84c0a372a020 615
AnnaBridge 167:84c0a372a020 616 /*******************************************************************************/
AnnaBridge 167:84c0a372a020 617 /* I2C Master Interface */
AnnaBridge 167:84c0a372a020 618
AnnaBridge 167:84c0a372a020 619 #define MXC_CFG_I2CM_INSTANCES (3)
AnnaBridge 167:84c0a372a020 620 #define MXC_I2CM_FIFO_DEPTH (8)
AnnaBridge 167:84c0a372a020 621
AnnaBridge 167:84c0a372a020 622 #define MXC_BASE_I2CM0 ((uint32_t)0x40016000UL)
AnnaBridge 167:84c0a372a020 623 #define MXC_I2CM0 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM0)
AnnaBridge 167:84c0a372a020 624 #define MXC_BASE_I2CM1 ((uint32_t)0x40017000UL)
AnnaBridge 167:84c0a372a020 625 #define MXC_I2CM1 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM1)
AnnaBridge 167:84c0a372a020 626 #define MXC_BASE_I2CM2 ((uint32_t)0x40018000UL)
AnnaBridge 167:84c0a372a020 627 #define MXC_I2CM2 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM2)
AnnaBridge 167:84c0a372a020 628 #define MXC_BASE_I2CM0_FIFO ((uint32_t)0x40107000UL)
AnnaBridge 167:84c0a372a020 629 #define MXC_I2CM0_FIFO ((mxc_i2cm_fifo_regs_t *)MXC_BASE_I2CM0_FIFO)
AnnaBridge 167:84c0a372a020 630 #define MXC_BASE_I2CM1_FIFO ((uint32_t)0x40108000UL)
AnnaBridge 167:84c0a372a020 631 #define MXC_I2CM1_FIFO ((mxc_i2cm_fifo_regs_t *)MXC_BASE_I2CM1_FIFO)
AnnaBridge 167:84c0a372a020 632 #define MXC_BASE_I2CM2_FIFO ((uint32_t)0x40109000UL)
AnnaBridge 167:84c0a372a020 633 #define MXC_I2CM2_FIFO ((mxc_i2cm_fifo_regs_t *)MXC_BASE_I2CM2_FIFO)
AnnaBridge 167:84c0a372a020 634
AnnaBridge 167:84c0a372a020 635 #define MXC_I2CM_GET_IRQ(i) (IRQn_Type)((i) == 0 ? I2CM0_IRQn : \
AnnaBridge 167:84c0a372a020 636 (i) == 1 ? I2CM1_IRQn : \
AnnaBridge 167:84c0a372a020 637 (i) == 2 ? I2CM2_IRQn : 0)
AnnaBridge 167:84c0a372a020 638
AnnaBridge 167:84c0a372a020 639 #define MXC_I2CM_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2CM0 : \
AnnaBridge 167:84c0a372a020 640 (i) == 1 ? MXC_BASE_I2CM1 : \
AnnaBridge 167:84c0a372a020 641 (i) == 2 ? MXC_BASE_I2CM2 : 0)
AnnaBridge 167:84c0a372a020 642
AnnaBridge 167:84c0a372a020 643 #define MXC_I2CM_GET_I2CM(i) ((i) == 0 ? MXC_I2CM0 : \
AnnaBridge 167:84c0a372a020 644 (i) == 1 ? MXC_I2CM1 : \
AnnaBridge 167:84c0a372a020 645 (i) == 2 ? MXC_I2CM2 : 0)
AnnaBridge 167:84c0a372a020 646
AnnaBridge 167:84c0a372a020 647 #define MXC_I2CM_GET_IDX(p) ((p) == MXC_I2CM0 ? 0 : \
AnnaBridge 167:84c0a372a020 648 (p) == MXC_I2CM1 ? 1 : \
AnnaBridge 167:84c0a372a020 649 (p) == MXC_I2CM2 ? 2 : -1)
AnnaBridge 167:84c0a372a020 650
AnnaBridge 167:84c0a372a020 651 #define MXC_I2CM_GET_BASE_FIFO(i) ((i) == 0 ? MXC_BASE_I2CM0_FIFO : \
AnnaBridge 167:84c0a372a020 652 (i) == 1 ? MXC_BASE_I2CM1_FIFO : \
AnnaBridge 167:84c0a372a020 653 (i) == 2 ? MXC_BASE_I2CM2_FIFO : 0)
AnnaBridge 167:84c0a372a020 654
AnnaBridge 167:84c0a372a020 655 #define MXC_I2CM_GET_FIFO(i) ((i) == 0 ? MXC_I2CM0_FIFO : \
AnnaBridge 167:84c0a372a020 656 (i) == 1 ? MXC_I2CM1_FIFO : \
AnnaBridge 167:84c0a372a020 657 (i) == 2 ? MXC_I2CM2_FIFO : 0)
AnnaBridge 167:84c0a372a020 658
AnnaBridge 167:84c0a372a020 659 /*******************************************************************************/
AnnaBridge 167:84c0a372a020 660 /* I2C Slave Interface (Mailbox type) */
AnnaBridge 167:84c0a372a020 661
AnnaBridge 167:84c0a372a020 662 #define MXC_CFG_I2CS_INSTANCES (1)
AnnaBridge 167:84c0a372a020 663 #define MXC_CFG_I2CS_BUFFER_SIZE (32)
AnnaBridge 167:84c0a372a020 664
AnnaBridge 167:84c0a372a020 665 #define MXC_BASE_I2CS ((uint32_t)0x40019000UL)
AnnaBridge 167:84c0a372a020 666 #define MXC_I2CS ((mxc_i2cs_regs_t *)MXC_BASE_I2CS)
AnnaBridge 167:84c0a372a020 667
AnnaBridge 167:84c0a372a020 668 #define MXC_I2CS_GET_IRQ(i) (IRQn_Type)((i) == 0 ? I2CS_IRQn : 0)
AnnaBridge 167:84c0a372a020 669
AnnaBridge 167:84c0a372a020 670 #define MXC_I2CS_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2CS : 0)
AnnaBridge 167:84c0a372a020 671
AnnaBridge 167:84c0a372a020 672 #define MXC_I2CS_GET_I2CS(i) ((i) == 0 ? MXC_I2CS : 0)
AnnaBridge 167:84c0a372a020 673
AnnaBridge 167:84c0a372a020 674 #define MXC_I2CS_GET_IDX(p) ((p) == MXC_I2CS ? 0 : -1)
AnnaBridge 167:84c0a372a020 675
AnnaBridge 167:84c0a372a020 676 /*******************************************************************************/
AnnaBridge 167:84c0a372a020 677 /* SPI Master Interface */
AnnaBridge 167:84c0a372a020 678
AnnaBridge 167:84c0a372a020 679 #define MXC_CFG_SPIM_INSTANCES (3)
AnnaBridge 167:84c0a372a020 680 #define MXC_CFG_SPIM_FIFO_DEPTH (16)
AnnaBridge 167:84c0a372a020 681
AnnaBridge 167:84c0a372a020 682 #define MXC_BASE_SPIM0 ((uint32_t)0x4001A000UL)
AnnaBridge 167:84c0a372a020 683 #define MXC_SPIM0 ((mxc_spim_regs_t *)MXC_BASE_SPIM0)
AnnaBridge 167:84c0a372a020 684 #define MXC_BASE_SPIM1 ((uint32_t)0x4001B000UL)
AnnaBridge 167:84c0a372a020 685 #define MXC_SPIM1 ((mxc_spim_regs_t *)MXC_BASE_SPIM1)
AnnaBridge 167:84c0a372a020 686 #define MXC_BASE_SPIM2 ((uint32_t)0x4001C000UL)
AnnaBridge 167:84c0a372a020 687 #define MXC_SPIM2 ((mxc_spim_regs_t *)MXC_BASE_SPIM2)
AnnaBridge 167:84c0a372a020 688 #define MXC_BASE_SPIM0_FIFO ((uint32_t)0x4010A000UL)
AnnaBridge 167:84c0a372a020 689 #define MXC_SPIM0_FIFO ((mxc_spim_fifo_regs_t *)MXC_BASE_SPIM0_FIFO)
AnnaBridge 167:84c0a372a020 690 #define MXC_BASE_SPIM1_FIFO ((uint32_t)0x4010B000UL)
AnnaBridge 167:84c0a372a020 691 #define MXC_SPIM1_FIFO ((mxc_spim_fifo_regs_t *)MXC_BASE_SPIM1_FIFO)
AnnaBridge 167:84c0a372a020 692 #define MXC_BASE_SPIM2_FIFO ((uint32_t)0x4010C000UL)
AnnaBridge 167:84c0a372a020 693 #define MXC_SPIM2_FIFO ((mxc_spim_fifo_regs_t *)MXC_BASE_SPIM2_FIFO)
AnnaBridge 167:84c0a372a020 694
AnnaBridge 167:84c0a372a020 695 #define MXC_SPIM_GET_IRQ(i) (IRQn_Type)((i) == 0 ? SPIM0_IRQn : \
AnnaBridge 167:84c0a372a020 696 (i) == 1 ? SPIM1_IRQn : \
AnnaBridge 167:84c0a372a020 697 (i) == 2 ? SPIM2_IRQn : 0)
AnnaBridge 167:84c0a372a020 698
AnnaBridge 167:84c0a372a020 699 #define MXC_SPIM_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPIM0 : \
AnnaBridge 167:84c0a372a020 700 (i) == 1 ? MXC_BASE_SPIM1 : \
AnnaBridge 167:84c0a372a020 701 (i) == 2 ? MXC_BASE_SPIM2 : 0)
AnnaBridge 167:84c0a372a020 702
AnnaBridge 167:84c0a372a020 703 #define MXC_SPIM_GET_SPIM(i) ((i) == 0 ? MXC_SPIM0 : \
AnnaBridge 167:84c0a372a020 704 (i) == 1 ? MXC_SPIM1 : \
AnnaBridge 167:84c0a372a020 705 (i) == 2 ? MXC_SPIM2 : 0)
AnnaBridge 167:84c0a372a020 706
AnnaBridge 167:84c0a372a020 707 #define MXC_SPIM_GET_IDX(p) ((p) == MXC_SPIM0 ? 0 : \
AnnaBridge 167:84c0a372a020 708 (p) == MXC_SPIM1 ? 1 : \
AnnaBridge 167:84c0a372a020 709 (p) == MXC_SPIM2 ? 2 : -1)
AnnaBridge 167:84c0a372a020 710
AnnaBridge 167:84c0a372a020 711 #define MXC_SPIM_GET_BASE_FIFO(i) ((i) == 0 ? MXC_BASE_SPIM0_FIFO : \
AnnaBridge 167:84c0a372a020 712 (i) == 1 ? MXC_BASE_SPIM1_FIFO : \
AnnaBridge 167:84c0a372a020 713 (i) == 2 ? MXC_BASE_SPIM2_FIFO : 0)
AnnaBridge 167:84c0a372a020 714
AnnaBridge 167:84c0a372a020 715 #define MXC_SPIM_GET_SPIM_FIFO(i) ((i) == 0 ? MXC_SPIM0_FIFO : \
AnnaBridge 167:84c0a372a020 716 (i) == 1 ? MXC_SPIM1_FIFO : \
AnnaBridge 167:84c0a372a020 717 (i) == 2 ? MXC_SPIM2_FIFO : 0)
AnnaBridge 167:84c0a372a020 718
AnnaBridge 167:84c0a372a020 719
AnnaBridge 167:84c0a372a020 720
AnnaBridge 167:84c0a372a020 721 /*******************************************************************************/
AnnaBridge 167:84c0a372a020 722 /* 1-Wire Master Interface */
AnnaBridge 167:84c0a372a020 723
AnnaBridge 167:84c0a372a020 724 #define MXC_CFG_OWM_INSTANCES (1)
AnnaBridge 167:84c0a372a020 725
AnnaBridge 167:84c0a372a020 726 #define MXC_BASE_OWM ((uint32_t)0x4001E000UL)
AnnaBridge 167:84c0a372a020 727 #define MXC_OWM ((mxc_owm_regs_t *)MXC_BASE_OWM)
AnnaBridge 167:84c0a372a020 728
AnnaBridge 167:84c0a372a020 729 #define MXC_OWM_GET_IRQ(i) (IRQn_Type)((i) == 0 ? OWM_IRQn : 0)
AnnaBridge 167:84c0a372a020 730
AnnaBridge 167:84c0a372a020 731 #define MXC_OWM_GET_BASE(i) ((i) == 0 ? MXC_BASE_OWM : 0)
AnnaBridge 167:84c0a372a020 732
AnnaBridge 167:84c0a372a020 733 #define MXC_OWM_GET_OWM(i) ((i) == 0 ? MXC_OWM : 0)
AnnaBridge 167:84c0a372a020 734
AnnaBridge 167:84c0a372a020 735 #define MXC_OWM_GET_IDX(p) ((p) == MXC_OWM ? 0 : -1)
AnnaBridge 167:84c0a372a020 736
AnnaBridge 167:84c0a372a020 737
AnnaBridge 167:84c0a372a020 738 /*******************************************************************************/
AnnaBridge 167:84c0a372a020 739 /* ADC / AFE */
AnnaBridge 167:84c0a372a020 740
AnnaBridge 167:84c0a372a020 741 #define MXC_CFG_ADC_FIFO_DEPTH (32)
AnnaBridge 167:84c0a372a020 742
AnnaBridge 167:84c0a372a020 743 #define MXC_BASE_ADC ((uint32_t)0x4001F000UL)
AnnaBridge 167:84c0a372a020 744 #define MXC_ADC ((mxc_adc_regs_t *)MXC_BASE_ADC)
AnnaBridge 167:84c0a372a020 745
AnnaBridge 167:84c0a372a020 746
AnnaBridge 167:84c0a372a020 747
AnnaBridge 167:84c0a372a020 748 /*******************************************************************************/
AnnaBridge 167:84c0a372a020 749 /* SPIB AHB-to-SPI Bridge */
AnnaBridge 167:84c0a372a020 750
AnnaBridge 167:84c0a372a020 751 #define MXC_BASE_SPIB ((uint32_t)0x4000D000UL)
AnnaBridge 167:84c0a372a020 752 #define MXC_SPIB ((mxc_spib_regs_t *)MXC_BASE_SPIB)
AnnaBridge 167:84c0a372a020 753
AnnaBridge 167:84c0a372a020 754
AnnaBridge 167:84c0a372a020 755
AnnaBridge 167:84c0a372a020 756 /*******************************************************************************/
AnnaBridge 167:84c0a372a020 757 /* SPI Slave Interface */
AnnaBridge 167:84c0a372a020 758 #define MXC_CFG_SPIS_INSTANCES (1)
AnnaBridge 167:84c0a372a020 759 #define MXC_CFG_SPIS_FIFO_DEPTH (32)
AnnaBridge 167:84c0a372a020 760
AnnaBridge 167:84c0a372a020 761 #define MXC_BASE_SPIS ((uint32_t)0x40020000UL)
AnnaBridge 167:84c0a372a020 762 #define MXC_SPIS ((mxc_spis_regs_t *)MXC_BASE_SPIS)
AnnaBridge 167:84c0a372a020 763 #define MXC_BASE_SPIS_FIFO ((uint32_t)0x4010E000UL)
AnnaBridge 167:84c0a372a020 764 #define MXC_SPIS_FIFO ((mxc_spis_fifo_regs_t *)MXC_BASE_SPIS_FIFO)
AnnaBridge 167:84c0a372a020 765
AnnaBridge 167:84c0a372a020 766 #define MXC_SPIS_GET_IRQ(i) (IRQn_Type)((i) == 0 ? SPIS_IRQn : 0)
AnnaBridge 167:84c0a372a020 767
AnnaBridge 167:84c0a372a020 768 #define MXC_SPIS_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPIS : 0)
AnnaBridge 167:84c0a372a020 769
AnnaBridge 167:84c0a372a020 770 #define MXC_SPIS_GET_SPIS(i) ((i) == 0 ? MXC_SPIS : 0)
AnnaBridge 167:84c0a372a020 771
AnnaBridge 167:84c0a372a020 772 #define MXC_SPIS_GET_IDX(p) ((p) == MXC_SPIS ? 0 : -1)
AnnaBridge 167:84c0a372a020 773
AnnaBridge 167:84c0a372a020 774 #define MXC_SPIS_GET_BASE_FIFO(i) ((i) == 0 ? MXC_BASE_SPIS_FIFO : 0)
AnnaBridge 167:84c0a372a020 775
AnnaBridge 167:84c0a372a020 776 #define MXC_SPIS_GET_SPIS_FIFO(i) ((i) == 0 ? MXC_SPIS_FIFO :0)
AnnaBridge 167:84c0a372a020 777
AnnaBridge 167:84c0a372a020 778 /*******************************************************************************/
AnnaBridge 167:84c0a372a020 779 /* Bit Shifting */
AnnaBridge 167:84c0a372a020 780
AnnaBridge 167:84c0a372a020 781 #define MXC_F_BIT_0 (1 << 0)
AnnaBridge 167:84c0a372a020 782 #define MXC_F_BIT_1 (1 << 1)
AnnaBridge 167:84c0a372a020 783 #define MXC_F_BIT_2 (1 << 2)
AnnaBridge 167:84c0a372a020 784 #define MXC_F_BIT_3 (1 << 3)
AnnaBridge 167:84c0a372a020 785 #define MXC_F_BIT_4 (1 << 4)
AnnaBridge 167:84c0a372a020 786 #define MXC_F_BIT_5 (1 << 5)
AnnaBridge 167:84c0a372a020 787 #define MXC_F_BIT_6 (1 << 6)
AnnaBridge 167:84c0a372a020 788 #define MXC_F_BIT_7 (1 << 7)
AnnaBridge 167:84c0a372a020 789 #define MXC_F_BIT_8 (1 << 8)
AnnaBridge 167:84c0a372a020 790 #define MXC_F_BIT_9 (1 << 9)
AnnaBridge 167:84c0a372a020 791 #define MXC_F_BIT_10 (1 << 10)
AnnaBridge 167:84c0a372a020 792 #define MXC_F_BIT_11 (1 << 11)
AnnaBridge 167:84c0a372a020 793 #define MXC_F_BIT_12 (1 << 12)
AnnaBridge 167:84c0a372a020 794 #define MXC_F_BIT_13 (1 << 13)
AnnaBridge 167:84c0a372a020 795 #define MXC_F_BIT_14 (1 << 14)
AnnaBridge 167:84c0a372a020 796 #define MXC_F_BIT_15 (1 << 15)
AnnaBridge 167:84c0a372a020 797 #define MXC_F_BIT_16 (1 << 16)
AnnaBridge 167:84c0a372a020 798 #define MXC_F_BIT_17 (1 << 17)
AnnaBridge 167:84c0a372a020 799 #define MXC_F_BIT_18 (1 << 18)
AnnaBridge 167:84c0a372a020 800 #define MXC_F_BIT_19 (1 << 19)
AnnaBridge 167:84c0a372a020 801 #define MXC_F_BIT_20 (1 << 20)
AnnaBridge 167:84c0a372a020 802 #define MXC_F_BIT_21 (1 << 21)
AnnaBridge 167:84c0a372a020 803 #define MXC_F_BIT_22 (1 << 22)
AnnaBridge 167:84c0a372a020 804 #define MXC_F_BIT_23 (1 << 23)
AnnaBridge 167:84c0a372a020 805 #define MXC_F_BIT_24 (1 << 24)
AnnaBridge 167:84c0a372a020 806 #define MXC_F_BIT_25 (1 << 25)
AnnaBridge 167:84c0a372a020 807 #define MXC_F_BIT_26 (1 << 26)
AnnaBridge 167:84c0a372a020 808 #define MXC_F_BIT_27 (1 << 27)
AnnaBridge 167:84c0a372a020 809 #define MXC_F_BIT_28 (1 << 28)
AnnaBridge 167:84c0a372a020 810 #define MXC_F_BIT_29 (1 << 29)
AnnaBridge 167:84c0a372a020 811 #define MXC_F_BIT_30 (1 << 30)
AnnaBridge 167:84c0a372a020 812 #define MXC_F_BIT_31 (1 << 31)
AnnaBridge 167:84c0a372a020 813
AnnaBridge 167:84c0a372a020 814
AnnaBridge 167:84c0a372a020 815 /*******************************************************************************/
AnnaBridge 167:84c0a372a020 816
AnnaBridge 167:84c0a372a020 817 #define BITBAND(reg, bit) ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2))
AnnaBridge 167:84c0a372a020 818 #define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0)
AnnaBridge 167:84c0a372a020 819 #define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1)
AnnaBridge 167:84c0a372a020 820 #define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit))
AnnaBridge 167:84c0a372a020 821
AnnaBridge 167:84c0a372a020 822 #define MXC_SET_FIELD(reg, clr, set) (*(volatile uint32_t *)reg = ((*(volatile uint32_t *)reg & ~clr) | set))
AnnaBridge 167:84c0a372a020 823
AnnaBridge 167:84c0a372a020 824 /*******************************************************************************/
AnnaBridge 167:84c0a372a020 825
AnnaBridge 167:84c0a372a020 826 /* SCB CPACR Register Definitions */
AnnaBridge 167:84c0a372a020 827 /* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */
AnnaBridge 167:84c0a372a020 828 #define SCB_CPACR_CP10_Pos 20 /*!< SCB CPACR: Coprocessor 10 Position */
AnnaBridge 167:84c0a372a020 829 #define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos) /*!< SCB CPACR: Coprocessor 10 Mask */
AnnaBridge 167:84c0a372a020 830 #define SCB_CPACR_CP11_Pos 22 /*!< SCB CPACR: Coprocessor 11 Position */
AnnaBridge 167:84c0a372a020 831 #define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos) /*!< SCB CPACR: Coprocessor 11 Mask */
AnnaBridge 167:84c0a372a020 832
AnnaBridge 167:84c0a372a020 833 #endif /* _MAX32620_H_ */
AnnaBridge 167:84c0a372a020 834