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TARGET_NUCLEO_L4R5ZI_P/TOOLCHAIN_ARM_STD/stm32l4xx_ll_system.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	172:65be27845400	1	/**
AnnaBridge	172:65be27845400	2	******************************************************************************
AnnaBridge	172:65be27845400	3	* @file stm32l4xx_ll_system.h
AnnaBridge	172:65be27845400	4	* @author MCD Application Team
AnnaBridge	172:65be27845400	5	* @brief Header file of SYSTEM LL module.
AnnaBridge	172:65be27845400	6	@verbatim
AnnaBridge	172:65be27845400	7	==============================================================================
AnnaBridge	172:65be27845400	8	##### How to use this driver #####
AnnaBridge	172:65be27845400	9	==============================================================================
AnnaBridge	172:65be27845400	10	[..]
AnnaBridge	172:65be27845400	11	The LL SYSTEM driver contains a set of generic APIs that can be
AnnaBridge	172:65be27845400	12	used by user:
AnnaBridge	172:65be27845400	13	(+) Some of the FLASH features need to be handled in the SYSTEM file.
AnnaBridge	172:65be27845400	14	(+) Access to DBGCMU registers
AnnaBridge	172:65be27845400	15	(+) Access to SYSCFG registers
AnnaBridge	172:65be27845400	16	(+) Access to VREFBUF registers
AnnaBridge	172:65be27845400	17
AnnaBridge	172:65be27845400	18	@endverbatim
AnnaBridge	172:65be27845400	19	******************************************************************************
AnnaBridge	172:65be27845400	20	* @attention
AnnaBridge	172:65be27845400	21	*
AnnaBridge	172:65be27845400	22	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	172:65be27845400	23	*
AnnaBridge	172:65be27845400	24	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	172:65be27845400	25	* are permitted provided that the following conditions are met:
AnnaBridge	172:65be27845400	26	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	172:65be27845400	27	* this list of conditions and the following disclaimer.
AnnaBridge	172:65be27845400	28	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	172:65be27845400	29	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	172:65be27845400	30	* and/or other materials provided with the distribution.
AnnaBridge	172:65be27845400	31	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	172:65be27845400	32	* may be used to endorse or promote products derived from this software
AnnaBridge	172:65be27845400	33	* without specific prior written permission.
AnnaBridge	172:65be27845400	34	*
AnnaBridge	172:65be27845400	35	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	172:65be27845400	36	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	172:65be27845400	37	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	172:65be27845400	38	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	172:65be27845400	39	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	172:65be27845400	40	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	172:65be27845400	41	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	172:65be27845400	42	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	172:65be27845400	43	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	172:65be27845400	44	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	172:65be27845400	45	*
AnnaBridge	172:65be27845400	46	******************************************************************************
AnnaBridge	172:65be27845400	47	*/
AnnaBridge	172:65be27845400	48
AnnaBridge	172:65be27845400	49	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	172:65be27845400	50	#ifndef __STM32L4xx_LL_SYSTEM_H
AnnaBridge	172:65be27845400	51	#define __STM32L4xx_LL_SYSTEM_H
AnnaBridge	172:65be27845400	52
AnnaBridge	172:65be27845400	53	#ifdef __cplusplus
AnnaBridge	172:65be27845400	54	extern "C" {
AnnaBridge	172:65be27845400	55	#endif
AnnaBridge	172:65be27845400	56
AnnaBridge	172:65be27845400	57	/* Includes ------------------------------------------------------------------*/
AnnaBridge	172:65be27845400	58	#include "stm32l4xx.h"
AnnaBridge	172:65be27845400	59
AnnaBridge	172:65be27845400	60	/** @addtogroup STM32L4xx_LL_Driver
AnnaBridge	172:65be27845400	61	* @{
AnnaBridge	172:65be27845400	62	*/
AnnaBridge	172:65be27845400	63
AnnaBridge	172:65be27845400	64	#if defined (FLASH) \|\| defined (SYSCFG) \|\| defined (DBGMCU) \|\| defined (VREFBUF)
AnnaBridge	172:65be27845400	65
AnnaBridge	172:65be27845400	66	/** @defgroup SYSTEM_LL SYSTEM
AnnaBridge	172:65be27845400	67	* @{
AnnaBridge	172:65be27845400	68	*/
AnnaBridge	172:65be27845400	69
AnnaBridge	172:65be27845400	70	/* Private types -------------------------------------------------------------*/
AnnaBridge	172:65be27845400	71	/* Private variables ---------------------------------------------------------*/
AnnaBridge	172:65be27845400	72
AnnaBridge	172:65be27845400	73	/* Private constants ---------------------------------------------------------*/
AnnaBridge	172:65be27845400	74	/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
AnnaBridge	172:65be27845400	75	* @{
AnnaBridge	172:65be27845400	76	*/
AnnaBridge	172:65be27845400	77
AnnaBridge	172:65be27845400	78	/**
AnnaBridge	172:65be27845400	79	* @brief Power-down in Run mode Flash key
AnnaBridge	172:65be27845400	80	*/
AnnaBridge	172:65be27845400	81	#define FLASH_PDKEY1 0x04152637U /!< Flash power down key1 /
AnnaBridge	172:65be27845400	82	#define FLASH_PDKEY2 0xFAFBFCFDU /*!< Flash power down key2: used with FLASH_PDKEY1
AnnaBridge	172:65be27845400	83	to unlock the RUN_PD bit in FLASH_ACR */
AnnaBridge	172:65be27845400	84
AnnaBridge	172:65be27845400	85	/**
AnnaBridge	172:65be27845400	86	* @}
AnnaBridge	172:65be27845400	87	*/
AnnaBridge	172:65be27845400	88
AnnaBridge	172:65be27845400	89	/* Private macros ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	90
AnnaBridge	172:65be27845400	91	/* Exported types ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	92	/* Exported constants --------------------------------------------------------*/
AnnaBridge	172:65be27845400	93	/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
AnnaBridge	172:65be27845400	94	* @{
AnnaBridge	172:65be27845400	95	*/
AnnaBridge	172:65be27845400	96
AnnaBridge	172:65be27845400	97	/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
AnnaBridge	172:65be27845400	98	* @{
AnnaBridge	172:65be27845400	99	*/
AnnaBridge	172:65be27845400	100	#define LL_SYSCFG_REMAP_FLASH 0x00000000U /!< Main Flash memory mapped at 0x00000000 /
AnnaBridge	172:65be27845400	101	#define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 /!< System Flash memory mapped at 0x00000000 /
AnnaBridge	172:65be27845400	102	#define LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 \| SYSCFG_MEMRMP_MEM_MODE_0) /!< SRAM1 mapped at 0x00000000 /
AnnaBridge	172:65be27845400	103	#if defined(FMC_Bank1_R)
AnnaBridge	172:65be27845400	104	#define LL_SYSCFG_REMAP_FMC SYSCFG_MEMRMP_MEM_MODE_1 /!< FMC bank 1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 /
AnnaBridge	172:65be27845400	105	#endif /* FMC_Bank1_R */
AnnaBridge	172:65be27845400	106	#define LL_SYSCFG_REMAP_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 \| SYSCFG_MEMRMP_MEM_MODE_1) /!< QUADSPI memory mapped at 0x00000000 /
AnnaBridge	172:65be27845400	107	/**
AnnaBridge	172:65be27845400	108	* @}
AnnaBridge	172:65be27845400	109	*/
AnnaBridge	172:65be27845400	110
AnnaBridge	172:65be27845400	111	#if defined(SYSCFG_MEMRMP_FB_MODE)
AnnaBridge	172:65be27845400	112	/** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG BANK MODE
AnnaBridge	172:65be27845400	113	* @{
AnnaBridge	172:65be27845400	114	*/
AnnaBridge	172:65be27845400	115	#define LL_SYSCFG_BANKMODE_BANK1 0x00000000U /*!< Flash Bank1 mapped at 0x08000000 (and aliased @0x00000000)
AnnaBridge	172:65be27845400	116	and Flash Bank2 mapped at 0x08080000 (and aliased at 0x00080000) */
AnnaBridge	172:65be27845400	117	#define LL_SYSCFG_BANKMODE_BANK2 SYSCFG_MEMRMP_FB_MODE /*!< Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000)
AnnaBridge	172:65be27845400	118	and Flash Bank1 mapped at 0x08080000 (and aliased at 0x00080000) */
AnnaBridge	172:65be27845400	119	/**
AnnaBridge	172:65be27845400	120	* @}
AnnaBridge	172:65be27845400	121	*/
AnnaBridge	172:65be27845400	122
AnnaBridge	172:65be27845400	123	#endif /* SYSCFG_MEMRMP_FB_MODE */
AnnaBridge	172:65be27845400	124	/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
AnnaBridge	172:65be27845400	125	* @{
AnnaBridge	172:65be27845400	126	*/
AnnaBridge	172:65be27845400	127	#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /!< Enable Fast Mode Plus on PB6 /
AnnaBridge	172:65be27845400	128	#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /!< Enable Fast Mode Plus on PB7 /
AnnaBridge	172:65be27845400	129	#if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
AnnaBridge	172:65be27845400	130	#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /!< Enable Fast Mode Plus on PB8 /
AnnaBridge	172:65be27845400	131	#endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
AnnaBridge	172:65be27845400	132	#if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
AnnaBridge	172:65be27845400	133	#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /!< Enable Fast Mode Plus on PB9 /
AnnaBridge	172:65be27845400	134	#endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
AnnaBridge	172:65be27845400	135	#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /!< Enable Fast Mode Plus on I2C1 pins /
AnnaBridge	172:65be27845400	136	#if defined(I2C2)
AnnaBridge	172:65be27845400	137	#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /!< Enable Fast Mode Plus on I2C2 pins /
AnnaBridge	172:65be27845400	138	#endif /* I2C2 */
AnnaBridge	172:65be27845400	139	#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /!< Enable Fast Mode Plus on I2C3 pins /
AnnaBridge	172:65be27845400	140	#if defined(I2C4)
AnnaBridge	172:65be27845400	141	#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 SYSCFG_CFGR1_I2C4_FMP /!< Enable Fast Mode Plus on I2C4 pins /
AnnaBridge	172:65be27845400	142	#endif /* I2C4 */
AnnaBridge	172:65be27845400	143	/**
AnnaBridge	172:65be27845400	144	* @}
AnnaBridge	172:65be27845400	145	*/
AnnaBridge	172:65be27845400	146
AnnaBridge	172:65be27845400	147	/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
AnnaBridge	172:65be27845400	148	* @{
AnnaBridge	172:65be27845400	149	*/
AnnaBridge	172:65be27845400	150	#define LL_SYSCFG_EXTI_PORTA 0U /!< EXTI PORT A /
AnnaBridge	172:65be27845400	151	#define LL_SYSCFG_EXTI_PORTB 1U /!< EXTI PORT B /
AnnaBridge	172:65be27845400	152	#define LL_SYSCFG_EXTI_PORTC 2U /!< EXTI PORT C /
AnnaBridge	172:65be27845400	153	#define LL_SYSCFG_EXTI_PORTD 3U /!< EXTI PORT D /
AnnaBridge	172:65be27845400	154	#define LL_SYSCFG_EXTI_PORTE 4U /!< EXTI PORT E /
AnnaBridge	172:65be27845400	155	#if defined(GPIOF)
AnnaBridge	172:65be27845400	156	#define LL_SYSCFG_EXTI_PORTF 5U /!< EXTI PORT F /
AnnaBridge	172:65be27845400	157	#endif /* GPIOF */
AnnaBridge	172:65be27845400	158	#if defined(GPIOG)
AnnaBridge	172:65be27845400	159	#define LL_SYSCFG_EXTI_PORTG 6U /!< EXTI PORT G /
AnnaBridge	172:65be27845400	160	#endif /* GPIOG */
AnnaBridge	172:65be27845400	161	#define LL_SYSCFG_EXTI_PORTH 7U /!< EXTI PORT H /
AnnaBridge	172:65be27845400	162	#if defined(GPIOI)
AnnaBridge	172:65be27845400	163	#define LL_SYSCFG_EXTI_PORTI 8U /!< EXTI PORT I /
AnnaBridge	172:65be27845400	164	#endif /* GPIOI */
AnnaBridge	172:65be27845400	165	/**
AnnaBridge	172:65be27845400	166	* @}
AnnaBridge	172:65be27845400	167	*/
AnnaBridge	172:65be27845400	168
AnnaBridge	172:65be27845400	169	/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
AnnaBridge	172:65be27845400	170	* @{
AnnaBridge	172:65be27845400	171	*/
AnnaBridge	172:65be27845400	172	#define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0x000FU << 16U \| 0U) /* !< EXTI_POSITION_0 \| EXTICR[0] */
AnnaBridge	172:65be27845400	173	#define LL_SYSCFG_EXTI_LINE1 (uint32_t)(0x00F0U << 16U \| 0U) /* !< EXTI_POSITION_4 \| EXTICR[0] */
AnnaBridge	172:65be27845400	174	#define LL_SYSCFG_EXTI_LINE2 (uint32_t)(0x0F00U << 16U \| 0U) /* !< EXTI_POSITION_8 \| EXTICR[0] */
AnnaBridge	172:65be27845400	175	#define LL_SYSCFG_EXTI_LINE3 (uint32_t)(0xF000U << 16U \| 0U) /* !< EXTI_POSITION_12 \| EXTICR[0] */
AnnaBridge	172:65be27845400	176	#define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0x000FU << 16U \| 1U) /* !< EXTI_POSITION_0 \| EXTICR[1] */
AnnaBridge	172:65be27845400	177	#define LL_SYSCFG_EXTI_LINE5 (uint32_t)(0x00F0U << 16U \| 1U) /* !< EXTI_POSITION_4 \| EXTICR[1] */
AnnaBridge	172:65be27845400	178	#define LL_SYSCFG_EXTI_LINE6 (uint32_t)(0x0F00U << 16U \| 1U) /* !< EXTI_POSITION_8 \| EXTICR[1] */
AnnaBridge	172:65be27845400	179	#define LL_SYSCFG_EXTI_LINE7 (uint32_t)(0xF000U << 16U \| 1U) /* !< EXTI_POSITION_12 \| EXTICR[1] */
AnnaBridge	172:65be27845400	180	#define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0x000FU << 16U \| 2U) /* !< EXTI_POSITION_0 \| EXTICR[2] */
AnnaBridge	172:65be27845400	181	#define LL_SYSCFG_EXTI_LINE9 (uint32_t)(0x00F0U << 16U \| 2U) /* !< EXTI_POSITION_4 \| EXTICR[2] */
AnnaBridge	172:65be27845400	182	#define LL_SYSCFG_EXTI_LINE10 (uint32_t)(0x0F00U << 16U \| 2U) /* !< EXTI_POSITION_8 \| EXTICR[2] */
AnnaBridge	172:65be27845400	183	#define LL_SYSCFG_EXTI_LINE11 (uint32_t)(0xF000U << 16U \| 2U) /* !< EXTI_POSITION_12 \| EXTICR[2] */
AnnaBridge	172:65be27845400	184	#define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0x000FU << 16U \| 3U) /* !< EXTI_POSITION_0 \| EXTICR[3] */
AnnaBridge	172:65be27845400	185	#define LL_SYSCFG_EXTI_LINE13 (uint32_t)(0x00F0U << 16U \| 3U) /* !< EXTI_POSITION_4 \| EXTICR[3] */
AnnaBridge	172:65be27845400	186	#define LL_SYSCFG_EXTI_LINE14 (uint32_t)(0x0F00U << 16U \| 3U) /* !< EXTI_POSITION_8 \| EXTICR[3] */
AnnaBridge	172:65be27845400	187	#define LL_SYSCFG_EXTI_LINE15 (uint32_t)(0xF000U << 16U \| 3U) /* !< EXTI_POSITION_12 \| EXTICR[3] */
AnnaBridge	172:65be27845400	188	/**
AnnaBridge	172:65be27845400	189	* @}
AnnaBridge	172:65be27845400	190	*/
AnnaBridge	172:65be27845400	191
AnnaBridge	172:65be27845400	192	/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
AnnaBridge	172:65be27845400	193	* @{
AnnaBridge	172:65be27845400	194	*/
AnnaBridge	172:65be27845400	195	#define LL_SYSCFG_TIMBREAK_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal
AnnaBridge	172:65be27845400	196	with Break Input of TIM1/8/15/16/17 */
AnnaBridge	172:65be27845400	197	#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection
AnnaBridge	172:65be27845400	198	with TIM1/8/15/16/17 Break Input
AnnaBridge	172:65be27845400	199	and also the PVDE and PLS bits of the Power Control Interface */
AnnaBridge	172:65be27845400	200	#define LL_SYSCFG_TIMBREAK_SRAM2_PARITY SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM2_PARITY error signal
AnnaBridge	172:65be27845400	201	with Break Input of TIM1/8/15/16/17 */
AnnaBridge	172:65be27845400	202	#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4
AnnaBridge	172:65be27845400	203	with Break Input of TIM1/15/16/17 */
AnnaBridge	172:65be27845400	204	/**
AnnaBridge	172:65be27845400	205	* @}
AnnaBridge	172:65be27845400	206	*/
AnnaBridge	172:65be27845400	207
AnnaBridge	172:65be27845400	208	/** @defgroup SYSTEM_LL_EC_SRAM2WRP SYSCFG SRAM2 WRP
AnnaBridge	172:65be27845400	209	* @{
AnnaBridge	172:65be27845400	210	*/
AnnaBridge	172:65be27845400	211	#define LL_SYSCFG_SRAM2WRP_PAGE0 SYSCFG_SWPR_PAGE0 /!< SRAM2 Write protection page 0 /
AnnaBridge	172:65be27845400	212	#define LL_SYSCFG_SRAM2WRP_PAGE1 SYSCFG_SWPR_PAGE1 /!< SRAM2 Write protection page 1 /
AnnaBridge	172:65be27845400	213	#define LL_SYSCFG_SRAM2WRP_PAGE2 SYSCFG_SWPR_PAGE2 /!< SRAM2 Write protection page 2 /
AnnaBridge	172:65be27845400	214	#define LL_SYSCFG_SRAM2WRP_PAGE3 SYSCFG_SWPR_PAGE3 /!< SRAM2 Write protection page 3 /
AnnaBridge	172:65be27845400	215	#define LL_SYSCFG_SRAM2WRP_PAGE4 SYSCFG_SWPR_PAGE4 /!< SRAM2 Write protection page 4 /
AnnaBridge	172:65be27845400	216	#define LL_SYSCFG_SRAM2WRP_PAGE5 SYSCFG_SWPR_PAGE5 /!< SRAM2 Write protection page 5 /
AnnaBridge	172:65be27845400	217	#define LL_SYSCFG_SRAM2WRP_PAGE6 SYSCFG_SWPR_PAGE6 /!< SRAM2 Write protection page 6 /
AnnaBridge	172:65be27845400	218	#define LL_SYSCFG_SRAM2WRP_PAGE7 SYSCFG_SWPR_PAGE7 /!< SRAM2 Write protection page 7 /
AnnaBridge	172:65be27845400	219	#define LL_SYSCFG_SRAM2WRP_PAGE8 SYSCFG_SWPR_PAGE8 /!< SRAM2 Write protection page 8 /
AnnaBridge	172:65be27845400	220	#define LL_SYSCFG_SRAM2WRP_PAGE9 SYSCFG_SWPR_PAGE9 /!< SRAM2 Write protection page 9 /
AnnaBridge	172:65be27845400	221	#define LL_SYSCFG_SRAM2WRP_PAGE10 SYSCFG_SWPR_PAGE10 /!< SRAM2 Write protection page 10 /
AnnaBridge	172:65be27845400	222	#define LL_SYSCFG_SRAM2WRP_PAGE11 SYSCFG_SWPR_PAGE11 /!< SRAM2 Write protection page 11 /
AnnaBridge	172:65be27845400	223	#define LL_SYSCFG_SRAM2WRP_PAGE12 SYSCFG_SWPR_PAGE12 /!< SRAM2 Write protection page 12 /
AnnaBridge	172:65be27845400	224	#define LL_SYSCFG_SRAM2WRP_PAGE13 SYSCFG_SWPR_PAGE13 /!< SRAM2 Write protection page 13 /
AnnaBridge	172:65be27845400	225	#define LL_SYSCFG_SRAM2WRP_PAGE14 SYSCFG_SWPR_PAGE14 /!< SRAM2 Write protection page 14 /
AnnaBridge	172:65be27845400	226	#define LL_SYSCFG_SRAM2WRP_PAGE15 SYSCFG_SWPR_PAGE15 /!< SRAM2 Write protection page 15 /
AnnaBridge	172:65be27845400	227	#if defined(SYSCFG_SWPR_PAGE31)
AnnaBridge	172:65be27845400	228	#define LL_SYSCFG_SRAM2WRP_PAGE16 SYSCFG_SWPR_PAGE16 /!< SRAM2 Write protection page 16 /
AnnaBridge	172:65be27845400	229	#define LL_SYSCFG_SRAM2WRP_PAGE17 SYSCFG_SWPR_PAGE17 /!< SRAM2 Write protection page 17 /
AnnaBridge	172:65be27845400	230	#define LL_SYSCFG_SRAM2WRP_PAGE18 SYSCFG_SWPR_PAGE18 /!< SRAM2 Write protection page 18 /
AnnaBridge	172:65be27845400	231	#define LL_SYSCFG_SRAM2WRP_PAGE19 SYSCFG_SWPR_PAGE19 /!< SRAM2 Write protection page 19 /
AnnaBridge	172:65be27845400	232	#define LL_SYSCFG_SRAM2WRP_PAGE20 SYSCFG_SWPR_PAGE20 /!< SRAM2 Write protection page 20 /
AnnaBridge	172:65be27845400	233	#define LL_SYSCFG_SRAM2WRP_PAGE21 SYSCFG_SWPR_PAGE21 /!< SRAM2 Write protection page 21 /
AnnaBridge	172:65be27845400	234	#define LL_SYSCFG_SRAM2WRP_PAGE22 SYSCFG_SWPR_PAGE22 /!< SRAM2 Write protection page 22 /
AnnaBridge	172:65be27845400	235	#define LL_SYSCFG_SRAM2WRP_PAGE23 SYSCFG_SWPR_PAGE23 /!< SRAM2 Write protection page 23 /
AnnaBridge	172:65be27845400	236	#define LL_SYSCFG_SRAM2WRP_PAGE24 SYSCFG_SWPR_PAGE24 /!< SRAM2 Write protection page 24 /
AnnaBridge	172:65be27845400	237	#define LL_SYSCFG_SRAM2WRP_PAGE25 SYSCFG_SWPR_PAGE25 /!< SRAM2 Write protection page 25 /
AnnaBridge	172:65be27845400	238	#define LL_SYSCFG_SRAM2WRP_PAGE26 SYSCFG_SWPR_PAGE26 /!< SRAM2 Write protection page 26 /
AnnaBridge	172:65be27845400	239	#define LL_SYSCFG_SRAM2WRP_PAGE27 SYSCFG_SWPR_PAGE27 /!< SRAM2 Write protection page 27 /
AnnaBridge	172:65be27845400	240	#define LL_SYSCFG_SRAM2WRP_PAGE28 SYSCFG_SWPR_PAGE28 /!< SRAM2 Write protection page 28 /
AnnaBridge	172:65be27845400	241	#define LL_SYSCFG_SRAM2WRP_PAGE29 SYSCFG_SWPR_PAGE29 /!< SRAM2 Write protection page 29 /
AnnaBridge	172:65be27845400	242	#define LL_SYSCFG_SRAM2WRP_PAGE30 SYSCFG_SWPR_PAGE30 /!< SRAM2 Write protection page 30 /
AnnaBridge	172:65be27845400	243	#define LL_SYSCFG_SRAM2WRP_PAGE31 SYSCFG_SWPR_PAGE31 /!< SRAM2 Write protection page 31 /
AnnaBridge	172:65be27845400	244	#endif /* SYSCFG_SWPR_PAGE31 */
AnnaBridge	172:65be27845400	245	#if defined(SYSCFG_SWPR2_PAGE63)
AnnaBridge	172:65be27845400	246	#define LL_SYSCFG_SRAM2WRP_PAGE32 SYSCFG_SWPR2_PAGE32 /!< SRAM2 Write protection page 32 /
AnnaBridge	172:65be27845400	247	#define LL_SYSCFG_SRAM2WRP_PAGE33 SYSCFG_SWPR2_PAGE33 /!< SRAM2 Write protection page 33 /
AnnaBridge	172:65be27845400	248	#define LL_SYSCFG_SRAM2WRP_PAGE34 SYSCFG_SWPR2_PAGE34 /!< SRAM2 Write protection page 34 /
AnnaBridge	172:65be27845400	249	#define LL_SYSCFG_SRAM2WRP_PAGE35 SYSCFG_SWPR2_PAGE35 /!< SRAM2 Write protection page 35 /
AnnaBridge	172:65be27845400	250	#define LL_SYSCFG_SRAM2WRP_PAGE36 SYSCFG_SWPR2_PAGE36 /!< SRAM2 Write protection page 36 /
AnnaBridge	172:65be27845400	251	#define LL_SYSCFG_SRAM2WRP_PAGE37 SYSCFG_SWPR2_PAGE37 /!< SRAM2 Write protection page 37 /
AnnaBridge	172:65be27845400	252	#define LL_SYSCFG_SRAM2WRP_PAGE38 SYSCFG_SWPR2_PAGE38 /!< SRAM2 Write protection page 38 /
AnnaBridge	172:65be27845400	253	#define LL_SYSCFG_SRAM2WRP_PAGE39 SYSCFG_SWPR2_PAGE39 /!< SRAM2 Write protection page 39 /
AnnaBridge	172:65be27845400	254	#define LL_SYSCFG_SRAM2WRP_PAGE40 SYSCFG_SWPR2_PAGE40 /!< SRAM2 Write protection page 40 /
AnnaBridge	172:65be27845400	255	#define LL_SYSCFG_SRAM2WRP_PAGE41 SYSCFG_SWPR2_PAGE41 /!< SRAM2 Write protection page 41 /
AnnaBridge	172:65be27845400	256	#define LL_SYSCFG_SRAM2WRP_PAGE42 SYSCFG_SWPR2_PAGE42 /!< SRAM2 Write protection page 42 /
AnnaBridge	172:65be27845400	257	#define LL_SYSCFG_SRAM2WRP_PAGE43 SYSCFG_SWPR2_PAGE43 /!< SRAM2 Write protection page 43 /
AnnaBridge	172:65be27845400	258	#define LL_SYSCFG_SRAM2WRP_PAGE44 SYSCFG_SWPR2_PAGE44 /!< SRAM2 Write protection page 44 /
AnnaBridge	172:65be27845400	259	#define LL_SYSCFG_SRAM2WRP_PAGE45 SYSCFG_SWPR2_PAGE45 /!< SRAM2 Write protection page 45 /
AnnaBridge	172:65be27845400	260	#define LL_SYSCFG_SRAM2WRP_PAGE46 SYSCFG_SWPR2_PAGE46 /!< SRAM2 Write protection page 46 /
AnnaBridge	172:65be27845400	261	#define LL_SYSCFG_SRAM2WRP_PAGE47 SYSCFG_SWPR2_PAGE47 /!< SRAM2 Write protection page 47 /
AnnaBridge	172:65be27845400	262	#define LL_SYSCFG_SRAM2WRP_PAGE48 SYSCFG_SWPR2_PAGE48 /!< SRAM2 Write protection page 48 /
AnnaBridge	172:65be27845400	263	#define LL_SYSCFG_SRAM2WRP_PAGE49 SYSCFG_SWPR2_PAGE49 /!< SRAM2 Write protection page 49 /
AnnaBridge	172:65be27845400	264	#define LL_SYSCFG_SRAM2WRP_PAGE50 SYSCFG_SWPR2_PAGE50 /!< SRAM2 Write protection page 50 /
AnnaBridge	172:65be27845400	265	#define LL_SYSCFG_SRAM2WRP_PAGE51 SYSCFG_SWPR2_PAGE51 /!< SRAM2 Write protection page 51 /
AnnaBridge	172:65be27845400	266	#define LL_SYSCFG_SRAM2WRP_PAGE52 SYSCFG_SWPR2_PAGE52 /!< SRAM2 Write protection page 52 /
AnnaBridge	172:65be27845400	267	#define LL_SYSCFG_SRAM2WRP_PAGE53 SYSCFG_SWPR2_PAGE53 /!< SRAM2 Write protection page 53 /
AnnaBridge	172:65be27845400	268	#define LL_SYSCFG_SRAM2WRP_PAGE54 SYSCFG_SWPR2_PAGE54 /!< SRAM2 Write protection page 54 /
AnnaBridge	172:65be27845400	269	#define LL_SYSCFG_SRAM2WRP_PAGE55 SYSCFG_SWPR2_PAGE55 /!< SRAM2 Write protection page 55 /
AnnaBridge	172:65be27845400	270	#define LL_SYSCFG_SRAM2WRP_PAGE56 SYSCFG_SWPR2_PAGE56 /!< SRAM2 Write protection page 56 /
AnnaBridge	172:65be27845400	271	#define LL_SYSCFG_SRAM2WRP_PAGE57 SYSCFG_SWPR2_PAGE57 /!< SRAM2 Write protection page 57 /
AnnaBridge	172:65be27845400	272	#define LL_SYSCFG_SRAM2WRP_PAGE58 SYSCFG_SWPR2_PAGE58 /!< SRAM2 Write protection page 58 /
AnnaBridge	172:65be27845400	273	#define LL_SYSCFG_SRAM2WRP_PAGE59 SYSCFG_SWPR2_PAGE59 /!< SRAM2 Write protection page 59 /
AnnaBridge	172:65be27845400	274	#define LL_SYSCFG_SRAM2WRP_PAGE60 SYSCFG_SWPR2_PAGE60 /!< SRAM2 Write protection page 60 /
AnnaBridge	172:65be27845400	275	#define LL_SYSCFG_SRAM2WRP_PAGE61 SYSCFG_SWPR2_PAGE61 /!< SRAM2 Write protection page 61 /
AnnaBridge	172:65be27845400	276	#define LL_SYSCFG_SRAM2WRP_PAGE62 SYSCFG_SWPR2_PAGE62 /!< SRAM2 Write protection page 62 /
AnnaBridge	172:65be27845400	277	#define LL_SYSCFG_SRAM2WRP_PAGE63 SYSCFG_SWPR2_PAGE63 /!< SRAM2 Write protection page 63 /
AnnaBridge	172:65be27845400	278	#endif /* SYSCFG_SWPR2_PAGE63 */
AnnaBridge	172:65be27845400	279	/**
AnnaBridge	172:65be27845400	280	* @}
AnnaBridge	172:65be27845400	281	*/
AnnaBridge	172:65be27845400	282
AnnaBridge	172:65be27845400	283	/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
AnnaBridge	172:65be27845400	284	* @{
AnnaBridge	172:65be27845400	285	*/
AnnaBridge	172:65be27845400	286	#define LL_DBGMCU_TRACE_NONE 0x00000000U /!< TRACE pins not assigned (default state) /
AnnaBridge	172:65be27845400	287	#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /!< TRACE pin assignment for Asynchronous Mode /
AnnaBridge	172:65be27845400	288	#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE_0) /!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 /
AnnaBridge	172:65be27845400	289	#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE_1) /!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 /
AnnaBridge	172:65be27845400	290	#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE) /!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 /
AnnaBridge	172:65be27845400	291	/**
AnnaBridge	172:65be27845400	292	* @}
AnnaBridge	172:65be27845400	293	*/
AnnaBridge	172:65be27845400	294
AnnaBridge	172:65be27845400	295	/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
AnnaBridge	172:65be27845400	296	* @{
AnnaBridge	172:65be27845400	297	*/
AnnaBridge	172:65be27845400	298	#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP /!< The counter clock of TIM2 is stopped when the core is halted/
AnnaBridge	172:65be27845400	299	#if defined(TIM3)
AnnaBridge	172:65be27845400	300	#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP /!< The counter clock of TIM3 is stopped when the core is halted/
AnnaBridge	172:65be27845400	301	#endif /* TIM3 */
AnnaBridge	172:65be27845400	302	#if defined(TIM4)
AnnaBridge	172:65be27845400	303	#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP /!< The counter clock of TIM4 is stopped when the core is halted/
AnnaBridge	172:65be27845400	304	#endif /* TIM4 */
AnnaBridge	172:65be27845400	305	#if defined(TIM5)
AnnaBridge	172:65be27845400	306	#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1FZR1_DBG_TIM5_STOP /!< The counter clock of TIM5 is stopped when the core is halted/
AnnaBridge	172:65be27845400	307	#endif /* TIM5 */
AnnaBridge	172:65be27845400	308	#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP /!< The counter clock of TIM6 is stopped when the core is halted/
AnnaBridge	172:65be27845400	309	#if defined(TIM7)
AnnaBridge	172:65be27845400	310	#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP /!< The counter clock of TIM7 is stopped when the core is halted/
AnnaBridge	172:65be27845400	311	#endif /* TIM7 */
AnnaBridge	172:65be27845400	312	#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP /!< The clock of the RTC counter is stopped when the core is halted/
AnnaBridge	172:65be27845400	313	#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP /!< The window watchdog counter clock is stopped when the core is halted/
AnnaBridge	172:65be27845400	314	#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP /!< The independent watchdog counter clock is stopped when the core is halted/
AnnaBridge	172:65be27845400	315	#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP /!< The I2C1 SMBus timeout is frozen/
AnnaBridge	172:65be27845400	316	#if defined(I2C2)
AnnaBridge	172:65be27845400	317	#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP /!< The I2C2 SMBus timeout is frozen/
AnnaBridge	172:65be27845400	318	#endif /* I2C2 */
AnnaBridge	172:65be27845400	319	#define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP /!< The I2C3 SMBus timeout is frozen/
AnnaBridge	172:65be27845400	320	#define LL_DBGMCU_APB1_GRP1_CAN_STOP DBGMCU_APB1FZR1_DBG_CAN_STOP /!< The bxCAN receive registers are frozen/
AnnaBridge	172:65be27845400	321	#if defined(CAN2)
AnnaBridge	172:65be27845400	322	#define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_APB1FZR1_DBG_CAN2_STOP /!< The bxCAN2 receive registers are frozen/
AnnaBridge	172:65be27845400	323	#endif /* CAN2 */
AnnaBridge	172:65be27845400	324	#define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP /!< The counter clock of LPTIM1 is stopped when the core is halted/
AnnaBridge	172:65be27845400	325	/**
AnnaBridge	172:65be27845400	326	* @}
AnnaBridge	172:65be27845400	327	*/
AnnaBridge	172:65be27845400	328
AnnaBridge	172:65be27845400	329	/** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP
AnnaBridge	172:65be27845400	330	* @{
AnnaBridge	172:65be27845400	331	*/
AnnaBridge	172:65be27845400	332	#if defined(I2C4)
AnnaBridge	172:65be27845400	333	#define LL_DBGMCU_APB1_GRP2_I2C4_STOP DBGMCU_APB1FZR2_DBG_I2C4_STOP /!< The I2C4 SMBus timeout is frozen/
AnnaBridge	172:65be27845400	334	#endif /* I2C4 */
AnnaBridge	172:65be27845400	335	#define LL_DBGMCU_APB1_GRP2_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP /!< The counter clock of LPTIM2 is stopped when the core is halted/
AnnaBridge	172:65be27845400	336	/**
AnnaBridge	172:65be27845400	337	* @}
AnnaBridge	172:65be27845400	338	*/
AnnaBridge	172:65be27845400	339
AnnaBridge	172:65be27845400	340	/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
AnnaBridge	172:65be27845400	341	* @{
AnnaBridge	172:65be27845400	342	*/
AnnaBridge	172:65be27845400	343	#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP /!< The counter clock of TIM1 is stopped when the core is halted/
AnnaBridge	172:65be27845400	344	#if defined(TIM8)
AnnaBridge	172:65be27845400	345	#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP /!< The counter clock of TIM8 is stopped when the core is halted/
AnnaBridge	172:65be27845400	346	#endif /* TIM8 */
AnnaBridge	172:65be27845400	347	#define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP /!< The counter clock of TIM15 is stopped when the core is halted/
AnnaBridge	172:65be27845400	348	#define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP /!< The counter clock of TIM16 is stopped when the core is halted/
AnnaBridge	172:65be27845400	349	#if defined(TIM17)
AnnaBridge	172:65be27845400	350	#define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP /!< The counter clock of TIM17 is stopped when the core is halted/
AnnaBridge	172:65be27845400	351	#endif /* TIM17 */
AnnaBridge	172:65be27845400	352	/**
AnnaBridge	172:65be27845400	353	* @}
AnnaBridge	172:65be27845400	354	*/
AnnaBridge	172:65be27845400	355
AnnaBridge	172:65be27845400	356	#if defined(VREFBUF)
AnnaBridge	172:65be27845400	357	/** @defgroup SYSTEM_LL_EC_VOLTAGE VREFBUF VOLTAGE
AnnaBridge	172:65be27845400	358	* @{
AnnaBridge	172:65be27845400	359	*/
AnnaBridge	172:65be27845400	360	#define LL_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /!< Voltage reference scale 0 (VREF_OUT1) /
AnnaBridge	172:65be27845400	361	#define LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /!< Voltage reference scale 1 (VREF_OUT2) /
AnnaBridge	172:65be27845400	362	/**
AnnaBridge	172:65be27845400	363	* @}
AnnaBridge	172:65be27845400	364	*/
AnnaBridge	172:65be27845400	365	#endif /* VREFBUF */
AnnaBridge	172:65be27845400	366
AnnaBridge	172:65be27845400	367	/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
AnnaBridge	172:65be27845400	368	* @{
AnnaBridge	172:65be27845400	369	*/
AnnaBridge	172:65be27845400	370	#define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /!< FLASH Zero wait state /
AnnaBridge	172:65be27845400	371	#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /!< FLASH One wait state /
AnnaBridge	172:65be27845400	372	#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /!< FLASH Two wait states /
AnnaBridge	172:65be27845400	373	#define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /!< FLASH Three wait states /
AnnaBridge	172:65be27845400	374	#define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /!< FLASH Four wait states /
AnnaBridge	172:65be27845400	375	#if defined(FLASH_ACR_LATENCY_5WS)
AnnaBridge	172:65be27845400	376	#define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /!< FLASH five wait state /
AnnaBridge	172:65be27845400	377	#define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /!< FLASH six wait state /
AnnaBridge	172:65be27845400	378	#define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /!< FLASH seven wait states /
AnnaBridge	172:65be27845400	379	#define LL_FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /!< FLASH eight wait states /
AnnaBridge	172:65be27845400	380	#define LL_FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /!< FLASH nine wait states /
AnnaBridge	172:65be27845400	381	#define LL_FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /!< FLASH ten wait states /
AnnaBridge	172:65be27845400	382	#define LL_FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /!< FLASH eleven wait states /
AnnaBridge	172:65be27845400	383	#define LL_FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /!< FLASH twelve wait states /
AnnaBridge	172:65be27845400	384	#define LL_FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /!< FLASH thirteen wait states /
AnnaBridge	172:65be27845400	385	#define LL_FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /!< FLASH fourteen wait states /
AnnaBridge	172:65be27845400	386	#define LL_FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /!< FLASH fifteen wait states /
AnnaBridge	172:65be27845400	387	#endif
AnnaBridge	172:65be27845400	388	/**
AnnaBridge	172:65be27845400	389	* @}
AnnaBridge	172:65be27845400	390	*/
AnnaBridge	172:65be27845400	391
AnnaBridge	172:65be27845400	392	/**
AnnaBridge	172:65be27845400	393	* @}
AnnaBridge	172:65be27845400	394	*/
AnnaBridge	172:65be27845400	395
AnnaBridge	172:65be27845400	396	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	397
AnnaBridge	172:65be27845400	398	/* Exported functions --------------------------------------------------------*/
AnnaBridge	172:65be27845400	399	/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
AnnaBridge	172:65be27845400	400	* @{
AnnaBridge	172:65be27845400	401	*/
AnnaBridge	172:65be27845400	402
AnnaBridge	172:65be27845400	403	/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
AnnaBridge	172:65be27845400	404	* @{
AnnaBridge	172:65be27845400	405	*/
AnnaBridge	172:65be27845400	406
AnnaBridge	172:65be27845400	407	/**
AnnaBridge	172:65be27845400	408	* @brief Set memory mapping at address 0x00000000
AnnaBridge	172:65be27845400	409	* @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_SetRemapMemory
AnnaBridge	172:65be27845400	410	* @param Memory This parameter can be one of the following values:
AnnaBridge	172:65be27845400	411	* @arg @ref LL_SYSCFG_REMAP_FLASH
AnnaBridge	172:65be27845400	412	* @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
AnnaBridge	172:65be27845400	413	* @arg @ref LL_SYSCFG_REMAP_SRAM
AnnaBridge	172:65be27845400	414	* @arg @ref LL_SYSCFG_REMAP_FMC (*)
AnnaBridge	172:65be27845400	415	* @arg @ref LL_SYSCFG_REMAP_QUADSPI
AnnaBridge	172:65be27845400	416	*
AnnaBridge	172:65be27845400	417	* (*) value not defined in all devices
AnnaBridge	172:65be27845400	418	* @retval None
AnnaBridge	172:65be27845400	419	*/
AnnaBridge	172:65be27845400	420	__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
AnnaBridge	172:65be27845400	421	{
AnnaBridge	172:65be27845400	422	MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory);
AnnaBridge	172:65be27845400	423	}
AnnaBridge	172:65be27845400	424
AnnaBridge	172:65be27845400	425	/**
AnnaBridge	172:65be27845400	426	* @brief Get memory mapping at address 0x00000000
AnnaBridge	172:65be27845400	427	* @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_GetRemapMemory
AnnaBridge	172:65be27845400	428	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	429	* @arg @ref LL_SYSCFG_REMAP_FLASH
AnnaBridge	172:65be27845400	430	* @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
AnnaBridge	172:65be27845400	431	* @arg @ref LL_SYSCFG_REMAP_SRAM
AnnaBridge	172:65be27845400	432	* @arg @ref LL_SYSCFG_REMAP_FMC (*)
AnnaBridge	172:65be27845400	433	* @arg @ref LL_SYSCFG_REMAP_QUADSPI
AnnaBridge	172:65be27845400	434	*
AnnaBridge	172:65be27845400	435	* (*) value not defined in all devices
AnnaBridge	172:65be27845400	436	*/
AnnaBridge	172:65be27845400	437	__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
AnnaBridge	172:65be27845400	438	{
AnnaBridge	172:65be27845400	439	return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE));
AnnaBridge	172:65be27845400	440	}
AnnaBridge	172:65be27845400	441
AnnaBridge	172:65be27845400	442	#if defined(SYSCFG_MEMRMP_FB_MODE)
AnnaBridge	172:65be27845400	443	/**
AnnaBridge	172:65be27845400	444	* @brief Select Flash bank mode (Bank flashed at 0x08000000)
AnnaBridge	172:65be27845400	445	* @rmtoll SYSCFG_MEMRMP FB_MODE LL_SYSCFG_SetFlashBankMode
AnnaBridge	172:65be27845400	446	* @param Bank This parameter can be one of the following values:
AnnaBridge	172:65be27845400	447	* @arg @ref LL_SYSCFG_BANKMODE_BANK1
AnnaBridge	172:65be27845400	448	* @arg @ref LL_SYSCFG_BANKMODE_BANK2
AnnaBridge	172:65be27845400	449	* @retval None
AnnaBridge	172:65be27845400	450	*/
AnnaBridge	172:65be27845400	451	__STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank)
AnnaBridge	172:65be27845400	452	{
AnnaBridge	172:65be27845400	453	MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE, Bank);
AnnaBridge	172:65be27845400	454	}
AnnaBridge	172:65be27845400	455
AnnaBridge	172:65be27845400	456	/**
AnnaBridge	172:65be27845400	457	* @brief Get Flash bank mode (Bank flashed at 0x08000000)
AnnaBridge	172:65be27845400	458	* @rmtoll SYSCFG_MEMRMP FB_MODE LL_SYSCFG_GetFlashBankMode
AnnaBridge	172:65be27845400	459	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	460	* @arg @ref LL_SYSCFG_BANKMODE_BANK1
AnnaBridge	172:65be27845400	461	* @arg @ref LL_SYSCFG_BANKMODE_BANK2
AnnaBridge	172:65be27845400	462	*/
AnnaBridge	172:65be27845400	463	__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void)
AnnaBridge	172:65be27845400	464	{
AnnaBridge	172:65be27845400	465	return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE));
AnnaBridge	172:65be27845400	466	}
AnnaBridge	172:65be27845400	467	#endif /* SYSCFG_MEMRMP_FB_MODE */
AnnaBridge	172:65be27845400	468
AnnaBridge	172:65be27845400	469	/**
AnnaBridge	172:65be27845400	470	* @brief Firewall protection enabled
AnnaBridge	172:65be27845400	471	* @rmtoll SYSCFG_CFGR1 FWDIS LL_SYSCFG_EnableFirewall
AnnaBridge	172:65be27845400	472	* @retval None
AnnaBridge	172:65be27845400	473	*/
AnnaBridge	172:65be27845400	474	__STATIC_INLINE void LL_SYSCFG_EnableFirewall(void)
AnnaBridge	172:65be27845400	475	{
AnnaBridge	172:65be27845400	476	CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FWDIS);
AnnaBridge	172:65be27845400	477	}
AnnaBridge	172:65be27845400	478
AnnaBridge	172:65be27845400	479	/**
AnnaBridge	172:65be27845400	480	* @brief Check if Firewall protection is enabled or not
AnnaBridge	172:65be27845400	481	* @rmtoll SYSCFG_CFGR1 FWDIS LL_SYSCFG_IsEnabledFirewall
AnnaBridge	172:65be27845400	482	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	483	*/
AnnaBridge	172:65be27845400	484	__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledFirewall(void)
AnnaBridge	172:65be27845400	485	{
AnnaBridge	172:65be27845400	486	return !(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FWDIS) == SYSCFG_CFGR1_FWDIS);
AnnaBridge	172:65be27845400	487	}
AnnaBridge	172:65be27845400	488
AnnaBridge	172:65be27845400	489	/**
AnnaBridge	172:65be27845400	490	* @brief Enable I/O analog switch voltage booster.
AnnaBridge	172:65be27845400	491	* @note When voltage booster is enabled, I/O analog switches are supplied
AnnaBridge	172:65be27845400	492	* by a dedicated voltage booster, from VDD power domain. This is
AnnaBridge	172:65be27845400	493	* the recommended configuration with low VDDA voltage operation.
AnnaBridge	172:65be27845400	494	* @note The I/O analog switch voltage booster is relevant for peripherals
AnnaBridge	172:65be27845400	495	* using I/O in analog input: ADC, COMP, OPAMP.
AnnaBridge	172:65be27845400	496	* However, COMP and OPAMP inputs have a high impedance and
AnnaBridge	172:65be27845400	497	* voltage booster do not impact performance significantly.
AnnaBridge	172:65be27845400	498	* Therefore, the voltage booster is mainly intended for
AnnaBridge	172:65be27845400	499	* usage with ADC.
AnnaBridge	172:65be27845400	500	* @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_EnableAnalogBooster
AnnaBridge	172:65be27845400	501	* @retval None
AnnaBridge	172:65be27845400	502	*/
AnnaBridge	172:65be27845400	503	__STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void)
AnnaBridge	172:65be27845400	504	{
AnnaBridge	172:65be27845400	505	SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
AnnaBridge	172:65be27845400	506	}
AnnaBridge	172:65be27845400	507
AnnaBridge	172:65be27845400	508	/**
AnnaBridge	172:65be27845400	509	* @brief Disable I/O analog switch voltage booster.
AnnaBridge	172:65be27845400	510	* @note When voltage booster is enabled, I/O analog switches are supplied
AnnaBridge	172:65be27845400	511	* by a dedicated voltage booster, from VDD power domain. This is
AnnaBridge	172:65be27845400	512	* the recommended configuration with low VDDA voltage operation.
AnnaBridge	172:65be27845400	513	* @note The I/O analog switch voltage booster is relevant for peripherals
AnnaBridge	172:65be27845400	514	* using I/O in analog input: ADC, COMP, OPAMP.
AnnaBridge	172:65be27845400	515	* However, COMP and OPAMP inputs have a high impedance and
AnnaBridge	172:65be27845400	516	* voltage booster do not impact performance significantly.
AnnaBridge	172:65be27845400	517	* Therefore, the voltage booster is mainly intended for
AnnaBridge	172:65be27845400	518	* usage with ADC.
AnnaBridge	172:65be27845400	519	* @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_DisableAnalogBooster
AnnaBridge	172:65be27845400	520	* @retval None
AnnaBridge	172:65be27845400	521	*/
AnnaBridge	172:65be27845400	522	__STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void)
AnnaBridge	172:65be27845400	523	{
AnnaBridge	172:65be27845400	524	CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
AnnaBridge	172:65be27845400	525	}
AnnaBridge	172:65be27845400	526
AnnaBridge	172:65be27845400	527	/**
AnnaBridge	172:65be27845400	528	* @brief Enable the I2C fast mode plus driving capability.
AnnaBridge	172:65be27845400	529	* @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_EnableFastModePlus\n
AnnaBridge	172:65be27845400	530	* SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_EnableFastModePlus
AnnaBridge	172:65be27845400	531	* @param ConfigFastModePlus This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	532	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
AnnaBridge	172:65be27845400	533	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
AnnaBridge	172:65be27845400	534	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
AnnaBridge	172:65be27845400	535	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
AnnaBridge	172:65be27845400	536	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
AnnaBridge	172:65be27845400	537	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
AnnaBridge	172:65be27845400	538	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
AnnaBridge	172:65be27845400	539	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 (*)
AnnaBridge	172:65be27845400	540	*
AnnaBridge	172:65be27845400	541	* (*) value not defined in all devices
AnnaBridge	172:65be27845400	542	* @retval None
AnnaBridge	172:65be27845400	543	*/
AnnaBridge	172:65be27845400	544	__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
AnnaBridge	172:65be27845400	545	{
AnnaBridge	172:65be27845400	546	SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
AnnaBridge	172:65be27845400	547	}
AnnaBridge	172:65be27845400	548
AnnaBridge	172:65be27845400	549	/**
AnnaBridge	172:65be27845400	550	* @brief Disable the I2C fast mode plus driving capability.
AnnaBridge	172:65be27845400	551	* @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus\n
AnnaBridge	172:65be27845400	552	* SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_DisableFastModePlus
AnnaBridge	172:65be27845400	553	* @param ConfigFastModePlus This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	554	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
AnnaBridge	172:65be27845400	555	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
AnnaBridge	172:65be27845400	556	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
AnnaBridge	172:65be27845400	557	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
AnnaBridge	172:65be27845400	558	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
AnnaBridge	172:65be27845400	559	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
AnnaBridge	172:65be27845400	560	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
AnnaBridge	172:65be27845400	561	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 (*)
AnnaBridge	172:65be27845400	562	*
AnnaBridge	172:65be27845400	563	* (*) value not defined in all devices
AnnaBridge	172:65be27845400	564	* @retval None
AnnaBridge	172:65be27845400	565	*/
AnnaBridge	172:65be27845400	566	__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
AnnaBridge	172:65be27845400	567	{
AnnaBridge	172:65be27845400	568	CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
AnnaBridge	172:65be27845400	569	}
AnnaBridge	172:65be27845400	570
AnnaBridge	172:65be27845400	571	/**
AnnaBridge	172:65be27845400	572	* @brief Enable Floating Point Unit Invalid operation Interrupt
AnnaBridge	172:65be27845400	573	* @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_EnableIT_FPU_IOC
AnnaBridge	172:65be27845400	574	* @retval None
AnnaBridge	172:65be27845400	575	*/
AnnaBridge	172:65be27845400	576	__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void)
AnnaBridge	172:65be27845400	577	{
AnnaBridge	172:65be27845400	578	SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
AnnaBridge	172:65be27845400	579	}
AnnaBridge	172:65be27845400	580
AnnaBridge	172:65be27845400	581	/**
AnnaBridge	172:65be27845400	582	* @brief Enable Floating Point Unit Divide-by-zero Interrupt
AnnaBridge	172:65be27845400	583	* @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_EnableIT_FPU_DZC
AnnaBridge	172:65be27845400	584	* @retval None
AnnaBridge	172:65be27845400	585	*/
AnnaBridge	172:65be27845400	586	__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void)
AnnaBridge	172:65be27845400	587	{
AnnaBridge	172:65be27845400	588	SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
AnnaBridge	172:65be27845400	589	}
AnnaBridge	172:65be27845400	590
AnnaBridge	172:65be27845400	591	/**
AnnaBridge	172:65be27845400	592	* @brief Enable Floating Point Unit Underflow Interrupt
AnnaBridge	172:65be27845400	593	* @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_EnableIT_FPU_UFC
AnnaBridge	172:65be27845400	594	* @retval None
AnnaBridge	172:65be27845400	595	*/
AnnaBridge	172:65be27845400	596	__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void)
AnnaBridge	172:65be27845400	597	{
AnnaBridge	172:65be27845400	598	SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
AnnaBridge	172:65be27845400	599	}
AnnaBridge	172:65be27845400	600
AnnaBridge	172:65be27845400	601	/**
AnnaBridge	172:65be27845400	602	* @brief Enable Floating Point Unit Overflow Interrupt
AnnaBridge	172:65be27845400	603	* @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_EnableIT_FPU_OFC
AnnaBridge	172:65be27845400	604	* @retval None
AnnaBridge	172:65be27845400	605	*/
AnnaBridge	172:65be27845400	606	__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void)
AnnaBridge	172:65be27845400	607	{
AnnaBridge	172:65be27845400	608	SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
AnnaBridge	172:65be27845400	609	}
AnnaBridge	172:65be27845400	610
AnnaBridge	172:65be27845400	611	/**
AnnaBridge	172:65be27845400	612	* @brief Enable Floating Point Unit Input denormal Interrupt
AnnaBridge	172:65be27845400	613	* @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_EnableIT_FPU_IDC
AnnaBridge	172:65be27845400	614	* @retval None
AnnaBridge	172:65be27845400	615	*/
AnnaBridge	172:65be27845400	616	__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void)
AnnaBridge	172:65be27845400	617	{
AnnaBridge	172:65be27845400	618	SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
AnnaBridge	172:65be27845400	619	}
AnnaBridge	172:65be27845400	620
AnnaBridge	172:65be27845400	621	/**
AnnaBridge	172:65be27845400	622	* @brief Enable Floating Point Unit Inexact Interrupt
AnnaBridge	172:65be27845400	623	* @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_EnableIT_FPU_IXC
AnnaBridge	172:65be27845400	624	* @retval None
AnnaBridge	172:65be27845400	625	*/
AnnaBridge	172:65be27845400	626	__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void)
AnnaBridge	172:65be27845400	627	{
AnnaBridge	172:65be27845400	628	SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
AnnaBridge	172:65be27845400	629	}
AnnaBridge	172:65be27845400	630
AnnaBridge	172:65be27845400	631	/**
AnnaBridge	172:65be27845400	632	* @brief Disable Floating Point Unit Invalid operation Interrupt
AnnaBridge	172:65be27845400	633	* @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_DisableIT_FPU_IOC
AnnaBridge	172:65be27845400	634	* @retval None
AnnaBridge	172:65be27845400	635	*/
AnnaBridge	172:65be27845400	636	__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void)
AnnaBridge	172:65be27845400	637	{
AnnaBridge	172:65be27845400	638	CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
AnnaBridge	172:65be27845400	639	}
AnnaBridge	172:65be27845400	640
AnnaBridge	172:65be27845400	641	/**
AnnaBridge	172:65be27845400	642	* @brief Disable Floating Point Unit Divide-by-zero Interrupt
AnnaBridge	172:65be27845400	643	* @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_DisableIT_FPU_DZC
AnnaBridge	172:65be27845400	644	* @retval None
AnnaBridge	172:65be27845400	645	*/
AnnaBridge	172:65be27845400	646	__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void)
AnnaBridge	172:65be27845400	647	{
AnnaBridge	172:65be27845400	648	CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
AnnaBridge	172:65be27845400	649	}
AnnaBridge	172:65be27845400	650
AnnaBridge	172:65be27845400	651	/**
AnnaBridge	172:65be27845400	652	* @brief Disable Floating Point Unit Underflow Interrupt
AnnaBridge	172:65be27845400	653	* @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_DisableIT_FPU_UFC
AnnaBridge	172:65be27845400	654	* @retval None
AnnaBridge	172:65be27845400	655	*/
AnnaBridge	172:65be27845400	656	__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void)
AnnaBridge	172:65be27845400	657	{
AnnaBridge	172:65be27845400	658	CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
AnnaBridge	172:65be27845400	659	}
AnnaBridge	172:65be27845400	660
AnnaBridge	172:65be27845400	661	/**
AnnaBridge	172:65be27845400	662	* @brief Disable Floating Point Unit Overflow Interrupt
AnnaBridge	172:65be27845400	663	* @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_DisableIT_FPU_OFC
AnnaBridge	172:65be27845400	664	* @retval None
AnnaBridge	172:65be27845400	665	*/
AnnaBridge	172:65be27845400	666	__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void)
AnnaBridge	172:65be27845400	667	{
AnnaBridge	172:65be27845400	668	CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
AnnaBridge	172:65be27845400	669	}
AnnaBridge	172:65be27845400	670
AnnaBridge	172:65be27845400	671	/**
AnnaBridge	172:65be27845400	672	* @brief Disable Floating Point Unit Input denormal Interrupt
AnnaBridge	172:65be27845400	673	* @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_DisableIT_FPU_IDC
AnnaBridge	172:65be27845400	674	* @retval None
AnnaBridge	172:65be27845400	675	*/
AnnaBridge	172:65be27845400	676	__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void)
AnnaBridge	172:65be27845400	677	{
AnnaBridge	172:65be27845400	678	CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
AnnaBridge	172:65be27845400	679	}
AnnaBridge	172:65be27845400	680
AnnaBridge	172:65be27845400	681	/**
AnnaBridge	172:65be27845400	682	* @brief Disable Floating Point Unit Inexact Interrupt
AnnaBridge	172:65be27845400	683	* @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_DisableIT_FPU_IXC
AnnaBridge	172:65be27845400	684	* @retval None
AnnaBridge	172:65be27845400	685	*/
AnnaBridge	172:65be27845400	686	__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC(void)
AnnaBridge	172:65be27845400	687	{
AnnaBridge	172:65be27845400	688	CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
AnnaBridge	172:65be27845400	689	}
AnnaBridge	172:65be27845400	690
AnnaBridge	172:65be27845400	691	/**
AnnaBridge	172:65be27845400	692	* @brief Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.
AnnaBridge	172:65be27845400	693	* @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_IsEnabledIT_FPU_IOC
AnnaBridge	172:65be27845400	694	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	695	*/
AnnaBridge	172:65be27845400	696	__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void)
AnnaBridge	172:65be27845400	697	{
AnnaBridge	172:65be27845400	698	return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0) == (SYSCFG_CFGR1_FPU_IE_0));
AnnaBridge	172:65be27845400	699	}
AnnaBridge	172:65be27845400	700
AnnaBridge	172:65be27845400	701	/**
AnnaBridge	172:65be27845400	702	* @brief Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.
AnnaBridge	172:65be27845400	703	* @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_IsEnabledIT_FPU_DZC
AnnaBridge	172:65be27845400	704	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	705	*/
AnnaBridge	172:65be27845400	706	__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void)
AnnaBridge	172:65be27845400	707	{
AnnaBridge	172:65be27845400	708	return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1) == (SYSCFG_CFGR1_FPU_IE_1));
AnnaBridge	172:65be27845400	709	}
AnnaBridge	172:65be27845400	710
AnnaBridge	172:65be27845400	711	/**
AnnaBridge	172:65be27845400	712	* @brief Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.
AnnaBridge	172:65be27845400	713	* @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_IsEnabledIT_FPU_UFC
AnnaBridge	172:65be27845400	714	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	715	*/
AnnaBridge	172:65be27845400	716	__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void)
AnnaBridge	172:65be27845400	717	{
AnnaBridge	172:65be27845400	718	return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2) == (SYSCFG_CFGR1_FPU_IE_2));
AnnaBridge	172:65be27845400	719	}
AnnaBridge	172:65be27845400	720
AnnaBridge	172:65be27845400	721	/**
AnnaBridge	172:65be27845400	722	* @brief Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.
AnnaBridge	172:65be27845400	723	* @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_IsEnabledIT_FPU_OFC
AnnaBridge	172:65be27845400	724	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	725	*/
AnnaBridge	172:65be27845400	726	__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void)
AnnaBridge	172:65be27845400	727	{
AnnaBridge	172:65be27845400	728	return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3) == (SYSCFG_CFGR1_FPU_IE_3));
AnnaBridge	172:65be27845400	729	}
AnnaBridge	172:65be27845400	730
AnnaBridge	172:65be27845400	731	/**
AnnaBridge	172:65be27845400	732	* @brief Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.
AnnaBridge	172:65be27845400	733	* @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_IsEnabledIT_FPU_IDC
AnnaBridge	172:65be27845400	734	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	735	*/
AnnaBridge	172:65be27845400	736	__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void)
AnnaBridge	172:65be27845400	737	{
AnnaBridge	172:65be27845400	738	return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4) == (SYSCFG_CFGR1_FPU_IE_4));
AnnaBridge	172:65be27845400	739	}
AnnaBridge	172:65be27845400	740
AnnaBridge	172:65be27845400	741	/**
AnnaBridge	172:65be27845400	742	* @brief Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.
AnnaBridge	172:65be27845400	743	* @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_IsEnabledIT_FPU_IXC
AnnaBridge	172:65be27845400	744	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	745	*/
AnnaBridge	172:65be27845400	746	__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void)
AnnaBridge	172:65be27845400	747	{
AnnaBridge	172:65be27845400	748	return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5) == (SYSCFG_CFGR1_FPU_IE_5));
AnnaBridge	172:65be27845400	749	}
AnnaBridge	172:65be27845400	750
AnnaBridge	172:65be27845400	751	/**
AnnaBridge	172:65be27845400	752	* @brief Configure source input for the EXTI external interrupt.
AnnaBridge	172:65be27845400	753	* @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n
AnnaBridge	172:65be27845400	754	* SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n
AnnaBridge	172:65be27845400	755	* SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n
AnnaBridge	172:65be27845400	756	* SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource
AnnaBridge	172:65be27845400	757	* @param Port This parameter can be one of the following values:
AnnaBridge	172:65be27845400	758	* @arg @ref LL_SYSCFG_EXTI_PORTA
AnnaBridge	172:65be27845400	759	* @arg @ref LL_SYSCFG_EXTI_PORTB
AnnaBridge	172:65be27845400	760	* @arg @ref LL_SYSCFG_EXTI_PORTC
AnnaBridge	172:65be27845400	761	* @arg @ref LL_SYSCFG_EXTI_PORTD
AnnaBridge	172:65be27845400	762	* @arg @ref LL_SYSCFG_EXTI_PORTE
AnnaBridge	172:65be27845400	763	* @arg @ref LL_SYSCFG_EXTI_PORTF (*)
AnnaBridge	172:65be27845400	764	* @arg @ref LL_SYSCFG_EXTI_PORTG (*)
AnnaBridge	172:65be27845400	765	* @arg @ref LL_SYSCFG_EXTI_PORTH
AnnaBridge	172:65be27845400	766	* @arg @ref LL_SYSCFG_EXTI_PORTI (*)
AnnaBridge	172:65be27845400	767	*
AnnaBridge	172:65be27845400	768	* (*) value not defined in all devices
AnnaBridge	172:65be27845400	769	* @param Line This parameter can be one of the following values:
AnnaBridge	172:65be27845400	770	* @arg @ref LL_SYSCFG_EXTI_LINE0
AnnaBridge	172:65be27845400	771	* @arg @ref LL_SYSCFG_EXTI_LINE1
AnnaBridge	172:65be27845400	772	* @arg @ref LL_SYSCFG_EXTI_LINE2
AnnaBridge	172:65be27845400	773	* @arg @ref LL_SYSCFG_EXTI_LINE3
AnnaBridge	172:65be27845400	774	* @arg @ref LL_SYSCFG_EXTI_LINE4
AnnaBridge	172:65be27845400	775	* @arg @ref LL_SYSCFG_EXTI_LINE5
AnnaBridge	172:65be27845400	776	* @arg @ref LL_SYSCFG_EXTI_LINE6
AnnaBridge	172:65be27845400	777	* @arg @ref LL_SYSCFG_EXTI_LINE7
AnnaBridge	172:65be27845400	778	* @arg @ref LL_SYSCFG_EXTI_LINE8
AnnaBridge	172:65be27845400	779	* @arg @ref LL_SYSCFG_EXTI_LINE9
AnnaBridge	172:65be27845400	780	* @arg @ref LL_SYSCFG_EXTI_LINE10
AnnaBridge	172:65be27845400	781	* @arg @ref LL_SYSCFG_EXTI_LINE11
AnnaBridge	172:65be27845400	782	* @arg @ref LL_SYSCFG_EXTI_LINE12
AnnaBridge	172:65be27845400	783	* @arg @ref LL_SYSCFG_EXTI_LINE13
AnnaBridge	172:65be27845400	784	* @arg @ref LL_SYSCFG_EXTI_LINE14
AnnaBridge	172:65be27845400	785	* @arg @ref LL_SYSCFG_EXTI_LINE15
AnnaBridge	172:65be27845400	786	* @retval None
AnnaBridge	172:65be27845400	787	*/
AnnaBridge	172:65be27845400	788	__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
AnnaBridge	172:65be27845400	789	{
AnnaBridge	172:65be27845400	790	MODIFY_REG(SYSCFG->EXTICR[Line & 0xFFU], (Line >> 16U), Port << POSITION_VAL((Line >> 16U)));
AnnaBridge	172:65be27845400	791	}
AnnaBridge	172:65be27845400	792
AnnaBridge	172:65be27845400	793	/**
AnnaBridge	172:65be27845400	794	* @brief Get the configured defined for specific EXTI Line
AnnaBridge	172:65be27845400	795	* @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n
AnnaBridge	172:65be27845400	796	* SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n
AnnaBridge	172:65be27845400	797	* SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n
AnnaBridge	172:65be27845400	798	* SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource
AnnaBridge	172:65be27845400	799	* @param Line This parameter can be one of the following values:
AnnaBridge	172:65be27845400	800	* @arg @ref LL_SYSCFG_EXTI_LINE0
AnnaBridge	172:65be27845400	801	* @arg @ref LL_SYSCFG_EXTI_LINE1
AnnaBridge	172:65be27845400	802	* @arg @ref LL_SYSCFG_EXTI_LINE2
AnnaBridge	172:65be27845400	803	* @arg @ref LL_SYSCFG_EXTI_LINE3
AnnaBridge	172:65be27845400	804	* @arg @ref LL_SYSCFG_EXTI_LINE4
AnnaBridge	172:65be27845400	805	* @arg @ref LL_SYSCFG_EXTI_LINE5
AnnaBridge	172:65be27845400	806	* @arg @ref LL_SYSCFG_EXTI_LINE6
AnnaBridge	172:65be27845400	807	* @arg @ref LL_SYSCFG_EXTI_LINE7
AnnaBridge	172:65be27845400	808	* @arg @ref LL_SYSCFG_EXTI_LINE8
AnnaBridge	172:65be27845400	809	* @arg @ref LL_SYSCFG_EXTI_LINE9
AnnaBridge	172:65be27845400	810	* @arg @ref LL_SYSCFG_EXTI_LINE10
AnnaBridge	172:65be27845400	811	* @arg @ref LL_SYSCFG_EXTI_LINE11
AnnaBridge	172:65be27845400	812	* @arg @ref LL_SYSCFG_EXTI_LINE12
AnnaBridge	172:65be27845400	813	* @arg @ref LL_SYSCFG_EXTI_LINE13
AnnaBridge	172:65be27845400	814	* @arg @ref LL_SYSCFG_EXTI_LINE14
AnnaBridge	172:65be27845400	815	* @arg @ref LL_SYSCFG_EXTI_LINE15
AnnaBridge	172:65be27845400	816	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	817	* @arg @ref LL_SYSCFG_EXTI_PORTA
AnnaBridge	172:65be27845400	818	* @arg @ref LL_SYSCFG_EXTI_PORTB
AnnaBridge	172:65be27845400	819	* @arg @ref LL_SYSCFG_EXTI_PORTC
AnnaBridge	172:65be27845400	820	* @arg @ref LL_SYSCFG_EXTI_PORTD
AnnaBridge	172:65be27845400	821	* @arg @ref LL_SYSCFG_EXTI_PORTE
AnnaBridge	172:65be27845400	822	* @arg @ref LL_SYSCFG_EXTI_PORTF (*)
AnnaBridge	172:65be27845400	823	* @arg @ref LL_SYSCFG_EXTI_PORTG (*)
AnnaBridge	172:65be27845400	824	* @arg @ref LL_SYSCFG_EXTI_PORTH
AnnaBridge	172:65be27845400	825	* @arg @ref LL_SYSCFG_EXTI_PORTI (*)
AnnaBridge	172:65be27845400	826	*
AnnaBridge	172:65be27845400	827	* (*) value not defined in all devices
AnnaBridge	172:65be27845400	828	*/
AnnaBridge	172:65be27845400	829	__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
AnnaBridge	172:65be27845400	830	{
AnnaBridge	172:65be27845400	831	return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFFU], (Line >> 16U)) >> POSITION_VAL(Line >> 16U));
AnnaBridge	172:65be27845400	832	}
AnnaBridge	172:65be27845400	833
AnnaBridge	172:65be27845400	834	/**
AnnaBridge	172:65be27845400	835	* @brief Enable SRAM2 Erase (starts a hardware SRAM2 erase operation. This bit is
AnnaBridge	172:65be27845400	836	* automatically cleared at the end of the SRAM2 erase operation.)
AnnaBridge	172:65be27845400	837	* @note This bit is write-protected: setting this bit is possible only after the
AnnaBridge	172:65be27845400	838	* correct key sequence is written in the SYSCFG_SKR register as described in
AnnaBridge	172:65be27845400	839	* the Reference Manual.
AnnaBridge	172:65be27845400	840	* @rmtoll SYSCFG_SCSR SRAM2ER LL_SYSCFG_EnableSRAM2Erase
AnnaBridge	172:65be27845400	841	* @retval None
AnnaBridge	172:65be27845400	842	*/
AnnaBridge	172:65be27845400	843	__STATIC_INLINE void LL_SYSCFG_EnableSRAM2Erase(void)
AnnaBridge	172:65be27845400	844	{
AnnaBridge	172:65be27845400	845	/* Starts a hardware SRAM2 erase operation*/
AnnaBridge	172:65be27845400	846	SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER);
AnnaBridge	172:65be27845400	847	}
AnnaBridge	172:65be27845400	848
AnnaBridge	172:65be27845400	849	/**
AnnaBridge	172:65be27845400	850	* @brief Check if SRAM2 erase operation is on going
AnnaBridge	172:65be27845400	851	* @rmtoll SYSCFG_SCSR SRAM2BSY LL_SYSCFG_IsSRAM2EraseOngoing
AnnaBridge	172:65be27845400	852	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	853	*/
AnnaBridge	172:65be27845400	854	__STATIC_INLINE uint32_t LL_SYSCFG_IsSRAM2EraseOngoing(void)
AnnaBridge	172:65be27845400	855	{
AnnaBridge	172:65be27845400	856	return (READ_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2BSY) == (SYSCFG_SCSR_SRAM2BSY));
AnnaBridge	172:65be27845400	857	}
AnnaBridge	172:65be27845400	858
AnnaBridge	172:65be27845400	859	/**
AnnaBridge	172:65be27845400	860	* @brief Set connections to TIM1/8/15/16/17 Break inputs
AnnaBridge	172:65be27845400	861	* @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_SetTIMBreakInputs\n
AnnaBridge	172:65be27845400	862	* SYSCFG_CFGR2 SPL LL_SYSCFG_SetTIMBreakInputs\n
AnnaBridge	172:65be27845400	863	* SYSCFG_CFGR2 PVDL LL_SYSCFG_SetTIMBreakInputs\n
AnnaBridge	172:65be27845400	864	* SYSCFG_CFGR2 ECCL LL_SYSCFG_SetTIMBreakInputs
AnnaBridge	172:65be27845400	865	* @param Break This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	866	* @arg @ref LL_SYSCFG_TIMBREAK_ECC
AnnaBridge	172:65be27845400	867	* @arg @ref LL_SYSCFG_TIMBREAK_PVD
AnnaBridge	172:65be27845400	868	* @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_PARITY
AnnaBridge	172:65be27845400	869	* @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
AnnaBridge	172:65be27845400	870	* @retval None
AnnaBridge	172:65be27845400	871	*/
AnnaBridge	172:65be27845400	872	__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
AnnaBridge	172:65be27845400	873	{
AnnaBridge	172:65be27845400	874	MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL \| SYSCFG_CFGR2_SPL \| SYSCFG_CFGR2_PVDL \| SYSCFG_CFGR2_ECCL, Break);
AnnaBridge	172:65be27845400	875	}
AnnaBridge	172:65be27845400	876
AnnaBridge	172:65be27845400	877	/**
AnnaBridge	172:65be27845400	878	* @brief Get connections to TIM1/8/15/16/17 Break inputs
AnnaBridge	172:65be27845400	879	* @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_GetTIMBreakInputs\n
AnnaBridge	172:65be27845400	880	* SYSCFG_CFGR2 SPL LL_SYSCFG_GetTIMBreakInputs\n
AnnaBridge	172:65be27845400	881	* SYSCFG_CFGR2 PVDL LL_SYSCFG_GetTIMBreakInputs\n
AnnaBridge	172:65be27845400	882	* SYSCFG_CFGR2 ECCL LL_SYSCFG_GetTIMBreakInputs
AnnaBridge	172:65be27845400	883	* @retval Returned value can be can be a combination of the following values:
AnnaBridge	172:65be27845400	884	* @arg @ref LL_SYSCFG_TIMBREAK_ECC
AnnaBridge	172:65be27845400	885	* @arg @ref LL_SYSCFG_TIMBREAK_PVD
AnnaBridge	172:65be27845400	886	* @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_PARITY
AnnaBridge	172:65be27845400	887	* @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
AnnaBridge	172:65be27845400	888	*/
AnnaBridge	172:65be27845400	889	__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
AnnaBridge	172:65be27845400	890	{
AnnaBridge	172:65be27845400	891	return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL \| SYSCFG_CFGR2_SPL \| SYSCFG_CFGR2_PVDL \| SYSCFG_CFGR2_ECCL));
AnnaBridge	172:65be27845400	892	}
AnnaBridge	172:65be27845400	893
AnnaBridge	172:65be27845400	894	/**
AnnaBridge	172:65be27845400	895	* @brief Check if SRAM2 parity error detected
AnnaBridge	172:65be27845400	896	* @rmtoll SYSCFG_CFGR2 SPF LL_SYSCFG_IsActiveFlag_SP
AnnaBridge	172:65be27845400	897	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	898	*/
AnnaBridge	172:65be27845400	899	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void)
AnnaBridge	172:65be27845400	900	{
AnnaBridge	172:65be27845400	901	return (READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) == (SYSCFG_CFGR2_SPF));
AnnaBridge	172:65be27845400	902	}
AnnaBridge	172:65be27845400	903
AnnaBridge	172:65be27845400	904	/**
AnnaBridge	172:65be27845400	905	* @brief Clear SRAM2 parity error flag
AnnaBridge	172:65be27845400	906	* @rmtoll SYSCFG_CFGR2 SPF LL_SYSCFG_ClearFlag_SP
AnnaBridge	172:65be27845400	907	* @retval None
AnnaBridge	172:65be27845400	908	*/
AnnaBridge	172:65be27845400	909	__STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void)
AnnaBridge	172:65be27845400	910	{
AnnaBridge	172:65be27845400	911	SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF);
AnnaBridge	172:65be27845400	912	}
AnnaBridge	172:65be27845400	913
AnnaBridge	172:65be27845400	914	/**
AnnaBridge	172:65be27845400	915	* @brief Enable SRAM2 page write protection for Pages in range 0 to 31
AnnaBridge	172:65be27845400	916	* @note Write protection is cleared only by a system reset
AnnaBridge	172:65be27845400	917	* @rmtoll SYSCFG_SWPR PxWP LL_SYSCFG_EnableSRAM2PageWRP_0_31
AnnaBridge	172:65be27845400	918	* @param SRAM2WRP This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	919	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE0
AnnaBridge	172:65be27845400	920	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE1
AnnaBridge	172:65be27845400	921	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE2
AnnaBridge	172:65be27845400	922	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE3
AnnaBridge	172:65be27845400	923	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE4
AnnaBridge	172:65be27845400	924	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE5
AnnaBridge	172:65be27845400	925	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE6
AnnaBridge	172:65be27845400	926	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE7
AnnaBridge	172:65be27845400	927	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE8
AnnaBridge	172:65be27845400	928	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE9
AnnaBridge	172:65be27845400	929	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE10
AnnaBridge	172:65be27845400	930	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE11
AnnaBridge	172:65be27845400	931	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE12
AnnaBridge	172:65be27845400	932	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE13
AnnaBridge	172:65be27845400	933	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE14
AnnaBridge	172:65be27845400	934	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE15
AnnaBridge	172:65be27845400	935	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE16 (*)
AnnaBridge	172:65be27845400	936	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE17 (*)
AnnaBridge	172:65be27845400	937	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE18 (*)
AnnaBridge	172:65be27845400	938	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE19 (*)
AnnaBridge	172:65be27845400	939	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE20 (*)
AnnaBridge	172:65be27845400	940	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE21 (*)
AnnaBridge	172:65be27845400	941	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE22 (*)
AnnaBridge	172:65be27845400	942	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE23 (*)
AnnaBridge	172:65be27845400	943	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE24 (*)
AnnaBridge	172:65be27845400	944	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE25 (*)
AnnaBridge	172:65be27845400	945	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE26 (*)
AnnaBridge	172:65be27845400	946	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE27 (*)
AnnaBridge	172:65be27845400	947	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE28 (*)
AnnaBridge	172:65be27845400	948	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE29 (*)
AnnaBridge	172:65be27845400	949	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE30 (*)
AnnaBridge	172:65be27845400	950	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE31 (*)
AnnaBridge	172:65be27845400	951	*
AnnaBridge	172:65be27845400	952	* (*) value not defined in all devices
AnnaBridge	172:65be27845400	953	* @retval None
AnnaBridge	172:65be27845400	954	*/
AnnaBridge	172:65be27845400	955	/* Legacy define */
AnnaBridge	172:65be27845400	956	#define LL_SYSCFG_EnableSRAM2PageWRP LL_SYSCFG_EnableSRAM2PageWRP_0_31
AnnaBridge	172:65be27845400	957	__STATIC_INLINE void LL_SYSCFG_EnableSRAM2PageWRP_0_31(uint32_t SRAM2WRP)
AnnaBridge	172:65be27845400	958	{
AnnaBridge	172:65be27845400	959	SET_BIT(SYSCFG->SWPR, SRAM2WRP);
AnnaBridge	172:65be27845400	960	}
AnnaBridge	172:65be27845400	961
AnnaBridge	172:65be27845400	962	#if defined(SYSCFG_SWPR2_PAGE63)
AnnaBridge	172:65be27845400	963	/**
AnnaBridge	172:65be27845400	964	* @brief Enable SRAM2 page write protection for Pages in range 32 to 63
AnnaBridge	172:65be27845400	965	* @note Write protection is cleared only by a system reset
AnnaBridge	172:65be27845400	966	* @rmtoll SYSCFG_SWPR2 PxWP LL_SYSCFG_EnableSRAM2PageWRP_32_63
AnnaBridge	172:65be27845400	967	* @param SRAM2WRP This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	968	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE32 (*)
AnnaBridge	172:65be27845400	969	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE33 (*)
AnnaBridge	172:65be27845400	970	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE34 (*)
AnnaBridge	172:65be27845400	971	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE35 (*)
AnnaBridge	172:65be27845400	972	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE36 (*)
AnnaBridge	172:65be27845400	973	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE37 (*)
AnnaBridge	172:65be27845400	974	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE38 (*)
AnnaBridge	172:65be27845400	975	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE39 (*)
AnnaBridge	172:65be27845400	976	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE40 (*)
AnnaBridge	172:65be27845400	977	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE41 (*)
AnnaBridge	172:65be27845400	978	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE42 (*)
AnnaBridge	172:65be27845400	979	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE43 (*)
AnnaBridge	172:65be27845400	980	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE44 (*)
AnnaBridge	172:65be27845400	981	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE45 (*)
AnnaBridge	172:65be27845400	982	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE46 (*)
AnnaBridge	172:65be27845400	983	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE47 (*)
AnnaBridge	172:65be27845400	984	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE48 (*)
AnnaBridge	172:65be27845400	985	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE49 (*)
AnnaBridge	172:65be27845400	986	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE50 (*)
AnnaBridge	172:65be27845400	987	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE51 (*)
AnnaBridge	172:65be27845400	988	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE52 (*)
AnnaBridge	172:65be27845400	989	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE53 (*)
AnnaBridge	172:65be27845400	990	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE54 (*)
AnnaBridge	172:65be27845400	991	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE55 (*)
AnnaBridge	172:65be27845400	992	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE56 (*)
AnnaBridge	172:65be27845400	993	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE57 (*)
AnnaBridge	172:65be27845400	994	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE58 (*)
AnnaBridge	172:65be27845400	995	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE59 (*)
AnnaBridge	172:65be27845400	996	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE60 (*)
AnnaBridge	172:65be27845400	997	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE61 (*)
AnnaBridge	172:65be27845400	998	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE62 (*)
AnnaBridge	172:65be27845400	999	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE63 (*)
AnnaBridge	172:65be27845400	1000	*
AnnaBridge	172:65be27845400	1001	* (*) value not defined in all devices
AnnaBridge	172:65be27845400	1002	* @retval None
AnnaBridge	172:65be27845400	1003	*/
AnnaBridge	172:65be27845400	1004	__STATIC_INLINE void LL_SYSCFG_EnableSRAM2PageWRP_32_63(uint32_t SRAM2WRP)
AnnaBridge	172:65be27845400	1005	{
AnnaBridge	172:65be27845400	1006	SET_BIT(SYSCFG->SWPR2, SRAM2WRP);
AnnaBridge	172:65be27845400	1007	}
AnnaBridge	172:65be27845400	1008	#endif /* SYSCFG_SWPR2_PAGE63 */
AnnaBridge	172:65be27845400	1009
AnnaBridge	172:65be27845400	1010	/**
AnnaBridge	172:65be27845400	1011	* @brief SRAM2 page write protection lock prior to erase
AnnaBridge	172:65be27845400	1012	* @rmtoll SYSCFG_SKR KEY LL_SYSCFG_LockSRAM2WRP
AnnaBridge	172:65be27845400	1013	* @retval None
AnnaBridge	172:65be27845400	1014	*/
AnnaBridge	172:65be27845400	1015	__STATIC_INLINE void LL_SYSCFG_LockSRAM2WRP(void)
AnnaBridge	172:65be27845400	1016	{
AnnaBridge	172:65be27845400	1017	/* Writing a wrong key reactivates the write protection */
AnnaBridge	172:65be27845400	1018	WRITE_REG(SYSCFG->SKR, 0x00);
AnnaBridge	172:65be27845400	1019	}
AnnaBridge	172:65be27845400	1020
AnnaBridge	172:65be27845400	1021	/**
AnnaBridge	172:65be27845400	1022	* @brief SRAM2 page write protection unlock prior to erase
AnnaBridge	172:65be27845400	1023	* @rmtoll SYSCFG_SKR KEY LL_SYSCFG_UnlockSRAM2WRP
AnnaBridge	172:65be27845400	1024	* @retval None
AnnaBridge	172:65be27845400	1025	*/
AnnaBridge	172:65be27845400	1026	__STATIC_INLINE void LL_SYSCFG_UnlockSRAM2WRP(void)
AnnaBridge	172:65be27845400	1027	{
AnnaBridge	172:65be27845400	1028	/* unlock the write protection of the SRAM2ER bit */
AnnaBridge	172:65be27845400	1029	WRITE_REG(SYSCFG->SKR, 0xCA);
AnnaBridge	172:65be27845400	1030	WRITE_REG(SYSCFG->SKR, 0x53);
AnnaBridge	172:65be27845400	1031	}
AnnaBridge	172:65be27845400	1032
AnnaBridge	172:65be27845400	1033	/**
AnnaBridge	172:65be27845400	1034	* @}
AnnaBridge	172:65be27845400	1035	*/
AnnaBridge	172:65be27845400	1036
AnnaBridge	172:65be27845400	1037
AnnaBridge	172:65be27845400	1038	/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
AnnaBridge	172:65be27845400	1039	* @{
AnnaBridge	172:65be27845400	1040	*/
AnnaBridge	172:65be27845400	1041
AnnaBridge	172:65be27845400	1042	/**
AnnaBridge	172:65be27845400	1043	* @brief Return the device identifier
AnnaBridge	172:65be27845400	1044	* @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
AnnaBridge	172:65be27845400	1045	* @retval Values between Min_Data=0x00 and Max_Data=0xFFFF (ex: device ID is 0x6415)
AnnaBridge	172:65be27845400	1046	*/
AnnaBridge	172:65be27845400	1047	__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
AnnaBridge	172:65be27845400	1048	{
AnnaBridge	172:65be27845400	1049	return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
AnnaBridge	172:65be27845400	1050	}
AnnaBridge	172:65be27845400	1051
AnnaBridge	172:65be27845400	1052	/**
AnnaBridge	172:65be27845400	1053	* @brief Return the device revision identifier
AnnaBridge	172:65be27845400	1054	* @note This field indicates the revision of the device.
AnnaBridge	172:65be27845400	1055	* @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
AnnaBridge	172:65be27845400	1056	* @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
AnnaBridge	172:65be27845400	1057	*/
AnnaBridge	172:65be27845400	1058	__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
AnnaBridge	172:65be27845400	1059	{
AnnaBridge	172:65be27845400	1060	return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
AnnaBridge	172:65be27845400	1061	}
AnnaBridge	172:65be27845400	1062
AnnaBridge	172:65be27845400	1063	/**
AnnaBridge	172:65be27845400	1064	* @brief Enable the Debug Module during SLEEP mode
AnnaBridge	172:65be27845400	1065	* @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
AnnaBridge	172:65be27845400	1066	* @retval None
AnnaBridge	172:65be27845400	1067	*/
AnnaBridge	172:65be27845400	1068	__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
AnnaBridge	172:65be27845400	1069	{
AnnaBridge	172:65be27845400	1070	SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
AnnaBridge	172:65be27845400	1071	}
AnnaBridge	172:65be27845400	1072
AnnaBridge	172:65be27845400	1073	/**
AnnaBridge	172:65be27845400	1074	* @brief Disable the Debug Module during SLEEP mode
AnnaBridge	172:65be27845400	1075	* @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
AnnaBridge	172:65be27845400	1076	* @retval None
AnnaBridge	172:65be27845400	1077	*/
AnnaBridge	172:65be27845400	1078	__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
AnnaBridge	172:65be27845400	1079	{
AnnaBridge	172:65be27845400	1080	CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
AnnaBridge	172:65be27845400	1081	}
AnnaBridge	172:65be27845400	1082
AnnaBridge	172:65be27845400	1083	/**
AnnaBridge	172:65be27845400	1084	* @brief Enable the Debug Module during STOP mode
AnnaBridge	172:65be27845400	1085	* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
AnnaBridge	172:65be27845400	1086	* @retval None
AnnaBridge	172:65be27845400	1087	*/
AnnaBridge	172:65be27845400	1088	__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
AnnaBridge	172:65be27845400	1089	{
AnnaBridge	172:65be27845400	1090	SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
AnnaBridge	172:65be27845400	1091	}
AnnaBridge	172:65be27845400	1092
AnnaBridge	172:65be27845400	1093	/**
AnnaBridge	172:65be27845400	1094	* @brief Disable the Debug Module during STOP mode
AnnaBridge	172:65be27845400	1095	* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
AnnaBridge	172:65be27845400	1096	* @retval None
AnnaBridge	172:65be27845400	1097	*/
AnnaBridge	172:65be27845400	1098	__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
AnnaBridge	172:65be27845400	1099	{
AnnaBridge	172:65be27845400	1100	CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
AnnaBridge	172:65be27845400	1101	}
AnnaBridge	172:65be27845400	1102
AnnaBridge	172:65be27845400	1103	/**
AnnaBridge	172:65be27845400	1104	* @brief Enable the Debug Module during STANDBY mode
AnnaBridge	172:65be27845400	1105	* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
AnnaBridge	172:65be27845400	1106	* @retval None
AnnaBridge	172:65be27845400	1107	*/
AnnaBridge	172:65be27845400	1108	__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
AnnaBridge	172:65be27845400	1109	{
AnnaBridge	172:65be27845400	1110	SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
AnnaBridge	172:65be27845400	1111	}
AnnaBridge	172:65be27845400	1112
AnnaBridge	172:65be27845400	1113	/**
AnnaBridge	172:65be27845400	1114	* @brief Disable the Debug Module during STANDBY mode
AnnaBridge	172:65be27845400	1115	* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
AnnaBridge	172:65be27845400	1116	* @retval None
AnnaBridge	172:65be27845400	1117	*/
AnnaBridge	172:65be27845400	1118	__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
AnnaBridge	172:65be27845400	1119	{
AnnaBridge	172:65be27845400	1120	CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
AnnaBridge	172:65be27845400	1121	}
AnnaBridge	172:65be27845400	1122
AnnaBridge	172:65be27845400	1123	/**
AnnaBridge	172:65be27845400	1124	* @brief Set Trace pin assignment control
AnnaBridge	172:65be27845400	1125	* @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
AnnaBridge	172:65be27845400	1126	* DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
AnnaBridge	172:65be27845400	1127	* @param PinAssignment This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1128	* @arg @ref LL_DBGMCU_TRACE_NONE
AnnaBridge	172:65be27845400	1129	* @arg @ref LL_DBGMCU_TRACE_ASYNCH
AnnaBridge	172:65be27845400	1130	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
AnnaBridge	172:65be27845400	1131	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
AnnaBridge	172:65be27845400	1132	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
AnnaBridge	172:65be27845400	1133	* @retval None
AnnaBridge	172:65be27845400	1134	*/
AnnaBridge	172:65be27845400	1135	__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
AnnaBridge	172:65be27845400	1136	{
AnnaBridge	172:65be27845400	1137	MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE, PinAssignment);
AnnaBridge	172:65be27845400	1138	}
AnnaBridge	172:65be27845400	1139
AnnaBridge	172:65be27845400	1140	/**
AnnaBridge	172:65be27845400	1141	* @brief Get Trace pin assignment control
AnnaBridge	172:65be27845400	1142	* @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
AnnaBridge	172:65be27845400	1143	* DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
AnnaBridge	172:65be27845400	1144	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1145	* @arg @ref LL_DBGMCU_TRACE_NONE
AnnaBridge	172:65be27845400	1146	* @arg @ref LL_DBGMCU_TRACE_ASYNCH
AnnaBridge	172:65be27845400	1147	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
AnnaBridge	172:65be27845400	1148	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
AnnaBridge	172:65be27845400	1149	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
AnnaBridge	172:65be27845400	1150	*/
AnnaBridge	172:65be27845400	1151	__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
AnnaBridge	172:65be27845400	1152	{
AnnaBridge	172:65be27845400	1153	return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE));
AnnaBridge	172:65be27845400	1154	}
AnnaBridge	172:65be27845400	1155
AnnaBridge	172:65be27845400	1156	/**
AnnaBridge	172:65be27845400	1157	* @brief Freeze APB1 peripherals (group1 peripherals)
AnnaBridge	172:65be27845400	1158	* @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
AnnaBridge	172:65be27845400	1159	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	1160	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
AnnaBridge	172:65be27845400	1161	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
AnnaBridge	172:65be27845400	1162	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
AnnaBridge	172:65be27845400	1163	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
AnnaBridge	172:65be27845400	1164	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
AnnaBridge	172:65be27845400	1165	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
AnnaBridge	172:65be27845400	1166	* @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
AnnaBridge	172:65be27845400	1167	* @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
AnnaBridge	172:65be27845400	1168	* @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
AnnaBridge	172:65be27845400	1169	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
AnnaBridge	172:65be27845400	1170	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
AnnaBridge	172:65be27845400	1171	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
AnnaBridge	172:65be27845400	1172	* @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP
AnnaBridge	172:65be27845400	1173	* @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
AnnaBridge	172:65be27845400	1174	* @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
AnnaBridge	172:65be27845400	1175	*
AnnaBridge	172:65be27845400	1176	* (*) value not defined in all devices.
AnnaBridge	172:65be27845400	1177	* @retval None
AnnaBridge	172:65be27845400	1178	*/
AnnaBridge	172:65be27845400	1179	__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
AnnaBridge	172:65be27845400	1180	{
AnnaBridge	172:65be27845400	1181	SET_BIT(DBGMCU->APB1FZR1, Periphs);
AnnaBridge	172:65be27845400	1182	}
AnnaBridge	172:65be27845400	1183
AnnaBridge	172:65be27845400	1184	/**
AnnaBridge	172:65be27845400	1185	* @brief Freeze APB1 peripherals (group2 peripherals)
AnnaBridge	172:65be27845400	1186	* @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph
AnnaBridge	172:65be27845400	1187	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	1188	* @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP (*)
AnnaBridge	172:65be27845400	1189	* @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
AnnaBridge	172:65be27845400	1190	*
AnnaBridge	172:65be27845400	1191	* (*) value not defined in all devices.
AnnaBridge	172:65be27845400	1192	* @retval None
AnnaBridge	172:65be27845400	1193	*/
AnnaBridge	172:65be27845400	1194	__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
AnnaBridge	172:65be27845400	1195	{
AnnaBridge	172:65be27845400	1196	SET_BIT(DBGMCU->APB1FZR2, Periphs);
AnnaBridge	172:65be27845400	1197	}
AnnaBridge	172:65be27845400	1198
AnnaBridge	172:65be27845400	1199	/**
AnnaBridge	172:65be27845400	1200	* @brief Unfreeze APB1 peripherals (group1 peripherals)
AnnaBridge	172:65be27845400	1201	* @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
AnnaBridge	172:65be27845400	1202	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	1203	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
AnnaBridge	172:65be27845400	1204	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
AnnaBridge	172:65be27845400	1205	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
AnnaBridge	172:65be27845400	1206	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
AnnaBridge	172:65be27845400	1207	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
AnnaBridge	172:65be27845400	1208	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
AnnaBridge	172:65be27845400	1209	* @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
AnnaBridge	172:65be27845400	1210	* @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
AnnaBridge	172:65be27845400	1211	* @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
AnnaBridge	172:65be27845400	1212	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
AnnaBridge	172:65be27845400	1213	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
AnnaBridge	172:65be27845400	1214	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
AnnaBridge	172:65be27845400	1215	* @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP
AnnaBridge	172:65be27845400	1216	* @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
AnnaBridge	172:65be27845400	1217	* @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
AnnaBridge	172:65be27845400	1218	*
AnnaBridge	172:65be27845400	1219	* (*) value not defined in all devices.
AnnaBridge	172:65be27845400	1220	* @retval None
AnnaBridge	172:65be27845400	1221	*/
AnnaBridge	172:65be27845400	1222	__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
AnnaBridge	172:65be27845400	1223	{
AnnaBridge	172:65be27845400	1224	CLEAR_BIT(DBGMCU->APB1FZR1, Periphs);
AnnaBridge	172:65be27845400	1225	}
AnnaBridge	172:65be27845400	1226
AnnaBridge	172:65be27845400	1227	/**
AnnaBridge	172:65be27845400	1228	* @brief Unfreeze APB1 peripherals (group2 peripherals)
AnnaBridge	172:65be27845400	1229	* @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph
AnnaBridge	172:65be27845400	1230	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	1231	* @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP (*)
AnnaBridge	172:65be27845400	1232	* @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
AnnaBridge	172:65be27845400	1233	*
AnnaBridge	172:65be27845400	1234	* (*) value not defined in all devices.
AnnaBridge	172:65be27845400	1235	* @retval None
AnnaBridge	172:65be27845400	1236	*/
AnnaBridge	172:65be27845400	1237	__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
AnnaBridge	172:65be27845400	1238	{
AnnaBridge	172:65be27845400	1239	CLEAR_BIT(DBGMCU->APB1FZR2, Periphs);
AnnaBridge	172:65be27845400	1240	}
AnnaBridge	172:65be27845400	1241
AnnaBridge	172:65be27845400	1242	/**
AnnaBridge	172:65be27845400	1243	* @brief Freeze APB2 peripherals
AnnaBridge	172:65be27845400	1244	* @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
AnnaBridge	172:65be27845400	1245	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	1246	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
AnnaBridge	172:65be27845400	1247	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
AnnaBridge	172:65be27845400	1248	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
AnnaBridge	172:65be27845400	1249	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
AnnaBridge	172:65be27845400	1250	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
AnnaBridge	172:65be27845400	1251	*
AnnaBridge	172:65be27845400	1252	* (*) value not defined in all devices.
AnnaBridge	172:65be27845400	1253	* @retval None
AnnaBridge	172:65be27845400	1254	*/
AnnaBridge	172:65be27845400	1255	__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
AnnaBridge	172:65be27845400	1256	{
AnnaBridge	172:65be27845400	1257	SET_BIT(DBGMCU->APB2FZ, Periphs);
AnnaBridge	172:65be27845400	1258	}
AnnaBridge	172:65be27845400	1259
AnnaBridge	172:65be27845400	1260	/**
AnnaBridge	172:65be27845400	1261	* @brief Unfreeze APB2 peripherals
AnnaBridge	172:65be27845400	1262	* @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
AnnaBridge	172:65be27845400	1263	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	1264	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
AnnaBridge	172:65be27845400	1265	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
AnnaBridge	172:65be27845400	1266	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
AnnaBridge	172:65be27845400	1267	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
AnnaBridge	172:65be27845400	1268	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
AnnaBridge	172:65be27845400	1269	*
AnnaBridge	172:65be27845400	1270	* (*) value not defined in all devices.
AnnaBridge	172:65be27845400	1271	* @retval None
AnnaBridge	172:65be27845400	1272	*/
AnnaBridge	172:65be27845400	1273	__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
AnnaBridge	172:65be27845400	1274	{
AnnaBridge	172:65be27845400	1275	CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
AnnaBridge	172:65be27845400	1276	}
AnnaBridge	172:65be27845400	1277
AnnaBridge	172:65be27845400	1278	/**
AnnaBridge	172:65be27845400	1279	* @}
AnnaBridge	172:65be27845400	1280	*/
AnnaBridge	172:65be27845400	1281
AnnaBridge	172:65be27845400	1282	#if defined(VREFBUF)
AnnaBridge	172:65be27845400	1283	/** @defgroup SYSTEM_LL_EF_VREFBUF VREFBUF
AnnaBridge	172:65be27845400	1284	* @{
AnnaBridge	172:65be27845400	1285	*/
AnnaBridge	172:65be27845400	1286
AnnaBridge	172:65be27845400	1287	/**
AnnaBridge	172:65be27845400	1288	* @brief Enable Internal voltage reference
AnnaBridge	172:65be27845400	1289	* @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Enable
AnnaBridge	172:65be27845400	1290	* @retval None
AnnaBridge	172:65be27845400	1291	*/
AnnaBridge	172:65be27845400	1292	__STATIC_INLINE void LL_VREFBUF_Enable(void)
AnnaBridge	172:65be27845400	1293	{
AnnaBridge	172:65be27845400	1294	SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
AnnaBridge	172:65be27845400	1295	}
AnnaBridge	172:65be27845400	1296
AnnaBridge	172:65be27845400	1297	/**
AnnaBridge	172:65be27845400	1298	* @brief Disable Internal voltage reference
AnnaBridge	172:65be27845400	1299	* @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Disable
AnnaBridge	172:65be27845400	1300	* @retval None
AnnaBridge	172:65be27845400	1301	*/
AnnaBridge	172:65be27845400	1302	__STATIC_INLINE void LL_VREFBUF_Disable(void)
AnnaBridge	172:65be27845400	1303	{
AnnaBridge	172:65be27845400	1304	CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
AnnaBridge	172:65be27845400	1305	}
AnnaBridge	172:65be27845400	1306
AnnaBridge	172:65be27845400	1307	/**
AnnaBridge	172:65be27845400	1308	* @brief Enable high impedance (VREF+pin is high impedance)
AnnaBridge	172:65be27845400	1309	* @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_EnableHIZ
AnnaBridge	172:65be27845400	1310	* @retval None
AnnaBridge	172:65be27845400	1311	*/
AnnaBridge	172:65be27845400	1312	__STATIC_INLINE void LL_VREFBUF_EnableHIZ(void)
AnnaBridge	172:65be27845400	1313	{
AnnaBridge	172:65be27845400	1314	SET_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
AnnaBridge	172:65be27845400	1315	}
AnnaBridge	172:65be27845400	1316
AnnaBridge	172:65be27845400	1317	/**
AnnaBridge	172:65be27845400	1318	* @brief Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output)
AnnaBridge	172:65be27845400	1319	* @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_DisableHIZ
AnnaBridge	172:65be27845400	1320	* @retval None
AnnaBridge	172:65be27845400	1321	*/
AnnaBridge	172:65be27845400	1322	__STATIC_INLINE void LL_VREFBUF_DisableHIZ(void)
AnnaBridge	172:65be27845400	1323	{
AnnaBridge	172:65be27845400	1324	CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
AnnaBridge	172:65be27845400	1325	}
AnnaBridge	172:65be27845400	1326
AnnaBridge	172:65be27845400	1327	/**
AnnaBridge	172:65be27845400	1328	* @brief Set the Voltage reference scale
AnnaBridge	172:65be27845400	1329	* @rmtoll VREFBUF_CSR VRS LL_VREFBUF_SetVoltageScaling
AnnaBridge	172:65be27845400	1330	* @param Scale This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1331	* @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
AnnaBridge	172:65be27845400	1332	* @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
AnnaBridge	172:65be27845400	1333	* @retval None
AnnaBridge	172:65be27845400	1334	*/
AnnaBridge	172:65be27845400	1335	__STATIC_INLINE void LL_VREFBUF_SetVoltageScaling(uint32_t Scale)
AnnaBridge	172:65be27845400	1336	{
AnnaBridge	172:65be27845400	1337	MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, Scale);
AnnaBridge	172:65be27845400	1338	}
AnnaBridge	172:65be27845400	1339
AnnaBridge	172:65be27845400	1340	/**
AnnaBridge	172:65be27845400	1341	* @brief Get the Voltage reference scale
AnnaBridge	172:65be27845400	1342	* @rmtoll VREFBUF_CSR VRS LL_VREFBUF_GetVoltageScaling
AnnaBridge	172:65be27845400	1343	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1344	* @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
AnnaBridge	172:65be27845400	1345	* @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
AnnaBridge	172:65be27845400	1346	*/
AnnaBridge	172:65be27845400	1347	__STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling(void)
AnnaBridge	172:65be27845400	1348	{
AnnaBridge	172:65be27845400	1349	return (uint32_t)(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRS));
AnnaBridge	172:65be27845400	1350	}
AnnaBridge	172:65be27845400	1351
AnnaBridge	172:65be27845400	1352	/**
AnnaBridge	172:65be27845400	1353	* @brief Check if Voltage reference buffer is ready
AnnaBridge	172:65be27845400	1354	* @rmtoll VREFBUF_CSR VRR LL_VREFBUF_IsVREFReady
AnnaBridge	172:65be27845400	1355	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1356	*/
AnnaBridge	172:65be27845400	1357	__STATIC_INLINE uint32_t LL_VREFBUF_IsVREFReady(void)
AnnaBridge	172:65be27845400	1358	{
AnnaBridge	172:65be27845400	1359	return (READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == (VREFBUF_CSR_VRR));
AnnaBridge	172:65be27845400	1360	}
AnnaBridge	172:65be27845400	1361
AnnaBridge	172:65be27845400	1362	/**
AnnaBridge	172:65be27845400	1363	* @brief Get the trimming code for VREFBUF calibration
AnnaBridge	172:65be27845400	1364	* @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_GetTrimming
AnnaBridge	172:65be27845400	1365	* @retval Between 0 and 0x3F
AnnaBridge	172:65be27845400	1366	*/
AnnaBridge	172:65be27845400	1367	__STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming(void)
AnnaBridge	172:65be27845400	1368	{
AnnaBridge	172:65be27845400	1369	return (uint32_t)(READ_BIT(VREFBUF->CCR, VREFBUF_CCR_TRIM));
AnnaBridge	172:65be27845400	1370	}
AnnaBridge	172:65be27845400	1371
AnnaBridge	172:65be27845400	1372	/**
AnnaBridge	172:65be27845400	1373	* @brief Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage)
AnnaBridge	172:65be27845400	1374	* @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_SetTrimming
AnnaBridge	172:65be27845400	1375	* @param Value Between 0 and 0x3F
AnnaBridge	172:65be27845400	1376	* @retval None
AnnaBridge	172:65be27845400	1377	*/
AnnaBridge	172:65be27845400	1378	__STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value)
AnnaBridge	172:65be27845400	1379	{
AnnaBridge	172:65be27845400	1380	WRITE_REG(VREFBUF->CCR, Value);
AnnaBridge	172:65be27845400	1381	}
AnnaBridge	172:65be27845400	1382
AnnaBridge	172:65be27845400	1383	/**
AnnaBridge	172:65be27845400	1384	* @}
AnnaBridge	172:65be27845400	1385	*/
AnnaBridge	172:65be27845400	1386	#endif /* VREFBUF */
AnnaBridge	172:65be27845400	1387
AnnaBridge	172:65be27845400	1388	/** @defgroup SYSTEM_LL_EF_FLASH FLASH
AnnaBridge	172:65be27845400	1389	* @{
AnnaBridge	172:65be27845400	1390	*/
AnnaBridge	172:65be27845400	1391
AnnaBridge	172:65be27845400	1392	/**
AnnaBridge	172:65be27845400	1393	* @brief Set FLASH Latency
AnnaBridge	172:65be27845400	1394	* @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
AnnaBridge	172:65be27845400	1395	* @param Latency This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1396	* @arg @ref LL_FLASH_LATENCY_0
AnnaBridge	172:65be27845400	1397	* @arg @ref LL_FLASH_LATENCY_1
AnnaBridge	172:65be27845400	1398	* @arg @ref LL_FLASH_LATENCY_2
AnnaBridge	172:65be27845400	1399	* @arg @ref LL_FLASH_LATENCY_3
AnnaBridge	172:65be27845400	1400	* @arg @ref LL_FLASH_LATENCY_4
AnnaBridge	172:65be27845400	1401	* @arg @ref LL_FLASH_LATENCY_5 (*)
AnnaBridge	172:65be27845400	1402	* @arg @ref LL_FLASH_LATENCY_6 (*)
AnnaBridge	172:65be27845400	1403	* @arg @ref LL_FLASH_LATENCY_7 (*)
AnnaBridge	172:65be27845400	1404	* @arg @ref LL_FLASH_LATENCY_8 (*)
AnnaBridge	172:65be27845400	1405	* @arg @ref LL_FLASH_LATENCY_9 (*)
AnnaBridge	172:65be27845400	1406	* @arg @ref LL_FLASH_LATENCY_10 (*)
AnnaBridge	172:65be27845400	1407	* @arg @ref LL_FLASH_LATENCY_11 (*)
AnnaBridge	172:65be27845400	1408	* @arg @ref LL_FLASH_LATENCY_12 (*)
AnnaBridge	172:65be27845400	1409	* @arg @ref LL_FLASH_LATENCY_13 (*)
AnnaBridge	172:65be27845400	1410	* @arg @ref LL_FLASH_LATENCY_14 (*)
AnnaBridge	172:65be27845400	1411	* @arg @ref LL_FLASH_LATENCY_15 (*)
AnnaBridge	172:65be27845400	1412	*
AnnaBridge	172:65be27845400	1413	* (*) value not defined in all devices.
AnnaBridge	172:65be27845400	1414	* @retval None
AnnaBridge	172:65be27845400	1415	*/
AnnaBridge	172:65be27845400	1416	__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
AnnaBridge	172:65be27845400	1417	{
AnnaBridge	172:65be27845400	1418	MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
AnnaBridge	172:65be27845400	1419	}
AnnaBridge	172:65be27845400	1420
AnnaBridge	172:65be27845400	1421	/**
AnnaBridge	172:65be27845400	1422	* @brief Get FLASH Latency
AnnaBridge	172:65be27845400	1423	* @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
AnnaBridge	172:65be27845400	1424	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1425	* @arg @ref LL_FLASH_LATENCY_0
AnnaBridge	172:65be27845400	1426	* @arg @ref LL_FLASH_LATENCY_1
AnnaBridge	172:65be27845400	1427	* @arg @ref LL_FLASH_LATENCY_2
AnnaBridge	172:65be27845400	1428	* @arg @ref LL_FLASH_LATENCY_3
AnnaBridge	172:65be27845400	1429	* @arg @ref LL_FLASH_LATENCY_4
AnnaBridge	172:65be27845400	1430	* @arg @ref LL_FLASH_LATENCY_5 (*)
AnnaBridge	172:65be27845400	1431	* @arg @ref LL_FLASH_LATENCY_6 (*)
AnnaBridge	172:65be27845400	1432	* @arg @ref LL_FLASH_LATENCY_7 (*)
AnnaBridge	172:65be27845400	1433	* @arg @ref LL_FLASH_LATENCY_8 (*)
AnnaBridge	172:65be27845400	1434	* @arg @ref LL_FLASH_LATENCY_9 (*)
AnnaBridge	172:65be27845400	1435	* @arg @ref LL_FLASH_LATENCY_10 (*)
AnnaBridge	172:65be27845400	1436	* @arg @ref LL_FLASH_LATENCY_11 (*)
AnnaBridge	172:65be27845400	1437	* @arg @ref LL_FLASH_LATENCY_12 (*)
AnnaBridge	172:65be27845400	1438	* @arg @ref LL_FLASH_LATENCY_13 (*)
AnnaBridge	172:65be27845400	1439	* @arg @ref LL_FLASH_LATENCY_14 (*)
AnnaBridge	172:65be27845400	1440	* @arg @ref LL_FLASH_LATENCY_15 (*)
AnnaBridge	172:65be27845400	1441	*
AnnaBridge	172:65be27845400	1442	* (*) value not defined in all devices.
AnnaBridge	172:65be27845400	1443	*/
AnnaBridge	172:65be27845400	1444	__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
AnnaBridge	172:65be27845400	1445	{
AnnaBridge	172:65be27845400	1446	return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
AnnaBridge	172:65be27845400	1447	}
AnnaBridge	172:65be27845400	1448
AnnaBridge	172:65be27845400	1449	/**
AnnaBridge	172:65be27845400	1450	* @brief Enable Prefetch
AnnaBridge	172:65be27845400	1451	* @rmtoll FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch
AnnaBridge	172:65be27845400	1452	* @retval None
AnnaBridge	172:65be27845400	1453	*/
AnnaBridge	172:65be27845400	1454	__STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
AnnaBridge	172:65be27845400	1455	{
AnnaBridge	172:65be27845400	1456	SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
AnnaBridge	172:65be27845400	1457	}
AnnaBridge	172:65be27845400	1458
AnnaBridge	172:65be27845400	1459	/**
AnnaBridge	172:65be27845400	1460	* @brief Disable Prefetch
AnnaBridge	172:65be27845400	1461	* @rmtoll FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch
AnnaBridge	172:65be27845400	1462	* @retval None
AnnaBridge	172:65be27845400	1463	*/
AnnaBridge	172:65be27845400	1464	__STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
AnnaBridge	172:65be27845400	1465	{
AnnaBridge	172:65be27845400	1466	CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
AnnaBridge	172:65be27845400	1467	}
AnnaBridge	172:65be27845400	1468
AnnaBridge	172:65be27845400	1469	/**
AnnaBridge	172:65be27845400	1470	* @brief Check if Prefetch buffer is enabled
AnnaBridge	172:65be27845400	1471	* @rmtoll FLASH_ACR PRFTEN LL_FLASH_IsPrefetchEnabled
AnnaBridge	172:65be27845400	1472	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1473	*/
AnnaBridge	172:65be27845400	1474	__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
AnnaBridge	172:65be27845400	1475	{
AnnaBridge	172:65be27845400	1476	return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN));
AnnaBridge	172:65be27845400	1477	}
AnnaBridge	172:65be27845400	1478
AnnaBridge	172:65be27845400	1479	/**
AnnaBridge	172:65be27845400	1480	* @brief Enable Instruction cache
AnnaBridge	172:65be27845400	1481	* @rmtoll FLASH_ACR ICEN LL_FLASH_EnableInstCache
AnnaBridge	172:65be27845400	1482	* @retval None
AnnaBridge	172:65be27845400	1483	*/
AnnaBridge	172:65be27845400	1484	__STATIC_INLINE void LL_FLASH_EnableInstCache(void)
AnnaBridge	172:65be27845400	1485	{
AnnaBridge	172:65be27845400	1486	SET_BIT(FLASH->ACR, FLASH_ACR_ICEN);
AnnaBridge	172:65be27845400	1487	}
AnnaBridge	172:65be27845400	1488
AnnaBridge	172:65be27845400	1489	/**
AnnaBridge	172:65be27845400	1490	* @brief Disable Instruction cache
AnnaBridge	172:65be27845400	1491	* @rmtoll FLASH_ACR ICEN LL_FLASH_DisableInstCache
AnnaBridge	172:65be27845400	1492	* @retval None
AnnaBridge	172:65be27845400	1493	*/
AnnaBridge	172:65be27845400	1494	__STATIC_INLINE void LL_FLASH_DisableInstCache(void)
AnnaBridge	172:65be27845400	1495	{
AnnaBridge	172:65be27845400	1496	CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN);
AnnaBridge	172:65be27845400	1497	}
AnnaBridge	172:65be27845400	1498
AnnaBridge	172:65be27845400	1499	/**
AnnaBridge	172:65be27845400	1500	* @brief Enable Data cache
AnnaBridge	172:65be27845400	1501	* @rmtoll FLASH_ACR DCEN LL_FLASH_EnableDataCache
AnnaBridge	172:65be27845400	1502	* @retval None
AnnaBridge	172:65be27845400	1503	*/
AnnaBridge	172:65be27845400	1504	__STATIC_INLINE void LL_FLASH_EnableDataCache(void)
AnnaBridge	172:65be27845400	1505	{
AnnaBridge	172:65be27845400	1506	SET_BIT(FLASH->ACR, FLASH_ACR_DCEN);
AnnaBridge	172:65be27845400	1507	}
AnnaBridge	172:65be27845400	1508
AnnaBridge	172:65be27845400	1509	/**
AnnaBridge	172:65be27845400	1510	* @brief Disable Data cache
AnnaBridge	172:65be27845400	1511	* @rmtoll FLASH_ACR DCEN LL_FLASH_DisableDataCache
AnnaBridge	172:65be27845400	1512	* @retval None
AnnaBridge	172:65be27845400	1513	*/
AnnaBridge	172:65be27845400	1514	__STATIC_INLINE void LL_FLASH_DisableDataCache(void)
AnnaBridge	172:65be27845400	1515	{
AnnaBridge	172:65be27845400	1516	CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN);
AnnaBridge	172:65be27845400	1517	}
AnnaBridge	172:65be27845400	1518
AnnaBridge	172:65be27845400	1519	/**
AnnaBridge	172:65be27845400	1520	* @brief Enable Instruction cache reset
AnnaBridge	172:65be27845400	1521	* @note bit can be written only when the instruction cache is disabled
AnnaBridge	172:65be27845400	1522	* @rmtoll FLASH_ACR ICRST LL_FLASH_EnableInstCacheReset
AnnaBridge	172:65be27845400	1523	* @retval None
AnnaBridge	172:65be27845400	1524	*/
AnnaBridge	172:65be27845400	1525	__STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void)
AnnaBridge	172:65be27845400	1526	{
AnnaBridge	172:65be27845400	1527	SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);
AnnaBridge	172:65be27845400	1528	}
AnnaBridge	172:65be27845400	1529
AnnaBridge	172:65be27845400	1530	/**
AnnaBridge	172:65be27845400	1531	* @brief Disable Instruction cache reset
AnnaBridge	172:65be27845400	1532	* @rmtoll FLASH_ACR ICRST LL_FLASH_DisableInstCacheReset
AnnaBridge	172:65be27845400	1533	* @retval None
AnnaBridge	172:65be27845400	1534	*/
AnnaBridge	172:65be27845400	1535	__STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void)
AnnaBridge	172:65be27845400	1536	{
AnnaBridge	172:65be27845400	1537	CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST);
AnnaBridge	172:65be27845400	1538	}
AnnaBridge	172:65be27845400	1539
AnnaBridge	172:65be27845400	1540	/**
AnnaBridge	172:65be27845400	1541	* @brief Enable Data cache reset
AnnaBridge	172:65be27845400	1542	* @note bit can be written only when the data cache is disabled
AnnaBridge	172:65be27845400	1543	* @rmtoll FLASH_ACR DCRST LL_FLASH_EnableDataCacheReset
AnnaBridge	172:65be27845400	1544	* @retval None
AnnaBridge	172:65be27845400	1545	*/
AnnaBridge	172:65be27845400	1546	__STATIC_INLINE void LL_FLASH_EnableDataCacheReset(void)
AnnaBridge	172:65be27845400	1547	{
AnnaBridge	172:65be27845400	1548	SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);
AnnaBridge	172:65be27845400	1549	}
AnnaBridge	172:65be27845400	1550
AnnaBridge	172:65be27845400	1551	/**
AnnaBridge	172:65be27845400	1552	* @brief Disable Data cache reset
AnnaBridge	172:65be27845400	1553	* @rmtoll FLASH_ACR DCRST LL_FLASH_DisableDataCacheReset
AnnaBridge	172:65be27845400	1554	* @retval None
AnnaBridge	172:65be27845400	1555	*/
AnnaBridge	172:65be27845400	1556	__STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void)
AnnaBridge	172:65be27845400	1557	{
AnnaBridge	172:65be27845400	1558	CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST);
AnnaBridge	172:65be27845400	1559	}
AnnaBridge	172:65be27845400	1560
AnnaBridge	172:65be27845400	1561	/**
AnnaBridge	172:65be27845400	1562	* @brief Enable Flash Power-down mode during run mode or Low-power run mode
AnnaBridge	172:65be27845400	1563	* @note Flash memory can be put in power-down mode only when the code is executed
AnnaBridge	172:65be27845400	1564	* from RAM
AnnaBridge	172:65be27845400	1565	* @note Flash must not be accessed when power down is enabled
AnnaBridge	172:65be27845400	1566	* @note Flash must not be put in power-down while a program or an erase operation
AnnaBridge	172:65be27845400	1567	* is on-going
AnnaBridge	172:65be27845400	1568	* @rmtoll FLASH_ACR RUN_PD LL_FLASH_EnableRunPowerDown\n
AnnaBridge	172:65be27845400	1569	* FLASH_PDKEYR PDKEY1 LL_FLASH_EnableRunPowerDown\n
AnnaBridge	172:65be27845400	1570	* FLASH_PDKEYR PDKEY2 LL_FLASH_EnableRunPowerDown
AnnaBridge	172:65be27845400	1571	* @retval None
AnnaBridge	172:65be27845400	1572	*/
AnnaBridge	172:65be27845400	1573	__STATIC_INLINE void LL_FLASH_EnableRunPowerDown(void)
AnnaBridge	172:65be27845400	1574	{
AnnaBridge	172:65be27845400	1575	/* Following values must be written consecutively to unlock the RUN_PD bit in
AnnaBridge	172:65be27845400	1576	FLASH_ACR */
AnnaBridge	172:65be27845400	1577	WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
AnnaBridge	172:65be27845400	1578	WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
AnnaBridge	172:65be27845400	1579	SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
AnnaBridge	172:65be27845400	1580	}
AnnaBridge	172:65be27845400	1581
AnnaBridge	172:65be27845400	1582	/**
AnnaBridge	172:65be27845400	1583	* @brief Disable Flash Power-down mode during run mode or Low-power run mode
AnnaBridge	172:65be27845400	1584	* @rmtoll FLASH_ACR RUN_PD LL_FLASH_DisableRunPowerDown\n
AnnaBridge	172:65be27845400	1585	* FLASH_PDKEYR PDKEY1 LL_FLASH_DisableRunPowerDown\n
AnnaBridge	172:65be27845400	1586	* FLASH_PDKEYR PDKEY2 LL_FLASH_DisableRunPowerDown
AnnaBridge	172:65be27845400	1587	* @retval None
AnnaBridge	172:65be27845400	1588	*/
AnnaBridge	172:65be27845400	1589	__STATIC_INLINE void LL_FLASH_DisableRunPowerDown(void)
AnnaBridge	172:65be27845400	1590	{
AnnaBridge	172:65be27845400	1591	/* Following values must be written consecutively to unlock the RUN_PD bit in
AnnaBridge	172:65be27845400	1592	FLASH_ACR */
AnnaBridge	172:65be27845400	1593	WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
AnnaBridge	172:65be27845400	1594	WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
AnnaBridge	172:65be27845400	1595	CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
AnnaBridge	172:65be27845400	1596	}
AnnaBridge	172:65be27845400	1597
AnnaBridge	172:65be27845400	1598	/**
AnnaBridge	172:65be27845400	1599	* @brief Enable Flash Power-down mode during Sleep or Low-power sleep mode
AnnaBridge	172:65be27845400	1600	* @note Flash must not be put in power-down while a program or an erase operation
AnnaBridge	172:65be27845400	1601	* is on-going
AnnaBridge	172:65be27845400	1602	* @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_EnableSleepPowerDown
AnnaBridge	172:65be27845400	1603	* @retval None
AnnaBridge	172:65be27845400	1604	*/
AnnaBridge	172:65be27845400	1605	__STATIC_INLINE void LL_FLASH_EnableSleepPowerDown(void)
AnnaBridge	172:65be27845400	1606	{
AnnaBridge	172:65be27845400	1607	SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
AnnaBridge	172:65be27845400	1608	}
AnnaBridge	172:65be27845400	1609
AnnaBridge	172:65be27845400	1610	/**
AnnaBridge	172:65be27845400	1611	* @brief Disable Flash Power-down mode during Sleep or Low-power sleep mode
AnnaBridge	172:65be27845400	1612	* @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_DisableSleepPowerDown
AnnaBridge	172:65be27845400	1613	* @retval None
AnnaBridge	172:65be27845400	1614	*/
AnnaBridge	172:65be27845400	1615	__STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void)
AnnaBridge	172:65be27845400	1616	{
AnnaBridge	172:65be27845400	1617	CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
AnnaBridge	172:65be27845400	1618	}
AnnaBridge	172:65be27845400	1619
AnnaBridge	172:65be27845400	1620	/**
AnnaBridge	172:65be27845400	1621	* @}
AnnaBridge	172:65be27845400	1622	*/
AnnaBridge	172:65be27845400	1623
AnnaBridge	172:65be27845400	1624	/**
AnnaBridge	172:65be27845400	1625	* @}
AnnaBridge	172:65be27845400	1626	*/
AnnaBridge	172:65be27845400	1627
AnnaBridge	172:65be27845400	1628	/**
AnnaBridge	172:65be27845400	1629	* @}
AnnaBridge	172:65be27845400	1630	*/
AnnaBridge	172:65be27845400	1631
AnnaBridge	172:65be27845400	1632	#endif /* defined (FLASH) \|\| defined (SYSCFG) \|\| defined (DBGMCU) \|\| defined (VREFBUF) */
AnnaBridge	172:65be27845400	1633
AnnaBridge	172:65be27845400	1634	/**
AnnaBridge	172:65be27845400	1635	* @}
AnnaBridge	172:65be27845400	1636	*/
AnnaBridge	172:65be27845400	1637
AnnaBridge	172:65be27845400	1638	#ifdef __cplusplus
AnnaBridge	172:65be27845400	1639	}
AnnaBridge	172:65be27845400	1640	#endif
AnnaBridge	172:65be27845400	1641
AnnaBridge	172:65be27845400	1642	#endif /* __STM32L4xx_LL_SYSTEM_H */
AnnaBridge	172:65be27845400	1643
AnnaBridge	172:65be27845400	1644	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/