mbed - The official Mbed 2 C/C++ SDK provides the softwa…

Users » mbed_official » Code » mbed

mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_L4R5ZI_P/TOOLCHAIN_ARM_STD/stm32l4xx_ll_dma.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	172:65be27845400	1	/**
AnnaBridge	172:65be27845400	2	******************************************************************************
AnnaBridge	172:65be27845400	3	* @file stm32l4xx_ll_dma.h
AnnaBridge	172:65be27845400	4	* @author MCD Application Team
AnnaBridge	172:65be27845400	5	* @brief Header file of DMA LL module.
AnnaBridge	172:65be27845400	6	******************************************************************************
AnnaBridge	172:65be27845400	7	* @attention
AnnaBridge	172:65be27845400	8	*
AnnaBridge	172:65be27845400	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge	172:65be27845400	10	*
AnnaBridge	172:65be27845400	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	172:65be27845400	12	* are permitted provided that the following conditions are met:
AnnaBridge	172:65be27845400	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	172:65be27845400	14	* this list of conditions and the following disclaimer.
AnnaBridge	172:65be27845400	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	172:65be27845400	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	172:65be27845400	17	* and/or other materials provided with the distribution.
AnnaBridge	172:65be27845400	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	172:65be27845400	19	* may be used to endorse or promote products derived from this software
AnnaBridge	172:65be27845400	20	* without specific prior written permission.
AnnaBridge	172:65be27845400	21	*
AnnaBridge	172:65be27845400	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	172:65be27845400	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	172:65be27845400	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	172:65be27845400	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	172:65be27845400	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	172:65be27845400	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	172:65be27845400	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	172:65be27845400	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	172:65be27845400	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	172:65be27845400	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	172:65be27845400	32	*
AnnaBridge	172:65be27845400	33	******************************************************************************
AnnaBridge	172:65be27845400	34	*/
AnnaBridge	172:65be27845400	35
AnnaBridge	172:65be27845400	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	172:65be27845400	37	#ifndef __STM32L4xx_LL_DMA_H
AnnaBridge	172:65be27845400	38	#define __STM32L4xx_LL_DMA_H
AnnaBridge	172:65be27845400	39
AnnaBridge	172:65be27845400	40	#ifdef __cplusplus
AnnaBridge	172:65be27845400	41	extern "C" {
AnnaBridge	172:65be27845400	42	#endif
AnnaBridge	172:65be27845400	43
AnnaBridge	172:65be27845400	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	172:65be27845400	45	#include "stm32l4xx.h"
AnnaBridge	172:65be27845400	46	#if defined(DMAMUX1)
AnnaBridge	172:65be27845400	47	#include "stm32l4xx_ll_dmamux.h"
AnnaBridge	172:65be27845400	48	#endif /* DMAMUX1 */
AnnaBridge	172:65be27845400	49
AnnaBridge	172:65be27845400	50	/** @addtogroup STM32L4xx_LL_Driver
AnnaBridge	172:65be27845400	51	* @{
AnnaBridge	172:65be27845400	52	*/
AnnaBridge	172:65be27845400	53
AnnaBridge	172:65be27845400	54	#if defined (DMA1) \|\| defined (DMA2)
AnnaBridge	172:65be27845400	55
AnnaBridge	172:65be27845400	56	/** @defgroup DMA_LL DMA
AnnaBridge	172:65be27845400	57	* @{
AnnaBridge	172:65be27845400	58	*/
AnnaBridge	172:65be27845400	59
AnnaBridge	172:65be27845400	60	/* Private types -------------------------------------------------------------*/
AnnaBridge	172:65be27845400	61	/* Private variables ---------------------------------------------------------*/
AnnaBridge	172:65be27845400	62	/** @defgroup DMA_LL_Private_Variables DMA Private Variables
AnnaBridge	172:65be27845400	63	* @{
AnnaBridge	172:65be27845400	64	*/
AnnaBridge	172:65be27845400	65	/* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
AnnaBridge	172:65be27845400	66	static const uint8_t CHANNEL_OFFSET_TAB[] =
AnnaBridge	172:65be27845400	67	{
AnnaBridge	172:65be27845400	68	(uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
AnnaBridge	172:65be27845400	69	(uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
AnnaBridge	172:65be27845400	70	(uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
AnnaBridge	172:65be27845400	71	(uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
AnnaBridge	172:65be27845400	72	(uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
AnnaBridge	172:65be27845400	73	(uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
AnnaBridge	172:65be27845400	74	(uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
AnnaBridge	172:65be27845400	75	};
AnnaBridge	172:65be27845400	76	/**
AnnaBridge	172:65be27845400	77	* @}
AnnaBridge	172:65be27845400	78	*/
AnnaBridge	172:65be27845400	79
AnnaBridge	172:65be27845400	80	/* Private constants ---------------------------------------------------------*/
AnnaBridge	172:65be27845400	81	#if defined(DMAMUX1)
AnnaBridge	172:65be27845400	82	#else
AnnaBridge	172:65be27845400	83	/** @defgroup DMA_LL_Private_Constants DMA Private Constants
AnnaBridge	172:65be27845400	84	* @{
AnnaBridge	172:65be27845400	85	*/
AnnaBridge	172:65be27845400	86	/* Define used to get CSELR register offset */
AnnaBridge	172:65be27845400	87	#define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)
AnnaBridge	172:65be27845400	88
AnnaBridge	172:65be27845400	89	/* Defines used for the bit position in the register and perform offsets */
AnnaBridge	172:65be27845400	90	#define DMA_POSITION_CSELR_CXS POSITION_VAL(DMA_CSELR_C1S << ((Channel-1U)*4U))
AnnaBridge	172:65be27845400	91	/**
AnnaBridge	172:65be27845400	92	* @}
AnnaBridge	172:65be27845400	93	*/
AnnaBridge	172:65be27845400	94	#endif /* DMAMUX1 */
AnnaBridge	172:65be27845400	95
AnnaBridge	172:65be27845400	96	/* Private macros ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	97	#if defined(DMAMUX1)
AnnaBridge	172:65be27845400	98	/** @defgroup DMA_LL_Private_Macros DMA Private Macros
AnnaBridge	172:65be27845400	99	* @{
AnnaBridge	172:65be27845400	100	*/
AnnaBridge	172:65be27845400	101	/**
AnnaBridge	172:65be27845400	102	* @brief Helper macro to convert DMA Instance DMAx into DMAMUX channel
AnnaBridge	172:65be27845400	103	* @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
AnnaBridge	172:65be27845400	104	* DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7.
AnnaBridge	172:65be27845400	105	* @param __DMA_INSTANCE__ DMAx
AnnaBridge	172:65be27845400	106	* @retval Channel_Offset (LL_DMA_CHANNEL_7 or 0).
AnnaBridge	172:65be27845400	107	*/
AnnaBridge	172:65be27845400	108	#define __LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(__DMA_INSTANCE__) \
AnnaBridge	172:65be27845400	109	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) ? 0 : LL_DMA_CHANNEL_7)
AnnaBridge	172:65be27845400	110
AnnaBridge	172:65be27845400	111	/**
AnnaBridge	172:65be27845400	112	* @}
AnnaBridge	172:65be27845400	113	*/
AnnaBridge	172:65be27845400	114	#else
AnnaBridge	172:65be27845400	115	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	172:65be27845400	116	/** @defgroup DMA_LL_Private_Macros DMA Private Macros
AnnaBridge	172:65be27845400	117	* @{
AnnaBridge	172:65be27845400	118	*/
AnnaBridge	172:65be27845400	119	/**
AnnaBridge	172:65be27845400	120	* @}
AnnaBridge	172:65be27845400	121	*/
AnnaBridge	172:65be27845400	122	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	172:65be27845400	123	#endif /* DMAMUX1 */
AnnaBridge	172:65be27845400	124
AnnaBridge	172:65be27845400	125	/* Exported types ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	126	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	172:65be27845400	127	/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
AnnaBridge	172:65be27845400	128	* @{
AnnaBridge	172:65be27845400	129	*/
AnnaBridge	172:65be27845400	130	typedef struct
AnnaBridge	172:65be27845400	131	{
AnnaBridge	172:65be27845400	132	uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
AnnaBridge	172:65be27845400	133	or as Source base address in case of memory to memory transfer direction.
AnnaBridge	172:65be27845400	134
AnnaBridge	172:65be27845400	135	This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
AnnaBridge	172:65be27845400	136
AnnaBridge	172:65be27845400	137	uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
AnnaBridge	172:65be27845400	138	or as Destination base address in case of memory to memory transfer direction.
AnnaBridge	172:65be27845400	139
AnnaBridge	172:65be27845400	140	This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
AnnaBridge	172:65be27845400	141
AnnaBridge	172:65be27845400	142	uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
AnnaBridge	172:65be27845400	143	from memory to memory or from peripheral to memory.
AnnaBridge	172:65be27845400	144	This parameter can be a value of @ref DMA_LL_EC_DIRECTION
AnnaBridge	172:65be27845400	145
AnnaBridge	172:65be27845400	146	This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
AnnaBridge	172:65be27845400	147
AnnaBridge	172:65be27845400	148	uint32_t Mode; /*!< Specifies the normal or circular operation mode.
AnnaBridge	172:65be27845400	149	This parameter can be a value of @ref DMA_LL_EC_MODE
AnnaBridge	172:65be27845400	150	@note: The circular buffer mode cannot be used if the memory to memory
AnnaBridge	172:65be27845400	151	data transfer direction is configured on the selected Channel
AnnaBridge	172:65be27845400	152
AnnaBridge	172:65be27845400	153	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
AnnaBridge	172:65be27845400	154
AnnaBridge	172:65be27845400	155	uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
AnnaBridge	172:65be27845400	156	is incremented or not.
AnnaBridge	172:65be27845400	157	This parameter can be a value of @ref DMA_LL_EC_PERIPH
AnnaBridge	172:65be27845400	158
AnnaBridge	172:65be27845400	159	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
AnnaBridge	172:65be27845400	160
AnnaBridge	172:65be27845400	161	uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
AnnaBridge	172:65be27845400	162	is incremented or not.
AnnaBridge	172:65be27845400	163	This parameter can be a value of @ref DMA_LL_EC_MEMORY
AnnaBridge	172:65be27845400	164
AnnaBridge	172:65be27845400	165	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
AnnaBridge	172:65be27845400	166
AnnaBridge	172:65be27845400	167	uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
AnnaBridge	172:65be27845400	168	in case of memory to memory transfer direction.
AnnaBridge	172:65be27845400	169	This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
AnnaBridge	172:65be27845400	170
AnnaBridge	172:65be27845400	171	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
AnnaBridge	172:65be27845400	172
AnnaBridge	172:65be27845400	173	uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
AnnaBridge	172:65be27845400	174	in case of memory to memory transfer direction.
AnnaBridge	172:65be27845400	175	This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
AnnaBridge	172:65be27845400	176
AnnaBridge	172:65be27845400	177	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
AnnaBridge	172:65be27845400	178
AnnaBridge	172:65be27845400	179	uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
AnnaBridge	172:65be27845400	180	The data unit is equal to the source buffer configuration set in PeripheralSize
AnnaBridge	172:65be27845400	181	or MemorySize parameters depending in the transfer direction.
AnnaBridge	172:65be27845400	182	This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
AnnaBridge	172:65be27845400	183
AnnaBridge	172:65be27845400	184	This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
AnnaBridge	172:65be27845400	185	#if defined(DMAMUX1)
AnnaBridge	172:65be27845400	186
AnnaBridge	172:65be27845400	187	uint32_t PeriphRequest; /*!< Specifies the peripheral request.
AnnaBridge	172:65be27845400	188	This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST
AnnaBridge	172:65be27845400	189
AnnaBridge	172:65be27845400	190	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
AnnaBridge	172:65be27845400	191	#else
AnnaBridge	172:65be27845400	192
AnnaBridge	172:65be27845400	193	uint32_t PeriphRequest; /*!< Specifies the peripheral request.
AnnaBridge	172:65be27845400	194	This parameter can be a value of @ref DMA_LL_EC_REQUEST
AnnaBridge	172:65be27845400	195
AnnaBridge	172:65be27845400	196	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
AnnaBridge	172:65be27845400	197	#endif /* DMAMUX1 */
AnnaBridge	172:65be27845400	198
AnnaBridge	172:65be27845400	199	uint32_t Priority; /*!< Specifies the channel priority level.
AnnaBridge	172:65be27845400	200	This parameter can be a value of @ref DMA_LL_EC_PRIORITY
AnnaBridge	172:65be27845400	201
AnnaBridge	172:65be27845400	202	This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
AnnaBridge	172:65be27845400	203
AnnaBridge	172:65be27845400	204	} LL_DMA_InitTypeDef;
AnnaBridge	172:65be27845400	205	/**
AnnaBridge	172:65be27845400	206	* @}
AnnaBridge	172:65be27845400	207	*/
AnnaBridge	172:65be27845400	208	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	172:65be27845400	209
AnnaBridge	172:65be27845400	210	/* Exported constants --------------------------------------------------------*/
AnnaBridge	172:65be27845400	211	/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
AnnaBridge	172:65be27845400	212	* @{
AnnaBridge	172:65be27845400	213	*/
AnnaBridge	172:65be27845400	214	/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
AnnaBridge	172:65be27845400	215	* @brief Flags defines which can be used with LL_DMA_WriteReg function
AnnaBridge	172:65be27845400	216	* @{
AnnaBridge	172:65be27845400	217	*/
AnnaBridge	172:65be27845400	218	#define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /!< Channel 1 global flag /
AnnaBridge	172:65be27845400	219	#define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /!< Channel 1 transfer complete flag /
AnnaBridge	172:65be27845400	220	#define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /!< Channel 1 half transfer flag /
AnnaBridge	172:65be27845400	221	#define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /!< Channel 1 transfer error flag /
AnnaBridge	172:65be27845400	222	#define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /!< Channel 2 global flag /
AnnaBridge	172:65be27845400	223	#define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /!< Channel 2 transfer complete flag /
AnnaBridge	172:65be27845400	224	#define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /!< Channel 2 half transfer flag /
AnnaBridge	172:65be27845400	225	#define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /!< Channel 2 transfer error flag /
AnnaBridge	172:65be27845400	226	#define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /!< Channel 3 global flag /
AnnaBridge	172:65be27845400	227	#define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /!< Channel 3 transfer complete flag /
AnnaBridge	172:65be27845400	228	#define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /!< Channel 3 half transfer flag /
AnnaBridge	172:65be27845400	229	#define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /!< Channel 3 transfer error flag /
AnnaBridge	172:65be27845400	230	#define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /!< Channel 4 global flag /
AnnaBridge	172:65be27845400	231	#define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /!< Channel 4 transfer complete flag /
AnnaBridge	172:65be27845400	232	#define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /!< Channel 4 half transfer flag /
AnnaBridge	172:65be27845400	233	#define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /!< Channel 4 transfer error flag /
AnnaBridge	172:65be27845400	234	#define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /!< Channel 5 global flag /
AnnaBridge	172:65be27845400	235	#define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /!< Channel 5 transfer complete flag /
AnnaBridge	172:65be27845400	236	#define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /!< Channel 5 half transfer flag /
AnnaBridge	172:65be27845400	237	#define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /!< Channel 5 transfer error flag /
AnnaBridge	172:65be27845400	238	#define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /!< Channel 6 global flag /
AnnaBridge	172:65be27845400	239	#define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /!< Channel 6 transfer complete flag /
AnnaBridge	172:65be27845400	240	#define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /!< Channel 6 half transfer flag /
AnnaBridge	172:65be27845400	241	#define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /!< Channel 6 transfer error flag /
AnnaBridge	172:65be27845400	242	#define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /!< Channel 7 global flag /
AnnaBridge	172:65be27845400	243	#define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /!< Channel 7 transfer complete flag /
AnnaBridge	172:65be27845400	244	#define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /!< Channel 7 half transfer flag /
AnnaBridge	172:65be27845400	245	#define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /!< Channel 7 transfer error flag /
AnnaBridge	172:65be27845400	246	/**
AnnaBridge	172:65be27845400	247	* @}
AnnaBridge	172:65be27845400	248	*/
AnnaBridge	172:65be27845400	249
AnnaBridge	172:65be27845400	250	/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	172:65be27845400	251	* @brief Flags defines which can be used with LL_DMA_ReadReg function
AnnaBridge	172:65be27845400	252	* @{
AnnaBridge	172:65be27845400	253	*/
AnnaBridge	172:65be27845400	254	#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /!< Channel 1 global flag /
AnnaBridge	172:65be27845400	255	#define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /!< Channel 1 transfer complete flag /
AnnaBridge	172:65be27845400	256	#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /!< Channel 1 half transfer flag /
AnnaBridge	172:65be27845400	257	#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /!< Channel 1 transfer error flag /
AnnaBridge	172:65be27845400	258	#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /!< Channel 2 global flag /
AnnaBridge	172:65be27845400	259	#define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /!< Channel 2 transfer complete flag /
AnnaBridge	172:65be27845400	260	#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /!< Channel 2 half transfer flag /
AnnaBridge	172:65be27845400	261	#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /!< Channel 2 transfer error flag /
AnnaBridge	172:65be27845400	262	#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /!< Channel 3 global flag /
AnnaBridge	172:65be27845400	263	#define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /!< Channel 3 transfer complete flag /
AnnaBridge	172:65be27845400	264	#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /!< Channel 3 half transfer flag /
AnnaBridge	172:65be27845400	265	#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /!< Channel 3 transfer error flag /
AnnaBridge	172:65be27845400	266	#define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /!< Channel 4 global flag /
AnnaBridge	172:65be27845400	267	#define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /!< Channel 4 transfer complete flag /
AnnaBridge	172:65be27845400	268	#define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /!< Channel 4 half transfer flag /
AnnaBridge	172:65be27845400	269	#define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /!< Channel 4 transfer error flag /
AnnaBridge	172:65be27845400	270	#define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /!< Channel 5 global flag /
AnnaBridge	172:65be27845400	271	#define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /!< Channel 5 transfer complete flag /
AnnaBridge	172:65be27845400	272	#define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /!< Channel 5 half transfer flag /
AnnaBridge	172:65be27845400	273	#define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /!< Channel 5 transfer error flag /
AnnaBridge	172:65be27845400	274	#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /!< Channel 6 global flag /
AnnaBridge	172:65be27845400	275	#define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /!< Channel 6 transfer complete flag /
AnnaBridge	172:65be27845400	276	#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /!< Channel 6 half transfer flag /
AnnaBridge	172:65be27845400	277	#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /!< Channel 6 transfer error flag /
AnnaBridge	172:65be27845400	278	#define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /!< Channel 7 global flag /
AnnaBridge	172:65be27845400	279	#define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /!< Channel 7 transfer complete flag /
AnnaBridge	172:65be27845400	280	#define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /!< Channel 7 half transfer flag /
AnnaBridge	172:65be27845400	281	#define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /!< Channel 7 transfer error flag /
AnnaBridge	172:65be27845400	282	/**
AnnaBridge	172:65be27845400	283	* @}
AnnaBridge	172:65be27845400	284	*/
AnnaBridge	172:65be27845400	285
AnnaBridge	172:65be27845400	286	/** @defgroup DMA_LL_EC_IT IT Defines
AnnaBridge	172:65be27845400	287	* @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
AnnaBridge	172:65be27845400	288	* @{
AnnaBridge	172:65be27845400	289	*/
AnnaBridge	172:65be27845400	290	#define LL_DMA_CCR_TCIE DMA_CCR_TCIE /!< Transfer complete interrupt /
AnnaBridge	172:65be27845400	291	#define LL_DMA_CCR_HTIE DMA_CCR_HTIE /!< Half Transfer interrupt /
AnnaBridge	172:65be27845400	292	#define LL_DMA_CCR_TEIE DMA_CCR_TEIE /!< Transfer error interrupt /
AnnaBridge	172:65be27845400	293	/**
AnnaBridge	172:65be27845400	294	* @}
AnnaBridge	172:65be27845400	295	*/
AnnaBridge	172:65be27845400	296
AnnaBridge	172:65be27845400	297	/** @defgroup DMA_LL_EC_CHANNEL CHANNEL
AnnaBridge	172:65be27845400	298	* @{
AnnaBridge	172:65be27845400	299	*/
AnnaBridge	172:65be27845400	300	#define LL_DMA_CHANNEL_1 0x00000001U /!< DMA Channel 1 /
AnnaBridge	172:65be27845400	301	#define LL_DMA_CHANNEL_2 0x00000002U /!< DMA Channel 2 /
AnnaBridge	172:65be27845400	302	#define LL_DMA_CHANNEL_3 0x00000003U /!< DMA Channel 3 /
AnnaBridge	172:65be27845400	303	#define LL_DMA_CHANNEL_4 0x00000004U /!< DMA Channel 4 /
AnnaBridge	172:65be27845400	304	#define LL_DMA_CHANNEL_5 0x00000005U /!< DMA Channel 5 /
AnnaBridge	172:65be27845400	305	#define LL_DMA_CHANNEL_6 0x00000006U /!< DMA Channel 6 /
AnnaBridge	172:65be27845400	306	#define LL_DMA_CHANNEL_7 0x00000007U /!< DMA Channel 7 /
AnnaBridge	172:65be27845400	307	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	172:65be27845400	308	#define LL_DMA_CHANNEL_ALL 0xFFFF0000U /!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). /
AnnaBridge	172:65be27845400	309	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	172:65be27845400	310	/**
AnnaBridge	172:65be27845400	311	* @}
AnnaBridge	172:65be27845400	312	*/
AnnaBridge	172:65be27845400	313
AnnaBridge	172:65be27845400	314	/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
AnnaBridge	172:65be27845400	315	* @{
AnnaBridge	172:65be27845400	316	*/
AnnaBridge	172:65be27845400	317	#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /!< Peripheral to memory direction /
AnnaBridge	172:65be27845400	318	#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /!< Memory to peripheral direction /
AnnaBridge	172:65be27845400	319	#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /!< Memory to memory direction /
AnnaBridge	172:65be27845400	320	/**
AnnaBridge	172:65be27845400	321	* @}
AnnaBridge	172:65be27845400	322	*/
AnnaBridge	172:65be27845400	323
AnnaBridge	172:65be27845400	324	/** @defgroup DMA_LL_EC_MODE Transfer mode
AnnaBridge	172:65be27845400	325	* @{
AnnaBridge	172:65be27845400	326	*/
AnnaBridge	172:65be27845400	327	#define LL_DMA_MODE_NORMAL 0x00000000U /!< Normal Mode /
AnnaBridge	172:65be27845400	328	#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /!< Circular Mode /
AnnaBridge	172:65be27845400	329	/**
AnnaBridge	172:65be27845400	330	* @}
AnnaBridge	172:65be27845400	331	*/
AnnaBridge	172:65be27845400	332
AnnaBridge	172:65be27845400	333	/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
AnnaBridge	172:65be27845400	334	* @{
AnnaBridge	172:65be27845400	335	*/
AnnaBridge	172:65be27845400	336	#define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /!< Peripheral increment mode Enable /
AnnaBridge	172:65be27845400	337	#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /!< Peripheral increment mode Disable /
AnnaBridge	172:65be27845400	338	/**
AnnaBridge	172:65be27845400	339	* @}
AnnaBridge	172:65be27845400	340	*/
AnnaBridge	172:65be27845400	341
AnnaBridge	172:65be27845400	342	/** @defgroup DMA_LL_EC_MEMORY Memory increment mode
AnnaBridge	172:65be27845400	343	* @{
AnnaBridge	172:65be27845400	344	*/
AnnaBridge	172:65be27845400	345	#define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /!< Memory increment mode Enable /
AnnaBridge	172:65be27845400	346	#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /!< Memory increment mode Disable /
AnnaBridge	172:65be27845400	347	/**
AnnaBridge	172:65be27845400	348	* @}
AnnaBridge	172:65be27845400	349	*/
AnnaBridge	172:65be27845400	350
AnnaBridge	172:65be27845400	351	/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
AnnaBridge	172:65be27845400	352	* @{
AnnaBridge	172:65be27845400	353	*/
AnnaBridge	172:65be27845400	354	#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /!< Peripheral data alignment : Byte /
AnnaBridge	172:65be27845400	355	#define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /!< Peripheral data alignment : HalfWord /
AnnaBridge	172:65be27845400	356	#define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /!< Peripheral data alignment : Word /
AnnaBridge	172:65be27845400	357	/**
AnnaBridge	172:65be27845400	358	* @}
AnnaBridge	172:65be27845400	359	*/
AnnaBridge	172:65be27845400	360
AnnaBridge	172:65be27845400	361	/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
AnnaBridge	172:65be27845400	362	* @{
AnnaBridge	172:65be27845400	363	*/
AnnaBridge	172:65be27845400	364	#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /!< Memory data alignment : Byte /
AnnaBridge	172:65be27845400	365	#define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /!< Memory data alignment : HalfWord /
AnnaBridge	172:65be27845400	366	#define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /!< Memory data alignment : Word /
AnnaBridge	172:65be27845400	367	/**
AnnaBridge	172:65be27845400	368	* @}
AnnaBridge	172:65be27845400	369	*/
AnnaBridge	172:65be27845400	370
AnnaBridge	172:65be27845400	371	/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
AnnaBridge	172:65be27845400	372	* @{
AnnaBridge	172:65be27845400	373	*/
AnnaBridge	172:65be27845400	374	#define LL_DMA_PRIORITY_LOW 0x00000000U /!< Priority level : Low /
AnnaBridge	172:65be27845400	375	#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /!< Priority level : Medium /
AnnaBridge	172:65be27845400	376	#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /!< Priority level : High /
AnnaBridge	172:65be27845400	377	#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /!< Priority level : Very_High /
AnnaBridge	172:65be27845400	378	/**
AnnaBridge	172:65be27845400	379	* @}
AnnaBridge	172:65be27845400	380	*/
AnnaBridge	172:65be27845400	381
AnnaBridge	172:65be27845400	382	#if defined(DMAMUX1)
AnnaBridge	172:65be27845400	383	/** @defgroup DMAMUX_LL_EC_REQUEST Transfer request
AnnaBridge	172:65be27845400	384	* @{
AnnaBridge	172:65be27845400	385	*/
AnnaBridge	172:65be27845400	386	#define LL_DMAMUX_REQUEST_MEM2MEM 0U /!< Memory to memory transfer /
AnnaBridge	172:65be27845400	387	#define LL_DMAMUX_REQUEST_GENERATOR0 1U /!< DMAMUX request generator 0 /
AnnaBridge	172:65be27845400	388	#define LL_DMAMUX_REQUEST_GENERATOR1 2U /!< DMAMUX request generator 1 /
AnnaBridge	172:65be27845400	389	#define LL_DMAMUX_REQUEST_GENERATOR2 3U /!< DMAMUX request generator 2 /
AnnaBridge	172:65be27845400	390	#define LL_DMAMUX_REQUEST_GENERATOR3 4U /!< DMAMUX request generator 3 /
AnnaBridge	172:65be27845400	391	#define LL_DMAMUX_REQUEST_ADC1 5U /!< DMAMUX ADC1 request /
AnnaBridge	172:65be27845400	392	#define LL_DMAMUX_REQUEST_DAC1_CH1 6U /!< DMAMUX DAC1 CH1 request /
AnnaBridge	172:65be27845400	393	#define LL_DMAMUX_REQUEST_DAC1_CH2 7U /!< DMAMUX DAC1 CH2 request /
AnnaBridge	172:65be27845400	394	#define LL_DMAMUX_REQUEST_TIM6_UP 8U /!< DMAMUX TIM6 UP request /
AnnaBridge	172:65be27845400	395	#define LL_DMAMUX_REQUEST_TIM7_UP 9U /!< DMAMUX TIM7 UP request /
AnnaBridge	172:65be27845400	396	#define LL_DMAMUX_REQUEST_SPI1_RX 10U /!< DMAMUX SPI1 RX request /
AnnaBridge	172:65be27845400	397	#define LL_DMAMUX_REQUEST_SPI1_TX 11U /!< DMAMUX SPI1 TX request /
AnnaBridge	172:65be27845400	398	#define LL_DMAMUX_REQUEST_SPI2_RX 12U /!< DMAMUX SPI2 RX request /
AnnaBridge	172:65be27845400	399	#define LL_DMAMUX_REQUEST_SPI2_TX 13U /!< DMAMUX SPI2 TX request /
AnnaBridge	172:65be27845400	400	#define LL_DMAMUX_REQUEST_SPI3_RX 14U /!< DMAMUX SPI3 RX request /
AnnaBridge	172:65be27845400	401	#define LL_DMAMUX_REQUEST_SPI3_TX 15U /!< DMAMUX SPI3 TX request /
AnnaBridge	172:65be27845400	402	#define LL_DMAMUX_REQUEST_I2C1_RX 16U /!< DMAMUX I2C1 RX request /
AnnaBridge	172:65be27845400	403	#define LL_DMAMUX_REQUEST_I2C1_TX 17U /!< DMAMUX I2C1 TX request /
AnnaBridge	172:65be27845400	404	#define LL_DMAMUX_REQUEST_I2C2_RX 18U /!< DMAMUX I2C2 RX request /
AnnaBridge	172:65be27845400	405	#define LL_DMAMUX_REQUEST_I2C2_TX 19U /!< DMAMUX I2C2 TX request /
AnnaBridge	172:65be27845400	406	#define LL_DMAMUX_REQUEST_I2C3_RX 20U /!< DMAMUX I2C3 RX request /
AnnaBridge	172:65be27845400	407	#define LL_DMAMUX_REQUEST_I2C3_TX 21U /!< DMAMUX I2C3 TX request /
AnnaBridge	172:65be27845400	408	#define LL_DMAMUX_REQUEST_I2C4_RX 22U /!< DMAMUX I2C4 RX request /
AnnaBridge	172:65be27845400	409	#define LL_DMAMUX_REQUEST_I2C4_TX 23U /!< DMAMUX I2C4 TX request /
AnnaBridge	172:65be27845400	410	#define LL_DMAMUX_REQUEST_USART1_RX 24U /!< DMAMUX USART1 RX request /
AnnaBridge	172:65be27845400	411	#define LL_DMAMUX_REQUEST_USART1_TX 25U /!< DMAMUX USART1 TX request /
AnnaBridge	172:65be27845400	412	#define LL_DMAMUX_REQUEST_USART2_RX 26U /!< DMAMUX USART2 RX request /
AnnaBridge	172:65be27845400	413	#define LL_DMAMUX_REQUEST_USART2_TX 27U /!< DMAMUX USART2 TX request /
AnnaBridge	172:65be27845400	414	#define LL_DMAMUX_REQUEST_USART3_RX 28U /!< DMAMUX USART3 RX request /
AnnaBridge	172:65be27845400	415	#define LL_DMAMUX_REQUEST_USART3_TX 29U /!< DMAMUX USART3 TX request /
AnnaBridge	172:65be27845400	416	#define LL_DMAMUX_REQUEST_UART4_RX 30U /!< DMAMUX UART4 RX request /
AnnaBridge	172:65be27845400	417	#define LL_DMAMUX_REQUEST_UART4_TX 31U /!< DMAMUX UART4 TX request /
AnnaBridge	172:65be27845400	418	#define LL_DMAMUX_REQUEST_UART5_RX 32U /!< DMAMUX UART5 RX request /
AnnaBridge	172:65be27845400	419	#define LL_DMAMUX_REQUEST_UART5_TX 33U /!< DMAMUX UART5 TX request /
AnnaBridge	172:65be27845400	420	#define LL_DMAMUX_REQUEST_LPUART1_RX 34U /!< DMAMUX LPUART1 RX request /
AnnaBridge	172:65be27845400	421	#define LL_DMAMUX_REQUEST_LPUART1_TX 35U /!< DMAMUX LPUART1 TX request /
AnnaBridge	172:65be27845400	422	#define LL_DMAMUX_REQUEST_SAI1_A 36U /!< DMAMUX SAI1 A request /
AnnaBridge	172:65be27845400	423	#define LL_DMAMUX_REQUEST_SAI1_B 37U /!< DMAMUX SAI1 B request /
AnnaBridge	172:65be27845400	424	#define LL_DMAMUX_REQUEST_SAI2_A 38U /!< DMAMUX SAI2 A request /
AnnaBridge	172:65be27845400	425	#define LL_DMAMUX_REQUEST_SAI2_B 39U /!< DMAMUX SAI2 B request /
AnnaBridge	172:65be27845400	426	#define LL_DMAMUX_REQUEST_OSPI1 40U /!< DMAMUX OCTOSPI1 request /
AnnaBridge	172:65be27845400	427	#define LL_DMAMUX_REQUEST_OSPI2 41U /!< DMAMUX OCTOSPI2 request /
AnnaBridge	172:65be27845400	428	#define LL_DMAMUX_REQUEST_TIM1_CH1 42U /!< DMAMUX TIM1 CH1 request /
AnnaBridge	172:65be27845400	429	#define LL_DMAMUX_REQUEST_TIM1_CH2 43U /!< DMAMUX TIM1 CH2 request /
AnnaBridge	172:65be27845400	430	#define LL_DMAMUX_REQUEST_TIM1_CH3 44U /!< DMAMUX TIM1 CH3 request /
AnnaBridge	172:65be27845400	431	#define LL_DMAMUX_REQUEST_TIM1_CH4 45U /!< DMAMUX TIM1 CH4 request /
AnnaBridge	172:65be27845400	432	#define LL_DMAMUX_REQUEST_TIM1_UP 46U /!< DMAMUX TIM1 UP request /
AnnaBridge	172:65be27845400	433	#define LL_DMAMUX_REQUEST_TIM1_TRIG 47U /!< DMAMUX TIM1 TRIG request /
AnnaBridge	172:65be27845400	434	#define LL_DMAMUX_REQUEST_TIM1_COM 48U /!< DMAMUX TIM1 COM request /
AnnaBridge	172:65be27845400	435	#define LL_DMAMUX_REQUEST_TIM8_CH1 49U /!< DMAMUX TIM8 CH1 request /
AnnaBridge	172:65be27845400	436	#define LL_DMAMUX_REQUEST_TIM8_CH2 50U /!< DMAMUX TIM8 CH2 request /
AnnaBridge	172:65be27845400	437	#define LL_DMAMUX_REQUEST_TIM8_CH3 51U /!< DMAMUX TIM8 CH3 request /
AnnaBridge	172:65be27845400	438	#define LL_DMAMUX_REQUEST_TIM8_CH4 52U /!< DMAMUX TIM8 CH4 request /
AnnaBridge	172:65be27845400	439	#define LL_DMAMUX_REQUEST_TIM8_UP 53U /!< DMAMUX TIM8 UP request /
AnnaBridge	172:65be27845400	440	#define LL_DMAMUX_REQUEST_TIM8_TRIG 54U /!< DMAMUX TIM8 TRIG request /
AnnaBridge	172:65be27845400	441	#define LL_DMAMUX_REQUEST_TIM8_COM 55U /!< DMAMUX TIM8 COM request /
AnnaBridge	172:65be27845400	442	#define LL_DMAMUX_REQUEST_TIM2_CH1 56U /!< DMAMUX TIM2 CH1 request /
AnnaBridge	172:65be27845400	443	#define LL_DMAMUX_REQUEST_TIM2_CH2 57U /!< DMAMUX TIM2 CH2 request /
AnnaBridge	172:65be27845400	444	#define LL_DMAMUX_REQUEST_TIM2_CH3 58U /!< DMAMUX TIM2 CH3 request /
AnnaBridge	172:65be27845400	445	#define LL_DMAMUX_REQUEST_TIM2_CH4 59U /!< DMAMUX TIM2 CH4 request /
AnnaBridge	172:65be27845400	446	#define LL_DMAMUX_REQUEST_TIM2_UP 60U /!< DMAMUX TIM2 UP request /
AnnaBridge	172:65be27845400	447	#define LL_DMAMUX_REQUEST_TIM3_CH1 61U /!< DMAMUX TIM3 CH1 request /
AnnaBridge	172:65be27845400	448	#define LL_DMAMUX_REQUEST_TIM3_CH2 62U /!< DMAMUX TIM3 CH2 request /
AnnaBridge	172:65be27845400	449	#define LL_DMAMUX_REQUEST_TIM3_CH3 63U /!< DMAMUX TIM3 CH3 request /
AnnaBridge	172:65be27845400	450	#define LL_DMAMUX_REQUEST_TIM3_CH4 64U /!< DMAMUX TIM3 CH4 request /
AnnaBridge	172:65be27845400	451	#define LL_DMAMUX_REQUEST_TIM3_UP 65U /!< DMAMUX TIM3 UP request /
AnnaBridge	172:65be27845400	452	#define LL_DMAMUX_REQUEST_TIM3_TRIG 66U /!< DMAMUX TIM3 TRIG request /
AnnaBridge	172:65be27845400	453	#define LL_DMAMUX_REQUEST_TIM4_CH1 67U /!< DMAMUX TIM4 CH1 request /
AnnaBridge	172:65be27845400	454	#define LL_DMAMUX_REQUEST_TIM4_CH2 68U /!< DMAMUX TIM4 CH2 request /
AnnaBridge	172:65be27845400	455	#define LL_DMAMUX_REQUEST_TIM4_CH3 69U /!< DMAMUX TIM4 CH3 request /
AnnaBridge	172:65be27845400	456	#define LL_DMAMUX_REQUEST_TIM4_CH4 70U /!< DMAMUX TIM4 CH4 request /
AnnaBridge	172:65be27845400	457	#define LL_DMAMUX_REQUEST_TIM4_UP 71U /!< DMAMUX TIM4 UP request /
AnnaBridge	172:65be27845400	458	#define LL_DMAMUX_REQUEST_TIM5_CH1 72U /!< DMAMUX TIM5 CH1 request /
AnnaBridge	172:65be27845400	459	#define LL_DMAMUX_REQUEST_TIM5_CH2 73U /!< DMAMUX TIM5 CH2 request /
AnnaBridge	172:65be27845400	460	#define LL_DMAMUX_REQUEST_TIM5_CH3 74U /!< DMAMUX TIM5 CH3 request /
AnnaBridge	172:65be27845400	461	#define LL_DMAMUX_REQUEST_TIM5_CH4 75U /!< DMAMUX TIM5 CH4 request /
AnnaBridge	172:65be27845400	462	#define LL_DMAMUX_REQUEST_TIM5_UP 76U /!< DMAMUX TIM5 UP request /
AnnaBridge	172:65be27845400	463	#define LL_DMAMUX_REQUEST_TIM5_TRIG 77U /!< DMAMUX TIM5 TRIG request /
AnnaBridge	172:65be27845400	464	#define LL_DMAMUX_REQUEST_TIM15_CH1 78U /!< DMAMUX TIM15 CH1 request /
AnnaBridge	172:65be27845400	465	#define LL_DMAMUX_REQUEST_TIM15_UP 79U /!< DMAMUX TIM15 UP request /
AnnaBridge	172:65be27845400	466	#define LL_DMAMUX_REQUEST_TIM15_TRIG 80U /!< DMAMUX TIM15 TRIG request /
AnnaBridge	172:65be27845400	467	#define LL_DMAMUX_REQUEST_TIM15_COM 81U /!< DMAMUX TIM15 COM request /
AnnaBridge	172:65be27845400	468	#define LL_DMAMUX_REQUEST_TIM16_CH1 82U /!< DMAMUX TIM16 CH1 request /
AnnaBridge	172:65be27845400	469	#define LL_DMAMUX_REQUEST_TIM16_UP 83U /!< DMAMUX TIM16 UP request /
AnnaBridge	172:65be27845400	470	#define LL_DMAMUX_REQUEST_TIM17_CH1 84U /!< DMAMUX TIM17 CH1 request /
AnnaBridge	172:65be27845400	471	#define LL_DMAMUX_REQUEST_TIM17_UP 85U /!< DMAMUX TIM17 UP request /
AnnaBridge	172:65be27845400	472	#define LL_DMAMUX_REQUEST_DFSDM1_FLT0 86U /!< DMAMUX DFSDM1_FLT0 request /
AnnaBridge	172:65be27845400	473	#define LL_DMAMUX_REQUEST_DFSDM1_FLT1 87U /!< DMAMUX DFSDM1_FLT1 request /
AnnaBridge	172:65be27845400	474	#define LL_DMAMUX_REQUEST_DFSDM1_FLT2 88U /!< DMAMUX DFSDM1_FLT2 request /
AnnaBridge	172:65be27845400	475	#define LL_DMAMUX_REQUEST_DFSDM1_FLT3 89U /!< DMAMUX DFSDM1_FLT3 request /
AnnaBridge	172:65be27845400	476	#define LL_DMAMUX_REQUEST_DCMI 90U /!< DMAMUX DCMI request /
AnnaBridge	172:65be27845400	477	#define LL_DMAMUX_REQUEST_AES_IN 91U /!< DMAMUX AES_IN request /
AnnaBridge	172:65be27845400	478	#define LL_DMAMUX_REQUEST_AES_OUT 92U /!< DMAMUX AES_OUT request /
AnnaBridge	172:65be27845400	479	#define LL_DMAMUX_REQUEST_HASH_IN 93U /!< DMAMUX HASH_IN request /
AnnaBridge	172:65be27845400	480	/**
AnnaBridge	172:65be27845400	481	* @}
AnnaBridge	172:65be27845400	482	*/
AnnaBridge	172:65be27845400	483	#else
AnnaBridge	172:65be27845400	484	/** @defgroup DMA_LL_EC_REQUEST Transfer peripheral request
AnnaBridge	172:65be27845400	485	* @{
AnnaBridge	172:65be27845400	486	*/
AnnaBridge	172:65be27845400	487	#define LL_DMA_REQUEST_0 0x00000000U /!< DMA peripheral request 0 /
AnnaBridge	172:65be27845400	488	#define LL_DMA_REQUEST_1 0x00000001U /!< DMA peripheral request 1 /
AnnaBridge	172:65be27845400	489	#define LL_DMA_REQUEST_2 0x00000002U /!< DMA peripheral request 2 /
AnnaBridge	172:65be27845400	490	#define LL_DMA_REQUEST_3 0x00000003U /!< DMA peripheral request 3 /
AnnaBridge	172:65be27845400	491	#define LL_DMA_REQUEST_4 0x00000004U /!< DMA peripheral request 4 /
AnnaBridge	172:65be27845400	492	#define LL_DMA_REQUEST_5 0x00000005U /!< DMA peripheral request 5 /
AnnaBridge	172:65be27845400	493	#define LL_DMA_REQUEST_6 0x00000006U /!< DMA peripheral request 6 /
AnnaBridge	172:65be27845400	494	#define LL_DMA_REQUEST_7 0x00000007U /!< DMA peripheral request 7 /
AnnaBridge	172:65be27845400	495	/**
AnnaBridge	172:65be27845400	496	* @}
AnnaBridge	172:65be27845400	497	*/
AnnaBridge	172:65be27845400	498	#endif /* DMAMUX1 */
AnnaBridge	172:65be27845400	499
AnnaBridge	172:65be27845400	500	/**
AnnaBridge	172:65be27845400	501	* @}
AnnaBridge	172:65be27845400	502	*/
AnnaBridge	172:65be27845400	503
AnnaBridge	172:65be27845400	504	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	505	/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
AnnaBridge	172:65be27845400	506	* @{
AnnaBridge	172:65be27845400	507	*/
AnnaBridge	172:65be27845400	508
AnnaBridge	172:65be27845400	509	/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
AnnaBridge	172:65be27845400	510	* @{
AnnaBridge	172:65be27845400	511	*/
AnnaBridge	172:65be27845400	512	/**
AnnaBridge	172:65be27845400	513	* @brief Write a value in DMA register
AnnaBridge	172:65be27845400	514	* @param __INSTANCE__ DMA Instance
AnnaBridge	172:65be27845400	515	* @param __REG__ Register to be written
AnnaBridge	172:65be27845400	516	* @param __VALUE__ Value to be written in the register
AnnaBridge	172:65be27845400	517	* @retval None
AnnaBridge	172:65be27845400	518	*/
AnnaBridge	172:65be27845400	519	#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge	172:65be27845400	520
AnnaBridge	172:65be27845400	521	/**
AnnaBridge	172:65be27845400	522	* @brief Read a value in DMA register
AnnaBridge	172:65be27845400	523	* @param __INSTANCE__ DMA Instance
AnnaBridge	172:65be27845400	524	* @param __REG__ Register to be read
AnnaBridge	172:65be27845400	525	* @retval Register value
AnnaBridge	172:65be27845400	526	*/
AnnaBridge	172:65be27845400	527	#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge	172:65be27845400	528	/**
AnnaBridge	172:65be27845400	529	* @}
AnnaBridge	172:65be27845400	530	*/
AnnaBridge	172:65be27845400	531
AnnaBridge	172:65be27845400	532	/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
AnnaBridge	172:65be27845400	533	* @{
AnnaBridge	172:65be27845400	534	*/
AnnaBridge	172:65be27845400	535	/**
AnnaBridge	172:65be27845400	536	* @brief Convert DMAx_Channely into DMAx
AnnaBridge	172:65be27845400	537	* @param __CHANNEL_INSTANCE__ DMAx_Channely
AnnaBridge	172:65be27845400	538	* @retval DMAx
AnnaBridge	172:65be27845400	539	*/
AnnaBridge	172:65be27845400	540	#if defined(DMA2)
AnnaBridge	172:65be27845400	541	#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
AnnaBridge	172:65be27845400	542	(((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
AnnaBridge	172:65be27845400	543	#else
AnnaBridge	172:65be27845400	544	#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
AnnaBridge	172:65be27845400	545	#endif
AnnaBridge	172:65be27845400	546
AnnaBridge	172:65be27845400	547	/**
AnnaBridge	172:65be27845400	548	* @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
AnnaBridge	172:65be27845400	549	* @param __CHANNEL_INSTANCE__ DMAx_Channely
AnnaBridge	172:65be27845400	550	* @retval LL_DMA_CHANNEL_y
AnnaBridge	172:65be27845400	551	*/
AnnaBridge	172:65be27845400	552	#if defined (DMA2)
AnnaBridge	172:65be27845400	553	#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
AnnaBridge	172:65be27845400	554	#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
AnnaBridge	172:65be27845400	555	(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
AnnaBridge	172:65be27845400	556	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
AnnaBridge	172:65be27845400	557	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
AnnaBridge	172:65be27845400	558	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
AnnaBridge	172:65be27845400	559	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
AnnaBridge	172:65be27845400	560	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
AnnaBridge	172:65be27845400	561	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
AnnaBridge	172:65be27845400	562	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
AnnaBridge	172:65be27845400	563	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
AnnaBridge	172:65be27845400	564	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
AnnaBridge	172:65be27845400	565	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
AnnaBridge	172:65be27845400	566	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
AnnaBridge	172:65be27845400	567	LL_DMA_CHANNEL_7)
AnnaBridge	172:65be27845400	568	#else
AnnaBridge	172:65be27845400	569	#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
AnnaBridge	172:65be27845400	570	(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
AnnaBridge	172:65be27845400	571	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
AnnaBridge	172:65be27845400	572	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
AnnaBridge	172:65be27845400	573	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
AnnaBridge	172:65be27845400	574	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
AnnaBridge	172:65be27845400	575	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
AnnaBridge	172:65be27845400	576	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
AnnaBridge	172:65be27845400	577	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
AnnaBridge	172:65be27845400	578	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
AnnaBridge	172:65be27845400	579	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
AnnaBridge	172:65be27845400	580	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
AnnaBridge	172:65be27845400	581	LL_DMA_CHANNEL_7)
AnnaBridge	172:65be27845400	582	#endif
AnnaBridge	172:65be27845400	583	#else
AnnaBridge	172:65be27845400	584	#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
AnnaBridge	172:65be27845400	585	(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
AnnaBridge	172:65be27845400	586	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
AnnaBridge	172:65be27845400	587	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
AnnaBridge	172:65be27845400	588	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
AnnaBridge	172:65be27845400	589	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
AnnaBridge	172:65be27845400	590	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
AnnaBridge	172:65be27845400	591	LL_DMA_CHANNEL_7)
AnnaBridge	172:65be27845400	592	#endif
AnnaBridge	172:65be27845400	593
AnnaBridge	172:65be27845400	594	/**
AnnaBridge	172:65be27845400	595	* @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
AnnaBridge	172:65be27845400	596	* @param __DMA_INSTANCE__ DMAx
AnnaBridge	172:65be27845400	597	* @param __CHANNEL__ LL_DMA_CHANNEL_y
AnnaBridge	172:65be27845400	598	* @retval DMAx_Channely
AnnaBridge	172:65be27845400	599	*/
AnnaBridge	172:65be27845400	600	#if defined (DMA2)
AnnaBridge	172:65be27845400	601	#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
AnnaBridge	172:65be27845400	602	#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
AnnaBridge	172:65be27845400	603	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
AnnaBridge	172:65be27845400	604	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
AnnaBridge	172:65be27845400	605	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
AnnaBridge	172:65be27845400	606	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
AnnaBridge	172:65be27845400	607	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
AnnaBridge	172:65be27845400	608	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
AnnaBridge	172:65be27845400	609	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
AnnaBridge	172:65be27845400	610	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
AnnaBridge	172:65be27845400	611	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
AnnaBridge	172:65be27845400	612	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
AnnaBridge	172:65be27845400	613	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
AnnaBridge	172:65be27845400	614	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
AnnaBridge	172:65be27845400	615	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
AnnaBridge	172:65be27845400	616	DMA2_Channel7)
AnnaBridge	172:65be27845400	617	#else
AnnaBridge	172:65be27845400	618	#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
AnnaBridge	172:65be27845400	619	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
AnnaBridge	172:65be27845400	620	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
AnnaBridge	172:65be27845400	621	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
AnnaBridge	172:65be27845400	622	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
AnnaBridge	172:65be27845400	623	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
AnnaBridge	172:65be27845400	624	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
AnnaBridge	172:65be27845400	625	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
AnnaBridge	172:65be27845400	626	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
AnnaBridge	172:65be27845400	627	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
AnnaBridge	172:65be27845400	628	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
AnnaBridge	172:65be27845400	629	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
AnnaBridge	172:65be27845400	630	DMA1_Channel7)
AnnaBridge	172:65be27845400	631	#endif
AnnaBridge	172:65be27845400	632	#else
AnnaBridge	172:65be27845400	633	#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
AnnaBridge	172:65be27845400	634	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
AnnaBridge	172:65be27845400	635	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
AnnaBridge	172:65be27845400	636	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
AnnaBridge	172:65be27845400	637	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
AnnaBridge	172:65be27845400	638	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
AnnaBridge	172:65be27845400	639	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
AnnaBridge	172:65be27845400	640	DMA1_Channel7)
AnnaBridge	172:65be27845400	641	#endif
AnnaBridge	172:65be27845400	642
AnnaBridge	172:65be27845400	643	/**
AnnaBridge	172:65be27845400	644	* @}
AnnaBridge	172:65be27845400	645	*/
AnnaBridge	172:65be27845400	646
AnnaBridge	172:65be27845400	647	/**
AnnaBridge	172:65be27845400	648	* @}
AnnaBridge	172:65be27845400	649	*/
AnnaBridge	172:65be27845400	650
AnnaBridge	172:65be27845400	651	/* Exported functions --------------------------------------------------------*/
AnnaBridge	172:65be27845400	652	/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
AnnaBridge	172:65be27845400	653	* @{
AnnaBridge	172:65be27845400	654	*/
AnnaBridge	172:65be27845400	655
AnnaBridge	172:65be27845400	656	/** @defgroup DMA_LL_EF_Configuration Configuration
AnnaBridge	172:65be27845400	657	* @{
AnnaBridge	172:65be27845400	658	*/
AnnaBridge	172:65be27845400	659	/**
AnnaBridge	172:65be27845400	660	* @brief Enable DMA channel.
AnnaBridge	172:65be27845400	661	* @rmtoll CCR EN LL_DMA_EnableChannel
AnnaBridge	172:65be27845400	662	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	663	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	664	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	172:65be27845400	665	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	172:65be27845400	666	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	172:65be27845400	667	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	172:65be27845400	668	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	172:65be27845400	669	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	172:65be27845400	670	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	172:65be27845400	671	* @retval None
AnnaBridge	172:65be27845400	672	*/
AnnaBridge	172:65be27845400	673	__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	172:65be27845400	674	{
AnnaBridge	172:65be27845400	675	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
AnnaBridge	172:65be27845400	676	}
AnnaBridge	172:65be27845400	677
AnnaBridge	172:65be27845400	678	/**
AnnaBridge	172:65be27845400	679	* @brief Disable DMA channel.
AnnaBridge	172:65be27845400	680	* @rmtoll CCR EN LL_DMA_DisableChannel
AnnaBridge	172:65be27845400	681	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	682	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	683	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	172:65be27845400	684	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	172:65be27845400	685	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	172:65be27845400	686	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	172:65be27845400	687	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	172:65be27845400	688	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	172:65be27845400	689	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	172:65be27845400	690	* @retval None
AnnaBridge	172:65be27845400	691	*/
AnnaBridge	172:65be27845400	692	__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	172:65be27845400	693	{
AnnaBridge	172:65be27845400	694	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
AnnaBridge	172:65be27845400	695	}
AnnaBridge	172:65be27845400	696
AnnaBridge	172:65be27845400	697	/**
AnnaBridge	172:65be27845400	698	* @brief Check if DMA channel is enabled or disabled.
AnnaBridge	172:65be27845400	699	* @rmtoll CCR EN LL_DMA_IsEnabledChannel
AnnaBridge	172:65be27845400	700	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	701	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	702	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	172:65be27845400	703	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	172:65be27845400	704	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	172:65be27845400	705	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	172:65be27845400	706	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	172:65be27845400	707	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	172:65be27845400	708	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	172:65be27845400	709	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	710	*/
AnnaBridge	172:65be27845400	711	__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	172:65be27845400	712	{
AnnaBridge	172:65be27845400	713	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	172:65be27845400	714	DMA_CCR_EN) == (DMA_CCR_EN));
AnnaBridge	172:65be27845400	715	}
AnnaBridge	172:65be27845400	716
AnnaBridge	172:65be27845400	717	/**
AnnaBridge	172:65be27845400	718	* @brief Configure all parameters link to DMA transfer.
AnnaBridge	172:65be27845400	719	* @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
AnnaBridge	172:65be27845400	720	* CCR MEM2MEM LL_DMA_ConfigTransfer\n
AnnaBridge	172:65be27845400	721	* CCR CIRC LL_DMA_ConfigTransfer\n
AnnaBridge	172:65be27845400	722	* CCR PINC LL_DMA_ConfigTransfer\n
AnnaBridge	172:65be27845400	723	* CCR MINC LL_DMA_ConfigTransfer\n
AnnaBridge	172:65be27845400	724	* CCR PSIZE LL_DMA_ConfigTransfer\n
AnnaBridge	172:65be27845400	725	* CCR MSIZE LL_DMA_ConfigTransfer\n
AnnaBridge	172:65be27845400	726	* CCR PL LL_DMA_ConfigTransfer
AnnaBridge	172:65be27845400	727	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	728	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	729	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	172:65be27845400	730	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	172:65be27845400	731	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	172:65be27845400	732	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	172:65be27845400	733	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	172:65be27845400	734	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	172:65be27845400	735	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	172:65be27845400	736	* @param Configuration This parameter must be a combination of all the following values:
AnnaBridge	172:65be27845400	737	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge	172:65be27845400	738	* @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
AnnaBridge	172:65be27845400	739	* @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
AnnaBridge	172:65be27845400	740	* @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
AnnaBridge	172:65be27845400	741	* @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
AnnaBridge	172:65be27845400	742	* @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
AnnaBridge	172:65be27845400	743	* @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
AnnaBridge	172:65be27845400	744	* @retval None
AnnaBridge	172:65be27845400	745	*/
AnnaBridge	172:65be27845400	746	__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
AnnaBridge	172:65be27845400	747	{
AnnaBridge	172:65be27845400	748	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	172:65be27845400	749	DMA_CCR_DIR \| DMA_CCR_MEM2MEM \| DMA_CCR_CIRC \| DMA_CCR_PINC \| DMA_CCR_MINC \| DMA_CCR_PSIZE \| DMA_CCR_MSIZE \| DMA_CCR_PL,
AnnaBridge	172:65be27845400	750	Configuration);
AnnaBridge	172:65be27845400	751	}
AnnaBridge	172:65be27845400	752
AnnaBridge	172:65be27845400	753	/**
AnnaBridge	172:65be27845400	754	* @brief Set Data transfer direction (read from peripheral or from memory).
AnnaBridge	172:65be27845400	755	* @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
AnnaBridge	172:65be27845400	756	* CCR MEM2MEM LL_DMA_SetDataTransferDirection
AnnaBridge	172:65be27845400	757	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	758	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	759	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	172:65be27845400	760	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	172:65be27845400	761	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	172:65be27845400	762	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	172:65be27845400	763	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	172:65be27845400	764	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	172:65be27845400	765	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	172:65be27845400	766	* @param Direction This parameter can be one of the following values:
AnnaBridge	172:65be27845400	767	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
AnnaBridge	172:65be27845400	768	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
AnnaBridge	172:65be27845400	769	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge	172:65be27845400	770	* @retval None
AnnaBridge	172:65be27845400	771	*/
AnnaBridge	172:65be27845400	772	__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
AnnaBridge	172:65be27845400	773	{
AnnaBridge	172:65be27845400	774	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	172:65be27845400	775	DMA_CCR_DIR \| DMA_CCR_MEM2MEM, Direction);
AnnaBridge	172:65be27845400	776	}
AnnaBridge	172:65be27845400	777
AnnaBridge	172:65be27845400	778	/**
AnnaBridge	172:65be27845400	779	* @brief Get Data transfer direction (read from peripheral or from memory).
AnnaBridge	172:65be27845400	780	* @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
AnnaBridge	172:65be27845400	781	* CCR MEM2MEM LL_DMA_GetDataTransferDirection
AnnaBridge	172:65be27845400	782	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	783	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	784	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	172:65be27845400	785	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	172:65be27845400	786	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	172:65be27845400	787	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	172:65be27845400	788	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	172:65be27845400	789	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	172:65be27845400	790	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	172:65be27845400	791	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	792	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
AnnaBridge	172:65be27845400	793	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
AnnaBridge	172:65be27845400	794	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge	172:65be27845400	795	*/
AnnaBridge	172:65be27845400	796	__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	172:65be27845400	797	{
AnnaBridge	172:65be27845400	798	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	172:65be27845400	799	DMA_CCR_DIR \| DMA_CCR_MEM2MEM));
AnnaBridge	172:65be27845400	800	}
AnnaBridge	172:65be27845400	801
AnnaBridge	172:65be27845400	802	/**
AnnaBridge	172:65be27845400	803	* @brief Set DMA mode circular or normal.
AnnaBridge	172:65be27845400	804	* @note The circular buffer mode cannot be used if the memory-to-memory
AnnaBridge	172:65be27845400	805	* data transfer is configured on the selected Channel.
AnnaBridge	172:65be27845400	806	* @rmtoll CCR CIRC LL_DMA_SetMode
AnnaBridge	172:65be27845400	807	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	808	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	809	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	172:65be27845400	810	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	172:65be27845400	811	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	172:65be27845400	812	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	172:65be27845400	813	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	172:65be27845400	814	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	172:65be27845400	815	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	172:65be27845400	816	* @param Mode This parameter can be one of the following values:
AnnaBridge	172:65be27845400	817	* @arg @ref LL_DMA_MODE_NORMAL
AnnaBridge	172:65be27845400	818	* @arg @ref LL_DMA_MODE_CIRCULAR
AnnaBridge	172:65be27845400	819	* @retval None
AnnaBridge	172:65be27845400	820	*/
AnnaBridge	172:65be27845400	821	__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
AnnaBridge	172:65be27845400	822	{
AnnaBridge	172:65be27845400	823	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
AnnaBridge	172:65be27845400	824	Mode);
AnnaBridge	172:65be27845400	825	}
AnnaBridge	172:65be27845400	826
AnnaBridge	172:65be27845400	827	/**
AnnaBridge	172:65be27845400	828	* @brief Get DMA mode circular or normal.
AnnaBridge	172:65be27845400	829	* @rmtoll CCR CIRC LL_DMA_GetMode
AnnaBridge	172:65be27845400	830	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	831	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	832	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	172:65be27845400	833	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	172:65be27845400	834	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	172:65be27845400	835	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	172:65be27845400	836	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	172:65be27845400	837	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	172:65be27845400	838	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	172:65be27845400	839	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	840	* @arg @ref LL_DMA_MODE_NORMAL
AnnaBridge	172:65be27845400	841	* @arg @ref LL_DMA_MODE_CIRCULAR
AnnaBridge	172:65be27845400	842	*/
AnnaBridge	172:65be27845400	843	__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	172:65be27845400	844	{
AnnaBridge	172:65be27845400	845	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	172:65be27845400	846	DMA_CCR_CIRC));
AnnaBridge	172:65be27845400	847	}
AnnaBridge	172:65be27845400	848
AnnaBridge	172:65be27845400	849	/**
AnnaBridge	172:65be27845400	850	* @brief Set Peripheral increment mode.
AnnaBridge	172:65be27845400	851	* @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
AnnaBridge	172:65be27845400	852	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	853	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	854	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	172:65be27845400	855	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	172:65be27845400	856	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	172:65be27845400	857	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	172:65be27845400	858	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	172:65be27845400	859	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	172:65be27845400	860	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	172:65be27845400	861	* @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
AnnaBridge	172:65be27845400	862	* @arg @ref LL_DMA_PERIPH_INCREMENT
AnnaBridge	172:65be27845400	863	* @arg @ref LL_DMA_PERIPH_NOINCREMENT
AnnaBridge	172:65be27845400	864	* @retval None
AnnaBridge	172:65be27845400	865	*/
AnnaBridge	172:65be27845400	866	__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
AnnaBridge	172:65be27845400	867	{
AnnaBridge	172:65be27845400	868	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
AnnaBridge	172:65be27845400	869	PeriphOrM2MSrcIncMode);
AnnaBridge	172:65be27845400	870	}
AnnaBridge	172:65be27845400	871
AnnaBridge	172:65be27845400	872	/**
AnnaBridge	172:65be27845400	873	* @brief Get Peripheral increment mode.
AnnaBridge	172:65be27845400	874	* @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
AnnaBridge	172:65be27845400	875	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	876	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	877	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	172:65be27845400	878	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	172:65be27845400	879	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	172:65be27845400	880	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	172:65be27845400	881	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	172:65be27845400	882	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	172:65be27845400	883	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	172:65be27845400	884	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	885	* @arg @ref LL_DMA_PERIPH_INCREMENT
AnnaBridge	172:65be27845400	886	* @arg @ref LL_DMA_PERIPH_NOINCREMENT
AnnaBridge	172:65be27845400	887	*/
AnnaBridge	172:65be27845400	888	__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	172:65be27845400	889	{
AnnaBridge	172:65be27845400	890	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	172:65be27845400	891	DMA_CCR_PINC));
AnnaBridge	172:65be27845400	892	}
AnnaBridge	172:65be27845400	893
AnnaBridge	172:65be27845400	894	/**
AnnaBridge	172:65be27845400	895	* @brief Set Memory increment mode.
AnnaBridge	172:65be27845400	896	* @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
AnnaBridge	172:65be27845400	897	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	898	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	899	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	172:65be27845400	900	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	172:65be27845400	901	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	172:65be27845400	902	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	172:65be27845400	903	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	172:65be27845400	904	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	172:65be27845400	905	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	172:65be27845400	906	* @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
AnnaBridge	172:65be27845400	907	* @arg @ref LL_DMA_MEMORY_INCREMENT
AnnaBridge	172:65be27845400	908	* @arg @ref LL_DMA_MEMORY_NOINCREMENT
AnnaBridge	172:65be27845400	909	* @retval None
AnnaBridge	172:65be27845400	910	*/
AnnaBridge	172:65be27845400	911	__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
AnnaBridge	172:65be27845400	912	{
AnnaBridge	172:65be27845400	913	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
AnnaBridge	172:65be27845400	914	MemoryOrM2MDstIncMode);
AnnaBridge	172:65be27845400	915	}
AnnaBridge	172:65be27845400	916
AnnaBridge	172:65be27845400	917	/**
AnnaBridge	172:65be27845400	918	* @brief Get Memory increment mode.
AnnaBridge	172:65be27845400	919	* @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
AnnaBridge	172:65be27845400	920	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	921	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	922	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	172:65be27845400	923	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	172:65be27845400	924	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	172:65be27845400	925	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	172:65be27845400	926	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	172:65be27845400	927	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	172:65be27845400	928	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	172:65be27845400	929	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	930	* @arg @ref LL_DMA_MEMORY_INCREMENT
AnnaBridge	172:65be27845400	931	* @arg @ref LL_DMA_MEMORY_NOINCREMENT
AnnaBridge	172:65be27845400	932	*/
AnnaBridge	172:65be27845400	933	__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	172:65be27845400	934	{
AnnaBridge	172:65be27845400	935	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	172:65be27845400	936	DMA_CCR_MINC));
AnnaBridge	172:65be27845400	937	}
AnnaBridge	172:65be27845400	938
AnnaBridge	172:65be27845400	939	/**
AnnaBridge	172:65be27845400	940	* @brief Set Peripheral size.
AnnaBridge	172:65be27845400	941	* @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
AnnaBridge	172:65be27845400	942	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	943	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	944	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	172:65be27845400	945	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	172:65be27845400	946	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	172:65be27845400	947	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	172:65be27845400	948	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	172:65be27845400	949	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	172:65be27845400	950	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	172:65be27845400	951	* @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
AnnaBridge	172:65be27845400	952	* @arg @ref LL_DMA_PDATAALIGN_BYTE
AnnaBridge	172:65be27845400	953	* @arg @ref LL_DMA_PDATAALIGN_HALFWORD
AnnaBridge	172:65be27845400	954	* @arg @ref LL_DMA_PDATAALIGN_WORD
AnnaBridge	172:65be27845400	955	* @retval None
AnnaBridge	172:65be27845400	956	*/
AnnaBridge	172:65be27845400	957	__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
AnnaBridge	172:65be27845400	958	{
AnnaBridge	172:65be27845400	959	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
AnnaBridge	172:65be27845400	960	PeriphOrM2MSrcDataSize);
AnnaBridge	172:65be27845400	961	}
AnnaBridge	172:65be27845400	962
AnnaBridge	172:65be27845400	963	/**
AnnaBridge	172:65be27845400	964	* @brief Get Peripheral size.
AnnaBridge	172:65be27845400	965	* @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
AnnaBridge	172:65be27845400	966	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	967	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	968	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	172:65be27845400	969	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	172:65be27845400	970	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	172:65be27845400	971	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	172:65be27845400	972	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	172:65be27845400	973	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	172:65be27845400	974	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	172:65be27845400	975	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	976	* @arg @ref LL_DMA_PDATAALIGN_BYTE
AnnaBridge	172:65be27845400	977	* @arg @ref LL_DMA_PDATAALIGN_HALFWORD
AnnaBridge	172:65be27845400	978	* @arg @ref LL_DMA_PDATAALIGN_WORD
AnnaBridge	172:65be27845400	979	*/
AnnaBridge	172:65be27845400	980	__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	172:65be27845400	981	{
AnnaBridge	172:65be27845400	982	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	172:65be27845400	983	DMA_CCR_PSIZE));
AnnaBridge	172:65be27845400	984	}
AnnaBridge	172:65be27845400	985
AnnaBridge	172:65be27845400	986	/**
AnnaBridge	172:65be27845400	987	* @brief Set Memory size.
AnnaBridge	172:65be27845400	988	* @rmtoll CCR MSIZE LL_DMA_SetMemorySize
AnnaBridge	172:65be27845400	989	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	990	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	991	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	172:65be27845400	992	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	172:65be27845400	993	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	172:65be27845400	994	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	172:65be27845400	995	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	172:65be27845400	996	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	172:65be27845400	997	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	172:65be27845400	998	* @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
AnnaBridge	172:65be27845400	999	* @arg @ref LL_DMA_MDATAALIGN_BYTE
AnnaBridge	172:65be27845400	1000	* @arg @ref LL_DMA_MDATAALIGN_HALFWORD
AnnaBridge	172:65be27845400	1001	* @arg @ref LL_DMA_MDATAALIGN_WORD
AnnaBridge	172:65be27845400	1002	* @retval None
AnnaBridge	172:65be27845400	1003	*/
AnnaBridge	172:65be27845400	1004	__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
AnnaBridge	172:65be27845400	1005	{
AnnaBridge	172:65be27845400	1006	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
AnnaBridge	172:65be27845400	1007	MemoryOrM2MDstDataSize);
AnnaBridge	172:65be27845400	1008	}
AnnaBridge	172:65be27845400	1009
AnnaBridge	172:65be27845400	1010	/**
AnnaBridge	172:65be27845400	1011	* @brief Get Memory size.
AnnaBridge	172:65be27845400	1012	* @rmtoll CCR MSIZE LL_DMA_GetMemorySize
AnnaBridge	172:65be27845400	1013	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1014	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1015	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	172:65be27845400	1016	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	172:65be27845400	1017	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	172:65be27845400	1018	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	172:65be27845400	1019	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	172:65be27845400	1020	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	172:65be27845400	1021	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	172:65be27845400	1022	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1023	* @arg @ref LL_DMA_MDATAALIGN_BYTE
AnnaBridge	172:65be27845400	1024	* @arg @ref LL_DMA_MDATAALIGN_HALFWORD
AnnaBridge	172:65be27845400	1025	* @arg @ref LL_DMA_MDATAALIGN_WORD
AnnaBridge	172:65be27845400	1026	*/
AnnaBridge	172:65be27845400	1027	__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	172:65be27845400	1028	{
AnnaBridge	172:65be27845400	1029	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	172:65be27845400	1030	DMA_CCR_MSIZE));
AnnaBridge	172:65be27845400	1031	}
AnnaBridge	172:65be27845400	1032
AnnaBridge	172:65be27845400	1033	/**
AnnaBridge	172:65be27845400	1034	* @brief Set Channel priority level.
AnnaBridge	172:65be27845400	1035	* @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
AnnaBridge	172:65be27845400	1036	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1037	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1038	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	172:65be27845400	1039	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	172:65be27845400	1040	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	172:65be27845400	1041	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	172:65be27845400	1042	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	172:65be27845400	1043	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	172:65be27845400	1044	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	172:65be27845400	1045	* @param Priority This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1046	* @arg @ref LL_DMA_PRIORITY_LOW
AnnaBridge	172:65be27845400	1047	* @arg @ref LL_DMA_PRIORITY_MEDIUM
AnnaBridge	172:65be27845400	1048	* @arg @ref LL_DMA_PRIORITY_HIGH
AnnaBridge	172:65be27845400	1049	* @arg @ref LL_DMA_PRIORITY_VERYHIGH
AnnaBridge	172:65be27845400	1050	* @retval None
AnnaBridge	172:65be27845400	1051	*/
AnnaBridge	172:65be27845400	1052	__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
AnnaBridge	172:65be27845400	1053	{
AnnaBridge	172:65be27845400	1054	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
AnnaBridge	172:65be27845400	1055	Priority);
AnnaBridge	172:65be27845400	1056	}
AnnaBridge	172:65be27845400	1057
AnnaBridge	172:65be27845400	1058	/**
AnnaBridge	172:65be27845400	1059	* @brief Get Channel priority level.
AnnaBridge	172:65be27845400	1060	* @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
AnnaBridge	172:65be27845400	1061	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1062	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1063	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	172:65be27845400	1064	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	172:65be27845400	1065	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	172:65be27845400	1066	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	172:65be27845400	1067	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	172:65be27845400	1068	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	172:65be27845400	1069	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	172:65be27845400	1070	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1071	* @arg @ref LL_DMA_PRIORITY_LOW
AnnaBridge	172:65be27845400	1072	* @arg @ref LL_DMA_PRIORITY_MEDIUM
AnnaBridge	172:65be27845400	1073	* @arg @ref LL_DMA_PRIORITY_HIGH
AnnaBridge	172:65be27845400	1074	* @arg @ref LL_DMA_PRIORITY_VERYHIGH
AnnaBridge	172:65be27845400	1075	*/
AnnaBridge	172:65be27845400	1076	__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	172:65be27845400	1077	{
AnnaBridge	172:65be27845400	1078	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	172:65be27845400	1079	DMA_CCR_PL));
AnnaBridge	172:65be27845400	1080	}
AnnaBridge	172:65be27845400	1081
AnnaBridge	172:65be27845400	1082	/**
AnnaBridge	172:65be27845400	1083	* @brief Set Number of data to transfer.
AnnaBridge	172:65be27845400	1084	* @note This action has no effect if
AnnaBridge	172:65be27845400	1085	* channel is enabled.
AnnaBridge	172:65be27845400	1086	* @rmtoll CNDTR NDT LL_DMA_SetDataLength
AnnaBridge	172:65be27845400	1087	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1088	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1089	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	172:65be27845400	1090	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	172:65be27845400	1091	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	172:65be27845400	1092	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	172:65be27845400	1093	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	172:65be27845400	1094	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	172:65be27845400	1095	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	172:65be27845400	1096	* @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
AnnaBridge	172:65be27845400	1097	* @retval None
AnnaBridge	172:65be27845400	1098	*/
AnnaBridge	172:65be27845400	1099	__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
AnnaBridge	172:65be27845400	1100	{
AnnaBridge	172:65be27845400	1101	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
AnnaBridge	172:65be27845400	1102	DMA_CNDTR_NDT, NbData);
AnnaBridge	172:65be27845400	1103	}
AnnaBridge	172:65be27845400	1104
AnnaBridge	172:65be27845400	1105	/**
AnnaBridge	172:65be27845400	1106	* @brief Get Number of data to transfer.
AnnaBridge	172:65be27845400	1107	* @note Once the channel is enabled, the return value indicate the
AnnaBridge	172:65be27845400	1108	* remaining bytes to be transmitted.
AnnaBridge	172:65be27845400	1109	* @rmtoll CNDTR NDT LL_DMA_GetDataLength
AnnaBridge	172:65be27845400	1110	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1111	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1112	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	172:65be27845400	1113	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	172:65be27845400	1114	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	172:65be27845400	1115	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	172:65be27845400	1116	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	172:65be27845400	1117	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	172:65be27845400	1118	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	172:65be27845400	1119	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	172:65be27845400	1120	*/
AnnaBridge	172:65be27845400	1121	__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	172:65be27845400	1122	{
AnnaBridge	172:65be27845400	1123	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
AnnaBridge	172:65be27845400	1124	DMA_CNDTR_NDT));
AnnaBridge	172:65be27845400	1125	}
AnnaBridge	172:65be27845400	1126
AnnaBridge	172:65be27845400	1127	/**
AnnaBridge	172:65be27845400	1128	* @brief Configure the Source and Destination addresses.
AnnaBridge	172:65be27845400	1129	* @note This API must not be called when the DMA channel is enabled.
AnnaBridge	172:65be27845400	1130	* @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr).
AnnaBridge	172:65be27845400	1131	* @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
AnnaBridge	172:65be27845400	1132	* CMAR MA LL_DMA_ConfigAddresses
AnnaBridge	172:65be27845400	1133	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1134	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1135	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	172:65be27845400	1136	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	172:65be27845400	1137	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	172:65be27845400	1138	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	172:65be27845400	1139	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	172:65be27845400	1140	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	172:65be27845400	1141	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	172:65be27845400	1142	* @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	172:65be27845400	1143	* @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	172:65be27845400	1144	* @param Direction This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1145	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
AnnaBridge	172:65be27845400	1146	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
AnnaBridge	172:65be27845400	1147	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge	172:65be27845400	1148	* @retval None
AnnaBridge	172:65be27845400	1149	*/
AnnaBridge	172:65be27845400	1150	__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
AnnaBridge	172:65be27845400	1151	uint32_t DstAddress, uint32_t Direction)
AnnaBridge	172:65be27845400	1152	{
AnnaBridge	172:65be27845400	1153	/* Direction Memory to Periph */
AnnaBridge	172:65be27845400	1154	if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
AnnaBridge	172:65be27845400	1155	{
AnnaBridge	172:65be27845400	1156	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress);
AnnaBridge	172:65be27845400	1157	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress);
AnnaBridge	172:65be27845400	1158	}
AnnaBridge	172:65be27845400	1159	/* Direction Periph to Memory and Memory to Memory */
AnnaBridge	172:65be27845400	1160	else
AnnaBridge	172:65be27845400	1161	{
AnnaBridge	172:65be27845400	1162	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress);
AnnaBridge	172:65be27845400	1163	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress);
AnnaBridge	172:65be27845400	1164	}
AnnaBridge	172:65be27845400	1165	}
AnnaBridge	172:65be27845400	1166
AnnaBridge	172:65be27845400	1167	/**
AnnaBridge	172:65be27845400	1168	* @brief Set the Memory address.
AnnaBridge	172:65be27845400	1169	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge	172:65be27845400	1170	* @note This API must not be called when the DMA channel is enabled.
AnnaBridge	172:65be27845400	1171	* @rmtoll CMAR MA LL_DMA_SetMemoryAddress
AnnaBridge	172:65be27845400	1172	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1173	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1174	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	172:65be27845400	1175	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	172:65be27845400	1176	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	172:65be27845400	1177	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	172:65be27845400	1178	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	172:65be27845400	1179	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	172:65be27845400	1180	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	172:65be27845400	1181	* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	172:65be27845400	1182	* @retval None
AnnaBridge	172:65be27845400	1183	*/
AnnaBridge	172:65be27845400	1184	__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
AnnaBridge	172:65be27845400	1185	{
AnnaBridge	172:65be27845400	1186	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
AnnaBridge	172:65be27845400	1187	}
AnnaBridge	172:65be27845400	1188
AnnaBridge	172:65be27845400	1189	/**
AnnaBridge	172:65be27845400	1190	* @brief Set the Peripheral address.
AnnaBridge	172:65be27845400	1191	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge	172:65be27845400	1192	* @note This API must not be called when the DMA channel is enabled.
AnnaBridge	172:65be27845400	1193	* @rmtoll CPAR PA LL_DMA_SetPeriphAddress
AnnaBridge	172:65be27845400	1194	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1195	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1196	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	172:65be27845400	1197	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	172:65be27845400	1198	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	172:65be27845400	1199	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	172:65be27845400	1200	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	172:65be27845400	1201	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	172:65be27845400	1202	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	172:65be27845400	1203	* @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	172:65be27845400	1204	* @retval None
AnnaBridge	172:65be27845400	1205	*/
AnnaBridge	172:65be27845400	1206	__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
AnnaBridge	172:65be27845400	1207	{
AnnaBridge	172:65be27845400	1208	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress);
AnnaBridge	172:65be27845400	1209	}
AnnaBridge	172:65be27845400	1210
AnnaBridge	172:65be27845400	1211	/**
AnnaBridge	172:65be27845400	1212	* @brief Get Memory address.
AnnaBridge	172:65be27845400	1213	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge	172:65be27845400	1214	* @rmtoll CMAR MA LL_DMA_GetMemoryAddress
AnnaBridge	172:65be27845400	1215	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1216	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1217	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	172:65be27845400	1218	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	172:65be27845400	1219	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	172:65be27845400	1220	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	172:65be27845400	1221	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	172:65be27845400	1222	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	172:65be27845400	1223	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	172:65be27845400	1224	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	172:65be27845400	1225	*/
AnnaBridge	172:65be27845400	1226	__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	172:65be27845400	1227	{
AnnaBridge	172:65be27845400	1228	return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
AnnaBridge	172:65be27845400	1229	}
AnnaBridge	172:65be27845400	1230
AnnaBridge	172:65be27845400	1231	/**
AnnaBridge	172:65be27845400	1232	* @brief Get Peripheral address.
AnnaBridge	172:65be27845400	1233	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge	172:65be27845400	1234	* @rmtoll CPAR PA LL_DMA_GetPeriphAddress
AnnaBridge	172:65be27845400	1235	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1236	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1237	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	172:65be27845400	1238	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	172:65be27845400	1239	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	172:65be27845400	1240	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	172:65be27845400	1241	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	172:65be27845400	1242	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	172:65be27845400	1243	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	172:65be27845400	1244	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	172:65be27845400	1245	*/
AnnaBridge	172:65be27845400	1246	__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	172:65be27845400	1247	{
AnnaBridge	172:65be27845400	1248	return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
AnnaBridge	172:65be27845400	1249	}
AnnaBridge	172:65be27845400	1250
AnnaBridge	172:65be27845400	1251	/**
AnnaBridge	172:65be27845400	1252	* @brief Set the Memory to Memory Source address.
AnnaBridge	172:65be27845400	1253	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge	172:65be27845400	1254	* @note This API must not be called when the DMA channel is enabled.
AnnaBridge	172:65be27845400	1255	* @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
AnnaBridge	172:65be27845400	1256	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1257	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1258	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	172:65be27845400	1259	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	172:65be27845400	1260	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	172:65be27845400	1261	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	172:65be27845400	1262	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	172:65be27845400	1263	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	172:65be27845400	1264	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	172:65be27845400	1265	* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	172:65be27845400	1266	* @retval None
AnnaBridge	172:65be27845400	1267	*/
AnnaBridge	172:65be27845400	1268	__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
AnnaBridge	172:65be27845400	1269	{
AnnaBridge	172:65be27845400	1270	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress);
AnnaBridge	172:65be27845400	1271	}
AnnaBridge	172:65be27845400	1272
AnnaBridge	172:65be27845400	1273	/**
AnnaBridge	172:65be27845400	1274	* @brief Set the Memory to Memory Destination address.
AnnaBridge	172:65be27845400	1275	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge	172:65be27845400	1276	* @note This API must not be called when the DMA channel is enabled.
AnnaBridge	172:65be27845400	1277	* @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
AnnaBridge	172:65be27845400	1278	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1279	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1280	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	172:65be27845400	1281	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	172:65be27845400	1282	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	172:65be27845400	1283	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	172:65be27845400	1284	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	172:65be27845400	1285	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	172:65be27845400	1286	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	172:65be27845400	1287	* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	172:65be27845400	1288	* @retval None
AnnaBridge	172:65be27845400	1289	*/
AnnaBridge	172:65be27845400	1290	__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
AnnaBridge	172:65be27845400	1291	{
AnnaBridge	172:65be27845400	1292	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
AnnaBridge	172:65be27845400	1293	}
AnnaBridge	172:65be27845400	1294
AnnaBridge	172:65be27845400	1295	/**
AnnaBridge	172:65be27845400	1296	* @brief Get the Memory to Memory Source address.
AnnaBridge	172:65be27845400	1297	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge	172:65be27845400	1298	* @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
AnnaBridge	172:65be27845400	1299	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1300	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1301	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	172:65be27845400	1302	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	172:65be27845400	1303	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	172:65be27845400	1304	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	172:65be27845400	1305	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	172:65be27845400	1306	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	172:65be27845400	1307	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	172:65be27845400	1308	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	172:65be27845400	1309	*/
AnnaBridge	172:65be27845400	1310	__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	172:65be27845400	1311	{
AnnaBridge	172:65be27845400	1312	return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
AnnaBridge	172:65be27845400	1313	}
AnnaBridge	172:65be27845400	1314
AnnaBridge	172:65be27845400	1315	/**
AnnaBridge	172:65be27845400	1316	* @brief Get the Memory to Memory Destination address.
AnnaBridge	172:65be27845400	1317	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge	172:65be27845400	1318	* @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
AnnaBridge	172:65be27845400	1319	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1320	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1321	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	172:65be27845400	1322	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	172:65be27845400	1323	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	172:65be27845400	1324	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	172:65be27845400	1325	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	172:65be27845400	1326	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	172:65be27845400	1327	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	172:65be27845400	1328	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	172:65be27845400	1329	*/
AnnaBridge	172:65be27845400	1330	__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	172:65be27845400	1331	{
AnnaBridge	172:65be27845400	1332	return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
AnnaBridge	172:65be27845400	1333	}
AnnaBridge	172:65be27845400	1334
AnnaBridge	172:65be27845400	1335	#if defined(DMAMUX1)
AnnaBridge	172:65be27845400	1336	/**
AnnaBridge	172:65be27845400	1337	* @brief Set DMA request for DMA Channels on DMAMUX Channel x.
AnnaBridge	172:65be27845400	1338	* @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
AnnaBridge	172:65be27845400	1339	* DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7.
AnnaBridge	172:65be27845400	1340	* @rmtoll CxCR DMAREQ_ID LL_DMA_SetPeriphRequest
AnnaBridge	172:65be27845400	1341	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1342	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1343	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	172:65be27845400	1344	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	172:65be27845400	1345	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	172:65be27845400	1346	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	172:65be27845400	1347	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	172:65be27845400	1348	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	172:65be27845400	1349	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	172:65be27845400	1350	* @param Request This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1351	* @arg @ref LL_DMAMUX_REQUEST_MEM2MEM
AnnaBridge	172:65be27845400	1352	* @arg @ref LL_DMAMUX_REQUEST_GENERATOR0
AnnaBridge	172:65be27845400	1353	* @arg @ref LL_DMAMUX_REQUEST_GENERATOR1
AnnaBridge	172:65be27845400	1354	* @arg @ref LL_DMAMUX_REQUEST_GENERATOR2
AnnaBridge	172:65be27845400	1355	* @arg @ref LL_DMAMUX_REQUEST_GENERATOR3
AnnaBridge	172:65be27845400	1356	* @arg @ref LL_DMAMUX_REQUEST_ADC1
AnnaBridge	172:65be27845400	1357	* @arg @ref LL_DMAMUX_REQUEST_DAC1_CH1
AnnaBridge	172:65be27845400	1358	* @arg @ref LL_DMAMUX_REQUEST_DAC1_CH2
AnnaBridge	172:65be27845400	1359	* @arg @ref LL_DMAMUX_REQUEST_TIM6_UP
AnnaBridge	172:65be27845400	1360	* @arg @ref LL_DMAMUX_REQUEST_TIM7_UP
AnnaBridge	172:65be27845400	1361	* @arg @ref LL_DMAMUX_REQUEST_SPI1_RX
AnnaBridge	172:65be27845400	1362	* @arg @ref LL_DMAMUX_REQUEST_SPI1_TX
AnnaBridge	172:65be27845400	1363	* @arg @ref LL_DMAMUX_REQUEST_SPI2_RX
AnnaBridge	172:65be27845400	1364	* @arg @ref LL_DMAMUX_REQUEST_SPI2_TX
AnnaBridge	172:65be27845400	1365	* @arg @ref LL_DMAMUX_REQUEST_SPI3_RX
AnnaBridge	172:65be27845400	1366	* @arg @ref LL_DMAMUX_REQUEST_SPI3_TX
AnnaBridge	172:65be27845400	1367	* @arg @ref LL_DMAMUX_REQUEST_I2C1_RX
AnnaBridge	172:65be27845400	1368	* @arg @ref LL_DMAMUX_REQUEST_I2C1_TX
AnnaBridge	172:65be27845400	1369	* @arg @ref LL_DMAMUX_REQUEST_I2C2_RX
AnnaBridge	172:65be27845400	1370	* @arg @ref LL_DMAMUX_REQUEST_I2C2_TX
AnnaBridge	172:65be27845400	1371	* @arg @ref LL_DMAMUX_REQUEST_I2C3_RX
AnnaBridge	172:65be27845400	1372	* @arg @ref LL_DMAMUX_REQUEST_I2C3_TX
AnnaBridge	172:65be27845400	1373	* @arg @ref LL_DMAMUX_REQUEST_I2C4_RX
AnnaBridge	172:65be27845400	1374	* @arg @ref LL_DMAMUX_REQUEST_I2C4_TX
AnnaBridge	172:65be27845400	1375	* @arg @ref LL_DMAMUX_REQUEST_USART1_RX
AnnaBridge	172:65be27845400	1376	* @arg @ref LL_DMAMUX_REQUEST_USART1_TX
AnnaBridge	172:65be27845400	1377	* @arg @ref LL_DMAMUX_REQUEST_USART2_RX
AnnaBridge	172:65be27845400	1378	* @arg @ref LL_DMAMUX_REQUEST_USART2_TX
AnnaBridge	172:65be27845400	1379	* @arg @ref LL_DMAMUX_REQUEST_USART3_RX
AnnaBridge	172:65be27845400	1380	* @arg @ref LL_DMAMUX_REQUEST_USART3_TX
AnnaBridge	172:65be27845400	1381	* @arg @ref LL_DMAMUX_REQUEST_UART4_RX
AnnaBridge	172:65be27845400	1382	* @arg @ref LL_DMAMUX_REQUEST_UART4_TX
AnnaBridge	172:65be27845400	1383	* @arg @ref LL_DMAMUX_REQUEST_UART5_RX
AnnaBridge	172:65be27845400	1384	* @arg @ref LL_DMAMUX_REQUEST_UART5_TX
AnnaBridge	172:65be27845400	1385	* @arg @ref LL_DMAMUX_REQUEST_LPUART1_RX
AnnaBridge	172:65be27845400	1386	* @arg @ref LL_DMAMUX_REQUEST_LPUART1_TX
AnnaBridge	172:65be27845400	1387	* @arg @ref LL_DMAMUX_REQUEST_SAI1_A
AnnaBridge	172:65be27845400	1388	* @arg @ref LL_DMAMUX_REQUEST_SAI1_B
AnnaBridge	172:65be27845400	1389	* @arg @ref LL_DMAMUX_REQUEST_SAI2_A
AnnaBridge	172:65be27845400	1390	* @arg @ref LL_DMAMUX_REQUEST_SAI2_B
AnnaBridge	172:65be27845400	1391	* @arg @ref LL_DMAMUX_REQUEST_OSPI1
AnnaBridge	172:65be27845400	1392	* @arg @ref LL_DMAMUX_REQUEST_OSPI2
AnnaBridge	172:65be27845400	1393	* @arg @ref LL_DMAMUX_REQUEST_TIM1_CH1
AnnaBridge	172:65be27845400	1394	* @arg @ref LL_DMAMUX_REQUEST_TIM1_CH2
AnnaBridge	172:65be27845400	1395	* @arg @ref LL_DMAMUX_REQUEST_TIM1_CH3
AnnaBridge	172:65be27845400	1396	* @arg @ref LL_DMAMUX_REQUEST_TIM1_CH4
AnnaBridge	172:65be27845400	1397	* @arg @ref LL_DMAMUX_REQUEST_TIM1_UP
AnnaBridge	172:65be27845400	1398	* @arg @ref LL_DMAMUX_REQUEST_TIM1_TRIG
AnnaBridge	172:65be27845400	1399	* @arg @ref LL_DMAMUX_REQUEST_TIM1_COM
AnnaBridge	172:65be27845400	1400	* @arg @ref LL_DMAMUX_REQUEST_TIM8_CH1
AnnaBridge	172:65be27845400	1401	* @arg @ref LL_DMAMUX_REQUEST_TIM8_CH2
AnnaBridge	172:65be27845400	1402	* @arg @ref LL_DMAMUX_REQUEST_TIM8_CH3
AnnaBridge	172:65be27845400	1403	* @arg @ref LL_DMAMUX_REQUEST_TIM8_CH4
AnnaBridge	172:65be27845400	1404	* @arg @ref LL_DMAMUX_REQUEST_TIM8_UP
AnnaBridge	172:65be27845400	1405	* @arg @ref LL_DMAMUX_REQUEST_TIM8_TRIG
AnnaBridge	172:65be27845400	1406	* @arg @ref LL_DMAMUX_REQUEST_TIM8_COM
AnnaBridge	172:65be27845400	1407	* @arg @ref LL_DMAMUX_REQUEST_TIM2_CH1
AnnaBridge	172:65be27845400	1408	* @arg @ref LL_DMAMUX_REQUEST_TIM2_CH2
AnnaBridge	172:65be27845400	1409	* @arg @ref LL_DMAMUX_REQUEST_TIM2_CH3
AnnaBridge	172:65be27845400	1410	* @arg @ref LL_DMAMUX_REQUEST_TIM2_CH4
AnnaBridge	172:65be27845400	1411	* @arg @ref LL_DMAMUX_REQUEST_TIM2_UP
AnnaBridge	172:65be27845400	1412	* @arg @ref LL_DMAMUX_REQUEST_TIM3_CH1
AnnaBridge	172:65be27845400	1413	* @arg @ref LL_DMAMUX_REQUEST_TIM3_CH2
AnnaBridge	172:65be27845400	1414	* @arg @ref LL_DMAMUX_REQUEST_TIM3_CH3
AnnaBridge	172:65be27845400	1415	* @arg @ref LL_DMAMUX_REQUEST_TIM3_CH4
AnnaBridge	172:65be27845400	1416	* @arg @ref LL_DMAMUX_REQUEST_TIM3_UP
AnnaBridge	172:65be27845400	1417	* @arg @ref LL_DMAMUX_REQUEST_TIM3_TRIG
AnnaBridge	172:65be27845400	1418	* @arg @ref LL_DMAMUX_REQUEST_TIM4_CH1
AnnaBridge	172:65be27845400	1419	* @arg @ref LL_DMAMUX_REQUEST_TIM4_CH2
AnnaBridge	172:65be27845400	1420	* @arg @ref LL_DMAMUX_REQUEST_TIM4_CH3
AnnaBridge	172:65be27845400	1421	* @arg @ref LL_DMAMUX_REQUEST_TIM4_CH4
AnnaBridge	172:65be27845400	1422	* @arg @ref LL_DMAMUX_REQUEST_TIM4_UP
AnnaBridge	172:65be27845400	1423	* @arg @ref LL_DMAMUX_REQUEST_TIM5_CH1
AnnaBridge	172:65be27845400	1424	* @arg @ref LL_DMAMUX_REQUEST_TIM5_CH2
AnnaBridge	172:65be27845400	1425	* @arg @ref LL_DMAMUX_REQUEST_TIM5_CH3
AnnaBridge	172:65be27845400	1426	* @arg @ref LL_DMAMUX_REQUEST_TIM5_CH4
AnnaBridge	172:65be27845400	1427	* @arg @ref LL_DMAMUX_REQUEST_TIM5_UP
AnnaBridge	172:65be27845400	1428	* @arg @ref LL_DMAMUX_REQUEST_TIM5_TRIG
AnnaBridge	172:65be27845400	1429	* @arg @ref LL_DMAMUX_REQUEST_TIM15_CH1
AnnaBridge	172:65be27845400	1430	* @arg @ref LL_DMAMUX_REQUEST_TIM15_UP
AnnaBridge	172:65be27845400	1431	* @arg @ref LL_DMAMUX_REQUEST_TIM15_TRIG
AnnaBridge	172:65be27845400	1432	* @arg @ref LL_DMAMUX_REQUEST_TIM15_COM
AnnaBridge	172:65be27845400	1433	* @arg @ref LL_DMAMUX_REQUEST_TIM16_CH1
AnnaBridge	172:65be27845400	1434	* @arg @ref LL_DMAMUX_REQUEST_TIM16_UP
AnnaBridge	172:65be27845400	1435	* @arg @ref LL_DMAMUX_REQUEST_TIM17_CH1
AnnaBridge	172:65be27845400	1436	* @arg @ref LL_DMAMUX_REQUEST_TIM17_UP
AnnaBridge	172:65be27845400	1437	* @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT0
AnnaBridge	172:65be27845400	1438	* @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT1
AnnaBridge	172:65be27845400	1439	* @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT2
AnnaBridge	172:65be27845400	1440	* @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT3
AnnaBridge	172:65be27845400	1441	* @arg @ref LL_DMAMUX_REQUEST_DCMI
AnnaBridge	172:65be27845400	1442	* @arg @ref LL_DMAMUX_REQUEST_AES_IN
AnnaBridge	172:65be27845400	1443	* @arg @ref LL_DMAMUX_REQUEST_AES_OUT
AnnaBridge	172:65be27845400	1444	* @arg @ref LL_DMAMUX_REQUEST_HASH_IN
AnnaBridge	172:65be27845400	1445	* @retval None
AnnaBridge	172:65be27845400	1446	*/
AnnaBridge	172:65be27845400	1447	__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request)
AnnaBridge	172:65be27845400	1448	{
AnnaBridge	172:65be27845400	1449	MODIFY_REG(((DMAMUX_Channel_TypeDef)(uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE(Channel-1U)) + (uint32_t)(DMAMUX_CCR_SIZE*__LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
AnnaBridge	172:65be27845400	1450	}
AnnaBridge	172:65be27845400	1451
AnnaBridge	172:65be27845400	1452	/**
AnnaBridge	172:65be27845400	1453	* @brief Get DMA request for DMA Channels on DMAMUX Channel x.
AnnaBridge	172:65be27845400	1454	* @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
AnnaBridge	172:65be27845400	1455	* DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7.
AnnaBridge	172:65be27845400	1456	* @rmtoll CxCR DMAREQ_ID LL_DMA_GetPeriphRequest
AnnaBridge	172:65be27845400	1457	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1458	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1459	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	172:65be27845400	1460	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	172:65be27845400	1461	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	172:65be27845400	1462	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	172:65be27845400	1463	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	172:65be27845400	1464	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	172:65be27845400	1465	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	172:65be27845400	1466	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1467	* @arg @ref LL_DMAMUX_REQUEST_MEM2MEM
AnnaBridge	172:65be27845400	1468	* @arg @ref LL_DMAMUX_REQUEST_GENERATOR0
AnnaBridge	172:65be27845400	1469	* @arg @ref LL_DMAMUX_REQUEST_GENERATOR1
AnnaBridge	172:65be27845400	1470	* @arg @ref LL_DMAMUX_REQUEST_GENERATOR2
AnnaBridge	172:65be27845400	1471	* @arg @ref LL_DMAMUX_REQUEST_GENERATOR3
AnnaBridge	172:65be27845400	1472	* @arg @ref LL_DMAMUX_REQUEST_ADC1
AnnaBridge	172:65be27845400	1473	* @arg @ref LL_DMAMUX_REQUEST_DAC1_CH1
AnnaBridge	172:65be27845400	1474	* @arg @ref LL_DMAMUX_REQUEST_DAC1_CH2
AnnaBridge	172:65be27845400	1475	* @arg @ref LL_DMAMUX_REQUEST_TIM6_UP
AnnaBridge	172:65be27845400	1476	* @arg @ref LL_DMAMUX_REQUEST_TIM7_UP
AnnaBridge	172:65be27845400	1477	* @arg @ref LL_DMAMUX_REQUEST_SPI1_RX
AnnaBridge	172:65be27845400	1478	* @arg @ref LL_DMAMUX_REQUEST_SPI1_TX
AnnaBridge	172:65be27845400	1479	* @arg @ref LL_DMAMUX_REQUEST_SPI2_RX
AnnaBridge	172:65be27845400	1480	* @arg @ref LL_DMAMUX_REQUEST_SPI2_TX
AnnaBridge	172:65be27845400	1481	* @arg @ref LL_DMAMUX_REQUEST_SPI3_RX
AnnaBridge	172:65be27845400	1482	* @arg @ref LL_DMAMUX_REQUEST_SPI3_TX
AnnaBridge	172:65be27845400	1483	* @arg @ref LL_DMAMUX_REQUEST_I2C1_RX
AnnaBridge	172:65be27845400	1484	* @arg @ref LL_DMAMUX_REQUEST_I2C1_TX
AnnaBridge	172:65be27845400	1485	* @arg @ref LL_DMAMUX_REQUEST_I2C2_RX
AnnaBridge	172:65be27845400	1486	* @arg @ref LL_DMAMUX_REQUEST_I2C2_TX
AnnaBridge	172:65be27845400	1487	* @arg @ref LL_DMAMUX_REQUEST_I2C3_RX
AnnaBridge	172:65be27845400	1488	* @arg @ref LL_DMAMUX_REQUEST_I2C3_TX
AnnaBridge	172:65be27845400	1489	* @arg @ref LL_DMAMUX_REQUEST_I2C4_RX
AnnaBridge	172:65be27845400	1490	* @arg @ref LL_DMAMUX_REQUEST_I2C4_TX
AnnaBridge	172:65be27845400	1491	* @arg @ref LL_DMAMUX_REQUEST_USART1_RX
AnnaBridge	172:65be27845400	1492	* @arg @ref LL_DMAMUX_REQUEST_USART1_TX
AnnaBridge	172:65be27845400	1493	* @arg @ref LL_DMAMUX_REQUEST_USART2_RX
AnnaBridge	172:65be27845400	1494	* @arg @ref LL_DMAMUX_REQUEST_USART2_TX
AnnaBridge	172:65be27845400	1495	* @arg @ref LL_DMAMUX_REQUEST_USART3_RX
AnnaBridge	172:65be27845400	1496	* @arg @ref LL_DMAMUX_REQUEST_USART3_TX
AnnaBridge	172:65be27845400	1497	* @arg @ref LL_DMAMUX_REQUEST_UART4_RX
AnnaBridge	172:65be27845400	1498	* @arg @ref LL_DMAMUX_REQUEST_UART4_TX
AnnaBridge	172:65be27845400	1499	* @arg @ref LL_DMAMUX_REQUEST_UART5_RX
AnnaBridge	172:65be27845400	1500	* @arg @ref LL_DMAMUX_REQUEST_UART5_TX
AnnaBridge	172:65be27845400	1501	* @arg @ref LL_DMAMUX_REQUEST_LPUART1_RX
AnnaBridge	172:65be27845400	1502	* @arg @ref LL_DMAMUX_REQUEST_LPUART1_TX
AnnaBridge	172:65be27845400	1503	* @arg @ref LL_DMAMUX_REQUEST_SAI1_A
AnnaBridge	172:65be27845400	1504	* @arg @ref LL_DMAMUX_REQUEST_SAI1_B
AnnaBridge	172:65be27845400	1505	* @arg @ref LL_DMAMUX_REQUEST_SAI2_A
AnnaBridge	172:65be27845400	1506	* @arg @ref LL_DMAMUX_REQUEST_SAI2_B
AnnaBridge	172:65be27845400	1507	* @arg @ref LL_DMAMUX_REQUEST_OSPI1
AnnaBridge	172:65be27845400	1508	* @arg @ref LL_DMAMUX_REQUEST_OSPI2
AnnaBridge	172:65be27845400	1509	* @arg @ref LL_DMAMUX_REQUEST_TIM1_CH1
AnnaBridge	172:65be27845400	1510	* @arg @ref LL_DMAMUX_REQUEST_TIM1_CH2
AnnaBridge	172:65be27845400	1511	* @arg @ref LL_DMAMUX_REQUEST_TIM1_CH3
AnnaBridge	172:65be27845400	1512	* @arg @ref LL_DMAMUX_REQUEST_TIM1_CH4
AnnaBridge	172:65be27845400	1513	* @arg @ref LL_DMAMUX_REQUEST_TIM1_UP
AnnaBridge	172:65be27845400	1514	* @arg @ref LL_DMAMUX_REQUEST_TIM1_TRIG
AnnaBridge	172:65be27845400	1515	* @arg @ref LL_DMAMUX_REQUEST_TIM1_COM
AnnaBridge	172:65be27845400	1516	* @arg @ref LL_DMAMUX_REQUEST_TIM8_CH1
AnnaBridge	172:65be27845400	1517	* @arg @ref LL_DMAMUX_REQUEST_TIM8_CH2
AnnaBridge	172:65be27845400	1518	* @arg @ref LL_DMAMUX_REQUEST_TIM8_CH3
AnnaBridge	172:65be27845400	1519	* @arg @ref LL_DMAMUX_REQUEST_TIM8_CH4
AnnaBridge	172:65be27845400	1520	* @arg @ref LL_DMAMUX_REQUEST_TIM8_UP
AnnaBridge	172:65be27845400	1521	* @arg @ref LL_DMAMUX_REQUEST_TIM8_TRIG
AnnaBridge	172:65be27845400	1522	* @arg @ref LL_DMAMUX_REQUEST_TIM8_COM
AnnaBridge	172:65be27845400	1523	* @arg @ref LL_DMAMUX_REQUEST_TIM2_CH1
AnnaBridge	172:65be27845400	1524	* @arg @ref LL_DMAMUX_REQUEST_TIM2_CH2
AnnaBridge	172:65be27845400	1525	* @arg @ref LL_DMAMUX_REQUEST_TIM2_CH3
AnnaBridge	172:65be27845400	1526	* @arg @ref LL_DMAMUX_REQUEST_TIM2_CH4
AnnaBridge	172:65be27845400	1527	* @arg @ref LL_DMAMUX_REQUEST_TIM2_UP
AnnaBridge	172:65be27845400	1528	* @arg @ref LL_DMAMUX_REQUEST_TIM3_CH1
AnnaBridge	172:65be27845400	1529	* @arg @ref LL_DMAMUX_REQUEST_TIM3_CH2
AnnaBridge	172:65be27845400	1530	* @arg @ref LL_DMAMUX_REQUEST_TIM3_CH3
AnnaBridge	172:65be27845400	1531	* @arg @ref LL_DMAMUX_REQUEST_TIM3_CH4
AnnaBridge	172:65be27845400	1532	* @arg @ref LL_DMAMUX_REQUEST_TIM3_UP
AnnaBridge	172:65be27845400	1533	* @arg @ref LL_DMAMUX_REQUEST_TIM3_TRIG
AnnaBridge	172:65be27845400	1534	* @arg @ref LL_DMAMUX_REQUEST_TIM4_CH1
AnnaBridge	172:65be27845400	1535	* @arg @ref LL_DMAMUX_REQUEST_TIM4_CH2
AnnaBridge	172:65be27845400	1536	* @arg @ref LL_DMAMUX_REQUEST_TIM4_CH3
AnnaBridge	172:65be27845400	1537	* @arg @ref LL_DMAMUX_REQUEST_TIM4_CH4
AnnaBridge	172:65be27845400	1538	* @arg @ref LL_DMAMUX_REQUEST_TIM4_UP
AnnaBridge	172:65be27845400	1539	* @arg @ref LL_DMAMUX_REQUEST_TIM5_CH1
AnnaBridge	172:65be27845400	1540	* @arg @ref LL_DMAMUX_REQUEST_TIM5_CH2
AnnaBridge	172:65be27845400	1541	* @arg @ref LL_DMAMUX_REQUEST_TIM5_CH3
AnnaBridge	172:65be27845400	1542	* @arg @ref LL_DMAMUX_REQUEST_TIM5_CH4
AnnaBridge	172:65be27845400	1543	* @arg @ref LL_DMAMUX_REQUEST_TIM5_UP
AnnaBridge	172:65be27845400	1544	* @arg @ref LL_DMAMUX_REQUEST_TIM5_TRIG
AnnaBridge	172:65be27845400	1545	* @arg @ref LL_DMAMUX_REQUEST_TIM15_CH1
AnnaBridge	172:65be27845400	1546	* @arg @ref LL_DMAMUX_REQUEST_TIM15_UP
AnnaBridge	172:65be27845400	1547	* @arg @ref LL_DMAMUX_REQUEST_TIM15_TRIG
AnnaBridge	172:65be27845400	1548	* @arg @ref LL_DMAMUX_REQUEST_TIM15_COM
AnnaBridge	172:65be27845400	1549	* @arg @ref LL_DMAMUX_REQUEST_TIM16_CH1
AnnaBridge	172:65be27845400	1550	* @arg @ref LL_DMAMUX_REQUEST_TIM16_UP
AnnaBridge	172:65be27845400	1551	* @arg @ref LL_DMAMUX_REQUEST_TIM17_CH1
AnnaBridge	172:65be27845400	1552	* @arg @ref LL_DMAMUX_REQUEST_TIM17_UP
AnnaBridge	172:65be27845400	1553	* @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT0
AnnaBridge	172:65be27845400	1554	* @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT1
AnnaBridge	172:65be27845400	1555	* @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT2
AnnaBridge	172:65be27845400	1556	* @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT3
AnnaBridge	172:65be27845400	1557	* @arg @ref LL_DMAMUX_REQUEST_DCMI
AnnaBridge	172:65be27845400	1558	* @arg @ref LL_DMAMUX_REQUEST_AES_IN
AnnaBridge	172:65be27845400	1559	* @arg @ref LL_DMAMUX_REQUEST_AES_OUT
AnnaBridge	172:65be27845400	1560	* @arg @ref LL_DMAMUX_REQUEST_HASH_IN
AnnaBridge	172:65be27845400	1561	*/
AnnaBridge	172:65be27845400	1562	__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	172:65be27845400	1563	{
AnnaBridge	172:65be27845400	1564	return (READ_BIT(((DMAMUX_Channel_TypeDef)((uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE(Channel-1U)) + (uint32_t)(DMAMUX_CCR_SIZE*__LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx)))))->CCR, DMAMUX_CxCR_DMAREQ_ID));
AnnaBridge	172:65be27845400	1565	}
AnnaBridge	172:65be27845400	1566	#else
AnnaBridge	172:65be27845400	1567	/**
AnnaBridge	172:65be27845400	1568	* @brief Set DMA request for DMA instance on Channel x.
AnnaBridge	172:65be27845400	1569	* @note Please refer to Reference Manual to get the available mapping of Request value link to Channel Selection.
AnnaBridge	172:65be27845400	1570	* @rmtoll CSELR C1S LL_DMA_SetPeriphRequest\n
AnnaBridge	172:65be27845400	1571	* CSELR C2S LL_DMA_SetPeriphRequest\n
AnnaBridge	172:65be27845400	1572	* CSELR C3S LL_DMA_SetPeriphRequest\n
AnnaBridge	172:65be27845400	1573	* CSELR C4S LL_DMA_SetPeriphRequest\n
AnnaBridge	172:65be27845400	1574	* CSELR C5S LL_DMA_SetPeriphRequest\n
AnnaBridge	172:65be27845400	1575	* CSELR C6S LL_DMA_SetPeriphRequest\n
AnnaBridge	172:65be27845400	1576	* CSELR C7S LL_DMA_SetPeriphRequest
AnnaBridge	172:65be27845400	1577	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1578	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1579	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	172:65be27845400	1580	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	172:65be27845400	1581	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	172:65be27845400	1582	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	172:65be27845400	1583	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	172:65be27845400	1584	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	172:65be27845400	1585	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	172:65be27845400	1586	* @param PeriphRequest This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1587	* @arg @ref LL_DMA_REQUEST_0
AnnaBridge	172:65be27845400	1588	* @arg @ref LL_DMA_REQUEST_1
AnnaBridge	172:65be27845400	1589	* @arg @ref LL_DMA_REQUEST_2
AnnaBridge	172:65be27845400	1590	* @arg @ref LL_DMA_REQUEST_3
AnnaBridge	172:65be27845400	1591	* @arg @ref LL_DMA_REQUEST_4
AnnaBridge	172:65be27845400	1592	* @arg @ref LL_DMA_REQUEST_5
AnnaBridge	172:65be27845400	1593	* @arg @ref LL_DMA_REQUEST_6
AnnaBridge	172:65be27845400	1594	* @arg @ref LL_DMA_REQUEST_7
AnnaBridge	172:65be27845400	1595	* @retval None
AnnaBridge	172:65be27845400	1596	*/
AnnaBridge	172:65be27845400	1597	__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphRequest)
AnnaBridge	172:65be27845400	1598	{
AnnaBridge	172:65be27845400	1599	MODIFY_REG(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR,
AnnaBridge	172:65be27845400	1600	DMA_CSELR_C1S << ((Channel - 1U) * 4U), PeriphRequest << DMA_POSITION_CSELR_CXS);
AnnaBridge	172:65be27845400	1601	}
AnnaBridge	172:65be27845400	1602
AnnaBridge	172:65be27845400	1603	/**
AnnaBridge	172:65be27845400	1604	* @brief Get DMA request for DMA instance on Channel x.
AnnaBridge	172:65be27845400	1605	* @rmtoll CSELR C1S LL_DMA_GetPeriphRequest\n
AnnaBridge	172:65be27845400	1606	* CSELR C2S LL_DMA_GetPeriphRequest\n
AnnaBridge	172:65be27845400	1607	* CSELR C3S LL_DMA_GetPeriphRequest\n
AnnaBridge	172:65be27845400	1608	* CSELR C4S LL_DMA_GetPeriphRequest\n
AnnaBridge	172:65be27845400	1609	* CSELR C5S LL_DMA_GetPeriphRequest\n
AnnaBridge	172:65be27845400	1610	* CSELR C6S LL_DMA_GetPeriphRequest\n
AnnaBridge	172:65be27845400	1611	* CSELR C7S LL_DMA_GetPeriphRequest
AnnaBridge	172:65be27845400	1612	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1613	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1614	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	172:65be27845400	1615	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	172:65be27845400	1616	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	172:65be27845400	1617	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	172:65be27845400	1618	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	172:65be27845400	1619	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	172:65be27845400	1620	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	172:65be27845400	1621	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1622	* @arg @ref LL_DMA_REQUEST_0
AnnaBridge	172:65be27845400	1623	* @arg @ref LL_DMA_REQUEST_1
AnnaBridge	172:65be27845400	1624	* @arg @ref LL_DMA_REQUEST_2
AnnaBridge	172:65be27845400	1625	* @arg @ref LL_DMA_REQUEST_3
AnnaBridge	172:65be27845400	1626	* @arg @ref LL_DMA_REQUEST_4
AnnaBridge	172:65be27845400	1627	* @arg @ref LL_DMA_REQUEST_5
AnnaBridge	172:65be27845400	1628	* @arg @ref LL_DMA_REQUEST_6
AnnaBridge	172:65be27845400	1629	* @arg @ref LL_DMA_REQUEST_7
AnnaBridge	172:65be27845400	1630	*/
AnnaBridge	172:65be27845400	1631	__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	172:65be27845400	1632	{
AnnaBridge	172:65be27845400	1633	return (READ_BIT(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR,
AnnaBridge	172:65be27845400	1634	DMA_CSELR_C1S << ((Channel - 1U) * 4U)) >> DMA_POSITION_CSELR_CXS);
AnnaBridge	172:65be27845400	1635	}
AnnaBridge	172:65be27845400	1636	#endif /* DMAMUX1 */
AnnaBridge	172:65be27845400	1637
AnnaBridge	172:65be27845400	1638	/**
AnnaBridge	172:65be27845400	1639	* @}
AnnaBridge	172:65be27845400	1640	*/
AnnaBridge	172:65be27845400	1641
AnnaBridge	172:65be27845400	1642	/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
AnnaBridge	172:65be27845400	1643	* @{
AnnaBridge	172:65be27845400	1644	*/
AnnaBridge	172:65be27845400	1645
AnnaBridge	172:65be27845400	1646	/**
AnnaBridge	172:65be27845400	1647	* @brief Get Channel 1 global interrupt flag.
AnnaBridge	172:65be27845400	1648	* @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
AnnaBridge	172:65be27845400	1649	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1650	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1651	*/
AnnaBridge	172:65be27845400	1652	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	1653	{
AnnaBridge	172:65be27845400	1654	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1));
AnnaBridge	172:65be27845400	1655	}
AnnaBridge	172:65be27845400	1656
AnnaBridge	172:65be27845400	1657	/**
AnnaBridge	172:65be27845400	1658	* @brief Get Channel 2 global interrupt flag.
AnnaBridge	172:65be27845400	1659	* @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
AnnaBridge	172:65be27845400	1660	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1661	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1662	*/
AnnaBridge	172:65be27845400	1663	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	1664	{
AnnaBridge	172:65be27845400	1665	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2));
AnnaBridge	172:65be27845400	1666	}
AnnaBridge	172:65be27845400	1667
AnnaBridge	172:65be27845400	1668	/**
AnnaBridge	172:65be27845400	1669	* @brief Get Channel 3 global interrupt flag.
AnnaBridge	172:65be27845400	1670	* @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
AnnaBridge	172:65be27845400	1671	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1672	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1673	*/
AnnaBridge	172:65be27845400	1674	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	1675	{
AnnaBridge	172:65be27845400	1676	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3));
AnnaBridge	172:65be27845400	1677	}
AnnaBridge	172:65be27845400	1678
AnnaBridge	172:65be27845400	1679	/**
AnnaBridge	172:65be27845400	1680	* @brief Get Channel 4 global interrupt flag.
AnnaBridge	172:65be27845400	1681	* @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
AnnaBridge	172:65be27845400	1682	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1683	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1684	*/
AnnaBridge	172:65be27845400	1685	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	1686	{
AnnaBridge	172:65be27845400	1687	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4));
AnnaBridge	172:65be27845400	1688	}
AnnaBridge	172:65be27845400	1689
AnnaBridge	172:65be27845400	1690	/**
AnnaBridge	172:65be27845400	1691	* @brief Get Channel 5 global interrupt flag.
AnnaBridge	172:65be27845400	1692	* @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
AnnaBridge	172:65be27845400	1693	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1694	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1695	*/
AnnaBridge	172:65be27845400	1696	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	1697	{
AnnaBridge	172:65be27845400	1698	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5));
AnnaBridge	172:65be27845400	1699	}
AnnaBridge	172:65be27845400	1700
AnnaBridge	172:65be27845400	1701	/**
AnnaBridge	172:65be27845400	1702	* @brief Get Channel 6 global interrupt flag.
AnnaBridge	172:65be27845400	1703	* @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
AnnaBridge	172:65be27845400	1704	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1705	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1706	*/
AnnaBridge	172:65be27845400	1707	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	1708	{
AnnaBridge	172:65be27845400	1709	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6));
AnnaBridge	172:65be27845400	1710	}
AnnaBridge	172:65be27845400	1711
AnnaBridge	172:65be27845400	1712	/**
AnnaBridge	172:65be27845400	1713	* @brief Get Channel 7 global interrupt flag.
AnnaBridge	172:65be27845400	1714	* @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
AnnaBridge	172:65be27845400	1715	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1716	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1717	*/
AnnaBridge	172:65be27845400	1718	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	1719	{
AnnaBridge	172:65be27845400	1720	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7));
AnnaBridge	172:65be27845400	1721	}
AnnaBridge	172:65be27845400	1722
AnnaBridge	172:65be27845400	1723	/**
AnnaBridge	172:65be27845400	1724	* @brief Get Channel 1 transfer complete flag.
AnnaBridge	172:65be27845400	1725	* @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
AnnaBridge	172:65be27845400	1726	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1727	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1728	*/
AnnaBridge	172:65be27845400	1729	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	1730	{
AnnaBridge	172:65be27845400	1731	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1));
AnnaBridge	172:65be27845400	1732	}
AnnaBridge	172:65be27845400	1733
AnnaBridge	172:65be27845400	1734	/**
AnnaBridge	172:65be27845400	1735	* @brief Get Channel 2 transfer complete flag.
AnnaBridge	172:65be27845400	1736	* @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
AnnaBridge	172:65be27845400	1737	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1738	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1739	*/
AnnaBridge	172:65be27845400	1740	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	1741	{
AnnaBridge	172:65be27845400	1742	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2));
AnnaBridge	172:65be27845400	1743	}
AnnaBridge	172:65be27845400	1744
AnnaBridge	172:65be27845400	1745	/**
AnnaBridge	172:65be27845400	1746	* @brief Get Channel 3 transfer complete flag.
AnnaBridge	172:65be27845400	1747	* @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
AnnaBridge	172:65be27845400	1748	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1749	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1750	*/
AnnaBridge	172:65be27845400	1751	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	1752	{
AnnaBridge	172:65be27845400	1753	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3));
AnnaBridge	172:65be27845400	1754	}
AnnaBridge	172:65be27845400	1755
AnnaBridge	172:65be27845400	1756	/**
AnnaBridge	172:65be27845400	1757	* @brief Get Channel 4 transfer complete flag.
AnnaBridge	172:65be27845400	1758	* @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
AnnaBridge	172:65be27845400	1759	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1760	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1761	*/
AnnaBridge	172:65be27845400	1762	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	1763	{
AnnaBridge	172:65be27845400	1764	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4));
AnnaBridge	172:65be27845400	1765	}
AnnaBridge	172:65be27845400	1766
AnnaBridge	172:65be27845400	1767	/**
AnnaBridge	172:65be27845400	1768	* @brief Get Channel 5 transfer complete flag.
AnnaBridge	172:65be27845400	1769	* @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
AnnaBridge	172:65be27845400	1770	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1771	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1772	*/
AnnaBridge	172:65be27845400	1773	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	1774	{
AnnaBridge	172:65be27845400	1775	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5));
AnnaBridge	172:65be27845400	1776	}
AnnaBridge	172:65be27845400	1777
AnnaBridge	172:65be27845400	1778	/**
AnnaBridge	172:65be27845400	1779	* @brief Get Channel 6 transfer complete flag.
AnnaBridge	172:65be27845400	1780	* @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
AnnaBridge	172:65be27845400	1781	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1782	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1783	*/
AnnaBridge	172:65be27845400	1784	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	1785	{
AnnaBridge	172:65be27845400	1786	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6));
AnnaBridge	172:65be27845400	1787	}
AnnaBridge	172:65be27845400	1788
AnnaBridge	172:65be27845400	1789	/**
AnnaBridge	172:65be27845400	1790	* @brief Get Channel 7 transfer complete flag.
AnnaBridge	172:65be27845400	1791	* @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
AnnaBridge	172:65be27845400	1792	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1793	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1794	*/
AnnaBridge	172:65be27845400	1795	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	1796	{
AnnaBridge	172:65be27845400	1797	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7));
AnnaBridge	172:65be27845400	1798	}
AnnaBridge	172:65be27845400	1799
AnnaBridge	172:65be27845400	1800	/**
AnnaBridge	172:65be27845400	1801	* @brief Get Channel 1 half transfer flag.
AnnaBridge	172:65be27845400	1802	* @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
AnnaBridge	172:65be27845400	1803	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1804	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1805	*/
AnnaBridge	172:65be27845400	1806	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	1807	{
AnnaBridge	172:65be27845400	1808	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1));
AnnaBridge	172:65be27845400	1809	}
AnnaBridge	172:65be27845400	1810
AnnaBridge	172:65be27845400	1811	/**
AnnaBridge	172:65be27845400	1812	* @brief Get Channel 2 half transfer flag.
AnnaBridge	172:65be27845400	1813	* @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
AnnaBridge	172:65be27845400	1814	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1815	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1816	*/
AnnaBridge	172:65be27845400	1817	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	1818	{
AnnaBridge	172:65be27845400	1819	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2));
AnnaBridge	172:65be27845400	1820	}
AnnaBridge	172:65be27845400	1821
AnnaBridge	172:65be27845400	1822	/**
AnnaBridge	172:65be27845400	1823	* @brief Get Channel 3 half transfer flag.
AnnaBridge	172:65be27845400	1824	* @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
AnnaBridge	172:65be27845400	1825	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1826	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1827	*/
AnnaBridge	172:65be27845400	1828	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	1829	{
AnnaBridge	172:65be27845400	1830	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3));
AnnaBridge	172:65be27845400	1831	}
AnnaBridge	172:65be27845400	1832
AnnaBridge	172:65be27845400	1833	/**
AnnaBridge	172:65be27845400	1834	* @brief Get Channel 4 half transfer flag.
AnnaBridge	172:65be27845400	1835	* @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
AnnaBridge	172:65be27845400	1836	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1837	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1838	*/
AnnaBridge	172:65be27845400	1839	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	1840	{
AnnaBridge	172:65be27845400	1841	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4));
AnnaBridge	172:65be27845400	1842	}
AnnaBridge	172:65be27845400	1843
AnnaBridge	172:65be27845400	1844	/**
AnnaBridge	172:65be27845400	1845	* @brief Get Channel 5 half transfer flag.
AnnaBridge	172:65be27845400	1846	* @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
AnnaBridge	172:65be27845400	1847	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1848	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1849	*/
AnnaBridge	172:65be27845400	1850	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	1851	{
AnnaBridge	172:65be27845400	1852	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5));
AnnaBridge	172:65be27845400	1853	}
AnnaBridge	172:65be27845400	1854
AnnaBridge	172:65be27845400	1855	/**
AnnaBridge	172:65be27845400	1856	* @brief Get Channel 6 half transfer flag.
AnnaBridge	172:65be27845400	1857	* @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
AnnaBridge	172:65be27845400	1858	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1859	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1860	*/
AnnaBridge	172:65be27845400	1861	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	1862	{
AnnaBridge	172:65be27845400	1863	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6));
AnnaBridge	172:65be27845400	1864	}
AnnaBridge	172:65be27845400	1865
AnnaBridge	172:65be27845400	1866	/**
AnnaBridge	172:65be27845400	1867	* @brief Get Channel 7 half transfer flag.
AnnaBridge	172:65be27845400	1868	* @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
AnnaBridge	172:65be27845400	1869	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1870	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1871	*/
AnnaBridge	172:65be27845400	1872	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	1873	{
AnnaBridge	172:65be27845400	1874	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7));
AnnaBridge	172:65be27845400	1875	}
AnnaBridge	172:65be27845400	1876
AnnaBridge	172:65be27845400	1877	/**
AnnaBridge	172:65be27845400	1878	* @brief Get Channel 1 transfer error flag.
AnnaBridge	172:65be27845400	1879	* @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
AnnaBridge	172:65be27845400	1880	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1881	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1882	*/
AnnaBridge	172:65be27845400	1883	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	1884	{
AnnaBridge	172:65be27845400	1885	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1));
AnnaBridge	172:65be27845400	1886	}
AnnaBridge	172:65be27845400	1887
AnnaBridge	172:65be27845400	1888	/**
AnnaBridge	172:65be27845400	1889	* @brief Get Channel 2 transfer error flag.
AnnaBridge	172:65be27845400	1890	* @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
AnnaBridge	172:65be27845400	1891	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1892	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1893	*/
AnnaBridge	172:65be27845400	1894	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	1895	{
AnnaBridge	172:65be27845400	1896	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2));
AnnaBridge	172:65be27845400	1897	}
AnnaBridge	172:65be27845400	1898
AnnaBridge	172:65be27845400	1899	/**
AnnaBridge	172:65be27845400	1900	* @brief Get Channel 3 transfer error flag.
AnnaBridge	172:65be27845400	1901	* @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
AnnaBridge	172:65be27845400	1902	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1903	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1904	*/
AnnaBridge	172:65be27845400	1905	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	1906	{
AnnaBridge	172:65be27845400	1907	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3));
AnnaBridge	172:65be27845400	1908	}
AnnaBridge	172:65be27845400	1909
AnnaBridge	172:65be27845400	1910	/**
AnnaBridge	172:65be27845400	1911	* @brief Get Channel 4 transfer error flag.
AnnaBridge	172:65be27845400	1912	* @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
AnnaBridge	172:65be27845400	1913	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1914	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1915	*/
AnnaBridge	172:65be27845400	1916	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	1917	{
AnnaBridge	172:65be27845400	1918	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4));
AnnaBridge	172:65be27845400	1919	}
AnnaBridge	172:65be27845400	1920
AnnaBridge	172:65be27845400	1921	/**
AnnaBridge	172:65be27845400	1922	* @brief Get Channel 5 transfer error flag.
AnnaBridge	172:65be27845400	1923	* @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
AnnaBridge	172:65be27845400	1924	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1925	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1926	*/
AnnaBridge	172:65be27845400	1927	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	1928	{
AnnaBridge	172:65be27845400	1929	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5));
AnnaBridge	172:65be27845400	1930	}
AnnaBridge	172:65be27845400	1931
AnnaBridge	172:65be27845400	1932	/**
AnnaBridge	172:65be27845400	1933	* @brief Get Channel 6 transfer error flag.
AnnaBridge	172:65be27845400	1934	* @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
AnnaBridge	172:65be27845400	1935	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1936	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1937	*/
AnnaBridge	172:65be27845400	1938	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	1939	{
AnnaBridge	172:65be27845400	1940	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6));
AnnaBridge	172:65be27845400	1941	}
AnnaBridge	172:65be27845400	1942
AnnaBridge	172:65be27845400	1943	/**
AnnaBridge	172:65be27845400	1944	* @brief Get Channel 7 transfer error flag.
AnnaBridge	172:65be27845400	1945	* @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
AnnaBridge	172:65be27845400	1946	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1947	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1948	*/
AnnaBridge	172:65be27845400	1949	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	1950	{
AnnaBridge	172:65be27845400	1951	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7));
AnnaBridge	172:65be27845400	1952	}
AnnaBridge	172:65be27845400	1953
AnnaBridge	172:65be27845400	1954	/**
AnnaBridge	172:65be27845400	1955	* @brief Clear Channel 1 global interrupt flag.
AnnaBridge	172:65be27845400	1956	* @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
AnnaBridge	172:65be27845400	1957	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1958	* @retval None
AnnaBridge	172:65be27845400	1959	*/
AnnaBridge	172:65be27845400	1960	__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	1961	{
AnnaBridge	172:65be27845400	1962	WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
AnnaBridge	172:65be27845400	1963	}
AnnaBridge	172:65be27845400	1964
AnnaBridge	172:65be27845400	1965	/**
AnnaBridge	172:65be27845400	1966	* @brief Clear Channel 2 global interrupt flag.
AnnaBridge	172:65be27845400	1967	* @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
AnnaBridge	172:65be27845400	1968	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1969	* @retval None
AnnaBridge	172:65be27845400	1970	*/
AnnaBridge	172:65be27845400	1971	__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	1972	{
AnnaBridge	172:65be27845400	1973	WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
AnnaBridge	172:65be27845400	1974	}
AnnaBridge	172:65be27845400	1975
AnnaBridge	172:65be27845400	1976	/**
AnnaBridge	172:65be27845400	1977	* @brief Clear Channel 3 global interrupt flag.
AnnaBridge	172:65be27845400	1978	* @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
AnnaBridge	172:65be27845400	1979	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1980	* @retval None
AnnaBridge	172:65be27845400	1981	*/
AnnaBridge	172:65be27845400	1982	__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	1983	{
AnnaBridge	172:65be27845400	1984	WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
AnnaBridge	172:65be27845400	1985	}
AnnaBridge	172:65be27845400	1986
AnnaBridge	172:65be27845400	1987	/**
AnnaBridge	172:65be27845400	1988	* @brief Clear Channel 4 global interrupt flag.
AnnaBridge	172:65be27845400	1989	* @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
AnnaBridge	172:65be27845400	1990	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1991	* @retval None
AnnaBridge	172:65be27845400	1992	*/
AnnaBridge	172:65be27845400	1993	__STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	1994	{
AnnaBridge	172:65be27845400	1995	WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
AnnaBridge	172:65be27845400	1996	}
AnnaBridge	172:65be27845400	1997
AnnaBridge	172:65be27845400	1998	/**
AnnaBridge	172:65be27845400	1999	* @brief Clear Channel 5 global interrupt flag.
AnnaBridge	172:65be27845400	2000	* @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
AnnaBridge	172:65be27845400	2001	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2002	* @retval None
AnnaBridge	172:65be27845400	2003	*/
AnnaBridge	172:65be27845400	2004	__STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2005	{
AnnaBridge	172:65be27845400	2006	WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
AnnaBridge	172:65be27845400	2007	}
AnnaBridge	172:65be27845400	2008
AnnaBridge	172:65be27845400	2009	/**
AnnaBridge	172:65be27845400	2010	* @brief Clear Channel 6 global interrupt flag.
AnnaBridge	172:65be27845400	2011	* @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
AnnaBridge	172:65be27845400	2012	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2013	* @retval None
AnnaBridge	172:65be27845400	2014	*/
AnnaBridge	172:65be27845400	2015	__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2016	{
AnnaBridge	172:65be27845400	2017	WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
AnnaBridge	172:65be27845400	2018	}
AnnaBridge	172:65be27845400	2019
AnnaBridge	172:65be27845400	2020	/**
AnnaBridge	172:65be27845400	2021	* @brief Clear Channel 7 global interrupt flag.
AnnaBridge	172:65be27845400	2022	* @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
AnnaBridge	172:65be27845400	2023	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2024	* @retval None
AnnaBridge	172:65be27845400	2025	*/
AnnaBridge	172:65be27845400	2026	__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2027	{
AnnaBridge	172:65be27845400	2028	WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
AnnaBridge	172:65be27845400	2029	}
AnnaBridge	172:65be27845400	2030
AnnaBridge	172:65be27845400	2031	/**
AnnaBridge	172:65be27845400	2032	* @brief Clear Channel 1 transfer complete flag.
AnnaBridge	172:65be27845400	2033	* @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
AnnaBridge	172:65be27845400	2034	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2035	* @retval None
AnnaBridge	172:65be27845400	2036	*/
AnnaBridge	172:65be27845400	2037	__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2038	{
AnnaBridge	172:65be27845400	2039	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
AnnaBridge	172:65be27845400	2040	}
AnnaBridge	172:65be27845400	2041
AnnaBridge	172:65be27845400	2042	/**
AnnaBridge	172:65be27845400	2043	* @brief Clear Channel 2 transfer complete flag.
AnnaBridge	172:65be27845400	2044	* @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
AnnaBridge	172:65be27845400	2045	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2046	* @retval None
AnnaBridge	172:65be27845400	2047	*/
AnnaBridge	172:65be27845400	2048	__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2049	{
AnnaBridge	172:65be27845400	2050	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
AnnaBridge	172:65be27845400	2051	}
AnnaBridge	172:65be27845400	2052
AnnaBridge	172:65be27845400	2053	/**
AnnaBridge	172:65be27845400	2054	* @brief Clear Channel 3 transfer complete flag.
AnnaBridge	172:65be27845400	2055	* @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
AnnaBridge	172:65be27845400	2056	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2057	* @retval None
AnnaBridge	172:65be27845400	2058	*/
AnnaBridge	172:65be27845400	2059	__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2060	{
AnnaBridge	172:65be27845400	2061	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
AnnaBridge	172:65be27845400	2062	}
AnnaBridge	172:65be27845400	2063
AnnaBridge	172:65be27845400	2064	/**
AnnaBridge	172:65be27845400	2065	* @brief Clear Channel 4 transfer complete flag.
AnnaBridge	172:65be27845400	2066	* @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
AnnaBridge	172:65be27845400	2067	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2068	* @retval None
AnnaBridge	172:65be27845400	2069	*/
AnnaBridge	172:65be27845400	2070	__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2071	{
AnnaBridge	172:65be27845400	2072	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
AnnaBridge	172:65be27845400	2073	}
AnnaBridge	172:65be27845400	2074
AnnaBridge	172:65be27845400	2075	/**
AnnaBridge	172:65be27845400	2076	* @brief Clear Channel 5 transfer complete flag.
AnnaBridge	172:65be27845400	2077	* @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
AnnaBridge	172:65be27845400	2078	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2079	* @retval None
AnnaBridge	172:65be27845400	2080	*/
AnnaBridge	172:65be27845400	2081	__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2082	{
AnnaBridge	172:65be27845400	2083	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
AnnaBridge	172:65be27845400	2084	}
AnnaBridge	172:65be27845400	2085
AnnaBridge	172:65be27845400	2086	/**
AnnaBridge	172:65be27845400	2087	* @brief Clear Channel 6 transfer complete flag.
AnnaBridge	172:65be27845400	2088	* @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
AnnaBridge	172:65be27845400	2089	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2090	* @retval None
AnnaBridge	172:65be27845400	2091	*/
AnnaBridge	172:65be27845400	2092	__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2093	{
AnnaBridge	172:65be27845400	2094	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
AnnaBridge	172:65be27845400	2095	}
AnnaBridge	172:65be27845400	2096
AnnaBridge	172:65be27845400	2097	/**
AnnaBridge	172:65be27845400	2098	* @brief Clear Channel 7 transfer complete flag.
AnnaBridge	172:65be27845400	2099	* @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
AnnaBridge	172:65be27845400	2100	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2101	* @retval None
AnnaBridge	172:65be27845400	2102	*/
AnnaBridge	172:65be27845400	2103	__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2104	{
AnnaBridge	172:65be27845400	2105	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
AnnaBridge	172:65be27845400	2106	}
AnnaBridge	172:65be27845400	2107
AnnaBridge	172:65be27845400	2108	/**
AnnaBridge	172:65be27845400	2109	* @brief Clear Channel 1 half transfer flag.
AnnaBridge	172:65be27845400	2110	* @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
AnnaBridge	172:65be27845400	2111	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2112	* @retval None
AnnaBridge	172:65be27845400	2113	*/
AnnaBridge	172:65be27845400	2114	__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2115	{
AnnaBridge	172:65be27845400	2116	WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
AnnaBridge	172:65be27845400	2117	}
AnnaBridge	172:65be27845400	2118
AnnaBridge	172:65be27845400	2119	/**
AnnaBridge	172:65be27845400	2120	* @brief Clear Channel 2 half transfer flag.
AnnaBridge	172:65be27845400	2121	* @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
AnnaBridge	172:65be27845400	2122	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2123	* @retval None
AnnaBridge	172:65be27845400	2124	*/
AnnaBridge	172:65be27845400	2125	__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2126	{
AnnaBridge	172:65be27845400	2127	WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
AnnaBridge	172:65be27845400	2128	}
AnnaBridge	172:65be27845400	2129
AnnaBridge	172:65be27845400	2130	/**
AnnaBridge	172:65be27845400	2131	* @brief Clear Channel 3 half transfer flag.
AnnaBridge	172:65be27845400	2132	* @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
AnnaBridge	172:65be27845400	2133	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2134	* @retval None
AnnaBridge	172:65be27845400	2135	*/
AnnaBridge	172:65be27845400	2136	__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2137	{
AnnaBridge	172:65be27845400	2138	WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
AnnaBridge	172:65be27845400	2139	}
AnnaBridge	172:65be27845400	2140
AnnaBridge	172:65be27845400	2141	/**
AnnaBridge	172:65be27845400	2142	* @brief Clear Channel 4 half transfer flag.
AnnaBridge	172:65be27845400	2143	* @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
AnnaBridge	172:65be27845400	2144	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2145	* @retval None
AnnaBridge	172:65be27845400	2146	*/
AnnaBridge	172:65be27845400	2147	__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2148	{
AnnaBridge	172:65be27845400	2149	WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
AnnaBridge	172:65be27845400	2150	}
AnnaBridge	172:65be27845400	2151
AnnaBridge	172:65be27845400	2152	/**
AnnaBridge	172:65be27845400	2153	* @brief Clear Channel 5 half transfer flag.
AnnaBridge	172:65be27845400	2154	* @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
AnnaBridge	172:65be27845400	2155	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2156	* @retval None
AnnaBridge	172:65be27845400	2157	*/
AnnaBridge	172:65be27845400	2158	__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2159	{
AnnaBridge	172:65be27845400	2160	WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
AnnaBridge	172:65be27845400	2161	}
AnnaBridge	172:65be27845400	2162
AnnaBridge	172:65be27845400	2163	/**
AnnaBridge	172:65be27845400	2164	* @brief Clear Channel 6 half transfer flag.
AnnaBridge	172:65be27845400	2165	* @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
AnnaBridge	172:65be27845400	2166	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2167	* @retval None
AnnaBridge	172:65be27845400	2168	*/
AnnaBridge	172:65be27845400	2169	__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2170	{
AnnaBridge	172:65be27845400	2171	WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
AnnaBridge	172:65be27845400	2172	}
AnnaBridge	172:65be27845400	2173
AnnaBridge	172:65be27845400	2174	/**
AnnaBridge	172:65be27845400	2175	* @brief Clear Channel 7 half transfer flag.
AnnaBridge	172:65be27845400	2176	* @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
AnnaBridge	172:65be27845400	2177	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2178	* @retval None
AnnaBridge	172:65be27845400	2179	*/
AnnaBridge	172:65be27845400	2180	__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2181	{
AnnaBridge	172:65be27845400	2182	WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
AnnaBridge	172:65be27845400	2183	}
AnnaBridge	172:65be27845400	2184
AnnaBridge	172:65be27845400	2185	/**
AnnaBridge	172:65be27845400	2186	* @brief Clear Channel 1 transfer error flag.
AnnaBridge	172:65be27845400	2187	* @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
AnnaBridge	172:65be27845400	2188	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2189	* @retval None
AnnaBridge	172:65be27845400	2190	*/
AnnaBridge	172:65be27845400	2191	__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2192	{
AnnaBridge	172:65be27845400	2193	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
AnnaBridge	172:65be27845400	2194	}
AnnaBridge	172:65be27845400	2195
AnnaBridge	172:65be27845400	2196	/**
AnnaBridge	172:65be27845400	2197	* @brief Clear Channel 2 transfer error flag.
AnnaBridge	172:65be27845400	2198	* @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
AnnaBridge	172:65be27845400	2199	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2200	* @retval None
AnnaBridge	172:65be27845400	2201	*/
AnnaBridge	172:65be27845400	2202	__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2203	{
AnnaBridge	172:65be27845400	2204	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
AnnaBridge	172:65be27845400	2205	}
AnnaBridge	172:65be27845400	2206
AnnaBridge	172:65be27845400	2207	/**
AnnaBridge	172:65be27845400	2208	* @brief Clear Channel 3 transfer error flag.
AnnaBridge	172:65be27845400	2209	* @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
AnnaBridge	172:65be27845400	2210	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2211	* @retval None
AnnaBridge	172:65be27845400	2212	*/
AnnaBridge	172:65be27845400	2213	__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2214	{
AnnaBridge	172:65be27845400	2215	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
AnnaBridge	172:65be27845400	2216	}
AnnaBridge	172:65be27845400	2217
AnnaBridge	172:65be27845400	2218	/**
AnnaBridge	172:65be27845400	2219	* @brief Clear Channel 4 transfer error flag.
AnnaBridge	172:65be27845400	2220	* @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
AnnaBridge	172:65be27845400	2221	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2222	* @retval None
AnnaBridge	172:65be27845400	2223	*/
AnnaBridge	172:65be27845400	2224	__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2225	{
AnnaBridge	172:65be27845400	2226	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
AnnaBridge	172:65be27845400	2227	}
AnnaBridge	172:65be27845400	2228
AnnaBridge	172:65be27845400	2229	/**
AnnaBridge	172:65be27845400	2230	* @brief Clear Channel 5 transfer error flag.
AnnaBridge	172:65be27845400	2231	* @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
AnnaBridge	172:65be27845400	2232	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2233	* @retval None
AnnaBridge	172:65be27845400	2234	*/
AnnaBridge	172:65be27845400	2235	__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2236	{
AnnaBridge	172:65be27845400	2237	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
AnnaBridge	172:65be27845400	2238	}
AnnaBridge	172:65be27845400	2239
AnnaBridge	172:65be27845400	2240	/**
AnnaBridge	172:65be27845400	2241	* @brief Clear Channel 6 transfer error flag.
AnnaBridge	172:65be27845400	2242	* @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
AnnaBridge	172:65be27845400	2243	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2244	* @retval None
AnnaBridge	172:65be27845400	2245	*/
AnnaBridge	172:65be27845400	2246	__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2247	{
AnnaBridge	172:65be27845400	2248	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
AnnaBridge	172:65be27845400	2249	}
AnnaBridge	172:65be27845400	2250
AnnaBridge	172:65be27845400	2251	/**
AnnaBridge	172:65be27845400	2252	* @brief Clear Channel 7 transfer error flag.
AnnaBridge	172:65be27845400	2253	* @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
AnnaBridge	172:65be27845400	2254	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2255	* @retval None
AnnaBridge	172:65be27845400	2256	*/
AnnaBridge	172:65be27845400	2257	__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2258	{
AnnaBridge	172:65be27845400	2259	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
AnnaBridge	172:65be27845400	2260	}
AnnaBridge	172:65be27845400	2261
AnnaBridge	172:65be27845400	2262	/**
AnnaBridge	172:65be27845400	2263	* @}
AnnaBridge	172:65be27845400	2264	*/
AnnaBridge	172:65be27845400	2265
AnnaBridge	172:65be27845400	2266	/** @defgroup DMA_LL_EF_IT_Management IT_Management
AnnaBridge	172:65be27845400	2267	* @{
AnnaBridge	172:65be27845400	2268	*/
AnnaBridge	172:65be27845400	2269	/**
AnnaBridge	172:65be27845400	2270	* @brief Enable Transfer complete interrupt.
AnnaBridge	172:65be27845400	2271	* @rmtoll CCR TCIE LL_DMA_EnableIT_TC
AnnaBridge	172:65be27845400	2272	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2273	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2274	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	172:65be27845400	2275	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	172:65be27845400	2276	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	172:65be27845400	2277	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	172:65be27845400	2278	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	172:65be27845400	2279	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	172:65be27845400	2280	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	172:65be27845400	2281	* @retval None
AnnaBridge	172:65be27845400	2282	*/
AnnaBridge	172:65be27845400	2283	__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	172:65be27845400	2284	{
AnnaBridge	172:65be27845400	2285	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
AnnaBridge	172:65be27845400	2286	}
AnnaBridge	172:65be27845400	2287
AnnaBridge	172:65be27845400	2288	/**
AnnaBridge	172:65be27845400	2289	* @brief Enable Half transfer interrupt.
AnnaBridge	172:65be27845400	2290	* @rmtoll CCR HTIE LL_DMA_EnableIT_HT
AnnaBridge	172:65be27845400	2291	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2292	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2293	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	172:65be27845400	2294	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	172:65be27845400	2295	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	172:65be27845400	2296	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	172:65be27845400	2297	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	172:65be27845400	2298	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	172:65be27845400	2299	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	172:65be27845400	2300	* @retval None
AnnaBridge	172:65be27845400	2301	*/
AnnaBridge	172:65be27845400	2302	__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	172:65be27845400	2303	{
AnnaBridge	172:65be27845400	2304	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
AnnaBridge	172:65be27845400	2305	}
AnnaBridge	172:65be27845400	2306
AnnaBridge	172:65be27845400	2307	/**
AnnaBridge	172:65be27845400	2308	* @brief Enable Transfer error interrupt.
AnnaBridge	172:65be27845400	2309	* @rmtoll CCR TEIE LL_DMA_EnableIT_TE
AnnaBridge	172:65be27845400	2310	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2311	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2312	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	172:65be27845400	2313	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	172:65be27845400	2314	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	172:65be27845400	2315	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	172:65be27845400	2316	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	172:65be27845400	2317	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	172:65be27845400	2318	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	172:65be27845400	2319	* @retval None
AnnaBridge	172:65be27845400	2320	*/
AnnaBridge	172:65be27845400	2321	__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	172:65be27845400	2322	{
AnnaBridge	172:65be27845400	2323	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
AnnaBridge	172:65be27845400	2324	}
AnnaBridge	172:65be27845400	2325
AnnaBridge	172:65be27845400	2326	/**
AnnaBridge	172:65be27845400	2327	* @brief Disable Transfer complete interrupt.
AnnaBridge	172:65be27845400	2328	* @rmtoll CCR TCIE LL_DMA_DisableIT_TC
AnnaBridge	172:65be27845400	2329	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2330	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2331	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	172:65be27845400	2332	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	172:65be27845400	2333	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	172:65be27845400	2334	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	172:65be27845400	2335	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	172:65be27845400	2336	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	172:65be27845400	2337	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	172:65be27845400	2338	* @retval None
AnnaBridge	172:65be27845400	2339	*/
AnnaBridge	172:65be27845400	2340	__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	172:65be27845400	2341	{
AnnaBridge	172:65be27845400	2342	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
AnnaBridge	172:65be27845400	2343	}
AnnaBridge	172:65be27845400	2344
AnnaBridge	172:65be27845400	2345	/**
AnnaBridge	172:65be27845400	2346	* @brief Disable Half transfer interrupt.
AnnaBridge	172:65be27845400	2347	* @rmtoll CCR HTIE LL_DMA_DisableIT_HT
AnnaBridge	172:65be27845400	2348	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2349	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2350	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	172:65be27845400	2351	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	172:65be27845400	2352	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	172:65be27845400	2353	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	172:65be27845400	2354	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	172:65be27845400	2355	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	172:65be27845400	2356	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	172:65be27845400	2357	* @retval None
AnnaBridge	172:65be27845400	2358	*/
AnnaBridge	172:65be27845400	2359	__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	172:65be27845400	2360	{
AnnaBridge	172:65be27845400	2361	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
AnnaBridge	172:65be27845400	2362	}
AnnaBridge	172:65be27845400	2363
AnnaBridge	172:65be27845400	2364	/**
AnnaBridge	172:65be27845400	2365	* @brief Disable Transfer error interrupt.
AnnaBridge	172:65be27845400	2366	* @rmtoll CCR TEIE LL_DMA_DisableIT_TE
AnnaBridge	172:65be27845400	2367	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2368	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2369	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	172:65be27845400	2370	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	172:65be27845400	2371	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	172:65be27845400	2372	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	172:65be27845400	2373	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	172:65be27845400	2374	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	172:65be27845400	2375	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	172:65be27845400	2376	* @retval None
AnnaBridge	172:65be27845400	2377	*/
AnnaBridge	172:65be27845400	2378	__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	172:65be27845400	2379	{
AnnaBridge	172:65be27845400	2380	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
AnnaBridge	172:65be27845400	2381	}
AnnaBridge	172:65be27845400	2382
AnnaBridge	172:65be27845400	2383	/**
AnnaBridge	172:65be27845400	2384	* @brief Check if Transfer complete Interrupt is enabled.
AnnaBridge	172:65be27845400	2385	* @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
AnnaBridge	172:65be27845400	2386	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2387	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2388	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	172:65be27845400	2389	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	172:65be27845400	2390	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	172:65be27845400	2391	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	172:65be27845400	2392	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	172:65be27845400	2393	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	172:65be27845400	2394	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	172:65be27845400	2395	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	2396	*/
AnnaBridge	172:65be27845400	2397	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	172:65be27845400	2398	{
AnnaBridge	172:65be27845400	2399	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	172:65be27845400	2400	DMA_CCR_TCIE) == (DMA_CCR_TCIE));
AnnaBridge	172:65be27845400	2401	}
AnnaBridge	172:65be27845400	2402
AnnaBridge	172:65be27845400	2403	/**
AnnaBridge	172:65be27845400	2404	* @brief Check if Half transfer Interrupt is enabled.
AnnaBridge	172:65be27845400	2405	* @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
AnnaBridge	172:65be27845400	2406	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2407	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2408	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	172:65be27845400	2409	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	172:65be27845400	2410	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	172:65be27845400	2411	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	172:65be27845400	2412	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	172:65be27845400	2413	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	172:65be27845400	2414	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	172:65be27845400	2415	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	2416	*/
AnnaBridge	172:65be27845400	2417	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	172:65be27845400	2418	{
AnnaBridge	172:65be27845400	2419	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	172:65be27845400	2420	DMA_CCR_HTIE) == (DMA_CCR_HTIE));
AnnaBridge	172:65be27845400	2421	}
AnnaBridge	172:65be27845400	2422
AnnaBridge	172:65be27845400	2423	/**
AnnaBridge	172:65be27845400	2424	* @brief Check if Transfer error Interrupt is enabled.
AnnaBridge	172:65be27845400	2425	* @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
AnnaBridge	172:65be27845400	2426	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2427	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2428	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	172:65be27845400	2429	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	172:65be27845400	2430	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	172:65be27845400	2431	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	172:65be27845400	2432	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	172:65be27845400	2433	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	172:65be27845400	2434	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	172:65be27845400	2435	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	2436	*/
AnnaBridge	172:65be27845400	2437	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	172:65be27845400	2438	{
AnnaBridge	172:65be27845400	2439	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	172:65be27845400	2440	DMA_CCR_TEIE) == (DMA_CCR_TEIE));
AnnaBridge	172:65be27845400	2441	}
AnnaBridge	172:65be27845400	2442
AnnaBridge	172:65be27845400	2443	/**
AnnaBridge	172:65be27845400	2444	* @}
AnnaBridge	172:65be27845400	2445	*/
AnnaBridge	172:65be27845400	2446
AnnaBridge	172:65be27845400	2447	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	172:65be27845400	2448	/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
AnnaBridge	172:65be27845400	2449	* @{
AnnaBridge	172:65be27845400	2450	*/
AnnaBridge	172:65be27845400	2451
AnnaBridge	172:65be27845400	2452	uint32_t LL_DMA_Init(DMA_TypeDef DMAx, uint32_t Channel, LL_DMA_InitTypeDef DMA_InitStruct);
AnnaBridge	172:65be27845400	2453	uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
AnnaBridge	172:65be27845400	2454	void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
AnnaBridge	172:65be27845400	2455
AnnaBridge	172:65be27845400	2456	/**
AnnaBridge	172:65be27845400	2457	* @}
AnnaBridge	172:65be27845400	2458	*/
AnnaBridge	172:65be27845400	2459	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	172:65be27845400	2460
AnnaBridge	172:65be27845400	2461	/**
AnnaBridge	172:65be27845400	2462	* @}
AnnaBridge	172:65be27845400	2463	*/
AnnaBridge	172:65be27845400	2464
AnnaBridge	172:65be27845400	2465	/**
AnnaBridge	172:65be27845400	2466	* @}
AnnaBridge	172:65be27845400	2467	*/
AnnaBridge	172:65be27845400	2468
AnnaBridge	172:65be27845400	2469	#endif /* DMA1 \|\| DMA2 */
AnnaBridge	172:65be27845400	2470
AnnaBridge	172:65be27845400	2471	/**
AnnaBridge	172:65be27845400	2472	* @}
AnnaBridge	172:65be27845400	2473	*/
AnnaBridge	172:65be27845400	2474
AnnaBridge	172:65be27845400	2475	#ifdef __cplusplus
AnnaBridge	172:65be27845400	2476	}
AnnaBridge	172:65be27845400	2477	#endif
AnnaBridge	172:65be27845400	2478
AnnaBridge	172:65be27845400	2479	#endif /* __STM32L4xx_LL_DMA_H */
AnnaBridge	172:65be27845400	2480
AnnaBridge	172:65be27845400	2481	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/