mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_L4R5ZI_P/TOOLCHAIN_ARM_STD/stm32l4xx_ll_cortex.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 172:65be27845400 1 /**
AnnaBridge 172:65be27845400 2 ******************************************************************************
AnnaBridge 172:65be27845400 3 * @file stm32l4xx_ll_cortex.h
AnnaBridge 172:65be27845400 4 * @author MCD Application Team
AnnaBridge 172:65be27845400 5 * @brief Header file of CORTEX LL module.
AnnaBridge 172:65be27845400 6 @verbatim
AnnaBridge 172:65be27845400 7 ==============================================================================
AnnaBridge 172:65be27845400 8 ##### How to use this driver #####
AnnaBridge 172:65be27845400 9 ==============================================================================
AnnaBridge 172:65be27845400 10 [..]
AnnaBridge 172:65be27845400 11 The LL CORTEX driver contains a set of generic APIs that can be
AnnaBridge 172:65be27845400 12 used by user:
AnnaBridge 172:65be27845400 13 (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
AnnaBridge 172:65be27845400 14 functions
AnnaBridge 172:65be27845400 15 (+) Low power mode configuration (SCB register of Cortex-MCU)
AnnaBridge 172:65be27845400 16 (+) MPU API to configure and enable regions
AnnaBridge 172:65be27845400 17 (+) API to access to MCU info (CPUID register)
AnnaBridge 172:65be27845400 18 (+) API to enable fault handler (SHCSR accesses)
AnnaBridge 172:65be27845400 19
AnnaBridge 172:65be27845400 20 @endverbatim
AnnaBridge 172:65be27845400 21 ******************************************************************************
AnnaBridge 172:65be27845400 22 * @attention
AnnaBridge 172:65be27845400 23 *
AnnaBridge 172:65be27845400 24 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 172:65be27845400 25 *
AnnaBridge 172:65be27845400 26 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 172:65be27845400 27 * are permitted provided that the following conditions are met:
AnnaBridge 172:65be27845400 28 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 172:65be27845400 29 * this list of conditions and the following disclaimer.
AnnaBridge 172:65be27845400 30 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 172:65be27845400 31 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 172:65be27845400 32 * and/or other materials provided with the distribution.
AnnaBridge 172:65be27845400 33 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 172:65be27845400 34 * may be used to endorse or promote products derived from this software
AnnaBridge 172:65be27845400 35 * without specific prior written permission.
AnnaBridge 172:65be27845400 36 *
AnnaBridge 172:65be27845400 37 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 172:65be27845400 38 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 172:65be27845400 39 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 172:65be27845400 40 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 172:65be27845400 41 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 172:65be27845400 42 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 172:65be27845400 43 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 172:65be27845400 44 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 172:65be27845400 45 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 172:65be27845400 46 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 172:65be27845400 47 *
AnnaBridge 172:65be27845400 48 ******************************************************************************
AnnaBridge 172:65be27845400 49 */
AnnaBridge 172:65be27845400 50
AnnaBridge 172:65be27845400 51 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 172:65be27845400 52 #ifndef __STM32L4xx_LL_CORTEX_H
AnnaBridge 172:65be27845400 53 #define __STM32L4xx_LL_CORTEX_H
AnnaBridge 172:65be27845400 54
AnnaBridge 172:65be27845400 55 #ifdef __cplusplus
AnnaBridge 172:65be27845400 56 extern "C" {
AnnaBridge 172:65be27845400 57 #endif
AnnaBridge 172:65be27845400 58
AnnaBridge 172:65be27845400 59 /* Includes ------------------------------------------------------------------*/
AnnaBridge 172:65be27845400 60 #include "stm32l4xx.h"
AnnaBridge 172:65be27845400 61
AnnaBridge 172:65be27845400 62 /** @addtogroup STM32L4xx_LL_Driver
AnnaBridge 172:65be27845400 63 * @{
AnnaBridge 172:65be27845400 64 */
AnnaBridge 172:65be27845400 65
AnnaBridge 172:65be27845400 66 /** @defgroup CORTEX_LL CORTEX
AnnaBridge 172:65be27845400 67 * @{
AnnaBridge 172:65be27845400 68 */
AnnaBridge 172:65be27845400 69
AnnaBridge 172:65be27845400 70 /* Private types -------------------------------------------------------------*/
AnnaBridge 172:65be27845400 71 /* Private variables ---------------------------------------------------------*/
AnnaBridge 172:65be27845400 72
AnnaBridge 172:65be27845400 73 /* Private constants ---------------------------------------------------------*/
AnnaBridge 172:65be27845400 74
AnnaBridge 172:65be27845400 75 /* Private macros ------------------------------------------------------------*/
AnnaBridge 172:65be27845400 76
AnnaBridge 172:65be27845400 77 /* Exported types ------------------------------------------------------------*/
AnnaBridge 172:65be27845400 78 /* Exported constants --------------------------------------------------------*/
AnnaBridge 172:65be27845400 79 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
AnnaBridge 172:65be27845400 80 * @{
AnnaBridge 172:65be27845400 81 */
AnnaBridge 172:65be27845400 82
AnnaBridge 172:65be27845400 83 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
AnnaBridge 172:65be27845400 84 * @{
AnnaBridge 172:65be27845400 85 */
AnnaBridge 172:65be27845400 86 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/
AnnaBridge 172:65be27845400 87 #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
AnnaBridge 172:65be27845400 88 /**
AnnaBridge 172:65be27845400 89 * @}
AnnaBridge 172:65be27845400 90 */
AnnaBridge 172:65be27845400 91
AnnaBridge 172:65be27845400 92 /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
AnnaBridge 172:65be27845400 93 * @{
AnnaBridge 172:65be27845400 94 */
AnnaBridge 172:65be27845400 95 #define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
AnnaBridge 172:65be27845400 96 #define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
AnnaBridge 172:65be27845400 97 #define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
AnnaBridge 172:65be27845400 98 /**
AnnaBridge 172:65be27845400 99 * @}
AnnaBridge 172:65be27845400 100 */
AnnaBridge 172:65be27845400 101
AnnaBridge 172:65be27845400 102 #if __MPU_PRESENT
AnnaBridge 172:65be27845400 103
AnnaBridge 172:65be27845400 104 /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
AnnaBridge 172:65be27845400 105 * @{
AnnaBridge 172:65be27845400 106 */
AnnaBridge 172:65be27845400 107 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */
AnnaBridge 172:65be27845400 108 #define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
AnnaBridge 172:65be27845400 109 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
AnnaBridge 172:65be27845400 110 #define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
AnnaBridge 172:65be27845400 111 /**
AnnaBridge 172:65be27845400 112 * @}
AnnaBridge 172:65be27845400 113 */
AnnaBridge 172:65be27845400 114
AnnaBridge 172:65be27845400 115 /** @defgroup CORTEX_LL_EC_REGION MPU Region Number
AnnaBridge 172:65be27845400 116 * @{
AnnaBridge 172:65be27845400 117 */
AnnaBridge 172:65be27845400 118 #define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */
AnnaBridge 172:65be27845400 119 #define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */
AnnaBridge 172:65be27845400 120 #define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */
AnnaBridge 172:65be27845400 121 #define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */
AnnaBridge 172:65be27845400 122 #define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */
AnnaBridge 172:65be27845400 123 #define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */
AnnaBridge 172:65be27845400 124 #define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */
AnnaBridge 172:65be27845400 125 #define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */
AnnaBridge 172:65be27845400 126 /**
AnnaBridge 172:65be27845400 127 * @}
AnnaBridge 172:65be27845400 128 */
AnnaBridge 172:65be27845400 129
AnnaBridge 172:65be27845400 130 /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
AnnaBridge 172:65be27845400 131 * @{
AnnaBridge 172:65be27845400 132 */
AnnaBridge 172:65be27845400 133 #define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
AnnaBridge 172:65be27845400 134 #define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
AnnaBridge 172:65be27845400 135 #define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
AnnaBridge 172:65be27845400 136 #define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
AnnaBridge 172:65be27845400 137 #define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
AnnaBridge 172:65be27845400 138 #define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
AnnaBridge 172:65be27845400 139 #define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
AnnaBridge 172:65be27845400 140 #define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
AnnaBridge 172:65be27845400 141 #define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
AnnaBridge 172:65be27845400 142 #define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
AnnaBridge 172:65be27845400 143 #define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
AnnaBridge 172:65be27845400 144 #define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
AnnaBridge 172:65be27845400 145 #define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
AnnaBridge 172:65be27845400 146 #define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
AnnaBridge 172:65be27845400 147 #define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
AnnaBridge 172:65be27845400 148 #define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
AnnaBridge 172:65be27845400 149 #define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
AnnaBridge 172:65be27845400 150 #define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
AnnaBridge 172:65be27845400 151 #define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
AnnaBridge 172:65be27845400 152 #define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
AnnaBridge 172:65be27845400 153 #define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
AnnaBridge 172:65be27845400 154 #define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
AnnaBridge 172:65be27845400 155 #define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
AnnaBridge 172:65be27845400 156 #define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
AnnaBridge 172:65be27845400 157 #define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
AnnaBridge 172:65be27845400 158 #define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
AnnaBridge 172:65be27845400 159 #define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
AnnaBridge 172:65be27845400 160 #define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
AnnaBridge 172:65be27845400 161 /**
AnnaBridge 172:65be27845400 162 * @}
AnnaBridge 172:65be27845400 163 */
AnnaBridge 172:65be27845400 164
AnnaBridge 172:65be27845400 165 /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
AnnaBridge 172:65be27845400 166 * @{
AnnaBridge 172:65be27845400 167 */
AnnaBridge 172:65be27845400 168 #define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
AnnaBridge 172:65be27845400 169 #define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
AnnaBridge 172:65be27845400 170 #define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
AnnaBridge 172:65be27845400 171 #define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
AnnaBridge 172:65be27845400 172 #define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
AnnaBridge 172:65be27845400 173 #define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
AnnaBridge 172:65be27845400 174 /**
AnnaBridge 172:65be27845400 175 * @}
AnnaBridge 172:65be27845400 176 */
AnnaBridge 172:65be27845400 177
AnnaBridge 172:65be27845400 178 /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
AnnaBridge 172:65be27845400 179 * @{
AnnaBridge 172:65be27845400 180 */
AnnaBridge 172:65be27845400 181 #define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
AnnaBridge 172:65be27845400 182 #define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
AnnaBridge 172:65be27845400 183 #define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
AnnaBridge 172:65be27845400 184 #define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
AnnaBridge 172:65be27845400 185 /**
AnnaBridge 172:65be27845400 186 * @}
AnnaBridge 172:65be27845400 187 */
AnnaBridge 172:65be27845400 188
AnnaBridge 172:65be27845400 189 /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
AnnaBridge 172:65be27845400 190 * @{
AnnaBridge 172:65be27845400 191 */
AnnaBridge 172:65be27845400 192 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */
AnnaBridge 172:65be27845400 193 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
AnnaBridge 172:65be27845400 194 /**
AnnaBridge 172:65be27845400 195 * @}
AnnaBridge 172:65be27845400 196 */
AnnaBridge 172:65be27845400 197
AnnaBridge 172:65be27845400 198 /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
AnnaBridge 172:65be27845400 199 * @{
AnnaBridge 172:65be27845400 200 */
AnnaBridge 172:65be27845400 201 #define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
AnnaBridge 172:65be27845400 202 #define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */
AnnaBridge 172:65be27845400 203 /**
AnnaBridge 172:65be27845400 204 * @}
AnnaBridge 172:65be27845400 205 */
AnnaBridge 172:65be27845400 206
AnnaBridge 172:65be27845400 207 /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
AnnaBridge 172:65be27845400 208 * @{
AnnaBridge 172:65be27845400 209 */
AnnaBridge 172:65be27845400 210 #define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
AnnaBridge 172:65be27845400 211 #define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */
AnnaBridge 172:65be27845400 212 /**
AnnaBridge 172:65be27845400 213 * @}
AnnaBridge 172:65be27845400 214 */
AnnaBridge 172:65be27845400 215
AnnaBridge 172:65be27845400 216 /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
AnnaBridge 172:65be27845400 217 * @{
AnnaBridge 172:65be27845400 218 */
AnnaBridge 172:65be27845400 219 #define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
AnnaBridge 172:65be27845400 220 #define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */
AnnaBridge 172:65be27845400 221 /**
AnnaBridge 172:65be27845400 222 * @}
AnnaBridge 172:65be27845400 223 */
AnnaBridge 172:65be27845400 224 #endif /* __MPU_PRESENT */
AnnaBridge 172:65be27845400 225 /**
AnnaBridge 172:65be27845400 226 * @}
AnnaBridge 172:65be27845400 227 */
AnnaBridge 172:65be27845400 228
AnnaBridge 172:65be27845400 229 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 172:65be27845400 230
AnnaBridge 172:65be27845400 231 /* Exported functions --------------------------------------------------------*/
AnnaBridge 172:65be27845400 232 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
AnnaBridge 172:65be27845400 233 * @{
AnnaBridge 172:65be27845400 234 */
AnnaBridge 172:65be27845400 235
AnnaBridge 172:65be27845400 236 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
AnnaBridge 172:65be27845400 237 * @{
AnnaBridge 172:65be27845400 238 */
AnnaBridge 172:65be27845400 239
AnnaBridge 172:65be27845400 240 /**
AnnaBridge 172:65be27845400 241 * @brief This function checks if the Systick counter flag is active or not.
AnnaBridge 172:65be27845400 242 * @note It can be used in timeout function on application side.
AnnaBridge 172:65be27845400 243 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
AnnaBridge 172:65be27845400 244 * @retval State of bit (1 or 0).
AnnaBridge 172:65be27845400 245 */
AnnaBridge 172:65be27845400 246 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
AnnaBridge 172:65be27845400 247 {
AnnaBridge 172:65be27845400 248 return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
AnnaBridge 172:65be27845400 249 }
AnnaBridge 172:65be27845400 250
AnnaBridge 172:65be27845400 251 /**
AnnaBridge 172:65be27845400 252 * @brief Configures the SysTick clock source
AnnaBridge 172:65be27845400 253 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
AnnaBridge 172:65be27845400 254 * @param Source This parameter can be one of the following values:
AnnaBridge 172:65be27845400 255 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
AnnaBridge 172:65be27845400 256 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
AnnaBridge 172:65be27845400 257 * @retval None
AnnaBridge 172:65be27845400 258 */
AnnaBridge 172:65be27845400 259 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
AnnaBridge 172:65be27845400 260 {
AnnaBridge 172:65be27845400 261 if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
AnnaBridge 172:65be27845400 262 {
AnnaBridge 172:65be27845400 263 SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
AnnaBridge 172:65be27845400 264 }
AnnaBridge 172:65be27845400 265 else
AnnaBridge 172:65be27845400 266 {
AnnaBridge 172:65be27845400 267 CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
AnnaBridge 172:65be27845400 268 }
AnnaBridge 172:65be27845400 269 }
AnnaBridge 172:65be27845400 270
AnnaBridge 172:65be27845400 271 /**
AnnaBridge 172:65be27845400 272 * @brief Get the SysTick clock source
AnnaBridge 172:65be27845400 273 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
AnnaBridge 172:65be27845400 274 * @retval Returned value can be one of the following values:
AnnaBridge 172:65be27845400 275 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
AnnaBridge 172:65be27845400 276 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
AnnaBridge 172:65be27845400 277 */
AnnaBridge 172:65be27845400 278 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
AnnaBridge 172:65be27845400 279 {
AnnaBridge 172:65be27845400 280 return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
AnnaBridge 172:65be27845400 281 }
AnnaBridge 172:65be27845400 282
AnnaBridge 172:65be27845400 283 /**
AnnaBridge 172:65be27845400 284 * @brief Enable SysTick exception request
AnnaBridge 172:65be27845400 285 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
AnnaBridge 172:65be27845400 286 * @retval None
AnnaBridge 172:65be27845400 287 */
AnnaBridge 172:65be27845400 288 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
AnnaBridge 172:65be27845400 289 {
AnnaBridge 172:65be27845400 290 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
AnnaBridge 172:65be27845400 291 }
AnnaBridge 172:65be27845400 292
AnnaBridge 172:65be27845400 293 /**
AnnaBridge 172:65be27845400 294 * @brief Disable SysTick exception request
AnnaBridge 172:65be27845400 295 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
AnnaBridge 172:65be27845400 296 * @retval None
AnnaBridge 172:65be27845400 297 */
AnnaBridge 172:65be27845400 298 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
AnnaBridge 172:65be27845400 299 {
AnnaBridge 172:65be27845400 300 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
AnnaBridge 172:65be27845400 301 }
AnnaBridge 172:65be27845400 302
AnnaBridge 172:65be27845400 303 /**
AnnaBridge 172:65be27845400 304 * @brief Checks if the SYSTICK interrupt is enabled or disabled.
AnnaBridge 172:65be27845400 305 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
AnnaBridge 172:65be27845400 306 * @retval State of bit (1 or 0).
AnnaBridge 172:65be27845400 307 */
AnnaBridge 172:65be27845400 308 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
AnnaBridge 172:65be27845400 309 {
AnnaBridge 172:65be27845400 310 return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
AnnaBridge 172:65be27845400 311 }
AnnaBridge 172:65be27845400 312
AnnaBridge 172:65be27845400 313 /**
AnnaBridge 172:65be27845400 314 * @}
AnnaBridge 172:65be27845400 315 */
AnnaBridge 172:65be27845400 316
AnnaBridge 172:65be27845400 317 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
AnnaBridge 172:65be27845400 318 * @{
AnnaBridge 172:65be27845400 319 */
AnnaBridge 172:65be27845400 320
AnnaBridge 172:65be27845400 321 /**
AnnaBridge 172:65be27845400 322 * @brief Processor uses sleep as its low power mode
AnnaBridge 172:65be27845400 323 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
AnnaBridge 172:65be27845400 324 * @retval None
AnnaBridge 172:65be27845400 325 */
AnnaBridge 172:65be27845400 326 __STATIC_INLINE void LL_LPM_EnableSleep(void)
AnnaBridge 172:65be27845400 327 {
AnnaBridge 172:65be27845400 328 /* Clear SLEEPDEEP bit of Cortex System Control Register */
AnnaBridge 172:65be27845400 329 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
AnnaBridge 172:65be27845400 330 }
AnnaBridge 172:65be27845400 331
AnnaBridge 172:65be27845400 332 /**
AnnaBridge 172:65be27845400 333 * @brief Processor uses deep sleep as its low power mode
AnnaBridge 172:65be27845400 334 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
AnnaBridge 172:65be27845400 335 * @retval None
AnnaBridge 172:65be27845400 336 */
AnnaBridge 172:65be27845400 337 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
AnnaBridge 172:65be27845400 338 {
AnnaBridge 172:65be27845400 339 /* Set SLEEPDEEP bit of Cortex System Control Register */
AnnaBridge 172:65be27845400 340 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
AnnaBridge 172:65be27845400 341 }
AnnaBridge 172:65be27845400 342
AnnaBridge 172:65be27845400 343 /**
AnnaBridge 172:65be27845400 344 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
AnnaBridge 172:65be27845400 345 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
AnnaBridge 172:65be27845400 346 * empty main application.
AnnaBridge 172:65be27845400 347 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
AnnaBridge 172:65be27845400 348 * @retval None
AnnaBridge 172:65be27845400 349 */
AnnaBridge 172:65be27845400 350 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
AnnaBridge 172:65be27845400 351 {
AnnaBridge 172:65be27845400 352 /* Set SLEEPONEXIT bit of Cortex System Control Register */
AnnaBridge 172:65be27845400 353 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
AnnaBridge 172:65be27845400 354 }
AnnaBridge 172:65be27845400 355
AnnaBridge 172:65be27845400 356 /**
AnnaBridge 172:65be27845400 357 * @brief Do not sleep when returning to Thread mode.
AnnaBridge 172:65be27845400 358 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
AnnaBridge 172:65be27845400 359 * @retval None
AnnaBridge 172:65be27845400 360 */
AnnaBridge 172:65be27845400 361 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
AnnaBridge 172:65be27845400 362 {
AnnaBridge 172:65be27845400 363 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
AnnaBridge 172:65be27845400 364 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
AnnaBridge 172:65be27845400 365 }
AnnaBridge 172:65be27845400 366
AnnaBridge 172:65be27845400 367 /**
AnnaBridge 172:65be27845400 368 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
AnnaBridge 172:65be27845400 369 * processor.
AnnaBridge 172:65be27845400 370 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
AnnaBridge 172:65be27845400 371 * @retval None
AnnaBridge 172:65be27845400 372 */
AnnaBridge 172:65be27845400 373 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
AnnaBridge 172:65be27845400 374 {
AnnaBridge 172:65be27845400 375 /* Set SEVEONPEND bit of Cortex System Control Register */
AnnaBridge 172:65be27845400 376 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
AnnaBridge 172:65be27845400 377 }
AnnaBridge 172:65be27845400 378
AnnaBridge 172:65be27845400 379 /**
AnnaBridge 172:65be27845400 380 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
AnnaBridge 172:65be27845400 381 * excluded
AnnaBridge 172:65be27845400 382 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
AnnaBridge 172:65be27845400 383 * @retval None
AnnaBridge 172:65be27845400 384 */
AnnaBridge 172:65be27845400 385 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
AnnaBridge 172:65be27845400 386 {
AnnaBridge 172:65be27845400 387 /* Clear SEVEONPEND bit of Cortex System Control Register */
AnnaBridge 172:65be27845400 388 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
AnnaBridge 172:65be27845400 389 }
AnnaBridge 172:65be27845400 390
AnnaBridge 172:65be27845400 391 /**
AnnaBridge 172:65be27845400 392 * @}
AnnaBridge 172:65be27845400 393 */
AnnaBridge 172:65be27845400 394
AnnaBridge 172:65be27845400 395 /** @defgroup CORTEX_LL_EF_HANDLER HANDLER
AnnaBridge 172:65be27845400 396 * @{
AnnaBridge 172:65be27845400 397 */
AnnaBridge 172:65be27845400 398
AnnaBridge 172:65be27845400 399 /**
AnnaBridge 172:65be27845400 400 * @brief Enable a fault in System handler control register (SHCSR)
AnnaBridge 172:65be27845400 401 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
AnnaBridge 172:65be27845400 402 * @param Fault This parameter can be a combination of the following values:
AnnaBridge 172:65be27845400 403 * @arg @ref LL_HANDLER_FAULT_USG
AnnaBridge 172:65be27845400 404 * @arg @ref LL_HANDLER_FAULT_BUS
AnnaBridge 172:65be27845400 405 * @arg @ref LL_HANDLER_FAULT_MEM
AnnaBridge 172:65be27845400 406 * @retval None
AnnaBridge 172:65be27845400 407 */
AnnaBridge 172:65be27845400 408 __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
AnnaBridge 172:65be27845400 409 {
AnnaBridge 172:65be27845400 410 /* Enable the system handler fault */
AnnaBridge 172:65be27845400 411 SET_BIT(SCB->SHCSR, Fault);
AnnaBridge 172:65be27845400 412 }
AnnaBridge 172:65be27845400 413
AnnaBridge 172:65be27845400 414 /**
AnnaBridge 172:65be27845400 415 * @brief Disable a fault in System handler control register (SHCSR)
AnnaBridge 172:65be27845400 416 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
AnnaBridge 172:65be27845400 417 * @param Fault This parameter can be a combination of the following values:
AnnaBridge 172:65be27845400 418 * @arg @ref LL_HANDLER_FAULT_USG
AnnaBridge 172:65be27845400 419 * @arg @ref LL_HANDLER_FAULT_BUS
AnnaBridge 172:65be27845400 420 * @arg @ref LL_HANDLER_FAULT_MEM
AnnaBridge 172:65be27845400 421 * @retval None
AnnaBridge 172:65be27845400 422 */
AnnaBridge 172:65be27845400 423 __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
AnnaBridge 172:65be27845400 424 {
AnnaBridge 172:65be27845400 425 /* Disable the system handler fault */
AnnaBridge 172:65be27845400 426 CLEAR_BIT(SCB->SHCSR, Fault);
AnnaBridge 172:65be27845400 427 }
AnnaBridge 172:65be27845400 428
AnnaBridge 172:65be27845400 429 /**
AnnaBridge 172:65be27845400 430 * @}
AnnaBridge 172:65be27845400 431 */
AnnaBridge 172:65be27845400 432
AnnaBridge 172:65be27845400 433 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
AnnaBridge 172:65be27845400 434 * @{
AnnaBridge 172:65be27845400 435 */
AnnaBridge 172:65be27845400 436
AnnaBridge 172:65be27845400 437 /**
AnnaBridge 172:65be27845400 438 * @brief Get Implementer code
AnnaBridge 172:65be27845400 439 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
AnnaBridge 172:65be27845400 440 * @retval Value should be equal to 0x41 for ARM
AnnaBridge 172:65be27845400 441 */
AnnaBridge 172:65be27845400 442 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
AnnaBridge 172:65be27845400 443 {
AnnaBridge 172:65be27845400 444 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
AnnaBridge 172:65be27845400 445 }
AnnaBridge 172:65be27845400 446
AnnaBridge 172:65be27845400 447 /**
AnnaBridge 172:65be27845400 448 * @brief Get Variant number (The r value in the rnpn product revision identifier)
AnnaBridge 172:65be27845400 449 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
AnnaBridge 172:65be27845400 450 * @retval Value between 0 and 255 (0x0: revision 0)
AnnaBridge 172:65be27845400 451 */
AnnaBridge 172:65be27845400 452 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
AnnaBridge 172:65be27845400 453 {
AnnaBridge 172:65be27845400 454 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
AnnaBridge 172:65be27845400 455 }
AnnaBridge 172:65be27845400 456
AnnaBridge 172:65be27845400 457 /**
AnnaBridge 172:65be27845400 458 * @brief Get Constant number
AnnaBridge 172:65be27845400 459 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
AnnaBridge 172:65be27845400 460 * @retval Value should be equal to 0xF for Cortex-M4 devices
AnnaBridge 172:65be27845400 461 */
AnnaBridge 172:65be27845400 462 __STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
AnnaBridge 172:65be27845400 463 {
AnnaBridge 172:65be27845400 464 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
AnnaBridge 172:65be27845400 465 }
AnnaBridge 172:65be27845400 466
AnnaBridge 172:65be27845400 467 /**
AnnaBridge 172:65be27845400 468 * @brief Get Part number
AnnaBridge 172:65be27845400 469 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
AnnaBridge 172:65be27845400 470 * @retval Value should be equal to 0xC24 for Cortex-M4
AnnaBridge 172:65be27845400 471 */
AnnaBridge 172:65be27845400 472 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
AnnaBridge 172:65be27845400 473 {
AnnaBridge 172:65be27845400 474 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
AnnaBridge 172:65be27845400 475 }
AnnaBridge 172:65be27845400 476
AnnaBridge 172:65be27845400 477 /**
AnnaBridge 172:65be27845400 478 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
AnnaBridge 172:65be27845400 479 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
AnnaBridge 172:65be27845400 480 * @retval Value between 0 and 255 (0x1: patch 1)
AnnaBridge 172:65be27845400 481 */
AnnaBridge 172:65be27845400 482 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
AnnaBridge 172:65be27845400 483 {
AnnaBridge 172:65be27845400 484 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
AnnaBridge 172:65be27845400 485 }
AnnaBridge 172:65be27845400 486
AnnaBridge 172:65be27845400 487 /**
AnnaBridge 172:65be27845400 488 * @}
AnnaBridge 172:65be27845400 489 */
AnnaBridge 172:65be27845400 490
AnnaBridge 172:65be27845400 491 #if __MPU_PRESENT
AnnaBridge 172:65be27845400 492 /** @defgroup CORTEX_LL_EF_MPU MPU
AnnaBridge 172:65be27845400 493 * @{
AnnaBridge 172:65be27845400 494 */
AnnaBridge 172:65be27845400 495
AnnaBridge 172:65be27845400 496 /**
AnnaBridge 172:65be27845400 497 * @brief Enable MPU with input options
AnnaBridge 172:65be27845400 498 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
AnnaBridge 172:65be27845400 499 * @param Options This parameter can be one of the following values:
AnnaBridge 172:65be27845400 500 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
AnnaBridge 172:65be27845400 501 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
AnnaBridge 172:65be27845400 502 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
AnnaBridge 172:65be27845400 503 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
AnnaBridge 172:65be27845400 504 * @retval None
AnnaBridge 172:65be27845400 505 */
AnnaBridge 172:65be27845400 506 __STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
AnnaBridge 172:65be27845400 507 {
AnnaBridge 172:65be27845400 508 /* Enable the MPU*/
AnnaBridge 172:65be27845400 509 WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
AnnaBridge 172:65be27845400 510 /* Ensure MPU settings take effects */
AnnaBridge 172:65be27845400 511 __DSB();
AnnaBridge 172:65be27845400 512 /* Sequence instruction fetches using update settings */
AnnaBridge 172:65be27845400 513 __ISB();
AnnaBridge 172:65be27845400 514 }
AnnaBridge 172:65be27845400 515
AnnaBridge 172:65be27845400 516 /**
AnnaBridge 172:65be27845400 517 * @brief Disable MPU
AnnaBridge 172:65be27845400 518 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
AnnaBridge 172:65be27845400 519 * @retval None
AnnaBridge 172:65be27845400 520 */
AnnaBridge 172:65be27845400 521 __STATIC_INLINE void LL_MPU_Disable(void)
AnnaBridge 172:65be27845400 522 {
AnnaBridge 172:65be27845400 523 /* Make sure outstanding transfers are done */
AnnaBridge 172:65be27845400 524 __DMB();
AnnaBridge 172:65be27845400 525 /* Disable MPU*/
AnnaBridge 172:65be27845400 526 WRITE_REG(MPU->CTRL, 0U);
AnnaBridge 172:65be27845400 527 }
AnnaBridge 172:65be27845400 528
AnnaBridge 172:65be27845400 529 /**
AnnaBridge 172:65be27845400 530 * @brief Check if MPU is enabled or not
AnnaBridge 172:65be27845400 531 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
AnnaBridge 172:65be27845400 532 * @retval State of bit (1 or 0).
AnnaBridge 172:65be27845400 533 */
AnnaBridge 172:65be27845400 534 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
AnnaBridge 172:65be27845400 535 {
AnnaBridge 172:65be27845400 536 return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
AnnaBridge 172:65be27845400 537 }
AnnaBridge 172:65be27845400 538
AnnaBridge 172:65be27845400 539 /**
AnnaBridge 172:65be27845400 540 * @brief Enable a MPU region
AnnaBridge 172:65be27845400 541 * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
AnnaBridge 172:65be27845400 542 * @param Region This parameter can be one of the following values:
AnnaBridge 172:65be27845400 543 * @arg @ref LL_MPU_REGION_NUMBER0
AnnaBridge 172:65be27845400 544 * @arg @ref LL_MPU_REGION_NUMBER1
AnnaBridge 172:65be27845400 545 * @arg @ref LL_MPU_REGION_NUMBER2
AnnaBridge 172:65be27845400 546 * @arg @ref LL_MPU_REGION_NUMBER3
AnnaBridge 172:65be27845400 547 * @arg @ref LL_MPU_REGION_NUMBER4
AnnaBridge 172:65be27845400 548 * @arg @ref LL_MPU_REGION_NUMBER5
AnnaBridge 172:65be27845400 549 * @arg @ref LL_MPU_REGION_NUMBER6
AnnaBridge 172:65be27845400 550 * @arg @ref LL_MPU_REGION_NUMBER7
AnnaBridge 172:65be27845400 551 * @retval None
AnnaBridge 172:65be27845400 552 */
AnnaBridge 172:65be27845400 553 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
AnnaBridge 172:65be27845400 554 {
AnnaBridge 172:65be27845400 555 /* Set Region number */
AnnaBridge 172:65be27845400 556 WRITE_REG(MPU->RNR, Region);
AnnaBridge 172:65be27845400 557 /* Enable the MPU region */
AnnaBridge 172:65be27845400 558 SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
AnnaBridge 172:65be27845400 559 }
AnnaBridge 172:65be27845400 560
AnnaBridge 172:65be27845400 561 /**
AnnaBridge 172:65be27845400 562 * @brief Configure and enable a region
AnnaBridge 172:65be27845400 563 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
AnnaBridge 172:65be27845400 564 * MPU_RBAR REGION LL_MPU_ConfigRegion\n
AnnaBridge 172:65be27845400 565 * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
AnnaBridge 172:65be27845400 566 * MPU_RASR XN LL_MPU_ConfigRegion\n
AnnaBridge 172:65be27845400 567 * MPU_RASR AP LL_MPU_ConfigRegion\n
AnnaBridge 172:65be27845400 568 * MPU_RASR S LL_MPU_ConfigRegion\n
AnnaBridge 172:65be27845400 569 * MPU_RASR C LL_MPU_ConfigRegion\n
AnnaBridge 172:65be27845400 570 * MPU_RASR B LL_MPU_ConfigRegion\n
AnnaBridge 172:65be27845400 571 * MPU_RASR SIZE LL_MPU_ConfigRegion
AnnaBridge 172:65be27845400 572 * @param Region This parameter can be one of the following values:
AnnaBridge 172:65be27845400 573 * @arg @ref LL_MPU_REGION_NUMBER0
AnnaBridge 172:65be27845400 574 * @arg @ref LL_MPU_REGION_NUMBER1
AnnaBridge 172:65be27845400 575 * @arg @ref LL_MPU_REGION_NUMBER2
AnnaBridge 172:65be27845400 576 * @arg @ref LL_MPU_REGION_NUMBER3
AnnaBridge 172:65be27845400 577 * @arg @ref LL_MPU_REGION_NUMBER4
AnnaBridge 172:65be27845400 578 * @arg @ref LL_MPU_REGION_NUMBER5
AnnaBridge 172:65be27845400 579 * @arg @ref LL_MPU_REGION_NUMBER6
AnnaBridge 172:65be27845400 580 * @arg @ref LL_MPU_REGION_NUMBER7
AnnaBridge 172:65be27845400 581 * @param Address Value of region base address
AnnaBridge 172:65be27845400 582 * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
AnnaBridge 172:65be27845400 583 * @param Attributes This parameter can be a combination of the following values:
AnnaBridge 172:65be27845400 584 * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
AnnaBridge 172:65be27845400 585 * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
AnnaBridge 172:65be27845400 586 * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
AnnaBridge 172:65be27845400 587 * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
AnnaBridge 172:65be27845400 588 * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
AnnaBridge 172:65be27845400 589 * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
AnnaBridge 172:65be27845400 590 * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
AnnaBridge 172:65be27845400 591 * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
AnnaBridge 172:65be27845400 592 * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
AnnaBridge 172:65be27845400 593 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
AnnaBridge 172:65be27845400 594 * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
AnnaBridge 172:65be27845400 595 * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
AnnaBridge 172:65be27845400 596 * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
AnnaBridge 172:65be27845400 597 * @retval None
AnnaBridge 172:65be27845400 598 */
AnnaBridge 172:65be27845400 599 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
AnnaBridge 172:65be27845400 600 {
AnnaBridge 172:65be27845400 601 /* Set Region number */
AnnaBridge 172:65be27845400 602 WRITE_REG(MPU->RNR, Region);
AnnaBridge 172:65be27845400 603 /* Set base address */
AnnaBridge 172:65be27845400 604 WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
AnnaBridge 172:65be27845400 605 /* Configure MPU */
AnnaBridge 172:65be27845400 606 WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
AnnaBridge 172:65be27845400 607 }
AnnaBridge 172:65be27845400 608
AnnaBridge 172:65be27845400 609 /**
AnnaBridge 172:65be27845400 610 * @brief Disable a region
AnnaBridge 172:65be27845400 611 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
AnnaBridge 172:65be27845400 612 * MPU_RASR ENABLE LL_MPU_DisableRegion
AnnaBridge 172:65be27845400 613 * @param Region This parameter can be one of the following values:
AnnaBridge 172:65be27845400 614 * @arg @ref LL_MPU_REGION_NUMBER0
AnnaBridge 172:65be27845400 615 * @arg @ref LL_MPU_REGION_NUMBER1
AnnaBridge 172:65be27845400 616 * @arg @ref LL_MPU_REGION_NUMBER2
AnnaBridge 172:65be27845400 617 * @arg @ref LL_MPU_REGION_NUMBER3
AnnaBridge 172:65be27845400 618 * @arg @ref LL_MPU_REGION_NUMBER4
AnnaBridge 172:65be27845400 619 * @arg @ref LL_MPU_REGION_NUMBER5
AnnaBridge 172:65be27845400 620 * @arg @ref LL_MPU_REGION_NUMBER6
AnnaBridge 172:65be27845400 621 * @arg @ref LL_MPU_REGION_NUMBER7
AnnaBridge 172:65be27845400 622 * @retval None
AnnaBridge 172:65be27845400 623 */
AnnaBridge 172:65be27845400 624 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
AnnaBridge 172:65be27845400 625 {
AnnaBridge 172:65be27845400 626 /* Set Region number */
AnnaBridge 172:65be27845400 627 WRITE_REG(MPU->RNR, Region);
AnnaBridge 172:65be27845400 628 /* Disable the MPU region */
AnnaBridge 172:65be27845400 629 CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
AnnaBridge 172:65be27845400 630 }
AnnaBridge 172:65be27845400 631
AnnaBridge 172:65be27845400 632 /**
AnnaBridge 172:65be27845400 633 * @}
AnnaBridge 172:65be27845400 634 */
AnnaBridge 172:65be27845400 635
AnnaBridge 172:65be27845400 636 #endif /* __MPU_PRESENT */
AnnaBridge 172:65be27845400 637 /**
AnnaBridge 172:65be27845400 638 * @}
AnnaBridge 172:65be27845400 639 */
AnnaBridge 172:65be27845400 640
AnnaBridge 172:65be27845400 641 /**
AnnaBridge 172:65be27845400 642 * @}
AnnaBridge 172:65be27845400 643 */
AnnaBridge 172:65be27845400 644
AnnaBridge 172:65be27845400 645 /**
AnnaBridge 172:65be27845400 646 * @}
AnnaBridge 172:65be27845400 647 */
AnnaBridge 172:65be27845400 648
AnnaBridge 172:65be27845400 649 #ifdef __cplusplus
AnnaBridge 172:65be27845400 650 }
AnnaBridge 172:65be27845400 651 #endif
AnnaBridge 172:65be27845400 652
AnnaBridge 172:65be27845400 653 #endif /* __STM32L4xx_LL_CORTEX_H */
AnnaBridge 172:65be27845400 654
AnnaBridge 172:65be27845400 655 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/