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TARGET_NUCLEO_L4R5ZI_P/TOOLCHAIN_ARM_STD/stm32l4xx_hal_tim_ex.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	172:65be27845400	1	/**
AnnaBridge	172:65be27845400	2	******************************************************************************
AnnaBridge	172:65be27845400	3	* @file stm32l4xx_hal_tim_ex.h
AnnaBridge	172:65be27845400	4	* @author MCD Application Team
AnnaBridge	172:65be27845400	5	* @brief Header file of TIM HAL Extended module.
AnnaBridge	172:65be27845400	6	******************************************************************************
AnnaBridge	172:65be27845400	7	* @attention
AnnaBridge	172:65be27845400	8	*
AnnaBridge	172:65be27845400	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	172:65be27845400	10	*
AnnaBridge	172:65be27845400	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	172:65be27845400	12	* are permitted provided that the following conditions are met:
AnnaBridge	172:65be27845400	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	172:65be27845400	14	* this list of conditions and the following disclaimer.
AnnaBridge	172:65be27845400	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	172:65be27845400	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	172:65be27845400	17	* and/or other materials provided with the distribution.
AnnaBridge	172:65be27845400	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	172:65be27845400	19	* may be used to endorse or promote products derived from this software
AnnaBridge	172:65be27845400	20	* without specific prior written permission.
AnnaBridge	172:65be27845400	21	*
AnnaBridge	172:65be27845400	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	172:65be27845400	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	172:65be27845400	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	172:65be27845400	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	172:65be27845400	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	172:65be27845400	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	172:65be27845400	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	172:65be27845400	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	172:65be27845400	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	172:65be27845400	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	172:65be27845400	32	*
AnnaBridge	172:65be27845400	33	******************************************************************************
AnnaBridge	172:65be27845400	34	*/
AnnaBridge	172:65be27845400	35
AnnaBridge	172:65be27845400	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	172:65be27845400	37	#ifndef __STM32L4xx_HAL_TIM_EX_H
AnnaBridge	172:65be27845400	38	#define __STM32L4xx_HAL_TIM_EX_H
AnnaBridge	172:65be27845400	39
AnnaBridge	172:65be27845400	40	#ifdef __cplusplus
AnnaBridge	172:65be27845400	41	extern "C" {
AnnaBridge	172:65be27845400	42	#endif
AnnaBridge	172:65be27845400	43
AnnaBridge	172:65be27845400	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	172:65be27845400	45	#include "stm32l4xx_hal_def.h"
AnnaBridge	172:65be27845400	46
AnnaBridge	172:65be27845400	47	/** @addtogroup STM32L4xx_HAL_Driver
AnnaBridge	172:65be27845400	48	* @{
AnnaBridge	172:65be27845400	49	*/
AnnaBridge	172:65be27845400	50
AnnaBridge	172:65be27845400	51	/** @addtogroup TIMEx
AnnaBridge	172:65be27845400	52	* @{
AnnaBridge	172:65be27845400	53	*/
AnnaBridge	172:65be27845400	54
AnnaBridge	172:65be27845400	55	/* Exported types ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	56	/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
AnnaBridge	172:65be27845400	57	* @{
AnnaBridge	172:65be27845400	58	*/
AnnaBridge	172:65be27845400	59
AnnaBridge	172:65be27845400	60	/**
AnnaBridge	172:65be27845400	61	* @brief TIM Hall sensor Configuration Structure definition
AnnaBridge	172:65be27845400	62	*/
AnnaBridge	172:65be27845400	63
AnnaBridge	172:65be27845400	64	typedef struct
AnnaBridge	172:65be27845400	65	{
AnnaBridge	172:65be27845400	66
AnnaBridge	172:65be27845400	67	uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
AnnaBridge	172:65be27845400	68	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
AnnaBridge	172:65be27845400	69
AnnaBridge	172:65be27845400	70	uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
AnnaBridge	172:65be27845400	71	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
AnnaBridge	172:65be27845400	72
AnnaBridge	172:65be27845400	73	uint32_t IC1Filter; /*!< Specifies the input capture filter.
AnnaBridge	172:65be27845400	74	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge	172:65be27845400	75
AnnaBridge	172:65be27845400	76	uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
AnnaBridge	172:65be27845400	77	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
AnnaBridge	172:65be27845400	78	} TIM_HallSensor_InitTypeDef;
AnnaBridge	172:65be27845400	79
AnnaBridge	172:65be27845400	80	/**
AnnaBridge	172:65be27845400	81	* @brief TIM Break/Break2 input configuration
AnnaBridge	172:65be27845400	82	*/
AnnaBridge	172:65be27845400	83	typedef struct {
AnnaBridge	172:65be27845400	84	uint32_t Source; /*!< Specifies the source of the timer break input.
AnnaBridge	172:65be27845400	85	This parameter can be a value of @ref TIMEx_Break_Input_Source */
AnnaBridge	172:65be27845400	86	uint32_t Enable; /*!< Specifies whether or not the break input source is enabled.
AnnaBridge	172:65be27845400	87	This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */
AnnaBridge	172:65be27845400	88	uint32_t Polarity; /*!< Specifies the break input source polarity.
AnnaBridge	172:65be27845400	89	This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity
AnnaBridge	172:65be27845400	90	Not relevant when analog watchdog output of the DFSDM1 used as break input source */
AnnaBridge	172:65be27845400	91	} TIMEx_BreakInputConfigTypeDef;
AnnaBridge	172:65be27845400	92
AnnaBridge	172:65be27845400	93	/**
AnnaBridge	172:65be27845400	94	* @}
AnnaBridge	172:65be27845400	95	*/
AnnaBridge	172:65be27845400	96	/* End of exported types -----------------------------------------------------*/
AnnaBridge	172:65be27845400	97
AnnaBridge	172:65be27845400	98	/* Exported constants --------------------------------------------------------*/
AnnaBridge	172:65be27845400	99	/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
AnnaBridge	172:65be27845400	100	* @{
AnnaBridge	172:65be27845400	101	*/
AnnaBridge	172:65be27845400	102
AnnaBridge	172:65be27845400	103	/** @defgroup TIMEx_Remap TIM Extended Remapping
AnnaBridge	172:65be27845400	104	* @{
AnnaBridge	172:65be27845400	105	*/
AnnaBridge	172:65be27845400	106	#define TIM_TIM1_ETR_ADC1_NONE ((uint32_t)(0x00000000)) /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/
AnnaBridge	172:65be27845400	107	#define TIM_TIM1_ETR_ADC1_AWD1 (TIM1_OR1_ETR_ADC1_RMP_0) /* !< TIM1_ETR is connected to ADC1 AWD1 */
AnnaBridge	172:65be27845400	108	#define TIM_TIM1_ETR_ADC1_AWD2 (TIM1_OR1_ETR_ADC1_RMP_1) /* !< TIM1_ETR is connected to ADC1 AWD2 */
AnnaBridge	172:65be27845400	109	#define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_OR1_ETR_ADC1_RMP_1 \| TIM1_OR1_ETR_ADC1_RMP_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */
AnnaBridge	172:65be27845400	110	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx) \|\| \
AnnaBridge	172:65be27845400	111	defined (STM32L496xx) \|\| defined (STM32L4A6xx)
AnnaBridge	172:65be27845400	112	#define TIM_TIM1_ETR_ADC3_NONE ((uint32_t)(0x00000000)) /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/
AnnaBridge	172:65be27845400	113	#define TIM_TIM1_ETR_ADC3_AWD1 (TIM1_OR1_ETR_ADC3_RMP_0) /* !< TIM1_ETR is connected to ADC3 AWD1 */
AnnaBridge	172:65be27845400	114	#define TIM_TIM1_ETR_ADC3_AWD2 (TIM1_OR1_ETR_ADC3_RMP_1) /* !< TIM1_ETR is connected to ADC3 AWD2 */
AnnaBridge	172:65be27845400	115	#define TIM_TIM1_ETR_ADC3_AWD3 (TIM1_OR1_ETR_ADC3_RMP_1 \| TIM1_OR1_ETR_ADC3_RMP_0) /* !< TIM1_ETR is connected to ADC3 AWD3 */
AnnaBridge	172:65be27845400	116	#endif /* STM32L471xx \|\| STM32L475xx \|\| STM32L476xx \|\| STM32L485xx \|\| STM32L486xx \|\| */
AnnaBridge	172:65be27845400	117	/* STM32L496xx \|\| STM32L4A6xx */
AnnaBridge	172:65be27845400	118	#define TIM_TIM1_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM1 TI1 is connected to GPIO */
AnnaBridge	172:65be27845400	119	#define TIM_TIM1_TI1_COMP1 (TIM1_OR1_TI1_RMP) /* !< TIM1 TI1 is connected to COMP1 */
AnnaBridge	172:65be27845400	120	#define TIM_TIM1_ETR_GPIO ((uint32_t)(0x00000000)) /* !< TIM1_ETR is connected to GPIO */
AnnaBridge	172:65be27845400	121	#define TIM_TIM1_ETR_COMP1 (TIM1_OR2_ETRSEL_0) /* !< TIM1_ETR is connected to COMP1 output */
AnnaBridge	172:65be27845400	122	#define TIM_TIM1_ETR_COMP2 (TIM1_OR2_ETRSEL_1) /* !< TIM1_ETR is connected to COMP2 output */
AnnaBridge	172:65be27845400	123
AnnaBridge	172:65be27845400	124	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx) \|\| \
AnnaBridge	172:65be27845400	125	defined (STM32L496xx) \|\| defined (STM32L4A6xx) \|\| \
AnnaBridge	172:65be27845400	126	defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	172:65be27845400	127	#define TIM_TIM2_ITR1_TIM8_TRGO ((uint32_t)(0x00000000)) /* !< TIM2_ITR1 is connected to TIM8_TRGO */
AnnaBridge	172:65be27845400	128	#define TIM_TIM2_ITR1_OTG_FS_SOF (TIM2_OR1_ITR1_RMP) /* !< TIM2_ITR1 is connected to OTG_FS SOF */
AnnaBridge	172:65be27845400	129	#endif /* STM32L471xx \|\| STM32L475xx \|\| STM32L476xx \|\| STM32L485xx \|\| STM32L486xx \|\| */
AnnaBridge	172:65be27845400	130	/* STM32L496xx \|\| STM32L4A6xx \|\| */
AnnaBridge	172:65be27845400	131	/* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	172:65be27845400	132	#if defined (STM32L431xx) \|\| defined (STM32L432xx) \|\| defined (STM32L433xx) \|\| defined (STM32L442xx) \|\| defined (STM32L443xx) \|\| \
AnnaBridge	172:65be27845400	133	defined (STM32L451xx) \|\| defined (STM32L452xx) \|\| defined (STM32L462xx)
AnnaBridge	172:65be27845400	134	#define TIM_TIM2_ITR1_NONE ((uint32_t)(0x00000000)) /* !< No internal trigger on TIM2_ITR1 */
AnnaBridge	172:65be27845400	135	#define TIM_TIM2_ITR1_USB_SOF (TIM2_OR1_ITR1_RMP) /* !< TIM2_ITR1 is connected to USB SOF */
AnnaBridge	172:65be27845400	136	#endif /* STM32L431xx \|\| STM32L432xx \|\| STM32L442xx \|\| STM32L433xx \|\| STM32L443xx \|\| */
AnnaBridge	172:65be27845400	137	/* STM32L451xx \|\| STM32L452xx \|\| STM32L462xx */
AnnaBridge	172:65be27845400	138	#define TIM_TIM2_ETR_GPIO ((uint32_t)(0x00000000)) /* !< TIM2_ETR is connected to GPIO */
AnnaBridge	172:65be27845400	139	#define TIM_TIM2_ETR_LSE (TIM2_OR1_ETR1_RMP) /* !< TIM2_ETR is connected to LSE */
AnnaBridge	172:65be27845400	140	#define TIM_TIM2_ETR_COMP1 (TIM2_OR2_ETRSEL_0) /* !< TIM2_ETR is connected to COMP1 output */
AnnaBridge	172:65be27845400	141	#define TIM_TIM2_ETR_COMP2 (TIM2_OR2_ETRSEL_1) /* !< TIM2_ETR is connected to COMP2 output */
AnnaBridge	172:65be27845400	142	#define TIM_TIM2_TI4_GPIO ((uint32_t)(0x00000000)) /* !< TIM2 TI4 is connected to GPIO */
AnnaBridge	172:65be27845400	143	#define TIM_TIM2_TI4_COMP1 (TIM2_OR1_TI4_RMP_0) /* !< TIM2 TI4 is connected to COMP1 output */
AnnaBridge	172:65be27845400	144	#define TIM_TIM2_TI4_COMP2 (TIM2_OR1_TI4_RMP_1) /* !< TIM2 TI4 is connected to COMP2 output */
AnnaBridge	172:65be27845400	145	#define TIM_TIM2_TI4_COMP1_COMP2 (TIM2_OR1_TI4_RMP_1\| TIM2_OR1_TI4_RMP_0) /* !< TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output2 */
AnnaBridge	172:65be27845400	146
AnnaBridge	172:65be27845400	147	#if defined (STM32L451xx) \|\| defined (STM32L452xx) \|\| defined (STM32L462xx) \|\| \
AnnaBridge	172:65be27845400	148	defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx) \|\| \
AnnaBridge	172:65be27845400	149	defined (STM32L496xx) \|\| defined (STM32L4A6xx) \|\| \
AnnaBridge	172:65be27845400	150	defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	172:65be27845400	151	#define TIM_TIM3_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM3 TI1 is connected to GPIO */
AnnaBridge	172:65be27845400	152	#define TIM_TIM3_TI1_COMP1 (TIM3_OR1_TI1_RMP_0) /* !< TIM3 TI1 is connected to COMP1 output */
AnnaBridge	172:65be27845400	153	#define TIM_TIM3_TI1_COMP2 (TIM3_OR1_TI1_RMP_1) /* !< TIM3 TI1 is connected to COMP2 output */
AnnaBridge	172:65be27845400	154	#define TIM_TIM3_TI1_COMP1_COMP2 (TIM3_OR1_TI1_RMP_1 \| TIM3_OR1_TI1_RMP_0) /* !< TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output2 */
AnnaBridge	172:65be27845400	155	#define TIM_TIM3_ETR_GPIO ((uint32_t)(0x00000000)) /* !< TIM3_ETR is connected to GPIO */
AnnaBridge	172:65be27845400	156	#define TIM_TIM3_ETR_COMP1 (TIM3_OR2_ETRSEL_0) /* !< TIM3_ETR is connected to COMP1 output */
AnnaBridge	172:65be27845400	157	#endif /* STM32L451xx \|\| STM32L452xx \|\| STM32L462xx \|\| */
AnnaBridge	172:65be27845400	158	/* STM32L471xx \|\| STM32L475xx \|\| STM32L476xx \|\| STM32L485xx \|\| STM32L486xx \|\| */
AnnaBridge	172:65be27845400	159	/* STM32L496xx \|\| STM32L4A6xx \|\| */
AnnaBridge	172:65be27845400	160	/* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	172:65be27845400	161
AnnaBridge	172:65be27845400	162	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx) \|\| \
AnnaBridge	172:65be27845400	163	defined (STM32L496xx) \|\| defined (STM32L4A6xx)
AnnaBridge	172:65be27845400	164	#define TIM_TIM8_ETR_ADC2_NONE ((uint32_t)(0x00000000)) /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/
AnnaBridge	172:65be27845400	165	#define TIM_TIM8_ETR_ADC2_AWD1 (TIM8_OR1_ETR_ADC2_RMP_0) /* !< TIM8_ETR is connected to ADC2 AWD1 */
AnnaBridge	172:65be27845400	166	#define TIM_TIM8_ETR_ADC2_AWD2 (TIM8_OR1_ETR_ADC2_RMP_1) /* !< TIM8_ETR is connected to ADC2 AWD2 */
AnnaBridge	172:65be27845400	167	#define TIM_TIM8_ETR_ADC2_AWD3 (TIM8_OR1_ETR_ADC2_RMP_1 \| TIM8_OR1_ETR_ADC2_RMP_0) /* !< TIM8_ETR is connected to ADC2 AWD3 */
AnnaBridge	172:65be27845400	168	#define TIM_TIM8_ETR_ADC3_NONE ((uint32_t)(0x00000000)) /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/
AnnaBridge	172:65be27845400	169	#define TIM_TIM8_ETR_ADC3_AWD1 (TIM8_OR1_ETR_ADC3_RMP_0) /* !< TIM8_ETR is connected to ADC3 AWD1 */
AnnaBridge	172:65be27845400	170	#define TIM_TIM8_ETR_ADC3_AWD2 (TIM8_OR1_ETR_ADC3_RMP_1) /* !< TIM8_ETR is connected to ADC3 AWD2 */
AnnaBridge	172:65be27845400	171	#define TIM_TIM8_ETR_ADC3_AWD3 (TIM8_OR1_ETR_ADC3_RMP_1 \| TIM8_OR1_ETR_ADC3_RMP_0) /* !< TIM8_ETR is connected to ADC3 AWD3 */
AnnaBridge	172:65be27845400	172	#endif /* STM32L471xx \|\| STM32L475xx \|\| STM32L476xx \|\| STM32L485xx \|\| STM32L486xx \|\| */
AnnaBridge	172:65be27845400	173	/* STM32L496xx \|\| STM32L4A6xx */
AnnaBridge	172:65be27845400	174	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx) \|\| \
AnnaBridge	172:65be27845400	175	defined (STM32L496xx) \|\| defined (STM32L4A6xx) \|\| \
AnnaBridge	172:65be27845400	176	defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	172:65be27845400	177	#define TIM_TIM8_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM8 TI1 is connected to GPIO */
AnnaBridge	172:65be27845400	178	#define TIM_TIM8_TI1_COMP2 (TIM8_OR1_TI1_RMP) /* !< TIM8 TI1 is connected to COMP1 */
AnnaBridge	172:65be27845400	179	#define TIM_TIM8_ETR_GPIO ((uint32_t)(0x00000000)) /* !< TIM8_ETR is connected to GPIO */
AnnaBridge	172:65be27845400	180	#define TIM_TIM8_ETR_COMP1 (TIM8_OR2_ETRSEL_0) /* !< TIM8_ETR is connected to COMP1 output */
AnnaBridge	172:65be27845400	181	#define TIM_TIM8_ETR_COMP2 (TIM8_OR2_ETRSEL_1) /* !< TIM8_ETR is connected to COMP2 output */
AnnaBridge	172:65be27845400	182	#endif /* STM32L471xx \|\| STM32L475xx \|\| STM32L476xx \|\| STM32L485xx \|\| STM32L486xx \|\| */
AnnaBridge	172:65be27845400	183	/* STM32L496xx \|\| STM32L4A6xx \|\| */
AnnaBridge	172:65be27845400	184	/* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	172:65be27845400	185
AnnaBridge	172:65be27845400	186	#define TIM_TIM15_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM15 TI1 is connected to GPIO */
AnnaBridge	172:65be27845400	187	#define TIM_TIM15_TI1_LSE (TIM15_OR1_TI1_RMP) /* !< TIM15 TI1 is connected to LSE */
AnnaBridge	172:65be27845400	188	#define TIM_TIM15_ENCODERMODE_NONE ((uint32_t)(0x00000000)) /* !< No redirection */
AnnaBridge	172:65be27845400	189	#define TIM_TIM15_ENCODERMODE_TIM2 (TIM15_OR1_ENCODER_MODE_0) /* !< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
AnnaBridge	172:65be27845400	190	#if defined (STM32L451xx) \|\| defined (STM32L452xx) \|\| defined (STM32L462xx) \|\| \
AnnaBridge	172:65be27845400	191	defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx) \|\| \
AnnaBridge	172:65be27845400	192	defined (STM32L496xx) \|\| defined (STM32L4A6xx) \|\| \
AnnaBridge	172:65be27845400	193	defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	172:65be27845400	194	#define TIM_TIM15_ENCODERMODE_TIM3 (TIM15_OR1_ENCODER_MODE_1) /* !< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
AnnaBridge	172:65be27845400	195	#endif /* STM32L451xx \|\| STM32L452xx \|\| STM32L462xx */
AnnaBridge	172:65be27845400	196	/* STM32L471xx \|\| STM32L475xx \|\| STM32L476xx \|\| STM32L485xx \|\| STM32L486xx \|\| */
AnnaBridge	172:65be27845400	197	/* STM32L496xx \|\| STM32L4A6xx \|\| */
AnnaBridge	172:65be27845400	198	/* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	172:65be27845400	199	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx) \|\| \
AnnaBridge	172:65be27845400	200	defined (STM32L496xx) \|\| defined (STM32L4A6xx) \|\| \
AnnaBridge	172:65be27845400	201	defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	172:65be27845400	202	#define TIM_TIM15_ENCODERMODE_TIM4 (TIM15_OR1_ENCODER_MODE_1 \| TIM15_OR1_ENCODER_MODE_0) /* !< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
AnnaBridge	172:65be27845400	203	#endif /* STM32L471xx \|\| STM32L475xx \|\| STM32L476xx \|\| STM32L485xx \|\| STM32L486xx \|\| */
AnnaBridge	172:65be27845400	204	/* STM32L496xx \|\| STM32L4A6xx \|\| */
AnnaBridge	172:65be27845400	205	/* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	172:65be27845400	206
AnnaBridge	172:65be27845400	207	#define TIM_TIM16_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM16 TI1 is connected to GPIO */
AnnaBridge	172:65be27845400	208	#define TIM_TIM16_TI1_LSI (TIM16_OR1_TI1_RMP_0) /* !< TIM16 TI1 is connected to LSI */
AnnaBridge	172:65be27845400	209	#define TIM_TIM16_TI1_LSE (TIM16_OR1_TI1_RMP_1) /* !< TIM16 TI1 is connected to LSE */
AnnaBridge	172:65be27845400	210	#define TIM_TIM16_TI1_RTC (TIM16_OR1_TI1_RMP_1 \| TIM16_OR1_TI1_RMP_0) /* !< TIM16 TI1 is connected to RTC wakeup interrupt */
AnnaBridge	172:65be27845400	211	#if defined (STM32L431xx) \|\| defined (STM32L432xx) \|\| defined (STM32L433xx) \|\| defined (STM32L442xx) \|\| defined (STM32L443xx) \|\| \
AnnaBridge	172:65be27845400	212	defined (STM32L451xx) \|\| defined (STM32L452xx) \|\| defined (STM32L462xx) \|\| \
AnnaBridge	172:65be27845400	213	defined (STM32L496xx) \|\| defined (STM32L4A6xx)
AnnaBridge	172:65be27845400	214	#define TIM_TIM16_TI1_MSI (TIM16_OR1_TI1_RMP_2) /* !< TIM16 TI1 is connected to MSI */
AnnaBridge	172:65be27845400	215	#define TIM_TIM16_TI1_HSE_32 (TIM16_OR1_TI1_RMP_2 \| TIM16_OR1_TI1_RMP_0) /* !< TIM16 TI1 is connected to HSE div 32 */
AnnaBridge	172:65be27845400	216	#define TIM_TIM16_TI1_MCO (TIM16_OR1_TI1_RMP_2 \| TIM16_OR1_TI1_RMP_1) /* !< TIM16 TI1 is connected to MCO */
AnnaBridge	172:65be27845400	217	#endif /* STM32L431xx \|\| STM32L432xx \|\| STM32L442xx \|\| STM32L433xx \|\| STM32L443xx \|\| */
AnnaBridge	172:65be27845400	218	/* STM32L451xx \|\| STM32L452xx \|\| STM32L462xx \|\| */
AnnaBridge	172:65be27845400	219	/* STM32L496xx \|\| STM32L4A6xx */
AnnaBridge	172:65be27845400	220
AnnaBridge	172:65be27845400	221	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx) \|\| \
AnnaBridge	172:65be27845400	222	defined (STM32L496xx) \|\| defined (STM32L4A6xx) \|\| \
AnnaBridge	172:65be27845400	223	defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	172:65be27845400	224	#define TIM_TIM17_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM17 TI1 is connected to GPIO */
AnnaBridge	172:65be27845400	225	#define TIM_TIM17_TI1_MSI (TIM17_OR1_TI1_RMP_0) /* !< TIM17 TI1 is connected to MSI */
AnnaBridge	172:65be27845400	226	#define TIM_TIM17_TI1_HSE_32 (TIM17_OR1_TI1_RMP_1) /* !< TIM17 TI1 is connected to HSE div 32 */
AnnaBridge	172:65be27845400	227	#define TIM_TIM17_TI1_MCO (TIM17_OR1_TI1_RMP_1 \| TIM17_OR1_TI1_RMP_0) /* !< TIM17 TI1 is connected to MCO */
AnnaBridge	172:65be27845400	228	#endif /* STM32L471xx \|\| STM32L475xx \|\| STM32L476xx \|\| STM32L485xx \|\| STM32L486xx \|\| */
AnnaBridge	172:65be27845400	229	/* STM32L496xx \|\| STM32L4A6xx \|\| */
AnnaBridge	172:65be27845400	230	/* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	172:65be27845400	231	/**
AnnaBridge	172:65be27845400	232	* @}
AnnaBridge	172:65be27845400	233	*/
AnnaBridge	172:65be27845400	234
AnnaBridge	172:65be27845400	235	/** @defgroup TIMEx_Break_Input TIM Extended Break input
AnnaBridge	172:65be27845400	236	* @{
AnnaBridge	172:65be27845400	237	*/
AnnaBridge	172:65be27845400	238	#define TIM_BREAKINPUT_BRK ((uint32_t)(0x00000001)) /* !< Timer break input */
AnnaBridge	172:65be27845400	239	#define TIM_BREAKINPUT_BRK2 ((uint32_t)(0x00000002)) /* !< Timer break2 input */
AnnaBridge	172:65be27845400	240	/**
AnnaBridge	172:65be27845400	241	* @}
AnnaBridge	172:65be27845400	242	*/
AnnaBridge	172:65be27845400	243
AnnaBridge	172:65be27845400	244	/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source
AnnaBridge	172:65be27845400	245	* @{
AnnaBridge	172:65be27845400	246	*/
AnnaBridge	172:65be27845400	247	#define TIM_BREAKINPUTSOURCE_BKIN ((uint32_t)(0x00000001)) /* !< An external source (GPIO) is connected to the BKIN pin */
AnnaBridge	172:65be27845400	248	#define TIM_BREAKINPUTSOURCE_COMP1 ((uint32_t)(0x00000002)) /* !< The COMP1 output is connected to the break input */
AnnaBridge	172:65be27845400	249	#define TIM_BREAKINPUTSOURCE_COMP2 ((uint32_t)(0x00000004)) /* !< The COMP2 output is connected to the break input */
AnnaBridge	172:65be27845400	250	#if defined (STM32L451xx) \|\| defined (STM32L452xx) \|\| defined (STM32L462xx) \|\| \
AnnaBridge	172:65be27845400	251	defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx) \|\| \
AnnaBridge	172:65be27845400	252	defined (STM32L496xx) \|\| defined (STM32L4A6xx) \|\| \
AnnaBridge	172:65be27845400	253	defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	172:65be27845400	254	#define TIM_BREAKINPUTSOURCE_DFSDM1 ((uint32_t)(0x00000008)) /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */
AnnaBridge	172:65be27845400	255	#endif /* STM32L451xx \|\| STM32L452xx \|\| STM32L462xx \|\| */
AnnaBridge	172:65be27845400	256	/* STM32L471xx \|\| STM32L475xx \|\| STM32L476xx \|\| STM32L485xx \|\| STM32L486xx \|\| */
AnnaBridge	172:65be27845400	257	/* STM32L496xx \|\| STM32L4A6xx \|\| */
AnnaBridge	172:65be27845400	258	/* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	172:65be27845400	259	/**
AnnaBridge	172:65be27845400	260	* @}
AnnaBridge	172:65be27845400	261	*/
AnnaBridge	172:65be27845400	262
AnnaBridge	172:65be27845400	263	/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling
AnnaBridge	172:65be27845400	264	* @{
AnnaBridge	172:65be27845400	265	*/
AnnaBridge	172:65be27845400	266	#define TIM_BREAKINPUTSOURCE_DISABLE ((uint32_t)(0x00000000)) /* !< Break input source is disabled */
AnnaBridge	172:65be27845400	267	#define TIM_BREAKINPUTSOURCE_ENABLE ((uint32_t)(0x00000001)) /* !< Break input source is enabled */
AnnaBridge	172:65be27845400	268	/**
AnnaBridge	172:65be27845400	269	* @}
AnnaBridge	172:65be27845400	270	*/
AnnaBridge	172:65be27845400	271
AnnaBridge	172:65be27845400	272	/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity
AnnaBridge	172:65be27845400	273	* @{
AnnaBridge	172:65be27845400	274	*/
AnnaBridge	172:65be27845400	275	#define TIM_BREAKINPUTSOURCE_POLARITY_LOW ((uint32_t)(0x00000001)) /* !< Break input source is active low */
AnnaBridge	172:65be27845400	276	#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH ((uint32_t)(0x00000000)) /* !< Break input source is active_high */
AnnaBridge	172:65be27845400	277	/**
AnnaBridge	172:65be27845400	278	* @}
AnnaBridge	172:65be27845400	279	*/
AnnaBridge	172:65be27845400	280
AnnaBridge	172:65be27845400	281	/**
AnnaBridge	172:65be27845400	282	* @}
AnnaBridge	172:65be27845400	283	*/
AnnaBridge	172:65be27845400	284	/* End of exported constants -------------------------------------------------*/
AnnaBridge	172:65be27845400	285
AnnaBridge	172:65be27845400	286	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	287	/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
AnnaBridge	172:65be27845400	288	* @{
AnnaBridge	172:65be27845400	289	*/
AnnaBridge	172:65be27845400	290
AnnaBridge	172:65be27845400	291	/**
AnnaBridge	172:65be27845400	292	* @}
AnnaBridge	172:65be27845400	293	*/
AnnaBridge	172:65be27845400	294	/* End of exported macro -----------------------------------------------------*/
AnnaBridge	172:65be27845400	295
AnnaBridge	172:65be27845400	296	/* Private macro -------------------------------------------------------------*/
AnnaBridge	172:65be27845400	297	/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
AnnaBridge	172:65be27845400	298	* @{
AnnaBridge	172:65be27845400	299	*/
AnnaBridge	172:65be27845400	300	#define IS_TIM_REMAP(__REMAP__) (((__REMAP__) <= (uint32_t)0x0001C01F))
AnnaBridge	172:65be27845400	301
AnnaBridge	172:65be27845400	302	#define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) \|\| \
AnnaBridge	172:65be27845400	303	((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
AnnaBridge	172:65be27845400	304
AnnaBridge	172:65be27845400	305	#if defined (STM32L451xx) \|\| defined (STM32L452xx) \|\| defined (STM32L462xx) \|\| \
AnnaBridge	172:65be27845400	306	defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx) \|\| \
AnnaBridge	172:65be27845400	307	defined (STM32L496xx) \|\| defined (STM32L4A6xx) \|\| \
AnnaBridge	172:65be27845400	308	defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	172:65be27845400	309	#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) \|\| \
AnnaBridge	172:65be27845400	310	((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) \|\| \
AnnaBridge	172:65be27845400	311	((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) \|\| \
AnnaBridge	172:65be27845400	312	((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM1))
AnnaBridge	172:65be27845400	313	#else
AnnaBridge	172:65be27845400	314	#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) \|\| \
AnnaBridge	172:65be27845400	315	((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) \|\| \
AnnaBridge	172:65be27845400	316	((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2))
AnnaBridge	172:65be27845400	317	#endif /* STM32L471xx \|\| STM32L475xx \|\| STM32L476xx \|\| STM32L485xx \|\| STM32L486xx \|\| */
AnnaBridge	172:65be27845400	318	/* STM32L496xx \|\| STM32L4A6xx \|\| */
AnnaBridge	172:65be27845400	319	/* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	172:65be27845400	320
AnnaBridge	172:65be27845400	321	#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) \|\| \
AnnaBridge	172:65be27845400	322	((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))
AnnaBridge	172:65be27845400	323
AnnaBridge	172:65be27845400	324	#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) \|\| \
AnnaBridge	172:65be27845400	325	((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))
AnnaBridge	172:65be27845400	326	/**
AnnaBridge	172:65be27845400	327	* @}
AnnaBridge	172:65be27845400	328	*/
AnnaBridge	172:65be27845400	329	/* End of private macro ------------------------------------------------------*/
AnnaBridge	172:65be27845400	330
AnnaBridge	172:65be27845400	331	/* Exported functions --------------------------------------------------------*/
AnnaBridge	172:65be27845400	332	/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
AnnaBridge	172:65be27845400	333	* @{
AnnaBridge	172:65be27845400	334	*/
AnnaBridge	172:65be27845400	335
AnnaBridge	172:65be27845400	336	/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
AnnaBridge	172:65be27845400	337	* @brief Timer Hall Sensor functions
AnnaBridge	172:65be27845400	338	* @{
AnnaBridge	172:65be27845400	339	*/
AnnaBridge	172:65be27845400	340	/* Timer Hall Sensor functions **********************************************/
AnnaBridge	172:65be27845400	341	HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef htim, TIM_HallSensor_InitTypeDef sConfig);
AnnaBridge	172:65be27845400	342	HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge	172:65be27845400	343
AnnaBridge	172:65be27845400	344	void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge	172:65be27845400	345	void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge	172:65be27845400	346
AnnaBridge	172:65be27845400	347	/* Blocking mode: Polling */
AnnaBridge	172:65be27845400	348	HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
AnnaBridge	172:65be27845400	349	HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
AnnaBridge	172:65be27845400	350	/* Non-Blocking mode: Interrupt */
AnnaBridge	172:65be27845400	351	HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
AnnaBridge	172:65be27845400	352	HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
AnnaBridge	172:65be27845400	353	/* Non-Blocking mode: DMA */
AnnaBridge	172:65be27845400	354	HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length);
AnnaBridge	172:65be27845400	355	HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
AnnaBridge	172:65be27845400	356	/**
AnnaBridge	172:65be27845400	357	* @}
AnnaBridge	172:65be27845400	358	*/
AnnaBridge	172:65be27845400	359
AnnaBridge	172:65be27845400	360	/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
AnnaBridge	172:65be27845400	361	* @brief Timer Complementary Output Compare functions
AnnaBridge	172:65be27845400	362	* @{
AnnaBridge	172:65be27845400	363	*/
AnnaBridge	172:65be27845400	364	/* Timer Complementary Output Compare functions *****************************/
AnnaBridge	172:65be27845400	365	/* Blocking mode: Polling */
AnnaBridge	172:65be27845400	366	HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	172:65be27845400	367	HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	172:65be27845400	368
AnnaBridge	172:65be27845400	369	/* Non-Blocking mode: Interrupt */
AnnaBridge	172:65be27845400	370	HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	172:65be27845400	371	HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	172:65be27845400	372
AnnaBridge	172:65be27845400	373	/* Non-Blocking mode: DMA */
AnnaBridge	172:65be27845400	374	HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
AnnaBridge	172:65be27845400	375	HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	172:65be27845400	376	/**
AnnaBridge	172:65be27845400	377	* @}
AnnaBridge	172:65be27845400	378	*/
AnnaBridge	172:65be27845400	379
AnnaBridge	172:65be27845400	380	/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
AnnaBridge	172:65be27845400	381	* @brief Timer Complementary PWM functions
AnnaBridge	172:65be27845400	382	* @{
AnnaBridge	172:65be27845400	383	*/
AnnaBridge	172:65be27845400	384	/* Timer Complementary PWM functions ****************************************/
AnnaBridge	172:65be27845400	385	/* Blocking mode: Polling */
AnnaBridge	172:65be27845400	386	HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	172:65be27845400	387	HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	172:65be27845400	388
AnnaBridge	172:65be27845400	389	/* Non-Blocking mode: Interrupt */
AnnaBridge	172:65be27845400	390	HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	172:65be27845400	391	HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	172:65be27845400	392	/* Non-Blocking mode: DMA */
AnnaBridge	172:65be27845400	393	HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
AnnaBridge	172:65be27845400	394	HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	172:65be27845400	395	/**
AnnaBridge	172:65be27845400	396	* @}
AnnaBridge	172:65be27845400	397	*/
AnnaBridge	172:65be27845400	398
AnnaBridge	172:65be27845400	399	/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
AnnaBridge	172:65be27845400	400	* @brief Timer Complementary One Pulse functions
AnnaBridge	172:65be27845400	401	* @{
AnnaBridge	172:65be27845400	402	*/
AnnaBridge	172:65be27845400	403	/* Timer Complementary One Pulse functions **********************************/
AnnaBridge	172:65be27845400	404	/* Blocking mode: Polling */
AnnaBridge	172:65be27845400	405	HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
AnnaBridge	172:65be27845400	406	HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
AnnaBridge	172:65be27845400	407
AnnaBridge	172:65be27845400	408	/* Non-Blocking mode: Interrupt */
AnnaBridge	172:65be27845400	409	HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
AnnaBridge	172:65be27845400	410	HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
AnnaBridge	172:65be27845400	411	/**
AnnaBridge	172:65be27845400	412	* @}
AnnaBridge	172:65be27845400	413	*/
AnnaBridge	172:65be27845400	414
AnnaBridge	172:65be27845400	415	/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
AnnaBridge	172:65be27845400	416	* @brief Peripheral Control functions
AnnaBridge	172:65be27845400	417	* @{
AnnaBridge	172:65be27845400	418	*/
AnnaBridge	172:65be27845400	419	/* Extended Control functions ************************************************/
AnnaBridge	172:65be27845400	420	HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
AnnaBridge	172:65be27845400	421	HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
AnnaBridge	172:65be27845400	422	HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
AnnaBridge	172:65be27845400	423	HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef htim, TIM_MasterConfigTypeDef sMasterConfig);
AnnaBridge	172:65be27845400	424	HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef htim, TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig);
AnnaBridge	172:65be27845400	425	HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef sBreakInputConfig);
AnnaBridge	172:65be27845400	426	HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
AnnaBridge	172:65be27845400	427	HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
AnnaBridge	172:65be27845400	428
AnnaBridge	172:65be27845400	429	/**
AnnaBridge	172:65be27845400	430	* @}
AnnaBridge	172:65be27845400	431	*/
AnnaBridge	172:65be27845400	432
AnnaBridge	172:65be27845400	433	/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
AnnaBridge	172:65be27845400	434	* @brief Extended Callbacks functions
AnnaBridge	172:65be27845400	435	* @{
AnnaBridge	172:65be27845400	436	*/
AnnaBridge	172:65be27845400	437	/* Extended Callback **********************************************************/
AnnaBridge	172:65be27845400	438	void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim);
AnnaBridge	172:65be27845400	439	void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
AnnaBridge	172:65be27845400	440	/**
AnnaBridge	172:65be27845400	441	* @}
AnnaBridge	172:65be27845400	442	*/
AnnaBridge	172:65be27845400	443
AnnaBridge	172:65be27845400	444	/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
AnnaBridge	172:65be27845400	445	* @brief Extended Peripheral State functions
AnnaBridge	172:65be27845400	446	* @{
AnnaBridge	172:65be27845400	447	*/
AnnaBridge	172:65be27845400	448	/* Extended Peripheral State functions ***************************************/
AnnaBridge	172:65be27845400	449	HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
AnnaBridge	172:65be27845400	450	/**
AnnaBridge	172:65be27845400	451	* @}
AnnaBridge	172:65be27845400	452	*/
AnnaBridge	172:65be27845400	453
AnnaBridge	172:65be27845400	454	/**
AnnaBridge	172:65be27845400	455	* @}
AnnaBridge	172:65be27845400	456	*/
AnnaBridge	172:65be27845400	457	/* End of exported functions -------------------------------------------------*/
AnnaBridge	172:65be27845400	458
AnnaBridge	172:65be27845400	459	/* Private functions----------------------------------------------------------*/
AnnaBridge	172:65be27845400	460	/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
AnnaBridge	172:65be27845400	461	* @{
AnnaBridge	172:65be27845400	462	*/
AnnaBridge	172:65be27845400	463	void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
AnnaBridge	172:65be27845400	464	/**
AnnaBridge	172:65be27845400	465	* @}
AnnaBridge	172:65be27845400	466	*/
AnnaBridge	172:65be27845400	467	/* End of private functions --------------------------------------------------*/
AnnaBridge	172:65be27845400	468
AnnaBridge	172:65be27845400	469	/**
AnnaBridge	172:65be27845400	470	* @}
AnnaBridge	172:65be27845400	471	*/
AnnaBridge	172:65be27845400	472
AnnaBridge	172:65be27845400	473	/**
AnnaBridge	172:65be27845400	474	* @}
AnnaBridge	172:65be27845400	475	*/
AnnaBridge	172:65be27845400	476
AnnaBridge	172:65be27845400	477	#ifdef __cplusplus
AnnaBridge	172:65be27845400	478	}
AnnaBridge	172:65be27845400	479	#endif
AnnaBridge	172:65be27845400	480
AnnaBridge	172:65be27845400	481
AnnaBridge	172:65be27845400	482	#endif /* __STM32L4xx_HAL_TIM_EX_H */
AnnaBridge	172:65be27845400	483
AnnaBridge	172:65be27845400	484	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/