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TARGET_NUCLEO_L4R5ZI_P/TOOLCHAIN_ARM_STD/stm32l4xx_hal_nand.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 172:65be27845400 1 /**
AnnaBridge 172:65be27845400 2 ******************************************************************************
AnnaBridge 172:65be27845400 3 * @file stm32l4xx_hal_nand.h
AnnaBridge 172:65be27845400 4 * @author MCD Application Team
AnnaBridge 172:65be27845400 5 * @brief Header file of NAND HAL module.
AnnaBridge 172:65be27845400 6 ******************************************************************************
AnnaBridge 172:65be27845400 7 * @attention
AnnaBridge 172:65be27845400 8 *
AnnaBridge 172:65be27845400 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 172:65be27845400 10 *
AnnaBridge 172:65be27845400 11 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 172:65be27845400 12 * are permitted provided that the following conditions are met:
AnnaBridge 172:65be27845400 13 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 172:65be27845400 14 * this list of conditions and the following disclaimer.
AnnaBridge 172:65be27845400 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 172:65be27845400 16 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 172:65be27845400 17 * and/or other materials provided with the distribution.
AnnaBridge 172:65be27845400 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 172:65be27845400 19 * may be used to endorse or promote products derived from this software
AnnaBridge 172:65be27845400 20 * without specific prior written permission.
AnnaBridge 172:65be27845400 21 *
AnnaBridge 172:65be27845400 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 172:65be27845400 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 172:65be27845400 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 172:65be27845400 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 172:65be27845400 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 172:65be27845400 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 172:65be27845400 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 172:65be27845400 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 172:65be27845400 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 172:65be27845400 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 172:65be27845400 32 *
AnnaBridge 172:65be27845400 33 ******************************************************************************
AnnaBridge 172:65be27845400 34 */
AnnaBridge 172:65be27845400 35
AnnaBridge 172:65be27845400 36 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 172:65be27845400 37 #ifndef __STM32L4xx_HAL_NAND_H
AnnaBridge 172:65be27845400 38 #define __STM32L4xx_HAL_NAND_H
AnnaBridge 172:65be27845400 39
AnnaBridge 172:65be27845400 40 #ifdef __cplusplus
AnnaBridge 172:65be27845400 41 extern "C" {
AnnaBridge 172:65be27845400 42 #endif
AnnaBridge 172:65be27845400 43
AnnaBridge 172:65be27845400 44 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
AnnaBridge 172:65be27845400 45 defined(STM32L496xx) || defined(STM32L4A6xx) || \
AnnaBridge 172:65be27845400 46 defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
AnnaBridge 172:65be27845400 47
AnnaBridge 172:65be27845400 48 /* Includes ------------------------------------------------------------------*/
AnnaBridge 172:65be27845400 49 #include "stm32l4xx_ll_fmc.h"
AnnaBridge 172:65be27845400 50
AnnaBridge 172:65be27845400 51 /** @addtogroup STM32L4xx_HAL_Driver
AnnaBridge 172:65be27845400 52 * @{
AnnaBridge 172:65be27845400 53 */
AnnaBridge 172:65be27845400 54
AnnaBridge 172:65be27845400 55 /** @addtogroup NAND
AnnaBridge 172:65be27845400 56 * @{
AnnaBridge 172:65be27845400 57 */
AnnaBridge 172:65be27845400 58
AnnaBridge 172:65be27845400 59 /** @addtogroup NAND_Private_Constants
AnnaBridge 172:65be27845400 60 * @{
AnnaBridge 172:65be27845400 61 */
AnnaBridge 172:65be27845400 62
AnnaBridge 172:65be27845400 63 #define NAND_DEVICE FMC_BANK3
AnnaBridge 172:65be27845400 64 #define NAND_WRITE_TIMEOUT ((uint32_t)1000)
AnnaBridge 172:65be27845400 65
AnnaBridge 172:65be27845400 66 #define CMD_AREA ((uint32_t)(1<<16)) /* A16 = CLE high */
AnnaBridge 172:65be27845400 67 #define ADDR_AREA ((uint32_t)(1<<17)) /* A17 = ALE high */
AnnaBridge 172:65be27845400 68
AnnaBridge 172:65be27845400 69 #define NAND_CMD_AREA_A ((uint8_t)0x00)
AnnaBridge 172:65be27845400 70 #define NAND_CMD_AREA_B ((uint8_t)0x01)
AnnaBridge 172:65be27845400 71 #define NAND_CMD_AREA_C ((uint8_t)0x50)
AnnaBridge 172:65be27845400 72 #define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)
AnnaBridge 172:65be27845400 73
AnnaBridge 172:65be27845400 74 #define NAND_CMD_WRITE0 ((uint8_t)0x80)
AnnaBridge 172:65be27845400 75 #define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
AnnaBridge 172:65be27845400 76 #define NAND_CMD_ERASE0 ((uint8_t)0x60)
AnnaBridge 172:65be27845400 77 #define NAND_CMD_ERASE1 ((uint8_t)0xD0)
AnnaBridge 172:65be27845400 78 #define NAND_CMD_READID ((uint8_t)0x90)
AnnaBridge 172:65be27845400 79 #define NAND_CMD_STATUS ((uint8_t)0x70)
AnnaBridge 172:65be27845400 80 #define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
AnnaBridge 172:65be27845400 81 #define NAND_CMD_RESET ((uint8_t)0xFF)
AnnaBridge 172:65be27845400 82
AnnaBridge 172:65be27845400 83 /* NAND memory status */
AnnaBridge 172:65be27845400 84 #define NAND_VALID_ADDRESS ((uint32_t)0x00000100)
AnnaBridge 172:65be27845400 85 #define NAND_INVALID_ADDRESS ((uint32_t)0x00000200)
AnnaBridge 172:65be27845400 86 #define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400)
AnnaBridge 172:65be27845400 87 #define NAND_BUSY ((uint32_t)0x00000000)
AnnaBridge 172:65be27845400 88 #define NAND_ERROR ((uint32_t)0x00000001)
AnnaBridge 172:65be27845400 89 #define NAND_READY ((uint32_t)0x00000040)
AnnaBridge 172:65be27845400 90
AnnaBridge 172:65be27845400 91 /**
AnnaBridge 172:65be27845400 92 * @}
AnnaBridge 172:65be27845400 93 */
AnnaBridge 172:65be27845400 94
AnnaBridge 172:65be27845400 95 /** @addtogroup NAND_Private_Macros
AnnaBridge 172:65be27845400 96 * @{
AnnaBridge 172:65be27845400 97 */
AnnaBridge 172:65be27845400 98
AnnaBridge 172:65be27845400 99 /**
AnnaBridge 172:65be27845400 100 * @brief NAND memory address computation.
AnnaBridge 172:65be27845400 101 * @param __ADDRESS__: NAND memory address.
AnnaBridge 172:65be27845400 102 * @param __HANDLE__: NAND handle.
AnnaBridge 172:65be27845400 103 * @retval NAND Raw address value
AnnaBridge 172:65be27845400 104 */
AnnaBridge 172:65be27845400 105 #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) (((__ADDRESS__)->Page) + \
AnnaBridge 172:65be27845400 106 (((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.ZoneSize)))* ((__HANDLE__)->Info.BlockSize * ((__HANDLE__)->Info.PageSize + (__HANDLE__)->Info.SpareAreaSize))))
AnnaBridge 172:65be27845400 107
AnnaBridge 172:65be27845400 108 /**
AnnaBridge 172:65be27845400 109 * @brief NAND memory address cycling.
AnnaBridge 172:65be27845400 110 * @param __ADDRESS__: NAND memory address.
AnnaBridge 172:65be27845400 111 * @retval NAND address cycling value.
AnnaBridge 172:65be27845400 112 */
AnnaBridge 172:65be27845400 113 #define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
AnnaBridge 172:65be27845400 114 #define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */
AnnaBridge 172:65be27845400 115 #define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */
AnnaBridge 172:65be27845400 116 #define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */
AnnaBridge 172:65be27845400 117
AnnaBridge 172:65be27845400 118 /**
AnnaBridge 172:65be27845400 119 * @}
AnnaBridge 172:65be27845400 120 */
AnnaBridge 172:65be27845400 121
AnnaBridge 172:65be27845400 122 /* Exported typedef ----------------------------------------------------------*/
AnnaBridge 172:65be27845400 123 /* Exported types ------------------------------------------------------------*/
AnnaBridge 172:65be27845400 124 /** @defgroup NAND_Exported_Types NAND Exported Types
AnnaBridge 172:65be27845400 125 * @{
AnnaBridge 172:65be27845400 126 */
AnnaBridge 172:65be27845400 127
AnnaBridge 172:65be27845400 128 /**
AnnaBridge 172:65be27845400 129 * @brief HAL NAND State structures definition
AnnaBridge 172:65be27845400 130 */
AnnaBridge 172:65be27845400 131 typedef enum
AnnaBridge 172:65be27845400 132 {
AnnaBridge 172:65be27845400 133 HAL_NAND_STATE_RESET = 0x00, /*!< NAND not yet initialized or disabled */
AnnaBridge 172:65be27845400 134 HAL_NAND_STATE_READY = 0x01, /*!< NAND initialized and ready for use */
AnnaBridge 172:65be27845400 135 HAL_NAND_STATE_BUSY = 0x02, /*!< NAND internal process is ongoing */
AnnaBridge 172:65be27845400 136 HAL_NAND_STATE_ERROR = 0x03 /*!< NAND error state */
AnnaBridge 172:65be27845400 137 }HAL_NAND_StateTypeDef;
AnnaBridge 172:65be27845400 138
AnnaBridge 172:65be27845400 139 /**
AnnaBridge 172:65be27845400 140 * @brief NAND Memory electronic signature Structure definition
AnnaBridge 172:65be27845400 141 */
AnnaBridge 172:65be27845400 142 typedef struct
AnnaBridge 172:65be27845400 143 {
AnnaBridge 172:65be27845400 144 /*<! NAND memory electronic signature maker and device IDs */
AnnaBridge 172:65be27845400 145
AnnaBridge 172:65be27845400 146 uint8_t Maker_Id;
AnnaBridge 172:65be27845400 147
AnnaBridge 172:65be27845400 148 uint8_t Device_Id;
AnnaBridge 172:65be27845400 149
AnnaBridge 172:65be27845400 150 uint8_t Third_Id;
AnnaBridge 172:65be27845400 151
AnnaBridge 172:65be27845400 152 uint8_t Fourth_Id;
AnnaBridge 172:65be27845400 153 }NAND_IDTypeDef;
AnnaBridge 172:65be27845400 154
AnnaBridge 172:65be27845400 155 /**
AnnaBridge 172:65be27845400 156 * @brief NAND Memory address Structure definition
AnnaBridge 172:65be27845400 157 */
AnnaBridge 172:65be27845400 158 typedef struct
AnnaBridge 172:65be27845400 159 {
AnnaBridge 172:65be27845400 160 uint16_t Page; /*!< NAND memory Page address */
AnnaBridge 172:65be27845400 161
AnnaBridge 172:65be27845400 162 uint16_t Zone; /*!< NAND memory Zone address */
AnnaBridge 172:65be27845400 163
AnnaBridge 172:65be27845400 164 uint16_t Block; /*!< NAND memory Block address */
AnnaBridge 172:65be27845400 165
AnnaBridge 172:65be27845400 166 }NAND_AddressTypeDef;
AnnaBridge 172:65be27845400 167
AnnaBridge 172:65be27845400 168 /**
AnnaBridge 172:65be27845400 169 * @brief NAND Memory info Structure definition
AnnaBridge 172:65be27845400 170 */
AnnaBridge 172:65be27845400 171 typedef struct
AnnaBridge 172:65be27845400 172 {
AnnaBridge 172:65be27845400 173 uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in K. bytes */
AnnaBridge 172:65be27845400 174
AnnaBridge 172:65be27845400 175 uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in K. bytes */
AnnaBridge 172:65be27845400 176
AnnaBridge 172:65be27845400 177 uint32_t BlockSize; /*!< NAND memory block size number of pages */
AnnaBridge 172:65be27845400 178
AnnaBridge 172:65be27845400 179 uint32_t BlockNbr; /*!< NAND memory number of blocks */
AnnaBridge 172:65be27845400 180
AnnaBridge 172:65be27845400 181 uint32_t ZoneSize; /*!< NAND memory zone size measured in number of blocks */
AnnaBridge 172:65be27845400 182 }NAND_InfoTypeDef;
AnnaBridge 172:65be27845400 183
AnnaBridge 172:65be27845400 184 /**
AnnaBridge 172:65be27845400 185 * @brief NAND handle Structure definition
AnnaBridge 172:65be27845400 186 */
AnnaBridge 172:65be27845400 187 typedef struct
AnnaBridge 172:65be27845400 188 {
AnnaBridge 172:65be27845400 189 FMC_NAND_TypeDef *Instance; /*!< Register base address */
AnnaBridge 172:65be27845400 190
AnnaBridge 172:65be27845400 191 FMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */
AnnaBridge 172:65be27845400 192
AnnaBridge 172:65be27845400 193 HAL_LockTypeDef Lock; /*!< NAND locking object */
AnnaBridge 172:65be27845400 194
AnnaBridge 172:65be27845400 195 __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */
AnnaBridge 172:65be27845400 196
AnnaBridge 172:65be27845400 197 NAND_InfoTypeDef Info; /*!< NAND characteristic information structure */
AnnaBridge 172:65be27845400 198 }NAND_HandleTypeDef;
AnnaBridge 172:65be27845400 199
AnnaBridge 172:65be27845400 200 /**
AnnaBridge 172:65be27845400 201 * @}
AnnaBridge 172:65be27845400 202 */
AnnaBridge 172:65be27845400 203
AnnaBridge 172:65be27845400 204 /* Exported constants --------------------------------------------------------*/
AnnaBridge 172:65be27845400 205 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 172:65be27845400 206 /** @defgroup NAND_Exported_Macros NAND Exported Macros
AnnaBridge 172:65be27845400 207 * @{
AnnaBridge 172:65be27845400 208 */
AnnaBridge 172:65be27845400 209
AnnaBridge 172:65be27845400 210 /** @brief Reset NAND handle state.
AnnaBridge 172:65be27845400 211 * @param __HANDLE__: specifies the NAND handle.
AnnaBridge 172:65be27845400 212 * @retval None
AnnaBridge 172:65be27845400 213 */
AnnaBridge 172:65be27845400 214 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
AnnaBridge 172:65be27845400 215
AnnaBridge 172:65be27845400 216 /**
AnnaBridge 172:65be27845400 217 * @}
AnnaBridge 172:65be27845400 218 */
AnnaBridge 172:65be27845400 219
AnnaBridge 172:65be27845400 220 /* Exported functions --------------------------------------------------------*/
AnnaBridge 172:65be27845400 221 /** @addtogroup NAND_Exported_Functions NAND Exported Functions
AnnaBridge 172:65be27845400 222 * @{
AnnaBridge 172:65be27845400 223 */
AnnaBridge 172:65be27845400 224
AnnaBridge 172:65be27845400 225 /** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
AnnaBridge 172:65be27845400 226 * @{
AnnaBridge 172:65be27845400 227 */
AnnaBridge 172:65be27845400 228
AnnaBridge 172:65be27845400 229 /* Initialization/de-initialization functions ********************************/
AnnaBridge 172:65be27845400 230 HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
AnnaBridge 172:65be27845400 231 HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
AnnaBridge 172:65be27845400 232 void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
AnnaBridge 172:65be27845400 233 void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
AnnaBridge 172:65be27845400 234 void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
AnnaBridge 172:65be27845400 235 void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
AnnaBridge 172:65be27845400 236
AnnaBridge 172:65be27845400 237 /**
AnnaBridge 172:65be27845400 238 * @}
AnnaBridge 172:65be27845400 239 */
AnnaBridge 172:65be27845400 240
AnnaBridge 172:65be27845400 241 /** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
AnnaBridge 172:65be27845400 242 * @{
AnnaBridge 172:65be27845400 243 */
AnnaBridge 172:65be27845400 244
AnnaBridge 172:65be27845400 245 /* IO operation functions ****************************************************/
AnnaBridge 172:65be27845400 246 HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
AnnaBridge 172:65be27845400 247 HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
AnnaBridge 172:65be27845400 248 HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
AnnaBridge 172:65be27845400 249 HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
AnnaBridge 172:65be27845400 250 HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
AnnaBridge 172:65be27845400 251 HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
AnnaBridge 172:65be27845400 252 HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
AnnaBridge 172:65be27845400 253 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
AnnaBridge 172:65be27845400 254 uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
AnnaBridge 172:65be27845400 255
AnnaBridge 172:65be27845400 256 /**
AnnaBridge 172:65be27845400 257 * @}
AnnaBridge 172:65be27845400 258 */
AnnaBridge 172:65be27845400 259
AnnaBridge 172:65be27845400 260 /** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
AnnaBridge 172:65be27845400 261 * @{
AnnaBridge 172:65be27845400 262 */
AnnaBridge 172:65be27845400 263
AnnaBridge 172:65be27845400 264 /* NAND Control functions ****************************************************/
AnnaBridge 172:65be27845400 265 HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
AnnaBridge 172:65be27845400 266 HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
AnnaBridge 172:65be27845400 267 HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
AnnaBridge 172:65be27845400 268
AnnaBridge 172:65be27845400 269 /**
AnnaBridge 172:65be27845400 270 * @}
AnnaBridge 172:65be27845400 271 */
AnnaBridge 172:65be27845400 272
AnnaBridge 172:65be27845400 273 /** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
AnnaBridge 172:65be27845400 274 * @{
AnnaBridge 172:65be27845400 275 */
AnnaBridge 172:65be27845400 276
AnnaBridge 172:65be27845400 277 /* NAND State functions *******************************************************/
AnnaBridge 172:65be27845400 278 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
AnnaBridge 172:65be27845400 279 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
AnnaBridge 172:65be27845400 280
AnnaBridge 172:65be27845400 281 /**
AnnaBridge 172:65be27845400 282 * @}
AnnaBridge 172:65be27845400 283 */
AnnaBridge 172:65be27845400 284
AnnaBridge 172:65be27845400 285 /**
AnnaBridge 172:65be27845400 286 * @}
AnnaBridge 172:65be27845400 287 */
AnnaBridge 172:65be27845400 288
AnnaBridge 172:65be27845400 289 /**
AnnaBridge 172:65be27845400 290 * @}
AnnaBridge 172:65be27845400 291 */
AnnaBridge 172:65be27845400 292
AnnaBridge 172:65be27845400 293 /**
AnnaBridge 172:65be27845400 294 * @}
AnnaBridge 172:65be27845400 295 */
AnnaBridge 172:65be27845400 296
AnnaBridge 172:65be27845400 297 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
AnnaBridge 172:65be27845400 298 /* STM32L496xx || STM32L4A6xx || */
AnnaBridge 172:65be27845400 299 /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
AnnaBridge 172:65be27845400 300
AnnaBridge 172:65be27845400 301 #ifdef __cplusplus
AnnaBridge 172:65be27845400 302 }
AnnaBridge 172:65be27845400 303 #endif
AnnaBridge 172:65be27845400 304
AnnaBridge 172:65be27845400 305 #endif /* __STM32L4xx_HAL_NAND_H */
AnnaBridge 172:65be27845400 306
AnnaBridge 172:65be27845400 307 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/