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TARGET_NUCLEO_L4R5ZI_P/TOOLCHAIN_ARM_STD/stm32l4xx_hal.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 172:65be27845400 | 1 | /** |
| AnnaBridge | 172:65be27845400 | 2 | ****************************************************************************** |
| AnnaBridge | 172:65be27845400 | 3 | * @file stm32l4xx_hal.h |
| AnnaBridge | 172:65be27845400 | 4 | * @author MCD Application Team |
| AnnaBridge | 172:65be27845400 | 5 | * @brief This file contains all the functions prototypes for the HAL |
| AnnaBridge | 172:65be27845400 | 6 | * module driver. |
| AnnaBridge | 172:65be27845400 | 7 | ****************************************************************************** |
| AnnaBridge | 172:65be27845400 | 8 | * @attention |
| AnnaBridge | 172:65be27845400 | 9 | * |
| AnnaBridge | 172:65be27845400 | 10 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
| AnnaBridge | 172:65be27845400 | 11 | * |
| AnnaBridge | 172:65be27845400 | 12 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 172:65be27845400 | 13 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 172:65be27845400 | 14 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 172:65be27845400 | 15 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 172:65be27845400 | 16 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 172:65be27845400 | 17 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 172:65be27845400 | 18 | * and/or other materials provided with the distribution. |
| AnnaBridge | 172:65be27845400 | 19 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 172:65be27845400 | 20 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 172:65be27845400 | 21 | * without specific prior written permission. |
| AnnaBridge | 172:65be27845400 | 22 | * |
| AnnaBridge | 172:65be27845400 | 23 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 172:65be27845400 | 24 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 172:65be27845400 | 25 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 172:65be27845400 | 26 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 172:65be27845400 | 27 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 172:65be27845400 | 28 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 172:65be27845400 | 29 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 172:65be27845400 | 30 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 172:65be27845400 | 31 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 172:65be27845400 | 32 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 172:65be27845400 | 33 | * |
| AnnaBridge | 172:65be27845400 | 34 | ****************************************************************************** |
| AnnaBridge | 172:65be27845400 | 35 | */ |
| AnnaBridge | 172:65be27845400 | 36 | |
| AnnaBridge | 172:65be27845400 | 37 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 38 | #ifndef __STM32L4xx_HAL_H |
| AnnaBridge | 172:65be27845400 | 39 | #define __STM32L4xx_HAL_H |
| AnnaBridge | 172:65be27845400 | 40 | |
| AnnaBridge | 172:65be27845400 | 41 | #ifdef __cplusplus |
| AnnaBridge | 172:65be27845400 | 42 | extern "C" { |
| AnnaBridge | 172:65be27845400 | 43 | #endif |
| AnnaBridge | 172:65be27845400 | 44 | |
| AnnaBridge | 172:65be27845400 | 45 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 46 | #include "stm32l4xx_hal_conf.h" |
| AnnaBridge | 172:65be27845400 | 47 | |
| AnnaBridge | 172:65be27845400 | 48 | /** @addtogroup STM32L4xx_HAL_Driver |
| AnnaBridge | 172:65be27845400 | 49 | * @{ |
| AnnaBridge | 172:65be27845400 | 50 | */ |
| AnnaBridge | 172:65be27845400 | 51 | |
| AnnaBridge | 172:65be27845400 | 52 | /** @addtogroup HAL |
| AnnaBridge | 172:65be27845400 | 53 | * @{ |
| AnnaBridge | 172:65be27845400 | 54 | */ |
| AnnaBridge | 172:65be27845400 | 55 | |
| AnnaBridge | 172:65be27845400 | 56 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 57 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 58 | /** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants |
| AnnaBridge | 172:65be27845400 | 59 | * @{ |
| AnnaBridge | 172:65be27845400 | 60 | */ |
| AnnaBridge | 172:65be27845400 | 61 | |
| AnnaBridge | 172:65be27845400 | 62 | /** @defgroup SYSCFG_BootMode Boot Mode |
| AnnaBridge | 172:65be27845400 | 63 | * @{ |
| AnnaBridge | 172:65be27845400 | 64 | */ |
| AnnaBridge | 172:65be27845400 | 65 | #define SYSCFG_BOOT_MAINFLASH ((uint32_t)0x00000000) |
| AnnaBridge | 172:65be27845400 | 66 | #define SYSCFG_BOOT_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 |
| AnnaBridge | 172:65be27845400 | 67 | |
| AnnaBridge | 172:65be27845400 | 68 | #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ |
| AnnaBridge | 172:65be27845400 | 69 | defined (STM32L496xx) || defined (STM32L4A6xx) || \ |
| AnnaBridge | 172:65be27845400 | 70 | defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
| AnnaBridge | 172:65be27845400 | 71 | #define SYSCFG_BOOT_FMC SYSCFG_MEMRMP_MEM_MODE_1 |
| AnnaBridge | 172:65be27845400 | 72 | #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ |
| AnnaBridge | 172:65be27845400 | 73 | /* STM32L496xx || STM32L4A6xx || */ |
| AnnaBridge | 172:65be27845400 | 74 | /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ |
| AnnaBridge | 172:65be27845400 | 75 | |
| AnnaBridge | 172:65be27845400 | 76 | #define SYSCFG_BOOT_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) |
| AnnaBridge | 172:65be27845400 | 77 | |
| AnnaBridge | 172:65be27845400 | 78 | #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
| AnnaBridge | 172:65be27845400 | 79 | #define SYSCFG_BOOT_OCTOPSPI1 (SYSCFG_MEMRMP_MEM_MODE_2) |
| AnnaBridge | 172:65be27845400 | 80 | #define SYSCFG_BOOT_OCTOPSPI2 (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_0) |
| AnnaBridge | 172:65be27845400 | 81 | #else |
| AnnaBridge | 172:65be27845400 | 82 | #define SYSCFG_BOOT_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1) |
| AnnaBridge | 172:65be27845400 | 83 | #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ |
| AnnaBridge | 172:65be27845400 | 84 | |
| AnnaBridge | 172:65be27845400 | 85 | /** |
| AnnaBridge | 172:65be27845400 | 86 | * @} |
| AnnaBridge | 172:65be27845400 | 87 | */ |
| AnnaBridge | 172:65be27845400 | 88 | |
| AnnaBridge | 172:65be27845400 | 89 | /** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts |
| AnnaBridge | 172:65be27845400 | 90 | * @{ |
| AnnaBridge | 172:65be27845400 | 91 | */ |
| AnnaBridge | 172:65be27845400 | 92 | #define SYSCFG_IT_FPU_IOC SYSCFG_CFGR1_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt */ |
| AnnaBridge | 172:65be27845400 | 93 | #define SYSCFG_IT_FPU_DZC SYSCFG_CFGR1_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */ |
| AnnaBridge | 172:65be27845400 | 94 | #define SYSCFG_IT_FPU_UFC SYSCFG_CFGR1_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */ |
| AnnaBridge | 172:65be27845400 | 95 | #define SYSCFG_IT_FPU_OFC SYSCFG_CFGR1_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */ |
| AnnaBridge | 172:65be27845400 | 96 | #define SYSCFG_IT_FPU_IDC SYSCFG_CFGR1_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */ |
| AnnaBridge | 172:65be27845400 | 97 | #define SYSCFG_IT_FPU_IXC SYSCFG_CFGR1_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */ |
| AnnaBridge | 172:65be27845400 | 98 | |
| AnnaBridge | 172:65be27845400 | 99 | /** |
| AnnaBridge | 172:65be27845400 | 100 | * @} |
| AnnaBridge | 172:65be27845400 | 101 | */ |
| AnnaBridge | 172:65be27845400 | 102 | |
| AnnaBridge | 172:65be27845400 | 103 | /** @defgroup SYSCFG_SRAM2WRP SRAM2 Page Write protection (0 to 31) |
| AnnaBridge | 172:65be27845400 | 104 | * @{ |
| AnnaBridge | 172:65be27845400 | 105 | */ |
| AnnaBridge | 172:65be27845400 | 106 | #define SYSCFG_SRAM2WRP_PAGE0 SYSCFG_SWPR_PAGE0 /*!< SRAM2 Write protection page 0 */ |
| AnnaBridge | 172:65be27845400 | 107 | #define SYSCFG_SRAM2WRP_PAGE1 SYSCFG_SWPR_PAGE1 /*!< SRAM2 Write protection page 1 */ |
| AnnaBridge | 172:65be27845400 | 108 | #define SYSCFG_SRAM2WRP_PAGE2 SYSCFG_SWPR_PAGE2 /*!< SRAM2 Write protection page 2 */ |
| AnnaBridge | 172:65be27845400 | 109 | #define SYSCFG_SRAM2WRP_PAGE3 SYSCFG_SWPR_PAGE3 /*!< SRAM2 Write protection page 3 */ |
| AnnaBridge | 172:65be27845400 | 110 | #define SYSCFG_SRAM2WRP_PAGE4 SYSCFG_SWPR_PAGE4 /*!< SRAM2 Write protection page 4 */ |
| AnnaBridge | 172:65be27845400 | 111 | #define SYSCFG_SRAM2WRP_PAGE5 SYSCFG_SWPR_PAGE5 /*!< SRAM2 Write protection page 5 */ |
| AnnaBridge | 172:65be27845400 | 112 | #define SYSCFG_SRAM2WRP_PAGE6 SYSCFG_SWPR_PAGE6 /*!< SRAM2 Write protection page 6 */ |
| AnnaBridge | 172:65be27845400 | 113 | #define SYSCFG_SRAM2WRP_PAGE7 SYSCFG_SWPR_PAGE7 /*!< SRAM2 Write protection page 7 */ |
| AnnaBridge | 172:65be27845400 | 114 | #define SYSCFG_SRAM2WRP_PAGE8 SYSCFG_SWPR_PAGE8 /*!< SRAM2 Write protection page 8 */ |
| AnnaBridge | 172:65be27845400 | 115 | #define SYSCFG_SRAM2WRP_PAGE9 SYSCFG_SWPR_PAGE9 /*!< SRAM2 Write protection page 9 */ |
| AnnaBridge | 172:65be27845400 | 116 | #define SYSCFG_SRAM2WRP_PAGE10 SYSCFG_SWPR_PAGE10 /*!< SRAM2 Write protection page 10 */ |
| AnnaBridge | 172:65be27845400 | 117 | #define SYSCFG_SRAM2WRP_PAGE11 SYSCFG_SWPR_PAGE11 /*!< SRAM2 Write protection page 11 */ |
| AnnaBridge | 172:65be27845400 | 118 | #define SYSCFG_SRAM2WRP_PAGE12 SYSCFG_SWPR_PAGE12 /*!< SRAM2 Write protection page 12 */ |
| AnnaBridge | 172:65be27845400 | 119 | #define SYSCFG_SRAM2WRP_PAGE13 SYSCFG_SWPR_PAGE13 /*!< SRAM2 Write protection page 13 */ |
| AnnaBridge | 172:65be27845400 | 120 | #define SYSCFG_SRAM2WRP_PAGE14 SYSCFG_SWPR_PAGE14 /*!< SRAM2 Write protection page 14 */ |
| AnnaBridge | 172:65be27845400 | 121 | #define SYSCFG_SRAM2WRP_PAGE15 SYSCFG_SWPR_PAGE15 /*!< SRAM2 Write protection page 15 */ |
| AnnaBridge | 172:65be27845400 | 122 | #if defined(SYSCFG_SWPR_PAGE31) |
| AnnaBridge | 172:65be27845400 | 123 | #define SYSCFG_SRAM2WRP_PAGE16 SYSCFG_SWPR_PAGE16 /*!< SRAM2 Write protection page 16 */ |
| AnnaBridge | 172:65be27845400 | 124 | #define SYSCFG_SRAM2WRP_PAGE17 SYSCFG_SWPR_PAGE17 /*!< SRAM2 Write protection page 17 */ |
| AnnaBridge | 172:65be27845400 | 125 | #define SYSCFG_SRAM2WRP_PAGE18 SYSCFG_SWPR_PAGE18 /*!< SRAM2 Write protection page 18 */ |
| AnnaBridge | 172:65be27845400 | 126 | #define SYSCFG_SRAM2WRP_PAGE19 SYSCFG_SWPR_PAGE19 /*!< SRAM2 Write protection page 19 */ |
| AnnaBridge | 172:65be27845400 | 127 | #define SYSCFG_SRAM2WRP_PAGE20 SYSCFG_SWPR_PAGE20 /*!< SRAM2 Write protection page 20 */ |
| AnnaBridge | 172:65be27845400 | 128 | #define SYSCFG_SRAM2WRP_PAGE21 SYSCFG_SWPR_PAGE21 /*!< SRAM2 Write protection page 21 */ |
| AnnaBridge | 172:65be27845400 | 129 | #define SYSCFG_SRAM2WRP_PAGE22 SYSCFG_SWPR_PAGE22 /*!< SRAM2 Write protection page 22 */ |
| AnnaBridge | 172:65be27845400 | 130 | #define SYSCFG_SRAM2WRP_PAGE23 SYSCFG_SWPR_PAGE23 /*!< SRAM2 Write protection page 23 */ |
| AnnaBridge | 172:65be27845400 | 131 | #define SYSCFG_SRAM2WRP_PAGE24 SYSCFG_SWPR_PAGE24 /*!< SRAM2 Write protection page 24 */ |
| AnnaBridge | 172:65be27845400 | 132 | #define SYSCFG_SRAM2WRP_PAGE25 SYSCFG_SWPR_PAGE25 /*!< SRAM2 Write protection page 25 */ |
| AnnaBridge | 172:65be27845400 | 133 | #define SYSCFG_SRAM2WRP_PAGE26 SYSCFG_SWPR_PAGE26 /*!< SRAM2 Write protection page 26 */ |
| AnnaBridge | 172:65be27845400 | 134 | #define SYSCFG_SRAM2WRP_PAGE27 SYSCFG_SWPR_PAGE27 /*!< SRAM2 Write protection page 27 */ |
| AnnaBridge | 172:65be27845400 | 135 | #define SYSCFG_SRAM2WRP_PAGE28 SYSCFG_SWPR_PAGE28 /*!< SRAM2 Write protection page 28 */ |
| AnnaBridge | 172:65be27845400 | 136 | #define SYSCFG_SRAM2WRP_PAGE29 SYSCFG_SWPR_PAGE29 /*!< SRAM2 Write protection page 29 */ |
| AnnaBridge | 172:65be27845400 | 137 | #define SYSCFG_SRAM2WRP_PAGE30 SYSCFG_SWPR_PAGE30 /*!< SRAM2 Write protection page 30 */ |
| AnnaBridge | 172:65be27845400 | 138 | #define SYSCFG_SRAM2WRP_PAGE31 SYSCFG_SWPR_PAGE31 /*!< SRAM2 Write protection page 31 */ |
| AnnaBridge | 172:65be27845400 | 139 | #endif /* SYSCFG_SWPR_PAGE31 */ |
| AnnaBridge | 172:65be27845400 | 140 | |
| AnnaBridge | 172:65be27845400 | 141 | /** |
| AnnaBridge | 172:65be27845400 | 142 | * @} |
| AnnaBridge | 172:65be27845400 | 143 | */ |
| AnnaBridge | 172:65be27845400 | 144 | |
| AnnaBridge | 172:65be27845400 | 145 | #if defined(SYSCFG_SWPR2_PAGE63) |
| AnnaBridge | 172:65be27845400 | 146 | /** @defgroup SYSCFG_SRAM2WRP_32_63 SRAM2 Page Write protection (32 to 63) |
| AnnaBridge | 172:65be27845400 | 147 | * @{ |
| AnnaBridge | 172:65be27845400 | 148 | */ |
| AnnaBridge | 172:65be27845400 | 149 | #define SYSCFG_SRAM2WRP_PAGE32 SYSCFG_SWPR2_PAGE32 /*!< SRAM2 Write protection page 32 */ |
| AnnaBridge | 172:65be27845400 | 150 | #define SYSCFG_SRAM2WRP_PAGE33 SYSCFG_SWPR2_PAGE33 /*!< SRAM2 Write protection page 33 */ |
| AnnaBridge | 172:65be27845400 | 151 | #define SYSCFG_SRAM2WRP_PAGE34 SYSCFG_SWPR2_PAGE34 /*!< SRAM2 Write protection page 34 */ |
| AnnaBridge | 172:65be27845400 | 152 | #define SYSCFG_SRAM2WRP_PAGE35 SYSCFG_SWPR2_PAGE35 /*!< SRAM2 Write protection page 35 */ |
| AnnaBridge | 172:65be27845400 | 153 | #define SYSCFG_SRAM2WRP_PAGE36 SYSCFG_SWPR2_PAGE36 /*!< SRAM2 Write protection page 36 */ |
| AnnaBridge | 172:65be27845400 | 154 | #define SYSCFG_SRAM2WRP_PAGE37 SYSCFG_SWPR2_PAGE37 /*!< SRAM2 Write protection page 37 */ |
| AnnaBridge | 172:65be27845400 | 155 | #define SYSCFG_SRAM2WRP_PAGE38 SYSCFG_SWPR2_PAGE38 /*!< SRAM2 Write protection page 38 */ |
| AnnaBridge | 172:65be27845400 | 156 | #define SYSCFG_SRAM2WRP_PAGE39 SYSCFG_SWPR2_PAGE39 /*!< SRAM2 Write protection page 39 */ |
| AnnaBridge | 172:65be27845400 | 157 | #define SYSCFG_SRAM2WRP_PAGE40 SYSCFG_SWPR2_PAGE40 /*!< SRAM2 Write protection page 40 */ |
| AnnaBridge | 172:65be27845400 | 158 | #define SYSCFG_SRAM2WRP_PAGE41 SYSCFG_SWPR2_PAGE41 /*!< SRAM2 Write protection page 41 */ |
| AnnaBridge | 172:65be27845400 | 159 | #define SYSCFG_SRAM2WRP_PAGE42 SYSCFG_SWPR2_PAGE42 /*!< SRAM2 Write protection page 42 */ |
| AnnaBridge | 172:65be27845400 | 160 | #define SYSCFG_SRAM2WRP_PAGE43 SYSCFG_SWPR2_PAGE43 /*!< SRAM2 Write protection page 43 */ |
| AnnaBridge | 172:65be27845400 | 161 | #define SYSCFG_SRAM2WRP_PAGE44 SYSCFG_SWPR2_PAGE44 /*!< SRAM2 Write protection page 44 */ |
| AnnaBridge | 172:65be27845400 | 162 | #define SYSCFG_SRAM2WRP_PAGE45 SYSCFG_SWPR2_PAGE45 /*!< SRAM2 Write protection page 45 */ |
| AnnaBridge | 172:65be27845400 | 163 | #define SYSCFG_SRAM2WRP_PAGE46 SYSCFG_SWPR2_PAGE46 /*!< SRAM2 Write protection page 46 */ |
| AnnaBridge | 172:65be27845400 | 164 | #define SYSCFG_SRAM2WRP_PAGE47 SYSCFG_SWPR2_PAGE47 /*!< SRAM2 Write protection page 47 */ |
| AnnaBridge | 172:65be27845400 | 165 | #define SYSCFG_SRAM2WRP_PAGE48 SYSCFG_SWPR2_PAGE48 /*!< SRAM2 Write protection page 48 */ |
| AnnaBridge | 172:65be27845400 | 166 | #define SYSCFG_SRAM2WRP_PAGE49 SYSCFG_SWPR2_PAGE49 /*!< SRAM2 Write protection page 49 */ |
| AnnaBridge | 172:65be27845400 | 167 | #define SYSCFG_SRAM2WRP_PAGE50 SYSCFG_SWPR2_PAGE50 /*!< SRAM2 Write protection page 50 */ |
| AnnaBridge | 172:65be27845400 | 168 | #define SYSCFG_SRAM2WRP_PAGE51 SYSCFG_SWPR2_PAGE51 /*!< SRAM2 Write protection page 51 */ |
| AnnaBridge | 172:65be27845400 | 169 | #define SYSCFG_SRAM2WRP_PAGE52 SYSCFG_SWPR2_PAGE52 /*!< SRAM2 Write protection page 52 */ |
| AnnaBridge | 172:65be27845400 | 170 | #define SYSCFG_SRAM2WRP_PAGE53 SYSCFG_SWPR2_PAGE53 /*!< SRAM2 Write protection page 53 */ |
| AnnaBridge | 172:65be27845400 | 171 | #define SYSCFG_SRAM2WRP_PAGE54 SYSCFG_SWPR2_PAGE54 /*!< SRAM2 Write protection page 54 */ |
| AnnaBridge | 172:65be27845400 | 172 | #define SYSCFG_SRAM2WRP_PAGE55 SYSCFG_SWPR2_PAGE55 /*!< SRAM2 Write protection page 55 */ |
| AnnaBridge | 172:65be27845400 | 173 | #define SYSCFG_SRAM2WRP_PAGE56 SYSCFG_SWPR2_PAGE56 /*!< SRAM2 Write protection page 56 */ |
| AnnaBridge | 172:65be27845400 | 174 | #define SYSCFG_SRAM2WRP_PAGE57 SYSCFG_SWPR2_PAGE57 /*!< SRAM2 Write protection page 57 */ |
| AnnaBridge | 172:65be27845400 | 175 | #define SYSCFG_SRAM2WRP_PAGE58 SYSCFG_SWPR2_PAGE58 /*!< SRAM2 Write protection page 58 */ |
| AnnaBridge | 172:65be27845400 | 176 | #define SYSCFG_SRAM2WRP_PAGE59 SYSCFG_SWPR2_PAGE59 /*!< SRAM2 Write protection page 59 */ |
| AnnaBridge | 172:65be27845400 | 177 | #define SYSCFG_SRAM2WRP_PAGE60 SYSCFG_SWPR2_PAGE60 /*!< SRAM2 Write protection page 60 */ |
| AnnaBridge | 172:65be27845400 | 178 | #define SYSCFG_SRAM2WRP_PAGE61 SYSCFG_SWPR2_PAGE61 /*!< SRAM2 Write protection page 61 */ |
| AnnaBridge | 172:65be27845400 | 179 | #define SYSCFG_SRAM2WRP_PAGE62 SYSCFG_SWPR2_PAGE62 /*!< SRAM2 Write protection page 62 */ |
| AnnaBridge | 172:65be27845400 | 180 | #define SYSCFG_SRAM2WRP_PAGE63 SYSCFG_SWPR2_PAGE63 /*!< SRAM2 Write protection page 63 */ |
| AnnaBridge | 172:65be27845400 | 181 | |
| AnnaBridge | 172:65be27845400 | 182 | /** |
| AnnaBridge | 172:65be27845400 | 183 | * @} |
| AnnaBridge | 172:65be27845400 | 184 | */ |
| AnnaBridge | 172:65be27845400 | 185 | #endif /* SYSCFG_SWPR2_PAGE63 */ |
| AnnaBridge | 172:65be27845400 | 186 | |
| AnnaBridge | 172:65be27845400 | 187 | #if defined(VREFBUF) |
| AnnaBridge | 172:65be27845400 | 188 | /** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale |
| AnnaBridge | 172:65be27845400 | 189 | * @{ |
| AnnaBridge | 172:65be27845400 | 190 | */ |
| AnnaBridge | 172:65be27845400 | 191 | #define SYSCFG_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */ |
| AnnaBridge | 172:65be27845400 | 192 | #define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /*!< Voltage reference scale 1 (VREF_OUT2) */ |
| AnnaBridge | 172:65be27845400 | 193 | |
| AnnaBridge | 172:65be27845400 | 194 | /** |
| AnnaBridge | 172:65be27845400 | 195 | * @} |
| AnnaBridge | 172:65be27845400 | 196 | */ |
| AnnaBridge | 172:65be27845400 | 197 | |
| AnnaBridge | 172:65be27845400 | 198 | /** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance |
| AnnaBridge | 172:65be27845400 | 199 | * @{ |
| AnnaBridge | 172:65be27845400 | 200 | */ |
| AnnaBridge | 172:65be27845400 | 201 | #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to Voltage reference buffer output */ |
| AnnaBridge | 172:65be27845400 | 202 | #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */ |
| AnnaBridge | 172:65be27845400 | 203 | |
| AnnaBridge | 172:65be27845400 | 204 | /** |
| AnnaBridge | 172:65be27845400 | 205 | * @} |
| AnnaBridge | 172:65be27845400 | 206 | */ |
| AnnaBridge | 172:65be27845400 | 207 | #endif /* VREFBUF */ |
| AnnaBridge | 172:65be27845400 | 208 | |
| AnnaBridge | 172:65be27845400 | 209 | /** @defgroup SYSCFG_flags_definition Flags |
| AnnaBridge | 172:65be27845400 | 210 | * @{ |
| AnnaBridge | 172:65be27845400 | 211 | */ |
| AnnaBridge | 172:65be27845400 | 212 | |
| AnnaBridge | 172:65be27845400 | 213 | #define SYSCFG_FLAG_SRAM2_PE SYSCFG_CFGR2_SPF /*!< SRAM2 parity error */ |
| AnnaBridge | 172:65be27845400 | 214 | #define SYSCFG_FLAG_SRAM2_BUSY SYSCFG_SCSR_SRAM2BSY /*!< SRAM2 busy by erase operation */ |
| AnnaBridge | 172:65be27845400 | 215 | |
| AnnaBridge | 172:65be27845400 | 216 | /** |
| AnnaBridge | 172:65be27845400 | 217 | * @} |
| AnnaBridge | 172:65be27845400 | 218 | */ |
| AnnaBridge | 172:65be27845400 | 219 | |
| AnnaBridge | 172:65be27845400 | 220 | /** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO |
| AnnaBridge | 172:65be27845400 | 221 | * @{ |
| AnnaBridge | 172:65be27845400 | 222 | */ |
| AnnaBridge | 172:65be27845400 | 223 | |
| AnnaBridge | 172:65be27845400 | 224 | /** @brief Fast-mode Plus driving capability on a specific GPIO |
| AnnaBridge | 172:65be27845400 | 225 | */ |
| AnnaBridge | 172:65be27845400 | 226 | #define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */ |
| AnnaBridge | 172:65be27845400 | 227 | #define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */ |
| AnnaBridge | 172:65be27845400 | 228 | #if defined(SYSCFG_CFGR1_I2C_PB8_FMP) |
| AnnaBridge | 172:65be27845400 | 229 | #define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */ |
| AnnaBridge | 172:65be27845400 | 230 | #endif /* SYSCFG_CFGR1_I2C_PB8_FMP */ |
| AnnaBridge | 172:65be27845400 | 231 | #if defined(SYSCFG_CFGR1_I2C_PB9_FMP) |
| AnnaBridge | 172:65be27845400 | 232 | #define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */ |
| AnnaBridge | 172:65be27845400 | 233 | #endif /* SYSCFG_CFGR1_I2C_PB9_FMP */ |
| AnnaBridge | 172:65be27845400 | 234 | |
| AnnaBridge | 172:65be27845400 | 235 | /** |
| AnnaBridge | 172:65be27845400 | 236 | * @} |
| AnnaBridge | 172:65be27845400 | 237 | */ |
| AnnaBridge | 172:65be27845400 | 238 | |
| AnnaBridge | 172:65be27845400 | 239 | /** |
| AnnaBridge | 172:65be27845400 | 240 | * @} |
| AnnaBridge | 172:65be27845400 | 241 | */ |
| AnnaBridge | 172:65be27845400 | 242 | |
| AnnaBridge | 172:65be27845400 | 243 | /* Exported macros -----------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 244 | |
| AnnaBridge | 172:65be27845400 | 245 | /** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros |
| AnnaBridge | 172:65be27845400 | 246 | * @{ |
| AnnaBridge | 172:65be27845400 | 247 | */ |
| AnnaBridge | 172:65be27845400 | 248 | |
| AnnaBridge | 172:65be27845400 | 249 | /** @brief Freeze/Unfreeze Peripherals in Debug mode |
| AnnaBridge | 172:65be27845400 | 250 | */ |
| AnnaBridge | 172:65be27845400 | 251 | #if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP) |
| AnnaBridge | 172:65be27845400 | 252 | #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) |
| AnnaBridge | 172:65be27845400 | 253 | #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) |
| AnnaBridge | 172:65be27845400 | 254 | #endif |
| AnnaBridge | 172:65be27845400 | 255 | |
| AnnaBridge | 172:65be27845400 | 256 | #if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP) |
| AnnaBridge | 172:65be27845400 | 257 | #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) |
| AnnaBridge | 172:65be27845400 | 258 | #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) |
| AnnaBridge | 172:65be27845400 | 259 | #endif |
| AnnaBridge | 172:65be27845400 | 260 | |
| AnnaBridge | 172:65be27845400 | 261 | #if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP) |
| AnnaBridge | 172:65be27845400 | 262 | #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) |
| AnnaBridge | 172:65be27845400 | 263 | #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) |
| AnnaBridge | 172:65be27845400 | 264 | #endif |
| AnnaBridge | 172:65be27845400 | 265 | |
| AnnaBridge | 172:65be27845400 | 266 | #if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP) |
| AnnaBridge | 172:65be27845400 | 267 | #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) |
| AnnaBridge | 172:65be27845400 | 268 | #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) |
| AnnaBridge | 172:65be27845400 | 269 | #endif |
| AnnaBridge | 172:65be27845400 | 270 | |
| AnnaBridge | 172:65be27845400 | 271 | #if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP) |
| AnnaBridge | 172:65be27845400 | 272 | #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) |
| AnnaBridge | 172:65be27845400 | 273 | #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) |
| AnnaBridge | 172:65be27845400 | 274 | #endif |
| AnnaBridge | 172:65be27845400 | 275 | |
| AnnaBridge | 172:65be27845400 | 276 | #if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP) |
| AnnaBridge | 172:65be27845400 | 277 | #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) |
| AnnaBridge | 172:65be27845400 | 278 | #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) |
| AnnaBridge | 172:65be27845400 | 279 | #endif |
| AnnaBridge | 172:65be27845400 | 280 | |
| AnnaBridge | 172:65be27845400 | 281 | #if defined(DBGMCU_APB1FZR1_DBG_RTC_STOP) |
| AnnaBridge | 172:65be27845400 | 282 | #define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP) |
| AnnaBridge | 172:65be27845400 | 283 | #define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP) |
| AnnaBridge | 172:65be27845400 | 284 | #endif |
| AnnaBridge | 172:65be27845400 | 285 | |
| AnnaBridge | 172:65be27845400 | 286 | #if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP) |
| AnnaBridge | 172:65be27845400 | 287 | #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) |
| AnnaBridge | 172:65be27845400 | 288 | #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) |
| AnnaBridge | 172:65be27845400 | 289 | #endif |
| AnnaBridge | 172:65be27845400 | 290 | |
| AnnaBridge | 172:65be27845400 | 291 | #if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP) |
| AnnaBridge | 172:65be27845400 | 292 | #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) |
| AnnaBridge | 172:65be27845400 | 293 | #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) |
| AnnaBridge | 172:65be27845400 | 294 | #endif |
| AnnaBridge | 172:65be27845400 | 295 | |
| AnnaBridge | 172:65be27845400 | 296 | #if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP) |
| AnnaBridge | 172:65be27845400 | 297 | #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) |
| AnnaBridge | 172:65be27845400 | 298 | #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) |
| AnnaBridge | 172:65be27845400 | 299 | #endif |
| AnnaBridge | 172:65be27845400 | 300 | |
| AnnaBridge | 172:65be27845400 | 301 | #if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP) |
| AnnaBridge | 172:65be27845400 | 302 | #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) |
| AnnaBridge | 172:65be27845400 | 303 | #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) |
| AnnaBridge | 172:65be27845400 | 304 | #endif |
| AnnaBridge | 172:65be27845400 | 305 | |
| AnnaBridge | 172:65be27845400 | 306 | #if defined(DBGMCU_APB1FZR1_DBG_I2C3_STOP) |
| AnnaBridge | 172:65be27845400 | 307 | #define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP) |
| AnnaBridge | 172:65be27845400 | 308 | #define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP) |
| AnnaBridge | 172:65be27845400 | 309 | #endif |
| AnnaBridge | 172:65be27845400 | 310 | |
| AnnaBridge | 172:65be27845400 | 311 | #if defined(DBGMCU_APB1FZR2_DBG_I2C4_STOP) |
| AnnaBridge | 172:65be27845400 | 312 | #define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP) |
| AnnaBridge | 172:65be27845400 | 313 | #define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP) |
| AnnaBridge | 172:65be27845400 | 314 | #endif |
| AnnaBridge | 172:65be27845400 | 315 | |
| AnnaBridge | 172:65be27845400 | 316 | #if defined(DBGMCU_APB1FZR1_DBG_CAN_STOP) |
| AnnaBridge | 172:65be27845400 | 317 | #define __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP) |
| AnnaBridge | 172:65be27845400 | 318 | #define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP) |
| AnnaBridge | 172:65be27845400 | 319 | #endif |
| AnnaBridge | 172:65be27845400 | 320 | |
| AnnaBridge | 172:65be27845400 | 321 | #if defined(DBGMCU_APB1FZR1_DBG_CAN2_STOP) |
| AnnaBridge | 172:65be27845400 | 322 | #define __HAL_DBGMCU_FREEZE_CAN2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN2_STOP) |
| AnnaBridge | 172:65be27845400 | 323 | #define __HAL_DBGMCU_UNFREEZE_CAN2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN2_STOP) |
| AnnaBridge | 172:65be27845400 | 324 | #endif |
| AnnaBridge | 172:65be27845400 | 325 | |
| AnnaBridge | 172:65be27845400 | 326 | #if defined(DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) |
| AnnaBridge | 172:65be27845400 | 327 | #define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) |
| AnnaBridge | 172:65be27845400 | 328 | #define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) |
| AnnaBridge | 172:65be27845400 | 329 | #endif |
| AnnaBridge | 172:65be27845400 | 330 | |
| AnnaBridge | 172:65be27845400 | 331 | #if defined(DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) |
| AnnaBridge | 172:65be27845400 | 332 | #define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) |
| AnnaBridge | 172:65be27845400 | 333 | #define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) |
| AnnaBridge | 172:65be27845400 | 334 | #endif |
| AnnaBridge | 172:65be27845400 | 335 | |
| AnnaBridge | 172:65be27845400 | 336 | #if defined(DBGMCU_APB2FZ_DBG_TIM1_STOP) |
| AnnaBridge | 172:65be27845400 | 337 | #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP) |
| AnnaBridge | 172:65be27845400 | 338 | #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP) |
| AnnaBridge | 172:65be27845400 | 339 | #endif |
| AnnaBridge | 172:65be27845400 | 340 | |
| AnnaBridge | 172:65be27845400 | 341 | #if defined(DBGMCU_APB2FZ_DBG_TIM8_STOP) |
| AnnaBridge | 172:65be27845400 | 342 | #define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP) |
| AnnaBridge | 172:65be27845400 | 343 | #define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP) |
| AnnaBridge | 172:65be27845400 | 344 | #endif |
| AnnaBridge | 172:65be27845400 | 345 | |
| AnnaBridge | 172:65be27845400 | 346 | #if defined(DBGMCU_APB2FZ_DBG_TIM15_STOP) |
| AnnaBridge | 172:65be27845400 | 347 | #define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP) |
| AnnaBridge | 172:65be27845400 | 348 | #define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP) |
| AnnaBridge | 172:65be27845400 | 349 | #endif |
| AnnaBridge | 172:65be27845400 | 350 | |
| AnnaBridge | 172:65be27845400 | 351 | #if defined(DBGMCU_APB2FZ_DBG_TIM16_STOP) |
| AnnaBridge | 172:65be27845400 | 352 | #define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP) |
| AnnaBridge | 172:65be27845400 | 353 | #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP) |
| AnnaBridge | 172:65be27845400 | 354 | #endif |
| AnnaBridge | 172:65be27845400 | 355 | |
| AnnaBridge | 172:65be27845400 | 356 | #if defined(DBGMCU_APB2FZ_DBG_TIM17_STOP) |
| AnnaBridge | 172:65be27845400 | 357 | #define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP) |
| AnnaBridge | 172:65be27845400 | 358 | #define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP) |
| AnnaBridge | 172:65be27845400 | 359 | #endif |
| AnnaBridge | 172:65be27845400 | 360 | |
| AnnaBridge | 172:65be27845400 | 361 | /** |
| AnnaBridge | 172:65be27845400 | 362 | * @} |
| AnnaBridge | 172:65be27845400 | 363 | */ |
| AnnaBridge | 172:65be27845400 | 364 | |
| AnnaBridge | 172:65be27845400 | 365 | /** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros |
| AnnaBridge | 172:65be27845400 | 366 | * @{ |
| AnnaBridge | 172:65be27845400 | 367 | */ |
| AnnaBridge | 172:65be27845400 | 368 | |
| AnnaBridge | 172:65be27845400 | 369 | /** @brief Main Flash memory mapped at 0x00000000. |
| AnnaBridge | 172:65be27845400 | 370 | */ |
| AnnaBridge | 172:65be27845400 | 371 | #define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE) |
| AnnaBridge | 172:65be27845400 | 372 | |
| AnnaBridge | 172:65be27845400 | 373 | /** @brief System Flash memory mapped at 0x00000000. |
| AnnaBridge | 172:65be27845400 | 374 | */ |
| AnnaBridge | 172:65be27845400 | 375 | #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0) |
| AnnaBridge | 172:65be27845400 | 376 | |
| AnnaBridge | 172:65be27845400 | 377 | /** @brief Embedded SRAM mapped at 0x00000000. |
| AnnaBridge | 172:65be27845400 | 378 | */ |
| AnnaBridge | 172:65be27845400 | 379 | #define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_1|SYSCFG_MEMRMP_MEM_MODE_0)) |
| AnnaBridge | 172:65be27845400 | 380 | |
| AnnaBridge | 172:65be27845400 | 381 | #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ |
| AnnaBridge | 172:65be27845400 | 382 | defined (STM32L496xx) || defined (STM32L4A6xx) || \ |
| AnnaBridge | 172:65be27845400 | 383 | defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
| AnnaBridge | 172:65be27845400 | 384 | |
| AnnaBridge | 172:65be27845400 | 385 | /** @brief FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000. |
| AnnaBridge | 172:65be27845400 | 386 | */ |
| AnnaBridge | 172:65be27845400 | 387 | #define __HAL_SYSCFG_REMAPMEMORY_FMC() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1) |
| AnnaBridge | 172:65be27845400 | 388 | |
| AnnaBridge | 172:65be27845400 | 389 | #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ |
| AnnaBridge | 172:65be27845400 | 390 | /* STM32L496xx || STM32L4A6xx || */ |
| AnnaBridge | 172:65be27845400 | 391 | /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ |
| AnnaBridge | 172:65be27845400 | 392 | |
| AnnaBridge | 172:65be27845400 | 393 | #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
| AnnaBridge | 172:65be27845400 | 394 | |
| AnnaBridge | 172:65be27845400 | 395 | /** @brief OCTOSPI mapped at 0x00000000. |
| AnnaBridge | 172:65be27845400 | 396 | */ |
| AnnaBridge | 172:65be27845400 | 397 | #define __HAL_SYSCFG_REMAPMEMORY_OCTOSPI1() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2)) |
| AnnaBridge | 172:65be27845400 | 398 | #define __HAL_SYSCFG_REMAPMEMORY_OCTOSPI2() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_0)) |
| AnnaBridge | 172:65be27845400 | 399 | |
| AnnaBridge | 172:65be27845400 | 400 | #else |
| AnnaBridge | 172:65be27845400 | 401 | |
| AnnaBridge | 172:65be27845400 | 402 | /** @brief QUADSPI mapped at 0x00000000. |
| AnnaBridge | 172:65be27845400 | 403 | */ |
| AnnaBridge | 172:65be27845400 | 404 | #define __HAL_SYSCFG_REMAPMEMORY_QUADSPI() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_1)) |
| AnnaBridge | 172:65be27845400 | 405 | |
| AnnaBridge | 172:65be27845400 | 406 | #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ |
| AnnaBridge | 172:65be27845400 | 407 | |
| AnnaBridge | 172:65be27845400 | 408 | /** |
| AnnaBridge | 172:65be27845400 | 409 | * @brief Return the boot mode as configured by user. |
| AnnaBridge | 172:65be27845400 | 410 | * @retval The boot mode as configured by user. The returned value can be one |
| AnnaBridge | 172:65be27845400 | 411 | * of the following values: |
| AnnaBridge | 172:65be27845400 | 412 | * @arg @ref SYSCFG_BOOT_MAINFLASH |
| AnnaBridge | 172:65be27845400 | 413 | * @arg @ref SYSCFG_BOOT_SYSTEMFLASH |
| AnnaBridge | 172:65be27845400 | 414 | @if STM32L486xx |
| AnnaBridge | 172:65be27845400 | 415 | * @arg @ref SYSCFG_BOOT_FMC |
| AnnaBridge | 172:65be27845400 | 416 | @endif |
| AnnaBridge | 172:65be27845400 | 417 | * @arg @ref SYSCFG_BOOT_SRAM |
| AnnaBridge | 172:65be27845400 | 418 | * @arg @ref SYSCFG_BOOT_QUADSPI |
| AnnaBridge | 172:65be27845400 | 419 | */ |
| AnnaBridge | 172:65be27845400 | 420 | #define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE) |
| AnnaBridge | 172:65be27845400 | 421 | |
| AnnaBridge | 172:65be27845400 | 422 | /** @brief SRAM2 page 0 to 31 write protection enable macro |
| AnnaBridge | 172:65be27845400 | 423 | * @param __SRAM2WRP__ This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP |
| AnnaBridge | 172:65be27845400 | 424 | * @note Write protection can only be disabled by a system reset |
| AnnaBridge | 172:65be27845400 | 425 | */ |
| AnnaBridge | 172:65be27845400 | 426 | #define __HAL_SYSCFG_SRAM2_WRP_1_31_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\ |
| AnnaBridge | 172:65be27845400 | 427 | SET_BIT(SYSCFG->SWPR, (__SRAM2WRP__));\ |
| AnnaBridge | 172:65be27845400 | 428 | }while(0) |
| AnnaBridge | 172:65be27845400 | 429 | |
| AnnaBridge | 172:65be27845400 | 430 | #if defined(SYSCFG_SWPR2_PAGE63) |
| AnnaBridge | 172:65be27845400 | 431 | /** @brief SRAM2 page 32 to 63 write protection enable macro |
| AnnaBridge | 172:65be27845400 | 432 | * @param __SRAM2WRP__ This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP_32_63 |
| AnnaBridge | 172:65be27845400 | 433 | * @note Write protection can only be disabled by a system reset |
| AnnaBridge | 172:65be27845400 | 434 | */ |
| AnnaBridge | 172:65be27845400 | 435 | #define __HAL_SYSCFG_SRAM2_WRP_32_63_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\ |
| AnnaBridge | 172:65be27845400 | 436 | SET_BIT(SYSCFG->SWPR2, (__SRAM2WRP__));\ |
| AnnaBridge | 172:65be27845400 | 437 | }while(0) |
| AnnaBridge | 172:65be27845400 | 438 | #endif /* SYSCFG_SWPR2_PAGE63 */ |
| AnnaBridge | 172:65be27845400 | 439 | |
| AnnaBridge | 172:65be27845400 | 440 | /** @brief SRAM2 page write protection unlock prior to erase |
| AnnaBridge | 172:65be27845400 | 441 | * @note Writing a wrong key reactivates the write protection |
| AnnaBridge | 172:65be27845400 | 442 | */ |
| AnnaBridge | 172:65be27845400 | 443 | #define __HAL_SYSCFG_SRAM2_WRP_UNLOCK() do {SYSCFG->SKR = 0xCA;\ |
| AnnaBridge | 172:65be27845400 | 444 | SYSCFG->SKR = 0x53;\ |
| AnnaBridge | 172:65be27845400 | 445 | }while(0) |
| AnnaBridge | 172:65be27845400 | 446 | |
| AnnaBridge | 172:65be27845400 | 447 | /** @brief SRAM2 erase |
| AnnaBridge | 172:65be27845400 | 448 | * @note __SYSCFG_GET_FLAG(SYSCFG_FLAG_SRAM2_BUSY) may be used to check end of erase |
| AnnaBridge | 172:65be27845400 | 449 | */ |
| AnnaBridge | 172:65be27845400 | 450 | #define __HAL_SYSCFG_SRAM2_ERASE() SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER) |
| AnnaBridge | 172:65be27845400 | 451 | |
| AnnaBridge | 172:65be27845400 | 452 | /** @brief Floating Point Unit interrupt enable/disable macros |
| AnnaBridge | 172:65be27845400 | 453 | * @param __INTERRUPT__ This parameter can be a value of @ref SYSCFG_FPU_Interrupts |
| AnnaBridge | 172:65be27845400 | 454 | */ |
| AnnaBridge | 172:65be27845400 | 455 | #define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ |
| AnnaBridge | 172:65be27845400 | 456 | SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\ |
| AnnaBridge | 172:65be27845400 | 457 | }while(0) |
| AnnaBridge | 172:65be27845400 | 458 | |
| AnnaBridge | 172:65be27845400 | 459 | #define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ |
| AnnaBridge | 172:65be27845400 | 460 | CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\ |
| AnnaBridge | 172:65be27845400 | 461 | }while(0) |
| AnnaBridge | 172:65be27845400 | 462 | |
| AnnaBridge | 172:65be27845400 | 463 | /** @brief SYSCFG Break ECC lock. |
| AnnaBridge | 172:65be27845400 | 464 | * Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input. |
| AnnaBridge | 172:65be27845400 | 465 | * @note The selected configuration is locked and can be unlocked only by system reset. |
| AnnaBridge | 172:65be27845400 | 466 | */ |
| AnnaBridge | 172:65be27845400 | 467 | #define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL) |
| AnnaBridge | 172:65be27845400 | 468 | |
| AnnaBridge | 172:65be27845400 | 469 | /** @brief SYSCFG Break Cortex-M4 Lockup lock. |
| AnnaBridge | 172:65be27845400 | 470 | * Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input. |
| AnnaBridge | 172:65be27845400 | 471 | * @note The selected configuration is locked and can be unlocked only by system reset. |
| AnnaBridge | 172:65be27845400 | 472 | */ |
| AnnaBridge | 172:65be27845400 | 473 | #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL) |
| AnnaBridge | 172:65be27845400 | 474 | |
| AnnaBridge | 172:65be27845400 | 475 | /** @brief SYSCFG Break PVD lock. |
| AnnaBridge | 172:65be27845400 | 476 | * Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register. |
| AnnaBridge | 172:65be27845400 | 477 | * @note The selected configuration is locked and can be unlocked only by system reset. |
| AnnaBridge | 172:65be27845400 | 478 | */ |
| AnnaBridge | 172:65be27845400 | 479 | #define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL) |
| AnnaBridge | 172:65be27845400 | 480 | |
| AnnaBridge | 172:65be27845400 | 481 | /** @brief SYSCFG Break SRAM2 parity lock. |
| AnnaBridge | 172:65be27845400 | 482 | * Enable and lock the SRAM2 parity error signal connection to TIM1/8/15/16/17 Break input. |
| AnnaBridge | 172:65be27845400 | 483 | * @note The selected configuration is locked and can be unlocked by system reset. |
| AnnaBridge | 172:65be27845400 | 484 | */ |
| AnnaBridge | 172:65be27845400 | 485 | #define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL) |
| AnnaBridge | 172:65be27845400 | 486 | |
| AnnaBridge | 172:65be27845400 | 487 | /** @brief Check SYSCFG flag is set or not. |
| AnnaBridge | 172:65be27845400 | 488 | * @param __FLAG__ specifies the flag to check. |
| AnnaBridge | 172:65be27845400 | 489 | * This parameter can be one of the following values: |
| AnnaBridge | 172:65be27845400 | 490 | * @arg @ref SYSCFG_FLAG_SRAM2_PE SRAM2 Parity Error Flag |
| AnnaBridge | 172:65be27845400 | 491 | * @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing |
| AnnaBridge | 172:65be27845400 | 492 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
| AnnaBridge | 172:65be27845400 | 493 | */ |
| AnnaBridge | 172:65be27845400 | 494 | #define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0) ? 1 : 0) |
| AnnaBridge | 172:65be27845400 | 495 | |
| AnnaBridge | 172:65be27845400 | 496 | /** @brief Set the SPF bit to clear the SRAM Parity Error Flag. |
| AnnaBridge | 172:65be27845400 | 497 | */ |
| AnnaBridge | 172:65be27845400 | 498 | #define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) |
| AnnaBridge | 172:65be27845400 | 499 | |
| AnnaBridge | 172:65be27845400 | 500 | /** @brief Fast-mode Plus driving capability enable/disable macros |
| AnnaBridge | 172:65be27845400 | 501 | * @param __FASTMODEPLUS__ This parameter can be a value of : |
| AnnaBridge | 172:65be27845400 | 502 | * @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6 |
| AnnaBridge | 172:65be27845400 | 503 | * @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7 |
| AnnaBridge | 172:65be27845400 | 504 | * @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8 |
| AnnaBridge | 172:65be27845400 | 505 | * @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9 |
| AnnaBridge | 172:65be27845400 | 506 | */ |
| AnnaBridge | 172:65be27845400 | 507 | #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ |
| AnnaBridge | 172:65be27845400 | 508 | SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ |
| AnnaBridge | 172:65be27845400 | 509 | }while(0) |
| AnnaBridge | 172:65be27845400 | 510 | |
| AnnaBridge | 172:65be27845400 | 511 | #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ |
| AnnaBridge | 172:65be27845400 | 512 | CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ |
| AnnaBridge | 172:65be27845400 | 513 | }while(0) |
| AnnaBridge | 172:65be27845400 | 514 | |
| AnnaBridge | 172:65be27845400 | 515 | /** |
| AnnaBridge | 172:65be27845400 | 516 | * @} |
| AnnaBridge | 172:65be27845400 | 517 | */ |
| AnnaBridge | 172:65be27845400 | 518 | |
| AnnaBridge | 172:65be27845400 | 519 | /* Private macros ------------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 520 | /** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros |
| AnnaBridge | 172:65be27845400 | 521 | * @{ |
| AnnaBridge | 172:65be27845400 | 522 | */ |
| AnnaBridge | 172:65be27845400 | 523 | |
| AnnaBridge | 172:65be27845400 | 524 | #define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \ |
| AnnaBridge | 172:65be27845400 | 525 | (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \ |
| AnnaBridge | 172:65be27845400 | 526 | (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \ |
| AnnaBridge | 172:65be27845400 | 527 | (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \ |
| AnnaBridge | 172:65be27845400 | 528 | (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \ |
| AnnaBridge | 172:65be27845400 | 529 | (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC)) |
| AnnaBridge | 172:65be27845400 | 530 | |
| AnnaBridge | 172:65be27845400 | 531 | #define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC) || \ |
| AnnaBridge | 172:65be27845400 | 532 | ((__CONFIG__) == SYSCFG_BREAK_PVD) || \ |
| AnnaBridge | 172:65be27845400 | 533 | ((__CONFIG__) == SYSCFG_BREAK_SRAM2_PARITY) || \ |
| AnnaBridge | 172:65be27845400 | 534 | ((__CONFIG__) == SYSCFG_BREAK_LOCKUP)) |
| AnnaBridge | 172:65be27845400 | 535 | |
| AnnaBridge | 172:65be27845400 | 536 | #define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0) && ((__PAGE__) <= 0xFFFFFFFF)) |
| AnnaBridge | 172:65be27845400 | 537 | |
| AnnaBridge | 172:65be27845400 | 538 | #if defined(VREFBUF) |
| AnnaBridge | 172:65be27845400 | 539 | #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \ |
| AnnaBridge | 172:65be27845400 | 540 | ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1)) |
| AnnaBridge | 172:65be27845400 | 541 | |
| AnnaBridge | 172:65be27845400 | 542 | #define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \ |
| AnnaBridge | 172:65be27845400 | 543 | ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE)) |
| AnnaBridge | 172:65be27845400 | 544 | |
| AnnaBridge | 172:65be27845400 | 545 | #define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0) && ((__VALUE__) <= VREFBUF_CCR_TRIM)) |
| AnnaBridge | 172:65be27845400 | 546 | #endif /* VREFBUF */ |
| AnnaBridge | 172:65be27845400 | 547 | |
| AnnaBridge | 172:65be27845400 | 548 | #if defined(SYSCFG_FASTMODEPLUS_PB8) && defined(SYSCFG_FASTMODEPLUS_PB9) |
| AnnaBridge | 172:65be27845400 | 549 | #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ |
| AnnaBridge | 172:65be27845400 | 550 | (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ |
| AnnaBridge | 172:65be27845400 | 551 | (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ |
| AnnaBridge | 172:65be27845400 | 552 | (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) |
| AnnaBridge | 172:65be27845400 | 553 | #elif defined(SYSCFG_FASTMODEPLUS_PB8) |
| AnnaBridge | 172:65be27845400 | 554 | #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ |
| AnnaBridge | 172:65be27845400 | 555 | (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ |
| AnnaBridge | 172:65be27845400 | 556 | (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8)) |
| AnnaBridge | 172:65be27845400 | 557 | #elif defined(SYSCFG_FASTMODEPLUS_PB9) |
| AnnaBridge | 172:65be27845400 | 558 | #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ |
| AnnaBridge | 172:65be27845400 | 559 | (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ |
| AnnaBridge | 172:65be27845400 | 560 | (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) |
| AnnaBridge | 172:65be27845400 | 561 | #else |
| AnnaBridge | 172:65be27845400 | 562 | #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ |
| AnnaBridge | 172:65be27845400 | 563 | (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7)) |
| AnnaBridge | 172:65be27845400 | 564 | #endif |
| AnnaBridge | 172:65be27845400 | 565 | /** |
| AnnaBridge | 172:65be27845400 | 566 | * @} |
| AnnaBridge | 172:65be27845400 | 567 | */ |
| AnnaBridge | 172:65be27845400 | 568 | |
| AnnaBridge | 172:65be27845400 | 569 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 570 | |
| AnnaBridge | 172:65be27845400 | 571 | /** @addtogroup HAL_Exported_Functions |
| AnnaBridge | 172:65be27845400 | 572 | * @{ |
| AnnaBridge | 172:65be27845400 | 573 | */ |
| AnnaBridge | 172:65be27845400 | 574 | |
| AnnaBridge | 172:65be27845400 | 575 | /** @addtogroup HAL_Exported_Functions_Group1 |
| AnnaBridge | 172:65be27845400 | 576 | * @{ |
| AnnaBridge | 172:65be27845400 | 577 | */ |
| AnnaBridge | 172:65be27845400 | 578 | |
| AnnaBridge | 172:65be27845400 | 579 | /* Initialization and de-initialization functions ******************************/ |
| AnnaBridge | 172:65be27845400 | 580 | HAL_StatusTypeDef HAL_Init(void); |
| AnnaBridge | 172:65be27845400 | 581 | HAL_StatusTypeDef HAL_DeInit(void); |
| AnnaBridge | 172:65be27845400 | 582 | void HAL_MspInit(void); |
| AnnaBridge | 172:65be27845400 | 583 | void HAL_MspDeInit(void); |
| AnnaBridge | 172:65be27845400 | 584 | HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); |
| AnnaBridge | 172:65be27845400 | 585 | |
| AnnaBridge | 172:65be27845400 | 586 | /** |
| AnnaBridge | 172:65be27845400 | 587 | * @} |
| AnnaBridge | 172:65be27845400 | 588 | */ |
| AnnaBridge | 172:65be27845400 | 589 | |
| AnnaBridge | 172:65be27845400 | 590 | /** @addtogroup HAL_Exported_Functions_Group2 |
| AnnaBridge | 172:65be27845400 | 591 | * @{ |
| AnnaBridge | 172:65be27845400 | 592 | */ |
| AnnaBridge | 172:65be27845400 | 593 | |
| AnnaBridge | 172:65be27845400 | 594 | /* Peripheral Control functions ************************************************/ |
| AnnaBridge | 172:65be27845400 | 595 | void HAL_IncTick(void); |
| AnnaBridge | 172:65be27845400 | 596 | void HAL_Delay(uint32_t Delay); |
| AnnaBridge | 172:65be27845400 | 597 | uint32_t HAL_GetTick(void); |
| AnnaBridge | 172:65be27845400 | 598 | void HAL_SuspendTick(void); |
| AnnaBridge | 172:65be27845400 | 599 | void HAL_ResumeTick(void); |
| AnnaBridge | 172:65be27845400 | 600 | uint32_t HAL_GetHalVersion(void); |
| AnnaBridge | 172:65be27845400 | 601 | uint32_t HAL_GetREVID(void); |
| AnnaBridge | 172:65be27845400 | 602 | uint32_t HAL_GetDEVID(void); |
| AnnaBridge | 172:65be27845400 | 603 | uint32_t HAL_GetUIDw0(void); |
| AnnaBridge | 172:65be27845400 | 604 | uint32_t HAL_GetUIDw1(void); |
| AnnaBridge | 172:65be27845400 | 605 | uint32_t HAL_GetUIDw2(void); |
| AnnaBridge | 172:65be27845400 | 606 | |
| AnnaBridge | 172:65be27845400 | 607 | /** |
| AnnaBridge | 172:65be27845400 | 608 | * @} |
| AnnaBridge | 172:65be27845400 | 609 | */ |
| AnnaBridge | 172:65be27845400 | 610 | |
| AnnaBridge | 172:65be27845400 | 611 | /** @addtogroup HAL_Exported_Functions_Group3 |
| AnnaBridge | 172:65be27845400 | 612 | * @{ |
| AnnaBridge | 172:65be27845400 | 613 | */ |
| AnnaBridge | 172:65be27845400 | 614 | |
| AnnaBridge | 172:65be27845400 | 615 | /* DBGMCU Peripheral Control functions *****************************************/ |
| AnnaBridge | 172:65be27845400 | 616 | void HAL_DBGMCU_EnableDBGSleepMode(void); |
| AnnaBridge | 172:65be27845400 | 617 | void HAL_DBGMCU_DisableDBGSleepMode(void); |
| AnnaBridge | 172:65be27845400 | 618 | void HAL_DBGMCU_EnableDBGStopMode(void); |
| AnnaBridge | 172:65be27845400 | 619 | void HAL_DBGMCU_DisableDBGStopMode(void); |
| AnnaBridge | 172:65be27845400 | 620 | void HAL_DBGMCU_EnableDBGStandbyMode(void); |
| AnnaBridge | 172:65be27845400 | 621 | void HAL_DBGMCU_DisableDBGStandbyMode(void); |
| AnnaBridge | 172:65be27845400 | 622 | |
| AnnaBridge | 172:65be27845400 | 623 | /** |
| AnnaBridge | 172:65be27845400 | 624 | * @} |
| AnnaBridge | 172:65be27845400 | 625 | */ |
| AnnaBridge | 172:65be27845400 | 626 | |
| AnnaBridge | 172:65be27845400 | 627 | /** @addtogroup HAL_Exported_Functions_Group4 |
| AnnaBridge | 172:65be27845400 | 628 | * @{ |
| AnnaBridge | 172:65be27845400 | 629 | */ |
| AnnaBridge | 172:65be27845400 | 630 | |
| AnnaBridge | 172:65be27845400 | 631 | /* SYSCFG Control functions ****************************************************/ |
| AnnaBridge | 172:65be27845400 | 632 | void HAL_SYSCFG_SRAM2Erase(void); |
| AnnaBridge | 172:65be27845400 | 633 | void HAL_SYSCFG_EnableMemorySwappingBank(void); |
| AnnaBridge | 172:65be27845400 | 634 | void HAL_SYSCFG_DisableMemorySwappingBank(void); |
| AnnaBridge | 172:65be27845400 | 635 | |
| AnnaBridge | 172:65be27845400 | 636 | #if defined(VREFBUF) |
| AnnaBridge | 172:65be27845400 | 637 | void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); |
| AnnaBridge | 172:65be27845400 | 638 | void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode); |
| AnnaBridge | 172:65be27845400 | 639 | void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); |
| AnnaBridge | 172:65be27845400 | 640 | HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void); |
| AnnaBridge | 172:65be27845400 | 641 | void HAL_SYSCFG_DisableVREFBUF(void); |
| AnnaBridge | 172:65be27845400 | 642 | #endif /* VREFBUF */ |
| AnnaBridge | 172:65be27845400 | 643 | |
| AnnaBridge | 172:65be27845400 | 644 | void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void); |
| AnnaBridge | 172:65be27845400 | 645 | void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void); |
| AnnaBridge | 172:65be27845400 | 646 | |
| AnnaBridge | 172:65be27845400 | 647 | /** |
| AnnaBridge | 172:65be27845400 | 648 | * @} |
| AnnaBridge | 172:65be27845400 | 649 | */ |
| AnnaBridge | 172:65be27845400 | 650 | |
| AnnaBridge | 172:65be27845400 | 651 | /** |
| AnnaBridge | 172:65be27845400 | 652 | * @} |
| AnnaBridge | 172:65be27845400 | 653 | */ |
| AnnaBridge | 172:65be27845400 | 654 | |
| AnnaBridge | 172:65be27845400 | 655 | /** |
| AnnaBridge | 172:65be27845400 | 656 | * @} |
| AnnaBridge | 172:65be27845400 | 657 | */ |
| AnnaBridge | 172:65be27845400 | 658 | |
| AnnaBridge | 172:65be27845400 | 659 | /** |
| AnnaBridge | 172:65be27845400 | 660 | * @} |
| AnnaBridge | 172:65be27845400 | 661 | */ |
| AnnaBridge | 172:65be27845400 | 662 | |
| AnnaBridge | 172:65be27845400 | 663 | #ifdef __cplusplus |
| AnnaBridge | 172:65be27845400 | 664 | } |
| AnnaBridge | 172:65be27845400 | 665 | #endif |
| AnnaBridge | 172:65be27845400 | 666 | |
| AnnaBridge | 172:65be27845400 | 667 | #endif /* __STM32L4xx_HAL_H */ |
| AnnaBridge | 172:65be27845400 | 668 | |
| AnnaBridge | 172:65be27845400 | 669 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
