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TARGET_NUCLEO_H743ZI/TOOLCHAIN_ARM_STD/stm32h7xx_ll_rcc.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	172:65be27845400	1	/**
AnnaBridge	172:65be27845400	2	******************************************************************************
AnnaBridge	172:65be27845400	3	* @file stm32h7xx_ll_rcc.h
AnnaBridge	172:65be27845400	4	* @author MCD Application Team
AnnaBridge	172:65be27845400	5	* @version $VERSION$
AnnaBridge	172:65be27845400	6	* @date $DATE$
AnnaBridge	172:65be27845400	7	* @brief Header file of RCC LL module.
AnnaBridge	172:65be27845400	8	******************************************************************************
AnnaBridge	172:65be27845400	9	* @attention
AnnaBridge	172:65be27845400	10	*
AnnaBridge	172:65be27845400	11	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
AnnaBridge	172:65be27845400	12	* All rights reserved.</center></h2>
AnnaBridge	172:65be27845400	13	*
AnnaBridge	172:65be27845400	14	* This software component is licensed by ST under BSD 3-Clause license,
AnnaBridge	172:65be27845400	15	* the "License"; You may not use this file except in compliance with the
AnnaBridge	172:65be27845400	16	* License. You may obtain a copy of the License at:
AnnaBridge	172:65be27845400	17	* opensource.org/licenses/BSD-3-Clause
AnnaBridge	172:65be27845400	18	*
AnnaBridge	172:65be27845400	19	******************************************************************************
AnnaBridge	172:65be27845400	20	*/
AnnaBridge	172:65be27845400	21
AnnaBridge	172:65be27845400	22	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	172:65be27845400	23	#ifndef STM32H7xx_LL_RCC_H
AnnaBridge	172:65be27845400	24	#define STM32H7xx_LL_RCC_H
AnnaBridge	172:65be27845400	25
AnnaBridge	172:65be27845400	26	#ifdef __cplusplus
AnnaBridge	172:65be27845400	27	extern "C" {
AnnaBridge	172:65be27845400	28	#endif
AnnaBridge	172:65be27845400	29
AnnaBridge	172:65be27845400	30	/* Includes ------------------------------------------------------------------*/
AnnaBridge	172:65be27845400	31	#include "stm32h7xx.h"
AnnaBridge	172:65be27845400	32	#include <math.h>
AnnaBridge	172:65be27845400	33
AnnaBridge	172:65be27845400	34	/** @addtogroup STM32H7xx_LL_Driver
AnnaBridge	172:65be27845400	35	* @{
AnnaBridge	172:65be27845400	36	*/
AnnaBridge	172:65be27845400	37
AnnaBridge	172:65be27845400	38	#if defined(RCC)
AnnaBridge	172:65be27845400	39
AnnaBridge	172:65be27845400	40	/** @defgroup RCC_LL RCC
AnnaBridge	172:65be27845400	41	* @{
AnnaBridge	172:65be27845400	42	*/
AnnaBridge	172:65be27845400	43
AnnaBridge	172:65be27845400	44	/* Private types -------------------------------------------------------------*/
AnnaBridge	172:65be27845400	45	/* Private variables ---------------------------------------------------------*/
AnnaBridge	172:65be27845400	46	/** @defgroup RCC_LL_Private_Variables RCC Private Variables
AnnaBridge	172:65be27845400	47	* @{
AnnaBridge	172:65be27845400	48	*/
AnnaBridge	172:65be27845400	49	static const uint8_t LL_RCC_PrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
AnnaBridge	172:65be27845400	50
AnnaBridge	172:65be27845400	51	/**
AnnaBridge	172:65be27845400	52	* @}
AnnaBridge	172:65be27845400	53	*/
AnnaBridge	172:65be27845400	54	/* Private constants ---------------------------------------------------------*/
AnnaBridge	172:65be27845400	55	/* Private macros ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	56	#if !defined(UNUSED)
AnnaBridge	172:65be27845400	57	#define UNUSED(x) ((void)(x))
AnnaBridge	172:65be27845400	58	#endif
AnnaBridge	172:65be27845400	59
AnnaBridge	172:65be27845400	60	/* 32 24 16 8 0
AnnaBridge	172:65be27845400	61	--------------------------------------------------------
AnnaBridge	172:65be27845400	62	\| Mask \| ClkSource \| Bit \| Register \|
AnnaBridge	172:65be27845400	63	\| \| Config \| Position \| Offset \|
AnnaBridge	172:65be27845400	64	--------------------------------------------------------*/
AnnaBridge	172:65be27845400	65
AnnaBridge	172:65be27845400	66	/* Clock source register offset Vs D1CCIPR regsiter */
AnnaBridge	172:65be27845400	67	#define D1CCIP 0x0UL
AnnaBridge	172:65be27845400	68	#define D2CCIP1 0x4UL
AnnaBridge	172:65be27845400	69	#define D2CCIP2 0x8UL
AnnaBridge	172:65be27845400	70	#define D3CCIP 0xCUL
AnnaBridge	172:65be27845400	71
AnnaBridge	172:65be27845400	72	#define REG_SHIFT 0U
AnnaBridge	172:65be27845400	73	#define POS_SHIFT 8U
AnnaBridge	172:65be27845400	74	#define CONFIG_SHIFT 16U
AnnaBridge	172:65be27845400	75	#define MASK_SHIFT 24U
AnnaBridge	172:65be27845400	76
AnnaBridge	172:65be27845400	77	#define LL_CLKSOURCE_SHIFT(__CLKSOURCE__) (((__CLKSOURCE__) >> POS_SHIFT ) & 0x1FUL)
AnnaBridge	172:65be27845400	78
AnnaBridge	172:65be27845400	79	#define LL_CLKSOURCE_MASK(__CLKSOURCE__) ((((__CLKSOURCE__) >> MASK_SHIFT ) & 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__))
AnnaBridge	172:65be27845400	80
AnnaBridge	172:65be27845400	81	#define LL_CLKSOURCE_CONFIG(__CLKSOURCE__) ((((__CLKSOURCE__) >> CONFIG_SHIFT) & 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__))
AnnaBridge	172:65be27845400	82
AnnaBridge	172:65be27845400	83	#define LL_CLKSOURCE_REG(__CLKSOURCE__) (((__CLKSOURCE__) >> REG_SHIFT ) & 0xFFUL)
AnnaBridge	172:65be27845400	84
AnnaBridge	172:65be27845400	85	#define LL_CLKSOURCE(__REG__, __MSK__, __POS__, __CLK__) ((uint32_t)((((__MSK__) >> (__POS__)) << MASK_SHIFT) \| \
AnnaBridge	172:65be27845400	86	(( __POS__ ) << POS_SHIFT) \| \
AnnaBridge	172:65be27845400	87	(( __REG__ ) << REG_SHIFT) \| \
AnnaBridge	172:65be27845400	88	(((__CLK__) >> (__POS__)) << CONFIG_SHIFT)))
AnnaBridge	172:65be27845400	89
AnnaBridge	172:65be27845400	90	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	172:65be27845400	91	/** @defgroup RCC_LL_Private_Macros RCC Private Macros
AnnaBridge	172:65be27845400	92	* @{
AnnaBridge	172:65be27845400	93	*/
AnnaBridge	172:65be27845400	94	/**
AnnaBridge	172:65be27845400	95	* @}
AnnaBridge	172:65be27845400	96	*/
AnnaBridge	172:65be27845400	97	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	172:65be27845400	98	/* Exported types ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	99	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	172:65be27845400	100	/** @defgroup RCC_LL_Exported_Types RCC Exported Types
AnnaBridge	172:65be27845400	101	* @{
AnnaBridge	172:65be27845400	102	*/
AnnaBridge	172:65be27845400	103
AnnaBridge	172:65be27845400	104	/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
AnnaBridge	172:65be27845400	105	* @{
AnnaBridge	172:65be27845400	106	*/
AnnaBridge	172:65be27845400	107
AnnaBridge	172:65be27845400	108	/**
AnnaBridge	172:65be27845400	109	* @brief RCC Clocks Frequency Structure
AnnaBridge	172:65be27845400	110	*/
AnnaBridge	172:65be27845400	111	typedef struct
AnnaBridge	172:65be27845400	112	{
AnnaBridge	172:65be27845400	113	uint32_t SYSCLK_Frequency;
AnnaBridge	172:65be27845400	114	uint32_t CPUCLK_Frequency;
AnnaBridge	172:65be27845400	115	uint32_t HCLK_Frequency;
AnnaBridge	172:65be27845400	116	uint32_t PCLK1_Frequency;
AnnaBridge	172:65be27845400	117	uint32_t PCLK2_Frequency;
AnnaBridge	172:65be27845400	118	uint32_t PCLK3_Frequency;
AnnaBridge	172:65be27845400	119	uint32_t PCLK4_Frequency;
AnnaBridge	172:65be27845400	120	} LL_RCC_ClocksTypeDef;
AnnaBridge	172:65be27845400	121
AnnaBridge	172:65be27845400	122	/**
AnnaBridge	172:65be27845400	123	* @}
AnnaBridge	172:65be27845400	124	*/
AnnaBridge	172:65be27845400	125
AnnaBridge	172:65be27845400	126	/**
AnnaBridge	172:65be27845400	127	* @brief PLL Clocks Frequency Structure
AnnaBridge	172:65be27845400	128	*/
AnnaBridge	172:65be27845400	129	typedef struct
AnnaBridge	172:65be27845400	130	{
AnnaBridge	172:65be27845400	131	uint32_t PLL_P_Frequency;
AnnaBridge	172:65be27845400	132	uint32_t PLL_Q_Frequency;
AnnaBridge	172:65be27845400	133	uint32_t PLL_R_Frequency;
AnnaBridge	172:65be27845400	134	} LL_PLL_ClocksTypeDef;
AnnaBridge	172:65be27845400	135
AnnaBridge	172:65be27845400	136	/**
AnnaBridge	172:65be27845400	137	* @}
AnnaBridge	172:65be27845400	138	*/
AnnaBridge	172:65be27845400	139
AnnaBridge	172:65be27845400	140	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	172:65be27845400	141
AnnaBridge	172:65be27845400	142	/* Exported constants --------------------------------------------------------*/
AnnaBridge	172:65be27845400	143	/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
AnnaBridge	172:65be27845400	144	* @{
AnnaBridge	172:65be27845400	145	*/
AnnaBridge	172:65be27845400	146
AnnaBridge	172:65be27845400	147	/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
AnnaBridge	172:65be27845400	148	* @brief Defines used to adapt values of different oscillators
AnnaBridge	172:65be27845400	149	* @note These values could be modified in the user environment according to
AnnaBridge	172:65be27845400	150	* HW set-up.
AnnaBridge	172:65be27845400	151	* @{
AnnaBridge	172:65be27845400	152	*/
AnnaBridge	172:65be27845400	153	#if !defined (HSE_VALUE)
AnnaBridge	172:65be27845400	154	#define HSE_VALUE 25000000U /!< Value of the HSE oscillator in Hz /
AnnaBridge	172:65be27845400	155	#endif /* HSE_VALUE */
AnnaBridge	172:65be27845400	156
AnnaBridge	172:65be27845400	157	#if !defined (HSI_VALUE)
AnnaBridge	172:65be27845400	158	#define HSI_VALUE 64000000U /!< Value of the HSI oscillator in Hz /
AnnaBridge	172:65be27845400	159	#endif /* HSI_VALUE */
AnnaBridge	172:65be27845400	160
AnnaBridge	172:65be27845400	161	#if !defined (CSI_VALUE)
AnnaBridge	172:65be27845400	162	#define CSI_VALUE 4000000U /!< Value of the CSI oscillator in Hz /
AnnaBridge	172:65be27845400	163	#endif /* CSI_VALUE */
AnnaBridge	172:65be27845400	164
AnnaBridge	172:65be27845400	165	#if !defined (LSE_VALUE)
AnnaBridge	172:65be27845400	166	#define LSE_VALUE 32768U /!< Value of the LSE oscillator in Hz /
AnnaBridge	172:65be27845400	167	#endif /* LSE_VALUE */
AnnaBridge	172:65be27845400	168
AnnaBridge	172:65be27845400	169	#if !defined (LSI_VALUE)
AnnaBridge	172:65be27845400	170	#define LSI_VALUE 32000U /!< Value of the LSI oscillator in Hz /
AnnaBridge	172:65be27845400	171	#endif /* LSI_VALUE */
AnnaBridge	172:65be27845400	172
AnnaBridge	172:65be27845400	173	#if !defined (EXTERNAL_CLOCK_VALUE)
AnnaBridge	172:65be27845400	174	#define EXTERNAL_CLOCK_VALUE 12288000U /!< Value of the I2S_CKIN external oscillator in Hz /
AnnaBridge	172:65be27845400	175	#endif /* EXTERNAL_CLOCK_VALUE */
AnnaBridge	172:65be27845400	176	/**
AnnaBridge	172:65be27845400	177	* @}
AnnaBridge	172:65be27845400	178	*/
AnnaBridge	172:65be27845400	179
AnnaBridge	172:65be27845400	180	/** @defgroup RCC_LL_EC_HSIDIV HSI oscillator divider
AnnaBridge	172:65be27845400	181	* @{
AnnaBridge	172:65be27845400	182	*/
AnnaBridge	172:65be27845400	183	#define LL_RCC_HSI_DIV1 RCC_CR_HSIDIV_1
AnnaBridge	172:65be27845400	184	#define LL_RCC_HSI_DIV2 RCC_CR_HSIDIV_2
AnnaBridge	172:65be27845400	185	#define LL_RCC_HSI_DIV4 RCC_CR_HSIDIV_4
AnnaBridge	172:65be27845400	186	#define LL_RCC_HSI_DIV8 RCC_CR_HSIDIV_8
AnnaBridge	172:65be27845400	187	/**
AnnaBridge	172:65be27845400	188	* @}
AnnaBridge	172:65be27845400	189	*/
AnnaBridge	172:65be27845400	190
AnnaBridge	172:65be27845400	191	/** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
AnnaBridge	172:65be27845400	192	* @{
AnnaBridge	172:65be27845400	193	*/
AnnaBridge	172:65be27845400	194	#define LL_RCC_LSEDRIVE_LOW (uint32_t)(0x00000000U)
AnnaBridge	172:65be27845400	195	#define LL_RCC_LSEDRIVE_MEDIUMLOW (uint32_t)(RCC_BDCR_LSEDRV_0)
AnnaBridge	172:65be27845400	196	#define LL_RCC_LSEDRIVE_MEDIUMHIGH (uint32_t)(RCC_BDCR_LSEDRV_1)
AnnaBridge	172:65be27845400	197	#define LL_RCC_LSEDRIVE_HIGH (uint32_t)(RCC_BDCR_LSEDRV)
AnnaBridge	172:65be27845400	198	/**
AnnaBridge	172:65be27845400	199	* @}
AnnaBridge	172:65be27845400	200	*/
AnnaBridge	172:65be27845400	201
AnnaBridge	172:65be27845400	202	/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
AnnaBridge	172:65be27845400	203	* @{
AnnaBridge	172:65be27845400	204	*/
AnnaBridge	172:65be27845400	205	#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI
AnnaBridge	172:65be27845400	206	#define LL_RCC_SYS_CLKSOURCE_CSI RCC_CFGR_SW_CSI
AnnaBridge	172:65be27845400	207	#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE
AnnaBridge	172:65be27845400	208	#define LL_RCC_SYS_CLKSOURCE_PLL1 RCC_CFGR_SW_PLL1
AnnaBridge	172:65be27845400	209	/**
AnnaBridge	172:65be27845400	210	* @}
AnnaBridge	172:65be27845400	211	*/
AnnaBridge	172:65be27845400	212
AnnaBridge	172:65be27845400	213	/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
AnnaBridge	172:65be27845400	214	* @{
AnnaBridge	172:65be27845400	215	*/
AnnaBridge	172:65be27845400	216	#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
AnnaBridge	172:65be27845400	217	#define LL_RCC_SYS_CLKSOURCE_STATUS_CSI RCC_CFGR_SWS_CSI /!< CSI used as system clock /
AnnaBridge	172:65be27845400	218	#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
AnnaBridge	172:65be27845400	219	#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL1 RCC_CFGR_SWS_PLL1 /!< PLL1 used as system clock /
AnnaBridge	172:65be27845400	220	/**
AnnaBridge	172:65be27845400	221	* @}
AnnaBridge	172:65be27845400	222	*/
AnnaBridge	172:65be27845400	223
AnnaBridge	172:65be27845400	224	/** @defgroup RCC_LL_EC_SYSWAKEUP_CLKSOURCE System wakeup clock source
AnnaBridge	172:65be27845400	225	* @{
AnnaBridge	172:65be27845400	226	*/
AnnaBridge	172:65be27845400	227	#define LL_RCC_SYSWAKEUP_CLKSOURCE_HSI (uint32_t)(0x00000000U)
AnnaBridge	172:65be27845400	228	#define LL_RCC_SYSWAKEUP_CLKSOURCE_CSI (uint32_t)(RCC_CFGR_STOPWUCK)
AnnaBridge	172:65be27845400	229	/**
AnnaBridge	172:65be27845400	230	* @}
AnnaBridge	172:65be27845400	231	*/
AnnaBridge	172:65be27845400	232
AnnaBridge	172:65be27845400	233	/** @defgroup RCC_LL_EC_KERWAKEUP_CLKSOURCE Kernel wakeup clock source
AnnaBridge	172:65be27845400	234	* @{
AnnaBridge	172:65be27845400	235	*/
AnnaBridge	172:65be27845400	236	#define LL_RCC_KERWAKEUP_CLKSOURCE_HSI (uint32_t)(0x00000000U)
AnnaBridge	172:65be27845400	237	#define LL_RCC_KERWAKEUP_CLKSOURCE_CSI (uint32_t)(RCC_CFGR_STOPKERWUCK)
AnnaBridge	172:65be27845400	238	/**
AnnaBridge	172:65be27845400	239	* @}
AnnaBridge	172:65be27845400	240	*/
AnnaBridge	172:65be27845400	241
AnnaBridge	172:65be27845400	242	/** @defgroup RCC_LL_EC_SYSCLK_DIV System prescaler
AnnaBridge	172:65be27845400	243	* @{
AnnaBridge	172:65be27845400	244	*/
AnnaBridge	172:65be27845400	245	#define LL_RCC_SYSCLK_DIV_1 RCC_D1CFGR_D1CPRE_DIV1
AnnaBridge	172:65be27845400	246	#define LL_RCC_SYSCLK_DIV_2 RCC_D1CFGR_D1CPRE_DIV2
AnnaBridge	172:65be27845400	247	#define LL_RCC_SYSCLK_DIV_4 RCC_D1CFGR_D1CPRE_DIV4
AnnaBridge	172:65be27845400	248	#define LL_RCC_SYSCLK_DIV_8 RCC_D1CFGR_D1CPRE_DIV8
AnnaBridge	172:65be27845400	249	#define LL_RCC_SYSCLK_DIV_16 RCC_D1CFGR_D1CPRE_DIV16
AnnaBridge	172:65be27845400	250	#define LL_RCC_SYSCLK_DIV_64 RCC_D1CFGR_D1CPRE_DIV64
AnnaBridge	172:65be27845400	251	#define LL_RCC_SYSCLK_DIV_128 RCC_D1CFGR_D1CPRE_DIV128
AnnaBridge	172:65be27845400	252	#define LL_RCC_SYSCLK_DIV_256 RCC_D1CFGR_D1CPRE_DIV256
AnnaBridge	172:65be27845400	253	#define LL_RCC_SYSCLK_DIV_512 RCC_D1CFGR_D1CPRE_DIV512
AnnaBridge	172:65be27845400	254	/**
AnnaBridge	172:65be27845400	255	* @}
AnnaBridge	172:65be27845400	256	*/
AnnaBridge	172:65be27845400	257
AnnaBridge	172:65be27845400	258	/** @defgroup RCC_LL_EC_AHB_DIV AHB prescaler
AnnaBridge	172:65be27845400	259	* @{
AnnaBridge	172:65be27845400	260	*/
AnnaBridge	172:65be27845400	261	#define LL_RCC_AHB_DIV_1 RCC_D1CFGR_HPRE_DIV1
AnnaBridge	172:65be27845400	262	#define LL_RCC_AHB_DIV_2 RCC_D1CFGR_HPRE_DIV2
AnnaBridge	172:65be27845400	263	#define LL_RCC_AHB_DIV_4 RCC_D1CFGR_HPRE_DIV4
AnnaBridge	172:65be27845400	264	#define LL_RCC_AHB_DIV_8 RCC_D1CFGR_HPRE_DIV8
AnnaBridge	172:65be27845400	265	#define LL_RCC_AHB_DIV_16 RCC_D1CFGR_HPRE_DIV16
AnnaBridge	172:65be27845400	266	#define LL_RCC_AHB_DIV_64 RCC_D1CFGR_HPRE_DIV64
AnnaBridge	172:65be27845400	267	#define LL_RCC_AHB_DIV_128 RCC_D1CFGR_HPRE_DIV128
AnnaBridge	172:65be27845400	268	#define LL_RCC_AHB_DIV_256 RCC_D1CFGR_HPRE_DIV256
AnnaBridge	172:65be27845400	269	#define LL_RCC_AHB_DIV_512 RCC_D1CFGR_HPRE_DIV512
AnnaBridge	172:65be27845400	270	/**
AnnaBridge	172:65be27845400	271	* @}
AnnaBridge	172:65be27845400	272	*/
AnnaBridge	172:65be27845400	273
AnnaBridge	172:65be27845400	274	/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
AnnaBridge	172:65be27845400	275	* @{
AnnaBridge	172:65be27845400	276	*/
AnnaBridge	172:65be27845400	277	#define LL_RCC_APB1_DIV_1 RCC_D2CFGR_D2PPRE1_DIV1
AnnaBridge	172:65be27845400	278	#define LL_RCC_APB1_DIV_2 RCC_D2CFGR_D2PPRE1_DIV2
AnnaBridge	172:65be27845400	279	#define LL_RCC_APB1_DIV_4 RCC_D2CFGR_D2PPRE1_DIV4
AnnaBridge	172:65be27845400	280	#define LL_RCC_APB1_DIV_8 RCC_D2CFGR_D2PPRE1_DIV8
AnnaBridge	172:65be27845400	281	#define LL_RCC_APB1_DIV_16 RCC_D2CFGR_D2PPRE1_DIV16
AnnaBridge	172:65be27845400	282	/**
AnnaBridge	172:65be27845400	283	* @}
AnnaBridge	172:65be27845400	284	*/
AnnaBridge	172:65be27845400	285
AnnaBridge	172:65be27845400	286	/** @defgroup RCC_LL_EC_APB2_DIV APB low-speed prescaler (APB2)
AnnaBridge	172:65be27845400	287	* @{
AnnaBridge	172:65be27845400	288	*/
AnnaBridge	172:65be27845400	289	#define LL_RCC_APB2_DIV_1 RCC_D2CFGR_D2PPRE2_DIV1
AnnaBridge	172:65be27845400	290	#define LL_RCC_APB2_DIV_2 RCC_D2CFGR_D2PPRE2_DIV2
AnnaBridge	172:65be27845400	291	#define LL_RCC_APB2_DIV_4 RCC_D2CFGR_D2PPRE2_DIV4
AnnaBridge	172:65be27845400	292	#define LL_RCC_APB2_DIV_8 RCC_D2CFGR_D2PPRE2_DIV8
AnnaBridge	172:65be27845400	293	#define LL_RCC_APB2_DIV_16 RCC_D2CFGR_D2PPRE2_DIV16
AnnaBridge	172:65be27845400	294	/**
AnnaBridge	172:65be27845400	295	* @}
AnnaBridge	172:65be27845400	296	*/
AnnaBridge	172:65be27845400	297
AnnaBridge	172:65be27845400	298	/** @defgroup RCC_LL_EC_APB3_DIV APB low-speed prescaler (APB3)
AnnaBridge	172:65be27845400	299	* @{
AnnaBridge	172:65be27845400	300	*/
AnnaBridge	172:65be27845400	301	#define LL_RCC_APB3_DIV_1 RCC_D1CFGR_D1PPRE_DIV1
AnnaBridge	172:65be27845400	302	#define LL_RCC_APB3_DIV_2 RCC_D1CFGR_D1PPRE_DIV2
AnnaBridge	172:65be27845400	303	#define LL_RCC_APB3_DIV_4 RCC_D1CFGR_D1PPRE_DIV4
AnnaBridge	172:65be27845400	304	#define LL_RCC_APB3_DIV_8 RCC_D1CFGR_D1PPRE_DIV8
AnnaBridge	172:65be27845400	305	#define LL_RCC_APB3_DIV_16 RCC_D1CFGR_D1PPRE_DIV16
AnnaBridge	172:65be27845400	306	/**
AnnaBridge	172:65be27845400	307	* @}
AnnaBridge	172:65be27845400	308	*/
AnnaBridge	172:65be27845400	309
AnnaBridge	172:65be27845400	310	/** @defgroup RCC_LL_EC_APB4_DIV APB low-speed prescaler (APB4)
AnnaBridge	172:65be27845400	311	* @{
AnnaBridge	172:65be27845400	312	*/
AnnaBridge	172:65be27845400	313	#define LL_RCC_APB4_DIV_1 RCC_D3CFGR_D3PPRE_DIV1
AnnaBridge	172:65be27845400	314	#define LL_RCC_APB4_DIV_2 RCC_D3CFGR_D3PPRE_DIV2
AnnaBridge	172:65be27845400	315	#define LL_RCC_APB4_DIV_4 RCC_D3CFGR_D3PPRE_DIV4
AnnaBridge	172:65be27845400	316	#define LL_RCC_APB4_DIV_8 RCC_D3CFGR_D3PPRE_DIV8
AnnaBridge	172:65be27845400	317	#define LL_RCC_APB4_DIV_16 RCC_D3CFGR_D3PPRE_DIV16
AnnaBridge	172:65be27845400	318	/**
AnnaBridge	172:65be27845400	319	* @}
AnnaBridge	172:65be27845400	320	*/
AnnaBridge	172:65be27845400	321
AnnaBridge	172:65be27845400	322	/** @defgroup RCC_LL_EC_MCOxSOURCE MCO source selection
AnnaBridge	172:65be27845400	323	* @{
AnnaBridge	172:65be27845400	324	*/
AnnaBridge	172:65be27845400	325	#define LL_RCC_MCO1SOURCE_HSI (uint32_t)((RCC_CFGR_MCO1>>16U) \| 0x00000000U)
AnnaBridge	172:65be27845400	326	#define LL_RCC_MCO1SOURCE_LSE (uint32_t)((RCC_CFGR_MCO1>>16U) \| RCC_CFGR_MCO1_0)
AnnaBridge	172:65be27845400	327	#define LL_RCC_MCO1SOURCE_HSE (uint32_t)((RCC_CFGR_MCO1>>16U) \| RCC_CFGR_MCO1_1)
AnnaBridge	172:65be27845400	328	#define LL_RCC_MCO1SOURCE_PLL1QCLK (uint32_t)((RCC_CFGR_MCO1>>16U) \| RCC_CFGR_MCO1_1\|RCC_CFGR_MCO1_0)
AnnaBridge	172:65be27845400	329	#define LL_RCC_MCO1SOURCE_HSI48 (uint32_t)((RCC_CFGR_MCO1>>16U) \| RCC_CFGR_MCO1_2)
AnnaBridge	172:65be27845400	330	#define LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)((RCC_CFGR_MCO2>>16U) \| 0x00000000U)
AnnaBridge	172:65be27845400	331	#define LL_RCC_MCO2SOURCE_PLL2PCLK (uint32_t)((RCC_CFGR_MCO2>>16U) \| RCC_CFGR_MCO2_0)
AnnaBridge	172:65be27845400	332	#define LL_RCC_MCO2SOURCE_HSE (uint32_t)((RCC_CFGR_MCO2>>16U) \| RCC_CFGR_MCO2_1)
AnnaBridge	172:65be27845400	333	#define LL_RCC_MCO2SOURCE_PLL1PCLK (uint32_t)((RCC_CFGR_MCO2>>16U) \| RCC_CFGR_MCO2_1\|RCC_CFGR_MCO2_0)
AnnaBridge	172:65be27845400	334	#define LL_RCC_MCO2SOURCE_CSI (uint32_t)((RCC_CFGR_MCO2>>16U) \| RCC_CFGR_MCO2_2)
AnnaBridge	172:65be27845400	335	#define LL_RCC_MCO2SOURCE_LSI (uint32_t)((RCC_CFGR_MCO2>>16U) \| RCC_CFGR_MCO2_2\|RCC_CFGR_MCO2_0)
AnnaBridge	172:65be27845400	336	/**
AnnaBridge	172:65be27845400	337	* @}
AnnaBridge	172:65be27845400	338	*/
AnnaBridge	172:65be27845400	339
AnnaBridge	172:65be27845400	340	/** @defgroup RCC_LL_EC_MCOx_DIV MCO prescaler
AnnaBridge	172:65be27845400	341	* @{
AnnaBridge	172:65be27845400	342	*/
AnnaBridge	172:65be27845400	343	#define LL_RCC_MCO1_DIV_1 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) \| RCC_CFGR_MCO1PRE_0)
AnnaBridge	172:65be27845400	344	#define LL_RCC_MCO1_DIV_2 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) \| RCC_CFGR_MCO1PRE_1)
AnnaBridge	172:65be27845400	345	#define LL_RCC_MCO1_DIV_3 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) \| RCC_CFGR_MCO1PRE_0 \| RCC_CFGR_MCO1PRE_1)
AnnaBridge	172:65be27845400	346	#define LL_RCC_MCO1_DIV_4 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) \| RCC_CFGR_MCO1PRE_2)
AnnaBridge	172:65be27845400	347	#define LL_RCC_MCO1_DIV_5 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) \| RCC_CFGR_MCO1PRE_0 \| RCC_CFGR_MCO1PRE_2)
AnnaBridge	172:65be27845400	348	#define LL_RCC_MCO1_DIV_6 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) \| RCC_CFGR_MCO1PRE_1 \| RCC_CFGR_MCO1PRE_2)
AnnaBridge	172:65be27845400	349	#define LL_RCC_MCO1_DIV_7 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) \| RCC_CFGR_MCO1PRE_0 \| RCC_CFGR_MCO1PRE_1 \| RCC_CFGR_MCO1PRE_2)
AnnaBridge	172:65be27845400	350	#define LL_RCC_MCO1_DIV_8 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) \| RCC_CFGR_MCO1PRE_3)
AnnaBridge	172:65be27845400	351	#define LL_RCC_MCO1_DIV_9 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) \| RCC_CFGR_MCO1PRE_0 \| RCC_CFGR_MCO1PRE_3)
AnnaBridge	172:65be27845400	352	#define LL_RCC_MCO1_DIV_10 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) \| RCC_CFGR_MCO1PRE_1 \| RCC_CFGR_MCO1PRE_3)
AnnaBridge	172:65be27845400	353	#define LL_RCC_MCO1_DIV_11 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) \| RCC_CFGR_MCO1PRE_0 \| RCC_CFGR_MCO1PRE_1 \| RCC_CFGR_MCO1PRE_3)
AnnaBridge	172:65be27845400	354	#define LL_RCC_MCO1_DIV_12 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) \| RCC_CFGR_MCO1PRE_2 \| RCC_CFGR_MCO1PRE_3)
AnnaBridge	172:65be27845400	355	#define LL_RCC_MCO1_DIV_13 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) \| RCC_CFGR_MCO1PRE_0 \| RCC_CFGR_MCO1PRE_2 \| RCC_CFGR_MCO1PRE_3)
AnnaBridge	172:65be27845400	356	#define LL_RCC_MCO1_DIV_14 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) \| RCC_CFGR_MCO1PRE_1 \| RCC_CFGR_MCO1PRE_2 \| RCC_CFGR_MCO1PRE_3)
AnnaBridge	172:65be27845400	357	#define LL_RCC_MCO1_DIV_15 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) \| RCC_CFGR_MCO1PRE)
AnnaBridge	172:65be27845400	358	#define LL_RCC_MCO2_DIV_1 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) \| RCC_CFGR_MCO2PRE_0)
AnnaBridge	172:65be27845400	359	#define LL_RCC_MCO2_DIV_2 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) \| RCC_CFGR_MCO2PRE_1)
AnnaBridge	172:65be27845400	360	#define LL_RCC_MCO2_DIV_3 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) \| RCC_CFGR_MCO2PRE_0 \| RCC_CFGR_MCO2PRE_1)
AnnaBridge	172:65be27845400	361	#define LL_RCC_MCO2_DIV_4 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) \| RCC_CFGR_MCO2PRE_2)
AnnaBridge	172:65be27845400	362	#define LL_RCC_MCO2_DIV_5 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) \| RCC_CFGR_MCO2PRE_0 \| RCC_CFGR_MCO2PRE_2)
AnnaBridge	172:65be27845400	363	#define LL_RCC_MCO2_DIV_6 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) \| RCC_CFGR_MCO2PRE_1 \| RCC_CFGR_MCO2PRE_2)
AnnaBridge	172:65be27845400	364	#define LL_RCC_MCO2_DIV_7 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) \| RCC_CFGR_MCO2PRE_0 \| RCC_CFGR_MCO2PRE_1 \| RCC_CFGR_MCO2PRE_2)
AnnaBridge	172:65be27845400	365	#define LL_RCC_MCO2_DIV_8 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) \| RCC_CFGR_MCO2PRE_3)
AnnaBridge	172:65be27845400	366	#define LL_RCC_MCO2_DIV_9 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) \| RCC_CFGR_MCO2PRE_0 \| RCC_CFGR_MCO2PRE_3)
AnnaBridge	172:65be27845400	367	#define LL_RCC_MCO2_DIV_10 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) \| RCC_CFGR_MCO2PRE_1 \| RCC_CFGR_MCO2PRE_3)
AnnaBridge	172:65be27845400	368	#define LL_RCC_MCO2_DIV_11 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) \| RCC_CFGR_MCO2PRE_0 \| RCC_CFGR_MCO2PRE_1 \| RCC_CFGR_MCO2PRE_3)
AnnaBridge	172:65be27845400	369	#define LL_RCC_MCO2_DIV_12 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) \| RCC_CFGR_MCO2PRE_2 \| RCC_CFGR_MCO2PRE_3)
AnnaBridge	172:65be27845400	370	#define LL_RCC_MCO2_DIV_13 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) \| RCC_CFGR_MCO2PRE_0 \| RCC_CFGR_MCO2PRE_2 \| RCC_CFGR_MCO2PRE_3)
AnnaBridge	172:65be27845400	371	#define LL_RCC_MCO2_DIV_14 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) \| RCC_CFGR_MCO2PRE_1 \| RCC_CFGR_MCO2PRE_2 \| RCC_CFGR_MCO2PRE_3)
AnnaBridge	172:65be27845400	372	#define LL_RCC_MCO2_DIV_15 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) \| RCC_CFGR_MCO2PRE)
AnnaBridge	172:65be27845400	373
AnnaBridge	172:65be27845400	374	/**
AnnaBridge	172:65be27845400	375	* @}
AnnaBridge	172:65be27845400	376	*/
AnnaBridge	172:65be27845400	377
AnnaBridge	172:65be27845400	378	/** @defgroup RCC_LL_EC_RTC_HSEDIV HSE prescaler for RTC clock
AnnaBridge	172:65be27845400	379	* @{
AnnaBridge	172:65be27845400	380	*/
AnnaBridge	172:65be27845400	381	#define LL_RCC_RTC_NOCLOCK (uint32_t)(0x00000000U)
AnnaBridge	172:65be27845400	382	#define LL_RCC_RTC_HSE_DIV_2 (uint32_t)(RCC_CFGR_RTCPRE_1)
AnnaBridge	172:65be27845400	383	#define LL_RCC_RTC_HSE_DIV_3 (uint32_t)(RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0)
AnnaBridge	172:65be27845400	384	#define LL_RCC_RTC_HSE_DIV_4 (uint32_t)(RCC_CFGR_RTCPRE_2)
AnnaBridge	172:65be27845400	385	#define LL_RCC_RTC_HSE_DIV_5 (uint32_t)(RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_0)
AnnaBridge	172:65be27845400	386	#define LL_RCC_RTC_HSE_DIV_6 (uint32_t)(RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1)
AnnaBridge	172:65be27845400	387	#define LL_RCC_RTC_HSE_DIV_7 (uint32_t)(RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0)
AnnaBridge	172:65be27845400	388	#define LL_RCC_RTC_HSE_DIV_8 (uint32_t)(RCC_CFGR_RTCPRE_3)
AnnaBridge	172:65be27845400	389	#define LL_RCC_RTC_HSE_DIV_9 (uint32_t)(RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_0)
AnnaBridge	172:65be27845400	390	#define LL_RCC_RTC_HSE_DIV_10 (uint32_t)(RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_1)
AnnaBridge	172:65be27845400	391	#define LL_RCC_RTC_HSE_DIV_11 (uint32_t)(RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0)
AnnaBridge	172:65be27845400	392	#define LL_RCC_RTC_HSE_DIV_12 (uint32_t)(RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2)
AnnaBridge	172:65be27845400	393	#define LL_RCC_RTC_HSE_DIV_13 (uint32_t)(RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_0)
AnnaBridge	172:65be27845400	394	#define LL_RCC_RTC_HSE_DIV_14 (uint32_t)(RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1)
AnnaBridge	172:65be27845400	395	#define LL_RCC_RTC_HSE_DIV_15 (uint32_t)(RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0)
AnnaBridge	172:65be27845400	396	#define LL_RCC_RTC_HSE_DIV_16 (uint32_t)(RCC_CFGR_RTCPRE_4)
AnnaBridge	172:65be27845400	397	#define LL_RCC_RTC_HSE_DIV_17 (uint32_t)(RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_0)
AnnaBridge	172:65be27845400	398	#define LL_RCC_RTC_HSE_DIV_18 (uint32_t)(RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_1)
AnnaBridge	172:65be27845400	399	#define LL_RCC_RTC_HSE_DIV_19 (uint32_t)(RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0)
AnnaBridge	172:65be27845400	400	#define LL_RCC_RTC_HSE_DIV_20 (uint32_t)(RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_2)
AnnaBridge	172:65be27845400	401	#define LL_RCC_RTC_HSE_DIV_21 (uint32_t)(RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_0)
AnnaBridge	172:65be27845400	402	#define LL_RCC_RTC_HSE_DIV_22 (uint32_t)(RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1)
AnnaBridge	172:65be27845400	403	#define LL_RCC_RTC_HSE_DIV_23 (uint32_t)(RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0)
AnnaBridge	172:65be27845400	404	#define LL_RCC_RTC_HSE_DIV_24 (uint32_t)(RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3)
AnnaBridge	172:65be27845400	405	#define LL_RCC_RTC_HSE_DIV_25 (uint32_t)(RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_0)
AnnaBridge	172:65be27845400	406	#define LL_RCC_RTC_HSE_DIV_26 (uint32_t)(RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_1)
AnnaBridge	172:65be27845400	407	#define LL_RCC_RTC_HSE_DIV_27 (uint32_t)(RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0)
AnnaBridge	172:65be27845400	408	#define LL_RCC_RTC_HSE_DIV_28 (uint32_t)(RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2)
AnnaBridge	172:65be27845400	409	#define LL_RCC_RTC_HSE_DIV_29 (uint32_t)(RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_0)
AnnaBridge	172:65be27845400	410	#define LL_RCC_RTC_HSE_DIV_30 (uint32_t)(RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1)
AnnaBridge	172:65be27845400	411	#define LL_RCC_RTC_HSE_DIV_31 (uint32_t)(RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0)
AnnaBridge	172:65be27845400	412	#define LL_RCC_RTC_HSE_DIV_32 (uint32_t)(RCC_CFGR_RTCPRE_5)
AnnaBridge	172:65be27845400	413	#define LL_RCC_RTC_HSE_DIV_33 (uint32_t)(RCC_CFGR_RTCPRE_5\|RCC_CFGR_RTCPRE_0)
AnnaBridge	172:65be27845400	414	#define LL_RCC_RTC_HSE_DIV_34 (uint32_t)(RCC_CFGR_RTCPRE_5\|RCC_CFGR_RTCPRE_1)
AnnaBridge	172:65be27845400	415	#define LL_RCC_RTC_HSE_DIV_35 (uint32_t)(RCC_CFGR_RTCPRE_5\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0)
AnnaBridge	172:65be27845400	416	#define LL_RCC_RTC_HSE_DIV_36 (uint32_t)(RCC_CFGR_RTCPRE_5\|RCC_CFGR_RTCPRE_2)
AnnaBridge	172:65be27845400	417	#define LL_RCC_RTC_HSE_DIV_37 (uint32_t)(RCC_CFGR_RTCPRE_5\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_0)
AnnaBridge	172:65be27845400	418	#define LL_RCC_RTC_HSE_DIV_38 (uint32_t)(RCC_CFGR_RTCPRE_5\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1)
AnnaBridge	172:65be27845400	419	#define LL_RCC_RTC_HSE_DIV_39 (uint32_t)(RCC_CFGR_RTCPRE_5\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0)
AnnaBridge	172:65be27845400	420	#define LL_RCC_RTC_HSE_DIV_40 (uint32_t)(RCC_CFGR_RTCPRE_5\|RCC_CFGR_RTCPRE_3)
AnnaBridge	172:65be27845400	421	#define LL_RCC_RTC_HSE_DIV_41 (uint32_t)(RCC_CFGR_RTCPRE_5\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_0)
AnnaBridge	172:65be27845400	422	#define LL_RCC_RTC_HSE_DIV_42 (uint32_t)(RCC_CFGR_RTCPRE_5\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_1)
AnnaBridge	172:65be27845400	423	#define LL_RCC_RTC_HSE_DIV_43 (uint32_t)(RCC_CFGR_RTCPRE_5\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0)
AnnaBridge	172:65be27845400	424	#define LL_RCC_RTC_HSE_DIV_44 (uint32_t)(RCC_CFGR_RTCPRE_5\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2)
AnnaBridge	172:65be27845400	425	#define LL_RCC_RTC_HSE_DIV_45 (uint32_t)(RCC_CFGR_RTCPRE_5\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_0)
AnnaBridge	172:65be27845400	426	#define LL_RCC_RTC_HSE_DIV_46 (uint32_t)(RCC_CFGR_RTCPRE_5\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1)
AnnaBridge	172:65be27845400	427	#define LL_RCC_RTC_HSE_DIV_47 (uint32_t)(RCC_CFGR_RTCPRE_5\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0)
AnnaBridge	172:65be27845400	428	#define LL_RCC_RTC_HSE_DIV_48 (uint32_t)(RCC_CFGR_RTCPRE_5\|RCC_CFGR_RTCPRE_4)
AnnaBridge	172:65be27845400	429	#define LL_RCC_RTC_HSE_DIV_49 (uint32_t)(RCC_CFGR_RTCPRE_5\|RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_0)
AnnaBridge	172:65be27845400	430	#define LL_RCC_RTC_HSE_DIV_50 (uint32_t)(RCC_CFGR_RTCPRE_5\|RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_1)
AnnaBridge	172:65be27845400	431	#define LL_RCC_RTC_HSE_DIV_51 (uint32_t)(RCC_CFGR_RTCPRE_5\|RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0)
AnnaBridge	172:65be27845400	432	#define LL_RCC_RTC_HSE_DIV_52 (uint32_t)(RCC_CFGR_RTCPRE_5\|RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_2)
AnnaBridge	172:65be27845400	433	#define LL_RCC_RTC_HSE_DIV_53 (uint32_t)(RCC_CFGR_RTCPRE_5\|RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_0)
AnnaBridge	172:65be27845400	434	#define LL_RCC_RTC_HSE_DIV_54 (uint32_t)(RCC_CFGR_RTCPRE_5\|RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1)
AnnaBridge	172:65be27845400	435	#define LL_RCC_RTC_HSE_DIV_55 (uint32_t)(RCC_CFGR_RTCPRE_5\|RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0)
AnnaBridge	172:65be27845400	436	#define LL_RCC_RTC_HSE_DIV_56 (uint32_t)(RCC_CFGR_RTCPRE_5\|RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3)
AnnaBridge	172:65be27845400	437	#define LL_RCC_RTC_HSE_DIV_57 (uint32_t)(RCC_CFGR_RTCPRE_5\|RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_0)
AnnaBridge	172:65be27845400	438	#define LL_RCC_RTC_HSE_DIV_58 (uint32_t)(RCC_CFGR_RTCPRE_5\|RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_1)
AnnaBridge	172:65be27845400	439	#define LL_RCC_RTC_HSE_DIV_59 (uint32_t)(RCC_CFGR_RTCPRE_5\|RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0)
AnnaBridge	172:65be27845400	440	#define LL_RCC_RTC_HSE_DIV_60 (uint32_t)(RCC_CFGR_RTCPRE_5\|RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2)
AnnaBridge	172:65be27845400	441	#define LL_RCC_RTC_HSE_DIV_61 (uint32_t)(RCC_CFGR_RTCPRE_5\|RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_0)
AnnaBridge	172:65be27845400	442	#define LL_RCC_RTC_HSE_DIV_62 (uint32_t)(RCC_CFGR_RTCPRE_5\|RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1)
AnnaBridge	172:65be27845400	443	#define LL_RCC_RTC_HSE_DIV_63 (uint32_t)(RCC_CFGR_RTCPRE_5\|RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0)
AnnaBridge	172:65be27845400	444	/**
AnnaBridge	172:65be27845400	445	* @}
AnnaBridge	172:65be27845400	446	*/
AnnaBridge	172:65be27845400	447
AnnaBridge	172:65be27845400	448	/** @defgroup RCC_LL_EC_USARTx_CLKSOURCE Peripheral USART clock source selection
AnnaBridge	172:65be27845400	449	* @{
AnnaBridge	172:65be27845400	450	*/
AnnaBridge	172:65be27845400	451	#define LL_RCC_USART16_CLKSOURCE_PCLK2 LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, 0x00000000U)
AnnaBridge	172:65be27845400	452	#define LL_RCC_USART16_CLKSOURCE_PLL2Q LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_0)
AnnaBridge	172:65be27845400	453	#define LL_RCC_USART16_CLKSOURCE_PLL3Q LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_1)
AnnaBridge	172:65be27845400	454	#define LL_RCC_USART16_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_0 \| RCC_D2CCIP2R_USART16SEL_1)
AnnaBridge	172:65be27845400	455	#define LL_RCC_USART16_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_2)
AnnaBridge	172:65be27845400	456	#define LL_RCC_USART16_CLKSOURCE_LSE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_0 \| RCC_D2CCIP2R_USART16SEL_2)
AnnaBridge	172:65be27845400	457	#define LL_RCC_USART234578_CLKSOURCE_PCLK1 LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, 0x00000000U)
AnnaBridge	172:65be27845400	458	#define LL_RCC_USART234578_CLKSOURCE_PLL2Q LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0)
AnnaBridge	172:65be27845400	459	#define LL_RCC_USART234578_CLKSOURCE_PLL3Q LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_1)
AnnaBridge	172:65be27845400	460	#define LL_RCC_USART234578_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0 \| RCC_D2CCIP2R_USART28SEL_1)
AnnaBridge	172:65be27845400	461	#define LL_RCC_USART234578_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_2)
AnnaBridge	172:65be27845400	462	#define LL_RCC_USART234578_CLKSOURCE_LSE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0 \| RCC_D2CCIP2R_USART28SEL_2)
AnnaBridge	172:65be27845400	463	/**
AnnaBridge	172:65be27845400	464	* @}
AnnaBridge	172:65be27845400	465	*/
AnnaBridge	172:65be27845400	466
AnnaBridge	172:65be27845400	467	/** @defgroup RCC_LL_EC_LPUARTx_CLKSOURCE Peripheral LPUART clock source selection
AnnaBridge	172:65be27845400	468	* @{
AnnaBridge	172:65be27845400	469	*/
AnnaBridge	172:65be27845400	470	#define LL_RCC_LPUART1_CLKSOURCE_PCLK4 (0x00000000U)
AnnaBridge	172:65be27845400	471	#define LL_RCC_LPUART1_CLKSOURCE_PLL2Q (RCC_D3CCIPR_LPUART1SEL_0)
AnnaBridge	172:65be27845400	472	#define LL_RCC_LPUART1_CLKSOURCE_PLL3Q (RCC_D3CCIPR_LPUART1SEL_1)
AnnaBridge	172:65be27845400	473	#define LL_RCC_LPUART1_CLKSOURCE_HSI (RCC_D3CCIPR_LPUART1SEL_0 \| RCC_D3CCIPR_LPUART1SEL_1)
AnnaBridge	172:65be27845400	474	#define LL_RCC_LPUART1_CLKSOURCE_CSI (RCC_D3CCIPR_LPUART1SEL_2)
AnnaBridge	172:65be27845400	475	#define LL_RCC_LPUART1_CLKSOURCE_LSE (RCC_D3CCIPR_LPUART1SEL_0 \| RCC_D3CCIPR_LPUART1SEL_2)
AnnaBridge	172:65be27845400	476	/**
AnnaBridge	172:65be27845400	477	* @}
AnnaBridge	172:65be27845400	478	*/
AnnaBridge	172:65be27845400	479
AnnaBridge	172:65be27845400	480	/** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE Peripheral I2C clock source selection
AnnaBridge	172:65be27845400	481	* @{
AnnaBridge	172:65be27845400	482	*/
AnnaBridge	172:65be27845400	483	#define LL_RCC_I2C123_CLKSOURCE_PCLK1 LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, 0x00000000U)
AnnaBridge	172:65be27845400	484	#define LL_RCC_I2C123_CLKSOURCE_PLL3R LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_0)
AnnaBridge	172:65be27845400	485	#define LL_RCC_I2C123_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_1)
AnnaBridge	172:65be27845400	486	#define LL_RCC_I2C123_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_0 \| RCC_D2CCIP2R_I2C123SEL_1)
AnnaBridge	172:65be27845400	487	#define LL_RCC_I2C4_CLKSOURCE_PCLK4 LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_I2C4SEL, RCC_D3CCIPR_I2C4SEL_Pos, 0x00000000U)
AnnaBridge	172:65be27845400	488	#define LL_RCC_I2C4_CLKSOURCE_PLL3R LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_I2C4SEL, RCC_D3CCIPR_I2C4SEL_Pos, RCC_D3CCIPR_I2C4SEL_0)
AnnaBridge	172:65be27845400	489	#define LL_RCC_I2C4_CLKSOURCE_HSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_I2C4SEL, RCC_D3CCIPR_I2C4SEL_Pos, RCC_D3CCIPR_I2C4SEL_1)
AnnaBridge	172:65be27845400	490	#define LL_RCC_I2C4_CLKSOURCE_CSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_I2C4SEL, RCC_D3CCIPR_I2C4SEL_Pos, RCC_D3CCIPR_I2C4SEL_0 \| RCC_D3CCIPR_I2C4SEL_1)
AnnaBridge	172:65be27845400	491	/**
AnnaBridge	172:65be27845400	492	* @}
AnnaBridge	172:65be27845400	493	*/
AnnaBridge	172:65be27845400	494
AnnaBridge	172:65be27845400	495	/** @defgroup RCC_LL_EC_LPTIMx_CLKSOURCE Peripheral LPTIM clock source selection
AnnaBridge	172:65be27845400	496	* @{
AnnaBridge	172:65be27845400	497	*/
AnnaBridge	172:65be27845400	498	#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, 0x00000000U)
AnnaBridge	172:65be27845400	499	#define LL_RCC_LPTIM1_CLKSOURCE_PLL2P LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, RCC_D2CCIP2R_LPTIM1SEL_0)
AnnaBridge	172:65be27845400	500	#define LL_RCC_LPTIM1_CLKSOURCE_PLL3R LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, RCC_D2CCIP2R_LPTIM1SEL_1)
AnnaBridge	172:65be27845400	501	#define LL_RCC_LPTIM1_CLKSOURCE_LSE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, RCC_D2CCIP2R_LPTIM1SEL_0 \| RCC_D2CCIP2R_LPTIM1SEL_1)
AnnaBridge	172:65be27845400	502	#define LL_RCC_LPTIM1_CLKSOURCE_LSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, RCC_D2CCIP2R_LPTIM1SEL_2)
AnnaBridge	172:65be27845400	503	#define LL_RCC_LPTIM1_CLKSOURCE_CLKP LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, RCC_D2CCIP2R_LPTIM1SEL_0 \| RCC_D2CCIP2R_LPTIM1SEL_2)
AnnaBridge	172:65be27845400	504	#define LL_RCC_LPTIM2_CLKSOURCE_PCLK4 LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, 0x00000000U)
AnnaBridge	172:65be27845400	505	#define LL_RCC_LPTIM2_CLKSOURCE_PLL2P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, RCC_D3CCIPR_LPTIM2SEL_0)
AnnaBridge	172:65be27845400	506	#define LL_RCC_LPTIM2_CLKSOURCE_PLL3R LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, RCC_D3CCIPR_LPTIM2SEL_1)
AnnaBridge	172:65be27845400	507	#define LL_RCC_LPTIM2_CLKSOURCE_LSE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, RCC_D3CCIPR_LPTIM2SEL_0 \| RCC_D3CCIPR_LPTIM2SEL_1)
AnnaBridge	172:65be27845400	508	#define LL_RCC_LPTIM2_CLKSOURCE_LSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, RCC_D3CCIPR_LPTIM2SEL_2)
AnnaBridge	172:65be27845400	509	#define LL_RCC_LPTIM2_CLKSOURCE_CLKP LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, RCC_D3CCIPR_LPTIM2SEL_0 \| RCC_D3CCIPR_LPTIM2SEL_2)
AnnaBridge	172:65be27845400	510	#define LL_RCC_LPTIM345_CLKSOURCE_PCLK4 LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, 0x00000000U)
AnnaBridge	172:65be27845400	511	#define LL_RCC_LPTIM345_CLKSOURCE_PLL2P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0)
AnnaBridge	172:65be27845400	512	#define LL_RCC_LPTIM345_CLKSOURCE_PLL3R LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_1)
AnnaBridge	172:65be27845400	513	#define LL_RCC_LPTIM345_CLKSOURCE_LSE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0 \| RCC_D3CCIPR_LPTIM345SEL_1)
AnnaBridge	172:65be27845400	514	#define LL_RCC_LPTIM345_CLKSOURCE_LSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_2)
AnnaBridge	172:65be27845400	515	#define LL_RCC_LPTIM345_CLKSOURCE_CLKP LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0 \| RCC_D3CCIPR_LPTIM345SEL_2)
AnnaBridge	172:65be27845400	516	/**
AnnaBridge	172:65be27845400	517	* @}
AnnaBridge	172:65be27845400	518	*/
AnnaBridge	172:65be27845400	519
AnnaBridge	172:65be27845400	520	/** @defgroup RCC_LL_EC_SAIx_CLKSOURCE Peripheral SAI clock source selection
AnnaBridge	172:65be27845400	521	* @{
AnnaBridge	172:65be27845400	522	*/
AnnaBridge	172:65be27845400	523	#define LL_RCC_SAI1_CLKSOURCE_PLL1Q LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, 0x00000000U)
AnnaBridge	172:65be27845400	524	#define LL_RCC_SAI1_CLKSOURCE_PLL2P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, RCC_D2CCIP1R_SAI1SEL_0)
AnnaBridge	172:65be27845400	525	#define LL_RCC_SAI1_CLKSOURCE_PLL3P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, RCC_D2CCIP1R_SAI1SEL_1)
AnnaBridge	172:65be27845400	526	#define LL_RCC_SAI1_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, RCC_D2CCIP1R_SAI1SEL_0 \| RCC_D2CCIP1R_SAI1SEL_1)
AnnaBridge	172:65be27845400	527	#define LL_RCC_SAI1_CLKSOURCE_CLKP LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, RCC_D2CCIP1R_SAI1SEL_2)
AnnaBridge	172:65be27845400	528	#define LL_RCC_SAI23_CLKSOURCE_PLL1Q LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, 0x00000000U)
AnnaBridge	172:65be27845400	529	#define LL_RCC_SAI23_CLKSOURCE_PLL2P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_0)
AnnaBridge	172:65be27845400	530	#define LL_RCC_SAI23_CLKSOURCE_PLL3P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_1)
AnnaBridge	172:65be27845400	531	#define LL_RCC_SAI23_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_0 \| RCC_D2CCIP1R_SAI23SEL_1)
AnnaBridge	172:65be27845400	532	#define LL_RCC_SAI23_CLKSOURCE_CLKP LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_2)
AnnaBridge	172:65be27845400	533	#define LL_RCC_SAI4A_CLKSOURCE_PLL1Q LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, 0x00000000U)
AnnaBridge	172:65be27845400	534	#define LL_RCC_SAI4A_CLKSOURCE_PLL2P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, RCC_D3CCIPR_SAI4ASEL_0)
AnnaBridge	172:65be27845400	535	#define LL_RCC_SAI4A_CLKSOURCE_PLL3P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, RCC_D3CCIPR_SAI4ASEL_1)
AnnaBridge	172:65be27845400	536	#define LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, RCC_D3CCIPR_SAI4ASEL_0 \| RCC_D3CCIPR_SAI4ASEL_1)
AnnaBridge	172:65be27845400	537	#define LL_RCC_SAI4A_CLKSOURCE_CLKP LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, RCC_D3CCIPR_SAI4ASEL_2)
AnnaBridge	172:65be27845400	538	#define LL_RCC_SAI4B_CLKSOURCE_PLL1Q LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, 0x00000000U)
AnnaBridge	172:65be27845400	539	#define LL_RCC_SAI4B_CLKSOURCE_PLL2P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, RCC_D3CCIPR_SAI4BSEL_0)
AnnaBridge	172:65be27845400	540	#define LL_RCC_SAI4B_CLKSOURCE_PLL3P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, RCC_D3CCIPR_SAI4BSEL_1)
AnnaBridge	172:65be27845400	541	#define LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, RCC_D3CCIPR_SAI4BSEL_0 \| RCC_D3CCIPR_SAI4BSEL_1)
AnnaBridge	172:65be27845400	542	#define LL_RCC_SAI4B_CLKSOURCE_CLKP LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, RCC_D3CCIPR_SAI4BSEL_2)
AnnaBridge	172:65be27845400	543	/**
AnnaBridge	172:65be27845400	544	* @}
AnnaBridge	172:65be27845400	545	*/
AnnaBridge	172:65be27845400	546
AnnaBridge	172:65be27845400	547	/** @defgroup RCC_LL_EC_SDMMC_CLKSOURCE Peripheral SDMMC clock source selection
AnnaBridge	172:65be27845400	548	* @{
AnnaBridge	172:65be27845400	549	*/
AnnaBridge	172:65be27845400	550	#define LL_RCC_SDMMC_CLKSOURCE_PLL1Q (0x00000000U)
AnnaBridge	172:65be27845400	551	#define LL_RCC_SDMMC_CLKSOURCE_PLL2R (RCC_D1CCIPR_SDMMCSEL)
AnnaBridge	172:65be27845400	552	/**
AnnaBridge	172:65be27845400	553	* @}
AnnaBridge	172:65be27845400	554	*/
AnnaBridge	172:65be27845400	555
AnnaBridge	172:65be27845400	556	/** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
AnnaBridge	172:65be27845400	557	* @{
AnnaBridge	172:65be27845400	558	*/
AnnaBridge	172:65be27845400	559	#define LL_RCC_RNG_CLKSOURCE_HSI48 (0x00000000U)
AnnaBridge	172:65be27845400	560	#define LL_RCC_RNG_CLKSOURCE_PLL1Q (RCC_D2CCIP2R_RNGSEL_0)
AnnaBridge	172:65be27845400	561	#define LL_RCC_RNG_CLKSOURCE_LSE (RCC_D2CCIP2R_RNGSEL_1)
AnnaBridge	172:65be27845400	562	#define LL_RCC_RNG_CLKSOURCE_LSI (RCC_D2CCIP2R_RNGSEL_1 \| RCC_D2CCIP2R_RNGSEL_0)
AnnaBridge	172:65be27845400	563	/**
AnnaBridge	172:65be27845400	564	* @}
AnnaBridge	172:65be27845400	565	*/
AnnaBridge	172:65be27845400	566
AnnaBridge	172:65be27845400	567	/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
AnnaBridge	172:65be27845400	568	* @{
AnnaBridge	172:65be27845400	569	*/
AnnaBridge	172:65be27845400	570	#define LL_RCC_USB_CLKSOURCE_DISABLE (0x00000000U)
AnnaBridge	172:65be27845400	571	#define LL_RCC_USB_CLKSOURCE_PLL1Q (RCC_D2CCIP2R_USBSEL_0)
AnnaBridge	172:65be27845400	572	#define LL_RCC_USB_CLKSOURCE_PLL3Q (RCC_D2CCIP2R_USBSEL_1)
AnnaBridge	172:65be27845400	573	#define LL_RCC_USB_CLKSOURCE_HSI48 (RCC_D2CCIP2R_USBSEL_1 \| RCC_D2CCIP2R_USBSEL_0)
AnnaBridge	172:65be27845400	574	/**
AnnaBridge	172:65be27845400	575	* @}
AnnaBridge	172:65be27845400	576	*/
AnnaBridge	172:65be27845400	577
AnnaBridge	172:65be27845400	578	/** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection
AnnaBridge	172:65be27845400	579	* @{
AnnaBridge	172:65be27845400	580	*/
AnnaBridge	172:65be27845400	581	#define LL_RCC_CEC_CLKSOURCE_LSE (0x00000000U)
AnnaBridge	172:65be27845400	582	#define LL_RCC_CEC_CLKSOURCE_LSI (RCC_D2CCIP2R_CECSEL_0)
AnnaBridge	172:65be27845400	583	#define LL_RCC_CEC_CLKSOURCE_CSI_DIV122 (RCC_D2CCIP2R_CECSEL_1)
AnnaBridge	172:65be27845400	584	/**
AnnaBridge	172:65be27845400	585	* @}
AnnaBridge	172:65be27845400	586	*/
AnnaBridge	172:65be27845400	587
AnnaBridge	172:65be27845400	588	/** @defgroup RCC_LL_EC_DFSDM_CLKSOURCE Peripheral DFSDM clock source selection
AnnaBridge	172:65be27845400	589	* @{
AnnaBridge	172:65be27845400	590	*/
AnnaBridge	172:65be27845400	591	#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 (0x00000000U)
AnnaBridge	172:65be27845400	592	#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK (RCC_D2CCIP1R_DFSDM1SEL)
AnnaBridge	172:65be27845400	593	/**
AnnaBridge	172:65be27845400	594	* @}
AnnaBridge	172:65be27845400	595	*/
AnnaBridge	172:65be27845400	596
AnnaBridge	172:65be27845400	597	/** @defgroup RCC_LL_EC_FMC_CLKSOURCE Peripheral FMC clock source selection
AnnaBridge	172:65be27845400	598	* @{
AnnaBridge	172:65be27845400	599	*/
AnnaBridge	172:65be27845400	600	#define LL_RCC_FMC_CLKSOURCE_HCLK (0x00000000U)
AnnaBridge	172:65be27845400	601	#define LL_RCC_FMC_CLKSOURCE_PLL1Q (RCC_D1CCIPR_FMCSEL_0)
AnnaBridge	172:65be27845400	602	#define LL_RCC_FMC_CLKSOURCE_PLL2R (RCC_D1CCIPR_FMCSEL_1)
AnnaBridge	172:65be27845400	603	#define LL_RCC_FMC_CLKSOURCE_CLKP (RCC_D1CCIPR_FMCSEL_0 \| RCC_D1CCIPR_FMCSEL_1)
AnnaBridge	172:65be27845400	604	/**
AnnaBridge	172:65be27845400	605	* @}
AnnaBridge	172:65be27845400	606	*/
AnnaBridge	172:65be27845400	607
AnnaBridge	172:65be27845400	608	/** @defgroup RCC_LL_EC_QSPI_CLKSOURCE Peripheral QSPI clock source selection
AnnaBridge	172:65be27845400	609	* @{
AnnaBridge	172:65be27845400	610	*/
AnnaBridge	172:65be27845400	611	#define LL_RCC_QSPI_CLKSOURCE_HCLK (0x00000000U)
AnnaBridge	172:65be27845400	612	#define LL_RCC_QSPI_CLKSOURCE_PLL1Q (RCC_D1CCIPR_QSPISEL_0)
AnnaBridge	172:65be27845400	613	#define LL_RCC_QSPI_CLKSOURCE_PLL2R (RCC_D1CCIPR_QSPISEL_1)
AnnaBridge	172:65be27845400	614	#define LL_RCC_QSPI_CLKSOURCE_CLKP (RCC_D1CCIPR_QSPISEL_0 \| RCC_D1CCIPR_QSPISEL_1)
AnnaBridge	172:65be27845400	615	/**
AnnaBridge	172:65be27845400	616	* @}
AnnaBridge	172:65be27845400	617	*/
AnnaBridge	172:65be27845400	618
AnnaBridge	172:65be27845400	619	/** @defgroup RCC_LL_EC_CLKP_CLKSOURCE Peripheral CLKP clock source selection
AnnaBridge	172:65be27845400	620	* @{
AnnaBridge	172:65be27845400	621	*/
AnnaBridge	172:65be27845400	622	#define LL_RCC_CLKP_CLKSOURCE_HSI (0x00000000U)
AnnaBridge	172:65be27845400	623	#define LL_RCC_CLKP_CLKSOURCE_CSI (RCC_D1CCIPR_CKPERSEL_0)
AnnaBridge	172:65be27845400	624	#define LL_RCC_CLKP_CLKSOURCE_HSE (RCC_D1CCIPR_CKPERSEL_1)
AnnaBridge	172:65be27845400	625	/**
AnnaBridge	172:65be27845400	626	* @}
AnnaBridge	172:65be27845400	627	*/
AnnaBridge	172:65be27845400	628
AnnaBridge	172:65be27845400	629	/** @defgroup RCC_LL_EC_SPIx_CLKSOURCE Peripheral SPI clock source selection
AnnaBridge	172:65be27845400	630	* @{
AnnaBridge	172:65be27845400	631	*/
AnnaBridge	172:65be27845400	632	#define LL_RCC_SPI123_CLKSOURCE_PLL1Q LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, 0x00000000U)
AnnaBridge	172:65be27845400	633	#define LL_RCC_SPI123_CLKSOURCE_PLL2P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_0)
AnnaBridge	172:65be27845400	634	#define LL_RCC_SPI123_CLKSOURCE_PLL3P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_1)
AnnaBridge	172:65be27845400	635	#define LL_RCC_SPI123_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_0 \| RCC_D2CCIP1R_SPI123SEL_1)
AnnaBridge	172:65be27845400	636	#define LL_RCC_SPI123_CLKSOURCE_CLKP LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_2)
AnnaBridge	172:65be27845400	637	#define LL_RCC_SPI45_CLKSOURCE_PCLK2 LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, 0x00000000U)
AnnaBridge	172:65be27845400	638	#define LL_RCC_SPI45_CLKSOURCE_PLL2Q LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, RCC_D2CCIP1R_SPI45SEL_0)
AnnaBridge	172:65be27845400	639	#define LL_RCC_SPI45_CLKSOURCE_PLL3Q LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, RCC_D2CCIP1R_SPI45SEL_1)
AnnaBridge	172:65be27845400	640	#define LL_RCC_SPI45_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, RCC_D2CCIP1R_SPI45SEL_0 \| RCC_D2CCIP1R_SPI45SEL_1)
AnnaBridge	172:65be27845400	641	#define LL_RCC_SPI45_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, RCC_D2CCIP1R_SPI45SEL_2)
AnnaBridge	172:65be27845400	642	#define LL_RCC_SPI45_CLKSOURCE_HSE LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, RCC_D2CCIP1R_SPI45SEL_0 \| RCC_D2CCIP1R_SPI45SEL_2)
AnnaBridge	172:65be27845400	643	#define LL_RCC_SPI6_CLKSOURCE_PCLK4 LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, 0x00000000U)
AnnaBridge	172:65be27845400	644	#define LL_RCC_SPI6_CLKSOURCE_PLL2Q LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, RCC_D3CCIPR_SPI6SEL_0)
AnnaBridge	172:65be27845400	645	#define LL_RCC_SPI6_CLKSOURCE_PLL3Q LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, RCC_D3CCIPR_SPI6SEL_1)
AnnaBridge	172:65be27845400	646	#define LL_RCC_SPI6_CLKSOURCE_HSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, RCC_D3CCIPR_SPI6SEL_0 \| RCC_D3CCIPR_SPI6SEL_1)
AnnaBridge	172:65be27845400	647	#define LL_RCC_SPI6_CLKSOURCE_CSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, RCC_D3CCIPR_SPI6SEL_2)
AnnaBridge	172:65be27845400	648	#define LL_RCC_SPI6_CLKSOURCE_HSE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, RCC_D3CCIPR_SPI6SEL_0 \| RCC_D3CCIPR_SPI6SEL_2)
AnnaBridge	172:65be27845400	649	/**
AnnaBridge	172:65be27845400	650	* @}
AnnaBridge	172:65be27845400	651	*/
AnnaBridge	172:65be27845400	652
AnnaBridge	172:65be27845400	653	/** @defgroup RCC_LL_EC_SPDIF_CLKSOURCE Peripheral SPDIF clock source selection
AnnaBridge	172:65be27845400	654	* @{
AnnaBridge	172:65be27845400	655	*/
AnnaBridge	172:65be27845400	656	#define LL_RCC_SPDIF_CLKSOURCE_PLL1Q (0x00000000U)
AnnaBridge	172:65be27845400	657	#define LL_RCC_SPDIF_CLKSOURCE_PLL2R (RCC_D2CCIP1R_SPDIFSEL_0)
AnnaBridge	172:65be27845400	658	#define LL_RCC_SPDIF_CLKSOURCE_PLL3R (RCC_D2CCIP1R_SPDIFSEL_1)
AnnaBridge	172:65be27845400	659	#define LL_RCC_SPDIF_CLKSOURCE_HSI (RCC_D2CCIP1R_SPDIFSEL_0 \| RCC_D2CCIP1R_SPDIFSEL_1)
AnnaBridge	172:65be27845400	660	/**
AnnaBridge	172:65be27845400	661	* @}
AnnaBridge	172:65be27845400	662	*/
AnnaBridge	172:65be27845400	663
AnnaBridge	172:65be27845400	664	/** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE Peripheral FDCAN clock source selection
AnnaBridge	172:65be27845400	665	* @{
AnnaBridge	172:65be27845400	666	*/
AnnaBridge	172:65be27845400	667	#define LL_RCC_FDCAN_CLKSOURCE_HSE (0x00000000U)
AnnaBridge	172:65be27845400	668	#define LL_RCC_FDCAN_CLKSOURCE_PLL1Q (RCC_D2CCIP1R_FDCANSEL_0)
AnnaBridge	172:65be27845400	669	#define LL_RCC_FDCAN_CLKSOURCE_PLL2Q (RCC_D2CCIP1R_FDCANSEL_1)
AnnaBridge	172:65be27845400	670	/**
AnnaBridge	172:65be27845400	671	* @}
AnnaBridge	172:65be27845400	672	*/
AnnaBridge	172:65be27845400	673
AnnaBridge	172:65be27845400	674	/** @defgroup RCC_LL_EC_SWP_CLKSOURCE Peripheral SWP clock source selection
AnnaBridge	172:65be27845400	675	* @{
AnnaBridge	172:65be27845400	676	*/
AnnaBridge	172:65be27845400	677	#define LL_RCC_SWP_CLKSOURCE_PCLK1 (0x00000000U)
AnnaBridge	172:65be27845400	678	#define LL_RCC_SWP_CLKSOURCE_HSI (RCC_D2CCIP1R_SWPSEL)
AnnaBridge	172:65be27845400	679	/**
AnnaBridge	172:65be27845400	680	* @}
AnnaBridge	172:65be27845400	681	*/
AnnaBridge	172:65be27845400	682
AnnaBridge	172:65be27845400	683	/** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection
AnnaBridge	172:65be27845400	684	* @{
AnnaBridge	172:65be27845400	685	*/
AnnaBridge	172:65be27845400	686	#define LL_RCC_ADC_CLKSOURCE_PLL2P (0x00000000U)
AnnaBridge	172:65be27845400	687	#define LL_RCC_ADC_CLKSOURCE_PLL3R (RCC_D3CCIPR_ADCSEL_0)
AnnaBridge	172:65be27845400	688	#define LL_RCC_ADC_CLKSOURCE_CLKP (RCC_D3CCIPR_ADCSEL_1)
AnnaBridge	172:65be27845400	689	/**
AnnaBridge	172:65be27845400	690	* @}
AnnaBridge	172:65be27845400	691	*/
AnnaBridge	172:65be27845400	692
AnnaBridge	172:65be27845400	693	/** @defgroup RCC_LL_EC_USARTx Peripheral USART get clock source
AnnaBridge	172:65be27845400	694	* @{
AnnaBridge	172:65be27845400	695	*/
AnnaBridge	172:65be27845400	696	#define LL_RCC_USART16_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, 0x00000000U)
AnnaBridge	172:65be27845400	697	#define LL_RCC_USART234578_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, 0x00000000U)
AnnaBridge	172:65be27845400	698	/**
AnnaBridge	172:65be27845400	699	* @}
AnnaBridge	172:65be27845400	700	*/
AnnaBridge	172:65be27845400	701
AnnaBridge	172:65be27845400	702	/** @defgroup RCC_LL_EC_LPUARTx Peripheral LPUART get clock source
AnnaBridge	172:65be27845400	703	* @{
AnnaBridge	172:65be27845400	704	*/
AnnaBridge	172:65be27845400	705	#define LL_RCC_LPUART1_CLKSOURCE RCC_D3CCIPR_LPUART1SEL
AnnaBridge	172:65be27845400	706	/**
AnnaBridge	172:65be27845400	707	* @}
AnnaBridge	172:65be27845400	708	*/
AnnaBridge	172:65be27845400	709
AnnaBridge	172:65be27845400	710	/** @defgroup RCC_LL_EC_I2Cx Peripheral I2C get clock source
AnnaBridge	172:65be27845400	711	* @{
AnnaBridge	172:65be27845400	712	*/
AnnaBridge	172:65be27845400	713	#define LL_RCC_I2C123_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, 0x00000000U)
AnnaBridge	172:65be27845400	714	#define LL_RCC_I2C4_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_I2C4SEL, RCC_D3CCIPR_I2C4SEL_Pos, 0x00000000U)
AnnaBridge	172:65be27845400	715	/**
AnnaBridge	172:65be27845400	716	* @}
AnnaBridge	172:65be27845400	717	*/
AnnaBridge	172:65be27845400	718
AnnaBridge	172:65be27845400	719	/** @defgroup RCC_LL_EC_LPTIMx Peripheral LPTIM get clock source
AnnaBridge	172:65be27845400	720	* @{
AnnaBridge	172:65be27845400	721	*/
AnnaBridge	172:65be27845400	722	#define LL_RCC_LPTIM1_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, 0x00000000U)
AnnaBridge	172:65be27845400	723	#define LL_RCC_LPTIM2_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, 0x00000000U)
AnnaBridge	172:65be27845400	724	#define LL_RCC_LPTIM345_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, 0x00000000U)
AnnaBridge	172:65be27845400	725	/**
AnnaBridge	172:65be27845400	726	* @}
AnnaBridge	172:65be27845400	727	*/
AnnaBridge	172:65be27845400	728
AnnaBridge	172:65be27845400	729	/** @defgroup RCC_LL_EC_SAIx Peripheral SAI get clock source
AnnaBridge	172:65be27845400	730	* @{
AnnaBridge	172:65be27845400	731	*/
AnnaBridge	172:65be27845400	732	#define LL_RCC_SAI1_CLKSOURCE LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, 0x00000000U)
AnnaBridge	172:65be27845400	733	#define LL_RCC_SAI23_CLKSOURCE LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, 0x00000000U)
AnnaBridge	172:65be27845400	734	#define LL_RCC_SAI4A_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, 0x00000000U)
AnnaBridge	172:65be27845400	735	#define LL_RCC_SAI4B_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, 0x00000000U)
AnnaBridge	172:65be27845400	736	/**
AnnaBridge	172:65be27845400	737	* @}
AnnaBridge	172:65be27845400	738	*/
AnnaBridge	172:65be27845400	739
AnnaBridge	172:65be27845400	740	/** @defgroup RCC_LL_EC_SDMMC Peripheral SDMMC get clock source
AnnaBridge	172:65be27845400	741	* @{
AnnaBridge	172:65be27845400	742	*/
AnnaBridge	172:65be27845400	743	#define LL_RCC_SDMMC_CLKSOURCE RCC_D1CCIPR_SDMMCSEL
AnnaBridge	172:65be27845400	744	/**
AnnaBridge	172:65be27845400	745	* @}
AnnaBridge	172:65be27845400	746	*/
AnnaBridge	172:65be27845400	747
AnnaBridge	172:65be27845400	748	/** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
AnnaBridge	172:65be27845400	749	* @{
AnnaBridge	172:65be27845400	750	*/
AnnaBridge	172:65be27845400	751	#define LL_RCC_RNG_CLKSOURCE RCC_D2CCIP2R_RNGSEL
AnnaBridge	172:65be27845400	752	/**
AnnaBridge	172:65be27845400	753	* @}
AnnaBridge	172:65be27845400	754	*/
AnnaBridge	172:65be27845400	755
AnnaBridge	172:65be27845400	756	/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
AnnaBridge	172:65be27845400	757	* @{
AnnaBridge	172:65be27845400	758	*/
AnnaBridge	172:65be27845400	759	#define LL_RCC_USB_CLKSOURCE RCC_D2CCIP2R_USBSEL
AnnaBridge	172:65be27845400	760	/**
AnnaBridge	172:65be27845400	761	* @}
AnnaBridge	172:65be27845400	762	*/
AnnaBridge	172:65be27845400	763
AnnaBridge	172:65be27845400	764	/** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source
AnnaBridge	172:65be27845400	765	* @{
AnnaBridge	172:65be27845400	766	*/
AnnaBridge	172:65be27845400	767	#define LL_RCC_CEC_CLKSOURCE RCC_D2CCIP2R_CECSEL
AnnaBridge	172:65be27845400	768	/**
AnnaBridge	172:65be27845400	769	* @}
AnnaBridge	172:65be27845400	770	*/
AnnaBridge	172:65be27845400	771
AnnaBridge	172:65be27845400	772	/** @defgroup RCC_LL_EC_DFSDM Peripheral DFSDM get clock source
AnnaBridge	172:65be27845400	773	* @{
AnnaBridge	172:65be27845400	774	*/
AnnaBridge	172:65be27845400	775	#define LL_RCC_DFSDM1_CLKSOURCE RCC_D2CCIP1R_DFSDM1SEL
AnnaBridge	172:65be27845400	776	/**
AnnaBridge	172:65be27845400	777	* @}
AnnaBridge	172:65be27845400	778	*/
AnnaBridge	172:65be27845400	779
AnnaBridge	172:65be27845400	780	/** @defgroup RCC_LL_EC_FMC Peripheral FMC get clock source
AnnaBridge	172:65be27845400	781	* @{
AnnaBridge	172:65be27845400	782	*/
AnnaBridge	172:65be27845400	783	#define LL_RCC_FMC_CLKSOURCE RCC_D1CCIPR_FMCSEL
AnnaBridge	172:65be27845400	784	/**
AnnaBridge	172:65be27845400	785	* @}
AnnaBridge	172:65be27845400	786	*/
AnnaBridge	172:65be27845400	787
AnnaBridge	172:65be27845400	788	/** @defgroup RCC_LL_EC_QSPI Peripheral QSPI get clock source
AnnaBridge	172:65be27845400	789	* @{
AnnaBridge	172:65be27845400	790	*/
AnnaBridge	172:65be27845400	791	#define LL_RCC_QSPI_CLKSOURCE RCC_D1CCIPR_QSPISEL
AnnaBridge	172:65be27845400	792	/**
AnnaBridge	172:65be27845400	793	* @}
AnnaBridge	172:65be27845400	794	*/
AnnaBridge	172:65be27845400	795
AnnaBridge	172:65be27845400	796	/** @defgroup RCC_LL_EC_CLKP Peripheral CLKP get clock source
AnnaBridge	172:65be27845400	797	* @{
AnnaBridge	172:65be27845400	798	*/
AnnaBridge	172:65be27845400	799	#define LL_RCC_CLKP_CLKSOURCE RCC_D1CCIPR_CKPERSEL
AnnaBridge	172:65be27845400	800	/**
AnnaBridge	172:65be27845400	801	* @}
AnnaBridge	172:65be27845400	802	*/
AnnaBridge	172:65be27845400	803
AnnaBridge	172:65be27845400	804	/** @defgroup RCC_LL_EC_SPIx Peripheral SPI get clock source
AnnaBridge	172:65be27845400	805	* @{
AnnaBridge	172:65be27845400	806	*/
AnnaBridge	172:65be27845400	807	#define LL_RCC_SPI123_CLKSOURCE LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, 0x00000000U)
AnnaBridge	172:65be27845400	808	#define LL_RCC_SPI45_CLKSOURCE LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, 0x00000000U)
AnnaBridge	172:65be27845400	809	#define LL_RCC_SPI6_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, 0x00000000U)
AnnaBridge	172:65be27845400	810	/**
AnnaBridge	172:65be27845400	811	* @}
AnnaBridge	172:65be27845400	812	*/
AnnaBridge	172:65be27845400	813
AnnaBridge	172:65be27845400	814	/** @defgroup RCC_LL_EC_SPDIF Peripheral SPDIF get clock source
AnnaBridge	172:65be27845400	815	* @{
AnnaBridge	172:65be27845400	816	*/
AnnaBridge	172:65be27845400	817	#define LL_RCC_SPDIF_CLKSOURCE RCC_D2CCIP1R_SPDIFSEL
AnnaBridge	172:65be27845400	818	/**
AnnaBridge	172:65be27845400	819	* @}
AnnaBridge	172:65be27845400	820	*/
AnnaBridge	172:65be27845400	821
AnnaBridge	172:65be27845400	822	/** @defgroup RCC_LL_EC_FDCAN Peripheral FDCAN get clock source
AnnaBridge	172:65be27845400	823	* @{
AnnaBridge	172:65be27845400	824	*/
AnnaBridge	172:65be27845400	825	#define LL_RCC_FDCAN_CLKSOURCE RCC_D2CCIP1R_FDCANSEL
AnnaBridge	172:65be27845400	826	/**
AnnaBridge	172:65be27845400	827	* @}
AnnaBridge	172:65be27845400	828	*/
AnnaBridge	172:65be27845400	829
AnnaBridge	172:65be27845400	830	/** @defgroup RCC_LL_EC_SWP Peripheral SWP get clock source
AnnaBridge	172:65be27845400	831	* @{
AnnaBridge	172:65be27845400	832	*/
AnnaBridge	172:65be27845400	833	#define LL_RCC_SWP_CLKSOURCE RCC_D2CCIP1R_SWPSEL
AnnaBridge	172:65be27845400	834	/**
AnnaBridge	172:65be27845400	835	* @}
AnnaBridge	172:65be27845400	836	*/
AnnaBridge	172:65be27845400	837
AnnaBridge	172:65be27845400	838	/** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source
AnnaBridge	172:65be27845400	839	* @{
AnnaBridge	172:65be27845400	840	*/
AnnaBridge	172:65be27845400	841	#define LL_RCC_ADC_CLKSOURCE RCC_D3CCIPR_ADCSEL
AnnaBridge	172:65be27845400	842	/**
AnnaBridge	172:65be27845400	843	* @}
AnnaBridge	172:65be27845400	844	*/
AnnaBridge	172:65be27845400	845
AnnaBridge	172:65be27845400	846	/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
AnnaBridge	172:65be27845400	847	* @{
AnnaBridge	172:65be27845400	848	*/
AnnaBridge	172:65be27845400	849	#define LL_RCC_RTC_CLKSOURCE_NONE (uint32_t)(0x00000000U)
AnnaBridge	172:65be27845400	850	#define LL_RCC_RTC_CLKSOURCE_LSE (uint32_t)(RCC_BDCR_RTCSEL_0)
AnnaBridge	172:65be27845400	851	#define LL_RCC_RTC_CLKSOURCE_LSI (uint32_t)(RCC_BDCR_RTCSEL_1)
AnnaBridge	172:65be27845400	852	#define LL_RCC_RTC_CLKSOURCE_HSE (uint32_t)(RCC_BDCR_RTCSEL_0 \| RCC_BDCR_RTCSEL_1)
AnnaBridge	172:65be27845400	853	/**
AnnaBridge	172:65be27845400	854	* @}
AnnaBridge	172:65be27845400	855	*/
AnnaBridge	172:65be27845400	856
AnnaBridge	172:65be27845400	857	/** @defgroup RCC_LL_EC_TIM_CLKPRESCALER Timers clocks prescalers selection
AnnaBridge	172:65be27845400	858	* @{
AnnaBridge	172:65be27845400	859	*/
AnnaBridge	172:65be27845400	860	#define LL_RCC_TIM_PRESCALER_TWICE (uint32_t)(0x00000000U)
AnnaBridge	172:65be27845400	861	#define LL_RCC_TIM_PRESCALER_FOUR_TIMES (uint32_t)(RCC_CFGR_TIMPRE)
AnnaBridge	172:65be27845400	862	/**
AnnaBridge	172:65be27845400	863	* @}
AnnaBridge	172:65be27845400	864	*/
AnnaBridge	172:65be27845400	865
AnnaBridge	172:65be27845400	866
AnnaBridge	172:65be27845400	867
AnnaBridge	172:65be27845400	868	/** @defgroup RCC_LL_EC_HRTIM_CLKSOURCE High Resolution Timers clock selection
AnnaBridge	172:65be27845400	869	* @{
AnnaBridge	172:65be27845400	870	*/
AnnaBridge	172:65be27845400	871	#define LL_RCC_HRTIM_CLKSOURCE_TIM (uint32_t)(0x00000000U) /* HRTIM Clock source is same as other timers */
AnnaBridge	172:65be27845400	872	#define LL_RCC_HRTIM_CLKSOURCE_CPU (uint32_t)(RCC_CFGR_HRTIMSEL) /* HRTIM Clock source is the CPU clock */
AnnaBridge	172:65be27845400	873	/**
AnnaBridge	172:65be27845400	874	* @}
AnnaBridge	172:65be27845400	875	*/
AnnaBridge	172:65be27845400	876
AnnaBridge	172:65be27845400	877	/** @defgroup RCC_LL_EC_PLLSOURCE All PLLs entry clock source
AnnaBridge	172:65be27845400	878	* @{
AnnaBridge	172:65be27845400	879	*/
AnnaBridge	172:65be27845400	880	#define LL_RCC_PLLSOURCE_HSI RCC_PLLCKSELR_PLLSRC_HSI
AnnaBridge	172:65be27845400	881	#define LL_RCC_PLLSOURCE_CSI RCC_PLLCKSELR_PLLSRC_CSI
AnnaBridge	172:65be27845400	882	#define LL_RCC_PLLSOURCE_HSE RCC_PLLCKSELR_PLLSRC_HSE
AnnaBridge	172:65be27845400	883	#define LL_RCC_PLLSOURCE_NONE RCC_PLLCKSELR_PLLSRC_NONE
AnnaBridge	172:65be27845400	884	/**
AnnaBridge	172:65be27845400	885	* @}
AnnaBridge	172:65be27845400	886	*/
AnnaBridge	172:65be27845400	887
AnnaBridge	172:65be27845400	888	/** @defgroup RCC_LL_EC_PLLINPUTRANGE All PLLs input range
AnnaBridge	172:65be27845400	889	* @{
AnnaBridge	172:65be27845400	890	*/
AnnaBridge	172:65be27845400	891	#define LL_RCC_PLLINPUTRANGE_1_2 (uint32_t)(0x00000000U)
AnnaBridge	172:65be27845400	892	#define LL_RCC_PLLINPUTRANGE_2_4 (uint32_t)(0x00000001)
AnnaBridge	172:65be27845400	893	#define LL_RCC_PLLINPUTRANGE_4_8 (uint32_t)(0x00000002)
AnnaBridge	172:65be27845400	894	#define LL_RCC_PLLINPUTRANGE_8_16 (uint32_t)(0x00000003)
AnnaBridge	172:65be27845400	895	/**
AnnaBridge	172:65be27845400	896	* @}
AnnaBridge	172:65be27845400	897	*/
AnnaBridge	172:65be27845400	898
AnnaBridge	172:65be27845400	899	/** @defgroup RCC_LL_EC_PLLVCORANGE All PLLs VCO range
AnnaBridge	172:65be27845400	900	* @{
AnnaBridge	172:65be27845400	901	*/
AnnaBridge	172:65be27845400	902	#define LL_RCC_PLLVCORANGE_WIDE (uint32_t)(0x00000000U) /* VCO output range: 192 to 836 MHz */
AnnaBridge	172:65be27845400	903	#define LL_RCC_PLLVCORANGE_MEDIUM (uint32_t)(0x00000001) /* VCO output range: 150 to 420 MHz */
AnnaBridge	172:65be27845400	904	/**
AnnaBridge	172:65be27845400	905	* @}
AnnaBridge	172:65be27845400	906	*/
AnnaBridge	172:65be27845400	907
AnnaBridge	172:65be27845400	908	/**
AnnaBridge	172:65be27845400	909	* @}
AnnaBridge	172:65be27845400	910	*/
AnnaBridge	172:65be27845400	911
AnnaBridge	172:65be27845400	912	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	913	/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
AnnaBridge	172:65be27845400	914	* @{
AnnaBridge	172:65be27845400	915	*/
AnnaBridge	172:65be27845400	916
AnnaBridge	172:65be27845400	917	/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge	172:65be27845400	918	* @{
AnnaBridge	172:65be27845400	919	*/
AnnaBridge	172:65be27845400	920
AnnaBridge	172:65be27845400	921	/**
AnnaBridge	172:65be27845400	922	* @brief Write a value in RCC register
AnnaBridge	172:65be27845400	923	* @param __REG__ Register to be written
AnnaBridge	172:65be27845400	924	* @param __VALUE__ Value to be written in the register
AnnaBridge	172:65be27845400	925	* @retval None
AnnaBridge	172:65be27845400	926	*/
AnnaBridge	172:65be27845400	927	#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
AnnaBridge	172:65be27845400	928
AnnaBridge	172:65be27845400	929	/**
AnnaBridge	172:65be27845400	930	* @brief Read a value in RCC register
AnnaBridge	172:65be27845400	931	* @param __REG__ Register to be read
AnnaBridge	172:65be27845400	932	* @retval Register value
AnnaBridge	172:65be27845400	933	*/
AnnaBridge	172:65be27845400	934	#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
AnnaBridge	172:65be27845400	935	/**
AnnaBridge	172:65be27845400	936	* @}
AnnaBridge	172:65be27845400	937	*/
AnnaBridge	172:65be27845400	938
AnnaBridge	172:65be27845400	939	/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
AnnaBridge	172:65be27845400	940	* @{
AnnaBridge	172:65be27845400	941	*/
AnnaBridge	172:65be27845400	942
AnnaBridge	172:65be27845400	943	/**
AnnaBridge	172:65be27845400	944	* @brief Helper macro to calculate the SYSCLK frequency
AnnaBridge	172:65be27845400	945	* @param __SYSINPUTCLKFREQ__ Frequency of the input of sys_ck (based on HSE/CSI/HSI/PLL1P)
AnnaBridge	172:65be27845400	946	* @param __SYSPRESCALER__ This parameter can be one of the following values:
AnnaBridge	172:65be27845400	947	* @arg @ref LL_RCC_SYSCLK_DIV_1
AnnaBridge	172:65be27845400	948	* @arg @ref LL_RCC_SYSCLK_DIV_2
AnnaBridge	172:65be27845400	949	* @arg @ref LL_RCC_SYSCLK_DIV_4
AnnaBridge	172:65be27845400	950	* @arg @ref LL_RCC_SYSCLK_DIV_8
AnnaBridge	172:65be27845400	951	* @arg @ref LL_RCC_SYSCLK_DIV_16
AnnaBridge	172:65be27845400	952	* @arg @ref LL_RCC_SYSCLK_DIV_64
AnnaBridge	172:65be27845400	953	* @arg @ref LL_RCC_SYSCLK_DIV_128
AnnaBridge	172:65be27845400	954	* @arg @ref LL_RCC_SYSCLK_DIV_256
AnnaBridge	172:65be27845400	955	* @arg @ref LL_RCC_SYSCLK_DIV_512
AnnaBridge	172:65be27845400	956	* @retval SYSCLK clock frequency (in Hz)
AnnaBridge	172:65be27845400	957	*/
AnnaBridge	172:65be27845400	958	#define LL_RCC_CALC_SYSCLK_FREQ(__SYSINPUTCLKFREQ__, __SYSPRESCALER__) ((__SYSINPUTCLKFREQ__) >> LL_RCC_PrescTable[((__SYSPRESCALER__) & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos])
AnnaBridge	172:65be27845400	959
AnnaBridge	172:65be27845400	960	/**
AnnaBridge	172:65be27845400	961	* @brief Helper macro to calculate the HCLK frequency
AnnaBridge	172:65be27845400	962	* @param __SYSCLKFREQ__ SYSCLK frequency.
AnnaBridge	172:65be27845400	963	* @param __HPRESCALER__ This parameter can be one of the following values:
AnnaBridge	172:65be27845400	964	* @arg @ref LL_RCC_AHB_DIV_1
AnnaBridge	172:65be27845400	965	* @arg @ref LL_RCC_AHB_DIV_2
AnnaBridge	172:65be27845400	966	* @arg @ref LL_RCC_AHB_DIV_4
AnnaBridge	172:65be27845400	967	* @arg @ref LL_RCC_AHB_DIV_8
AnnaBridge	172:65be27845400	968	* @arg @ref LL_RCC_AHB_DIV_16
AnnaBridge	172:65be27845400	969	* @arg @ref LL_RCC_AHB_DIV_64
AnnaBridge	172:65be27845400	970	* @arg @ref LL_RCC_AHB_DIV_128
AnnaBridge	172:65be27845400	971	* @arg @ref LL_RCC_AHB_DIV_256
AnnaBridge	172:65be27845400	972	* @arg @ref LL_RCC_AHB_DIV_512
AnnaBridge	172:65be27845400	973	* @retval HCLK clock frequency (in Hz)
AnnaBridge	172:65be27845400	974	*/
AnnaBridge	172:65be27845400	975	#define LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> LL_RCC_PrescTable[((__HPRESCALER__) & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos])
AnnaBridge	172:65be27845400	976
AnnaBridge	172:65be27845400	977	/**
AnnaBridge	172:65be27845400	978	* @brief Helper macro to calculate the PCLK1 frequency (ABP1)
AnnaBridge	172:65be27845400	979	* @param __HCLKFREQ__ HCLK frequency
AnnaBridge	172:65be27845400	980	* @param __APB1PRESCALER__ This parameter can be one of the following values:
AnnaBridge	172:65be27845400	981	* @arg @ref LL_RCC_APB1_DIV_1
AnnaBridge	172:65be27845400	982	* @arg @ref LL_RCC_APB1_DIV_2
AnnaBridge	172:65be27845400	983	* @arg @ref LL_RCC_APB1_DIV_4
AnnaBridge	172:65be27845400	984	* @arg @ref LL_RCC_APB1_DIV_8
AnnaBridge	172:65be27845400	985	* @arg @ref LL_RCC_APB1_DIV_16
AnnaBridge	172:65be27845400	986	* @retval PCLK1 clock frequency (in Hz)
AnnaBridge	172:65be27845400	987	*/
AnnaBridge	172:65be27845400	988	#define LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB1PRESCALER__) & RCC_D2CFGR_D2PPRE1) >> RCC_D2CFGR_D2PPRE1_Pos])
AnnaBridge	172:65be27845400	989
AnnaBridge	172:65be27845400	990	/**
AnnaBridge	172:65be27845400	991	* @brief Helper macro to calculate the PCLK2 frequency (ABP2)
AnnaBridge	172:65be27845400	992	* @param __HCLKFREQ__ HCLK frequency
AnnaBridge	172:65be27845400	993	* @param __APB2PRESCALER__ This parameter can be one of the following values:
AnnaBridge	172:65be27845400	994	* @arg @ref LL_RCC_APB2_DIV_1
AnnaBridge	172:65be27845400	995	* @arg @ref LL_RCC_APB2_DIV_2
AnnaBridge	172:65be27845400	996	* @arg @ref LL_RCC_APB2_DIV_4
AnnaBridge	172:65be27845400	997	* @arg @ref LL_RCC_APB2_DIV_8
AnnaBridge	172:65be27845400	998	* @arg @ref LL_RCC_APB2_DIV_16
AnnaBridge	172:65be27845400	999	* @retval PCLK2 clock frequency (in Hz)
AnnaBridge	172:65be27845400	1000	*/
AnnaBridge	172:65be27845400	1001	#define LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB2PRESCALER__) & RCC_D2CFGR_D2PPRE2) >> RCC_D2CFGR_D2PPRE2_Pos])
AnnaBridge	172:65be27845400	1002
AnnaBridge	172:65be27845400	1003	/**
AnnaBridge	172:65be27845400	1004	* @brief Helper macro to calculate the PCLK3 frequency (ABP3)
AnnaBridge	172:65be27845400	1005	* @param __HCLKFREQ__ HCLK frequency
AnnaBridge	172:65be27845400	1006	* @param __APB3PRESCALER__ This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1007	* @arg @ref LL_RCC_APB3_DIV_1
AnnaBridge	172:65be27845400	1008	* @arg @ref LL_RCC_APB3_DIV_2
AnnaBridge	172:65be27845400	1009	* @arg @ref LL_RCC_APB3_DIV_4
AnnaBridge	172:65be27845400	1010	* @arg @ref LL_RCC_APB3_DIV_8
AnnaBridge	172:65be27845400	1011	* @arg @ref LL_RCC_APB3_DIV_16
AnnaBridge	172:65be27845400	1012	* @retval PCLK1 clock frequency (in Hz)
AnnaBridge	172:65be27845400	1013	*/
AnnaBridge	172:65be27845400	1014	#define LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB3PRESCALER__) & RCC_D1CFGR_D1PPRE) >> RCC_D1CFGR_D1PPRE_Pos])
AnnaBridge	172:65be27845400	1015
AnnaBridge	172:65be27845400	1016	/**
AnnaBridge	172:65be27845400	1017	* @brief Helper macro to calculate the PCLK4 frequency (ABP4)
AnnaBridge	172:65be27845400	1018	* @param __HCLKFREQ__ HCLK frequency
AnnaBridge	172:65be27845400	1019	* @param __APB4PRESCALER__ This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1020	* @arg @ref LL_RCC_APB4_DIV_1
AnnaBridge	172:65be27845400	1021	* @arg @ref LL_RCC_APB4_DIV_2
AnnaBridge	172:65be27845400	1022	* @arg @ref LL_RCC_APB4_DIV_4
AnnaBridge	172:65be27845400	1023	* @arg @ref LL_RCC_APB4_DIV_8
AnnaBridge	172:65be27845400	1024	* @arg @ref LL_RCC_APB4_DIV_16
AnnaBridge	172:65be27845400	1025	* @retval PCLK1 clock frequency (in Hz)
AnnaBridge	172:65be27845400	1026	*/
AnnaBridge	172:65be27845400	1027	#define LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB4PRESCALER__) & RCC_D3CFGR_D3PPRE) >> RCC_D3CFGR_D3PPRE_Pos])
AnnaBridge	172:65be27845400	1028
AnnaBridge	172:65be27845400	1029	/**
AnnaBridge	172:65be27845400	1030	* @}
AnnaBridge	172:65be27845400	1031	*/
AnnaBridge	172:65be27845400	1032
AnnaBridge	172:65be27845400	1033	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	172:65be27845400	1034	/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
AnnaBridge	172:65be27845400	1035	* @{
AnnaBridge	172:65be27845400	1036	*/
AnnaBridge	172:65be27845400	1037	#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /!< No clock enabled for the peripheral /
AnnaBridge	172:65be27845400	1038	#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /!< Frequency cannot be provided as external clock /
AnnaBridge	172:65be27845400	1039	/**
AnnaBridge	172:65be27845400	1040	* @}
AnnaBridge	172:65be27845400	1041	*/
AnnaBridge	172:65be27845400	1042	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	172:65be27845400	1043
AnnaBridge	172:65be27845400	1044	/**
AnnaBridge	172:65be27845400	1045	* @}
AnnaBridge	172:65be27845400	1046	*/
AnnaBridge	172:65be27845400	1047
AnnaBridge	172:65be27845400	1048	/* Exported functions --------------------------------------------------------*/
AnnaBridge	172:65be27845400	1049	/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
AnnaBridge	172:65be27845400	1050	* @{
AnnaBridge	172:65be27845400	1051	*/
AnnaBridge	172:65be27845400	1052
AnnaBridge	172:65be27845400	1053	/** @defgroup RCC_LL_EF_HSE HSE
AnnaBridge	172:65be27845400	1054	* @{
AnnaBridge	172:65be27845400	1055	*/
AnnaBridge	172:65be27845400	1056
AnnaBridge	172:65be27845400	1057	/**
AnnaBridge	172:65be27845400	1058	* @brief Enable the Clock Security System.
AnnaBridge	172:65be27845400	1059	* @note Once HSE Clock Security System is enabled it cannot be changed anymore unless
AnnaBridge	172:65be27845400	1060	* a reset occurs or system enter in standby mode.
AnnaBridge	172:65be27845400	1061	* @rmtoll CR CSSHSEON LL_RCC_HSE_EnableCSS
AnnaBridge	172:65be27845400	1062	* @retval None
AnnaBridge	172:65be27845400	1063	*/
AnnaBridge	172:65be27845400	1064	__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
AnnaBridge	172:65be27845400	1065	{
AnnaBridge	172:65be27845400	1066	SET_BIT(RCC->CR, RCC_CR_CSSHSEON);
AnnaBridge	172:65be27845400	1067	}
AnnaBridge	172:65be27845400	1068
AnnaBridge	172:65be27845400	1069	/**
AnnaBridge	172:65be27845400	1070	* @brief Enable HSE external oscillator (HSE Bypass)
AnnaBridge	172:65be27845400	1071	* @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
AnnaBridge	172:65be27845400	1072	* @retval None
AnnaBridge	172:65be27845400	1073	*/
AnnaBridge	172:65be27845400	1074	__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
AnnaBridge	172:65be27845400	1075	{
AnnaBridge	172:65be27845400	1076	SET_BIT(RCC->CR, RCC_CR_HSEBYP);
AnnaBridge	172:65be27845400	1077	}
AnnaBridge	172:65be27845400	1078
AnnaBridge	172:65be27845400	1079	/**
AnnaBridge	172:65be27845400	1080	* @brief Disable HSE external oscillator (HSE Bypass)
AnnaBridge	172:65be27845400	1081	* @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
AnnaBridge	172:65be27845400	1082	* @retval None
AnnaBridge	172:65be27845400	1083	*/
AnnaBridge	172:65be27845400	1084	__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
AnnaBridge	172:65be27845400	1085	{
AnnaBridge	172:65be27845400	1086	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
AnnaBridge	172:65be27845400	1087	}
AnnaBridge	172:65be27845400	1088
AnnaBridge	172:65be27845400	1089	/**
AnnaBridge	172:65be27845400	1090	* @brief Enable HSE crystal oscillator (HSE ON)
AnnaBridge	172:65be27845400	1091	* @rmtoll CR HSEON LL_RCC_HSE_Enable
AnnaBridge	172:65be27845400	1092	* @retval None
AnnaBridge	172:65be27845400	1093	*/
AnnaBridge	172:65be27845400	1094	__STATIC_INLINE void LL_RCC_HSE_Enable(void)
AnnaBridge	172:65be27845400	1095	{
AnnaBridge	172:65be27845400	1096	SET_BIT(RCC->CR, RCC_CR_HSEON);
AnnaBridge	172:65be27845400	1097	}
AnnaBridge	172:65be27845400	1098
AnnaBridge	172:65be27845400	1099	/**
AnnaBridge	172:65be27845400	1100	* @brief Disable HSE crystal oscillator (HSE ON)
AnnaBridge	172:65be27845400	1101	* @rmtoll CR HSEON LL_RCC_HSE_Disable
AnnaBridge	172:65be27845400	1102	* @retval None
AnnaBridge	172:65be27845400	1103	*/
AnnaBridge	172:65be27845400	1104	__STATIC_INLINE void LL_RCC_HSE_Disable(void)
AnnaBridge	172:65be27845400	1105	{
AnnaBridge	172:65be27845400	1106	CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
AnnaBridge	172:65be27845400	1107	}
AnnaBridge	172:65be27845400	1108
AnnaBridge	172:65be27845400	1109	/**
AnnaBridge	172:65be27845400	1110	* @brief Check if HSE oscillator Ready
AnnaBridge	172:65be27845400	1111	* @rmtoll CR HSERDY LL_RCC_HSE_IsReady
AnnaBridge	172:65be27845400	1112	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1113	*/
AnnaBridge	172:65be27845400	1114	__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
AnnaBridge	172:65be27845400	1115	{
AnnaBridge	172:65be27845400	1116	return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY))?1UL:0UL);
AnnaBridge	172:65be27845400	1117	}
AnnaBridge	172:65be27845400	1118
AnnaBridge	172:65be27845400	1119	/**
AnnaBridge	172:65be27845400	1120	* @}
AnnaBridge	172:65be27845400	1121	*/
AnnaBridge	172:65be27845400	1122
AnnaBridge	172:65be27845400	1123	/** @defgroup RCC_LL_EF_HSI HSI
AnnaBridge	172:65be27845400	1124	* @{
AnnaBridge	172:65be27845400	1125	*/
AnnaBridge	172:65be27845400	1126
AnnaBridge	172:65be27845400	1127	/**
AnnaBridge	172:65be27845400	1128	* @brief Enable HSI oscillator
AnnaBridge	172:65be27845400	1129	* @rmtoll CR HSION LL_RCC_HSI_Enable
AnnaBridge	172:65be27845400	1130	* @retval None
AnnaBridge	172:65be27845400	1131	*/
AnnaBridge	172:65be27845400	1132	__STATIC_INLINE void LL_RCC_HSI_Enable(void)
AnnaBridge	172:65be27845400	1133	{
AnnaBridge	172:65be27845400	1134	SET_BIT(RCC->CR, RCC_CR_HSION);
AnnaBridge	172:65be27845400	1135	}
AnnaBridge	172:65be27845400	1136
AnnaBridge	172:65be27845400	1137	/**
AnnaBridge	172:65be27845400	1138	* @brief Disable HSI oscillator
AnnaBridge	172:65be27845400	1139	* @rmtoll CR HSION LL_RCC_HSI_Disable
AnnaBridge	172:65be27845400	1140	* @retval None
AnnaBridge	172:65be27845400	1141	*/
AnnaBridge	172:65be27845400	1142	__STATIC_INLINE void LL_RCC_HSI_Disable(void)
AnnaBridge	172:65be27845400	1143	{
AnnaBridge	172:65be27845400	1144	CLEAR_BIT(RCC->CR, RCC_CR_HSION);
AnnaBridge	172:65be27845400	1145	}
AnnaBridge	172:65be27845400	1146
AnnaBridge	172:65be27845400	1147	/**
AnnaBridge	172:65be27845400	1148	* @brief Check if HSI clock is ready
AnnaBridge	172:65be27845400	1149	* @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
AnnaBridge	172:65be27845400	1150	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1151	*/
AnnaBridge	172:65be27845400	1152	__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
AnnaBridge	172:65be27845400	1153	{
AnnaBridge	172:65be27845400	1154	return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY))?1UL:0UL);
AnnaBridge	172:65be27845400	1155	}
AnnaBridge	172:65be27845400	1156
AnnaBridge	172:65be27845400	1157	/**
AnnaBridge	172:65be27845400	1158	* @brief Check if HSI new divider applied and ready
AnnaBridge	172:65be27845400	1159	* @rmtoll CR HSIDIVF LL_RCC_HSI_IsDividerReady
AnnaBridge	172:65be27845400	1160	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1161	*/
AnnaBridge	172:65be27845400	1162	__STATIC_INLINE uint32_t LL_RCC_HSI_IsDividerReady(void)
AnnaBridge	172:65be27845400	1163	{
AnnaBridge	172:65be27845400	1164	return ((READ_BIT(RCC->CR, RCC_CR_HSIDIVF) == (RCC_CR_HSIDIVF))?1UL:0UL);
AnnaBridge	172:65be27845400	1165	}
AnnaBridge	172:65be27845400	1166
AnnaBridge	172:65be27845400	1167	/**
AnnaBridge	172:65be27845400	1168	* @brief Set HSI divider
AnnaBridge	172:65be27845400	1169	* @rmtoll CR HSIDIV LL_RCC_HSI_SetDivider
AnnaBridge	172:65be27845400	1170	* @param Divider This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1171	* @arg @ref LL_RCC_HSI_DIV1
AnnaBridge	172:65be27845400	1172	* @arg @ref LL_RCC_HSI_DIV2
AnnaBridge	172:65be27845400	1173	* @arg @ref LL_RCC_HSI_DIV4
AnnaBridge	172:65be27845400	1174	* @arg @ref LL_RCC_HSI_DIV8
AnnaBridge	172:65be27845400	1175	* @retval None.
AnnaBridge	172:65be27845400	1176	*/
AnnaBridge	172:65be27845400	1177	__STATIC_INLINE void LL_RCC_HSI_SetDivider(uint32_t Divider)
AnnaBridge	172:65be27845400	1178	{
AnnaBridge	172:65be27845400	1179	MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, Divider);
AnnaBridge	172:65be27845400	1180	}
AnnaBridge	172:65be27845400	1181
AnnaBridge	172:65be27845400	1182	/**
AnnaBridge	172:65be27845400	1183	* @brief Get HSI divider
AnnaBridge	172:65be27845400	1184	* @rmtoll CR HSIDIV LL_RCC_HSI_GetDivider
AnnaBridge	172:65be27845400	1185	* @retval can be one of the following values:
AnnaBridge	172:65be27845400	1186	* @arg @ref LL_RCC_HSI_DIV1
AnnaBridge	172:65be27845400	1187	* @arg @ref LL_RCC_HSI_DIV2
AnnaBridge	172:65be27845400	1188	* @arg @ref LL_RCC_HSI_DIV4
AnnaBridge	172:65be27845400	1189	* @arg @ref LL_RCC_HSI_DIV8
AnnaBridge	172:65be27845400	1190	*/
AnnaBridge	172:65be27845400	1191	__STATIC_INLINE uint32_t LL_RCC_HSI_GetDivider(void)
AnnaBridge	172:65be27845400	1192	{
AnnaBridge	172:65be27845400	1193	return (READ_BIT(RCC->CR, RCC_CR_HSIDIV));
AnnaBridge	172:65be27845400	1194	}
AnnaBridge	172:65be27845400	1195
AnnaBridge	172:65be27845400	1196	/**
AnnaBridge	172:65be27845400	1197	* @brief Enable HSI oscillator in Stop mode
AnnaBridge	172:65be27845400	1198	* @rmtoll CR HSIKERON LL_RCC_HSI_EnableStopMode
AnnaBridge	172:65be27845400	1199	* @retval None
AnnaBridge	172:65be27845400	1200	*/
AnnaBridge	172:65be27845400	1201	__STATIC_INLINE void LL_RCC_HSI_EnableStopMode(void)
AnnaBridge	172:65be27845400	1202	{
AnnaBridge	172:65be27845400	1203	SET_BIT(RCC->CR, RCC_CR_HSIKERON);
AnnaBridge	172:65be27845400	1204	}
AnnaBridge	172:65be27845400	1205
AnnaBridge	172:65be27845400	1206	/**
AnnaBridge	172:65be27845400	1207	* @brief Disable HSI oscillator in Stop mode
AnnaBridge	172:65be27845400	1208	* @rmtoll CR HSION LL_RCC_HSI_DisableStopMode
AnnaBridge	172:65be27845400	1209	* @retval None
AnnaBridge	172:65be27845400	1210	*/
AnnaBridge	172:65be27845400	1211	__STATIC_INLINE void LL_RCC_HSI_DisableStopMode(void)
AnnaBridge	172:65be27845400	1212	{
AnnaBridge	172:65be27845400	1213	CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
AnnaBridge	172:65be27845400	1214	}
AnnaBridge	172:65be27845400	1215
AnnaBridge	172:65be27845400	1216	/**
AnnaBridge	172:65be27845400	1217	* @brief Get HSI Calibration value
AnnaBridge	172:65be27845400	1218	* @note When HSITRIM is written, HSICAL is updated with the sum of
AnnaBridge	172:65be27845400	1219	* HSITRIM and the factory trim value
AnnaBridge	172:65be27845400	1220	* @rmtoll ICSCR HSICAL LL_RCC_HSI_GetCalibration
AnnaBridge	172:65be27845400	1221	* @retval A value between 0 and 4095 (0xFFF)
AnnaBridge	172:65be27845400	1222	*/
AnnaBridge	172:65be27845400	1223	__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
AnnaBridge	172:65be27845400	1224	{
AnnaBridge	172:65be27845400	1225	return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_ICSCR_HSICAL_Pos);
AnnaBridge	172:65be27845400	1226	}
AnnaBridge	172:65be27845400	1227
AnnaBridge	172:65be27845400	1228	/**
AnnaBridge	172:65be27845400	1229	* @brief Set HSI Calibration trimming
AnnaBridge	172:65be27845400	1230	* @note user-programmable trimming value that is added to the HSICAL
AnnaBridge	172:65be27845400	1231	* @note Default value is 64 (32 for Cut1.x), which, when added to the HSICAL value,
AnnaBridge	172:65be27845400	1232	* should trim the HSI to 64 MHz +/- 1 %
AnnaBridge	172:65be27845400	1233	* @rmtoll ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming
AnnaBridge	172:65be27845400	1234	* @param Value can be a value between 0 and 63
AnnaBridge	172:65be27845400	1235	* @retval None
AnnaBridge	172:65be27845400	1236	*/
AnnaBridge	172:65be27845400	1237	__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
AnnaBridge	172:65be27845400	1238	{
AnnaBridge	172:65be27845400	1239	MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos);
AnnaBridge	172:65be27845400	1240	}
AnnaBridge	172:65be27845400	1241
AnnaBridge	172:65be27845400	1242	/**
AnnaBridge	172:65be27845400	1243	* @brief Get HSI Calibration trimming
AnnaBridge	172:65be27845400	1244	* @rmtoll ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming
AnnaBridge	172:65be27845400	1245	* @retval A value between 0 and 63
AnnaBridge	172:65be27845400	1246	*/
AnnaBridge	172:65be27845400	1247	__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
AnnaBridge	172:65be27845400	1248	{
AnnaBridge	172:65be27845400	1249	return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);
AnnaBridge	172:65be27845400	1250	}
AnnaBridge	172:65be27845400	1251
AnnaBridge	172:65be27845400	1252	/**
AnnaBridge	172:65be27845400	1253	* @}
AnnaBridge	172:65be27845400	1254	*/
AnnaBridge	172:65be27845400	1255
AnnaBridge	172:65be27845400	1256	/** @defgroup RCC_LL_EF_CSI CSI
AnnaBridge	172:65be27845400	1257	* @{
AnnaBridge	172:65be27845400	1258	*/
AnnaBridge	172:65be27845400	1259
AnnaBridge	172:65be27845400	1260	/**
AnnaBridge	172:65be27845400	1261	* @brief Enable CSI oscillator
AnnaBridge	172:65be27845400	1262	* @rmtoll CR CSION LL_RCC_CSI_Enable
AnnaBridge	172:65be27845400	1263	* @retval None
AnnaBridge	172:65be27845400	1264	*/
AnnaBridge	172:65be27845400	1265	__STATIC_INLINE void LL_RCC_CSI_Enable(void)
AnnaBridge	172:65be27845400	1266	{
AnnaBridge	172:65be27845400	1267	SET_BIT(RCC->CR, RCC_CR_CSION);
AnnaBridge	172:65be27845400	1268	}
AnnaBridge	172:65be27845400	1269
AnnaBridge	172:65be27845400	1270	/**
AnnaBridge	172:65be27845400	1271	* @brief Disable CSI oscillator
AnnaBridge	172:65be27845400	1272	* @rmtoll CR CSION LL_RCC_CSI_Disable
AnnaBridge	172:65be27845400	1273	* @retval None
AnnaBridge	172:65be27845400	1274	*/
AnnaBridge	172:65be27845400	1275	__STATIC_INLINE void LL_RCC_CSI_Disable(void)
AnnaBridge	172:65be27845400	1276	{
AnnaBridge	172:65be27845400	1277	CLEAR_BIT(RCC->CR, RCC_CR_CSION);
AnnaBridge	172:65be27845400	1278	}
AnnaBridge	172:65be27845400	1279
AnnaBridge	172:65be27845400	1280	/**
AnnaBridge	172:65be27845400	1281	* @brief Check if CSI clock is ready
AnnaBridge	172:65be27845400	1282	* @rmtoll CR CSIRDY LL_RCC_CSI_IsReady
AnnaBridge	172:65be27845400	1283	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1284	*/
AnnaBridge	172:65be27845400	1285	__STATIC_INLINE uint32_t LL_RCC_CSI_IsReady(void)
AnnaBridge	172:65be27845400	1286	{
AnnaBridge	172:65be27845400	1287	return ((READ_BIT(RCC->CR, RCC_CR_CSIRDY) == (RCC_CR_CSIRDY))?1UL:0UL);
AnnaBridge	172:65be27845400	1288	}
AnnaBridge	172:65be27845400	1289
AnnaBridge	172:65be27845400	1290	/**
AnnaBridge	172:65be27845400	1291	* @brief Enable CSI oscillator in Stop mode
AnnaBridge	172:65be27845400	1292	* @rmtoll CR CSIKERON LL_RCC_CSI_EnableStopMode
AnnaBridge	172:65be27845400	1293	* @retval None
AnnaBridge	172:65be27845400	1294	*/
AnnaBridge	172:65be27845400	1295	__STATIC_INLINE void LL_RCC_CSI_EnableStopMode(void)
AnnaBridge	172:65be27845400	1296	{
AnnaBridge	172:65be27845400	1297	SET_BIT(RCC->CR, RCC_CR_CSIKERON);
AnnaBridge	172:65be27845400	1298	}
AnnaBridge	172:65be27845400	1299
AnnaBridge	172:65be27845400	1300	/**
AnnaBridge	172:65be27845400	1301	* @brief Disable CSI oscillator in Stop mode
AnnaBridge	172:65be27845400	1302	* @rmtoll CR CSIKERON LL_RCC_CSI_DisableStopMode
AnnaBridge	172:65be27845400	1303	* @retval None
AnnaBridge	172:65be27845400	1304	*/
AnnaBridge	172:65be27845400	1305	__STATIC_INLINE void LL_RCC_CSI_DisableStopMode(void)
AnnaBridge	172:65be27845400	1306	{
AnnaBridge	172:65be27845400	1307	CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON);
AnnaBridge	172:65be27845400	1308	}
AnnaBridge	172:65be27845400	1309
AnnaBridge	172:65be27845400	1310	/**
AnnaBridge	172:65be27845400	1311	* @brief Get CSI Calibration value
AnnaBridge	172:65be27845400	1312	* @note When CSITRIM is written, CSICAL is updated with the sum of
AnnaBridge	172:65be27845400	1313	* CSITRIM and the factory trim value
AnnaBridge	172:65be27845400	1314	* @rmtoll ICSCR CSICAL LL_RCC_CSI_GetCalibration
AnnaBridge	172:65be27845400	1315	* @retval A value between 0 and 255 (0xFF)
AnnaBridge	172:65be27845400	1316	*/
AnnaBridge	172:65be27845400	1317	__STATIC_INLINE uint32_t LL_RCC_CSI_GetCalibration(void)
AnnaBridge	172:65be27845400	1318	{
AnnaBridge	172:65be27845400	1319	return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_CSICAL) >> RCC_ICSCR_CSICAL_Pos);
AnnaBridge	172:65be27845400	1320	}
AnnaBridge	172:65be27845400	1321
AnnaBridge	172:65be27845400	1322	/**
AnnaBridge	172:65be27845400	1323	* @brief Set CSI Calibration trimming
AnnaBridge	172:65be27845400	1324	* @note user-programmable trimming value that is added to the CSICAL
AnnaBridge	172:65be27845400	1325	* @note Default value is 16, which, when added to the CSICAL value,
AnnaBridge	172:65be27845400	1326	* should trim the CSI to 4 MHz +/- 1 %
AnnaBridge	172:65be27845400	1327	* @rmtoll ICSCR CSITRIM LL_RCC_CSI_SetCalibTrimming
AnnaBridge	172:65be27845400	1328	* @param Value can be a value between 0 and 31
AnnaBridge	172:65be27845400	1329	* @retval None
AnnaBridge	172:65be27845400	1330	*/
AnnaBridge	172:65be27845400	1331	__STATIC_INLINE void LL_RCC_CSI_SetCalibTrimming(uint32_t Value)
AnnaBridge	172:65be27845400	1332	{
AnnaBridge	172:65be27845400	1333	MODIFY_REG(RCC->ICSCR, RCC_ICSCR_CSITRIM, Value << RCC_ICSCR_CSITRIM_Pos);
AnnaBridge	172:65be27845400	1334	}
AnnaBridge	172:65be27845400	1335
AnnaBridge	172:65be27845400	1336	/**
AnnaBridge	172:65be27845400	1337	* @brief Get CSI Calibration trimming
AnnaBridge	172:65be27845400	1338	* @rmtoll ICSCR CSITRIM LL_RCC_CSI_GetCalibTrimming
AnnaBridge	172:65be27845400	1339	* @retval A value between 0 and 31
AnnaBridge	172:65be27845400	1340	*/
AnnaBridge	172:65be27845400	1341	__STATIC_INLINE uint32_t LL_RCC_CSI_GetCalibTrimming(void)
AnnaBridge	172:65be27845400	1342	{
AnnaBridge	172:65be27845400	1343	return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_CSITRIM) >> RCC_ICSCR_CSITRIM_Pos);
AnnaBridge	172:65be27845400	1344	}
AnnaBridge	172:65be27845400	1345
AnnaBridge	172:65be27845400	1346	/**
AnnaBridge	172:65be27845400	1347	* @}
AnnaBridge	172:65be27845400	1348	*/
AnnaBridge	172:65be27845400	1349
AnnaBridge	172:65be27845400	1350	/** @defgroup RCC_LL_EF_HSI48 HSI48
AnnaBridge	172:65be27845400	1351	* @{
AnnaBridge	172:65be27845400	1352	*/
AnnaBridge	172:65be27845400	1353
AnnaBridge	172:65be27845400	1354	/**
AnnaBridge	172:65be27845400	1355	* @brief Enable HSI48 oscillator
AnnaBridge	172:65be27845400	1356	* @rmtoll CR HSI48ON LL_RCC_HSI48_Enable
AnnaBridge	172:65be27845400	1357	* @retval None
AnnaBridge	172:65be27845400	1358	*/
AnnaBridge	172:65be27845400	1359	__STATIC_INLINE void LL_RCC_HSI48_Enable(void)
AnnaBridge	172:65be27845400	1360	{
AnnaBridge	172:65be27845400	1361	SET_BIT(RCC->CR, RCC_CR_HSI48ON);
AnnaBridge	172:65be27845400	1362	}
AnnaBridge	172:65be27845400	1363
AnnaBridge	172:65be27845400	1364	/**
AnnaBridge	172:65be27845400	1365	* @brief Disable HSI48 oscillator
AnnaBridge	172:65be27845400	1366	* @rmtoll CR HSI48ON LL_RCC_HSI48_Disable
AnnaBridge	172:65be27845400	1367	* @retval None
AnnaBridge	172:65be27845400	1368	*/
AnnaBridge	172:65be27845400	1369	__STATIC_INLINE void LL_RCC_HSI48_Disable(void)
AnnaBridge	172:65be27845400	1370	{
AnnaBridge	172:65be27845400	1371	CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON);
AnnaBridge	172:65be27845400	1372	}
AnnaBridge	172:65be27845400	1373
AnnaBridge	172:65be27845400	1374	/**
AnnaBridge	172:65be27845400	1375	* @brief Check if HSI48 clock is ready
AnnaBridge	172:65be27845400	1376	* @rmtoll CR HSI48RDY LL_RCC_HSI48_IsReady
AnnaBridge	172:65be27845400	1377	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1378	*/
AnnaBridge	172:65be27845400	1379	__STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
AnnaBridge	172:65be27845400	1380	{
AnnaBridge	172:65be27845400	1381	return ((READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == (RCC_CR_HSI48RDY))?1UL:0UL);
AnnaBridge	172:65be27845400	1382	}
AnnaBridge	172:65be27845400	1383
AnnaBridge	172:65be27845400	1384	/**
AnnaBridge	172:65be27845400	1385	* @brief Get HSI48 Calibration value
AnnaBridge	172:65be27845400	1386	* @note When HSI48TRIM is written, HSI48CAL is updated with the sum of
AnnaBridge	172:65be27845400	1387	* HSI48TRIM and the factory trim value
AnnaBridge	172:65be27845400	1388	* @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration
AnnaBridge	172:65be27845400	1389	* @retval A value between 0 and 1023 (0x3FF)
AnnaBridge	172:65be27845400	1390	*/
AnnaBridge	172:65be27845400	1391	__STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
AnnaBridge	172:65be27845400	1392	{
AnnaBridge	172:65be27845400	1393	return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos);
AnnaBridge	172:65be27845400	1394	}
AnnaBridge	172:65be27845400	1395
AnnaBridge	172:65be27845400	1396	/**
AnnaBridge	172:65be27845400	1397	* @}
AnnaBridge	172:65be27845400	1398	*/
AnnaBridge	172:65be27845400	1399
AnnaBridge	172:65be27845400	1400	/** @defgroup RCC_LL_EF_D1CLK D1CKREADY
AnnaBridge	172:65be27845400	1401	* @{
AnnaBridge	172:65be27845400	1402	*/
AnnaBridge	172:65be27845400	1403
AnnaBridge	172:65be27845400	1404	/**
AnnaBridge	172:65be27845400	1405	* @brief Check if D1 clock is ready
AnnaBridge	172:65be27845400	1406	* @rmtoll CR D1CKRDY LL_RCC_D1CK_IsReady
AnnaBridge	172:65be27845400	1407	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1408	*/
AnnaBridge	172:65be27845400	1409	__STATIC_INLINE uint32_t LL_RCC_D1CK_IsReady(void)
AnnaBridge	172:65be27845400	1410	{
AnnaBridge	172:65be27845400	1411	return ((READ_BIT(RCC->CR, RCC_CR_D1CKRDY) == (RCC_CR_D1CKRDY))?1UL:0UL);
AnnaBridge	172:65be27845400	1412	}
AnnaBridge	172:65be27845400	1413
AnnaBridge	172:65be27845400	1414	/**
AnnaBridge	172:65be27845400	1415	* @}
AnnaBridge	172:65be27845400	1416	*/
AnnaBridge	172:65be27845400	1417
AnnaBridge	172:65be27845400	1418	/** @defgroup RCC_LL_EF_D2CLK D2CKREADY
AnnaBridge	172:65be27845400	1419	* @{
AnnaBridge	172:65be27845400	1420	*/
AnnaBridge	172:65be27845400	1421
AnnaBridge	172:65be27845400	1422	/**
AnnaBridge	172:65be27845400	1423	* @brief Check if D2 clock is ready
AnnaBridge	172:65be27845400	1424	* @rmtoll CR D2CKRDY LL_RCC_D2CK_IsReady
AnnaBridge	172:65be27845400	1425	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1426	*/
AnnaBridge	172:65be27845400	1427	__STATIC_INLINE uint32_t LL_RCC_D2CK_IsReady(void)
AnnaBridge	172:65be27845400	1428	{
AnnaBridge	172:65be27845400	1429	return ((READ_BIT(RCC->CR, RCC_CR_D2CKRDY) == (RCC_CR_D2CKRDY))?1UL:0UL);
AnnaBridge	172:65be27845400	1430	}
AnnaBridge	172:65be27845400	1431
AnnaBridge	172:65be27845400	1432	/**
AnnaBridge	172:65be27845400	1433	* @}
AnnaBridge	172:65be27845400	1434	*/
AnnaBridge	172:65be27845400	1435
AnnaBridge	172:65be27845400	1436	/** @defgroup RCC_LL_EF_SYSTEM_WIDE_RESET RESET
AnnaBridge	172:65be27845400	1437	* @{
AnnaBridge	172:65be27845400	1438	*/
AnnaBridge	172:65be27845400	1439
AnnaBridge	172:65be27845400	1440	/**
AnnaBridge	172:65be27845400	1441	* @brief Enable system wide reset for Window Watch Dog 1
AnnaBridge	172:65be27845400	1442	* @rmtoll GCR WW1RSC LL_RCC_WWDG1_EnableSystemReset
AnnaBridge	172:65be27845400	1443	* @retval None.
AnnaBridge	172:65be27845400	1444	*/
AnnaBridge	172:65be27845400	1445	__STATIC_INLINE void LL_RCC_WWDG1_EnableSystemReset(void)
AnnaBridge	172:65be27845400	1446	{
AnnaBridge	172:65be27845400	1447	SET_BIT(RCC->GCR, RCC_GCR_WW1RSC);
AnnaBridge	172:65be27845400	1448	}
AnnaBridge	172:65be27845400	1449
AnnaBridge	172:65be27845400	1450	/**
AnnaBridge	172:65be27845400	1451	* @brief Check if Window Watch Dog 1 reset is system wide
AnnaBridge	172:65be27845400	1452	* @rmtoll GCR WW1RSC LL_RCC_WWDG1_IsSystemReset
AnnaBridge	172:65be27845400	1453	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1454	*/
AnnaBridge	172:65be27845400	1455	__STATIC_INLINE uint32_t LL_RCC_WWDG1_IsSystemReset(void)
AnnaBridge	172:65be27845400	1456	{
AnnaBridge	172:65be27845400	1457	return ((READ_BIT(RCC->GCR, RCC_GCR_WW1RSC) == RCC_GCR_WW1RSC)?1UL:0UL);
AnnaBridge	172:65be27845400	1458	}
AnnaBridge	172:65be27845400	1459
AnnaBridge	172:65be27845400	1460	/**
AnnaBridge	172:65be27845400	1461	* @}
AnnaBridge	172:65be27845400	1462	*/
AnnaBridge	172:65be27845400	1463
AnnaBridge	172:65be27845400	1464
AnnaBridge	172:65be27845400	1465	/** @defgroup RCC_LL_EF_LSE LSE
AnnaBridge	172:65be27845400	1466	* @{
AnnaBridge	172:65be27845400	1467	*/
AnnaBridge	172:65be27845400	1468
AnnaBridge	172:65be27845400	1469	/**
AnnaBridge	172:65be27845400	1470	* @brief Enable the Clock Security System on LSE.
AnnaBridge	172:65be27845400	1471	* @note Once LSE Clock Security System is enabled it cannot be changed anymore unless
AnnaBridge	172:65be27845400	1472	* a clock failure is detected.
AnnaBridge	172:65be27845400	1473	* @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS
AnnaBridge	172:65be27845400	1474	* @retval None
AnnaBridge	172:65be27845400	1475	*/
AnnaBridge	172:65be27845400	1476	__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
AnnaBridge	172:65be27845400	1477	{
AnnaBridge	172:65be27845400	1478	SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
AnnaBridge	172:65be27845400	1479	}
AnnaBridge	172:65be27845400	1480
AnnaBridge	172:65be27845400	1481	/**
AnnaBridge	172:65be27845400	1482	* @brief Check if LSE failure is detected by Clock Security System
AnnaBridge	172:65be27845400	1483	* @rmtoll BDCR LSECSSD LL_RCC_LSE_IsFailureDetected
AnnaBridge	172:65be27845400	1484	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1485	*/
AnnaBridge	172:65be27845400	1486	__STATIC_INLINE uint32_t LL_RCC_LSE_IsFailureDetected(void)
AnnaBridge	172:65be27845400	1487	{
AnnaBridge	172:65be27845400	1488	return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD))?1UL:0UL);
AnnaBridge	172:65be27845400	1489	}
AnnaBridge	172:65be27845400	1490
AnnaBridge	172:65be27845400	1491	/**
AnnaBridge	172:65be27845400	1492	* @brief Enable Low Speed External (LSE) crystal.
AnnaBridge	172:65be27845400	1493	* @rmtoll BDCR LSEON LL_RCC_LSE_Enable
AnnaBridge	172:65be27845400	1494	* @retval None
AnnaBridge	172:65be27845400	1495	*/
AnnaBridge	172:65be27845400	1496	__STATIC_INLINE void LL_RCC_LSE_Enable(void)
AnnaBridge	172:65be27845400	1497	{
AnnaBridge	172:65be27845400	1498	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
AnnaBridge	172:65be27845400	1499	}
AnnaBridge	172:65be27845400	1500
AnnaBridge	172:65be27845400	1501	/**
AnnaBridge	172:65be27845400	1502	* @brief Disable Low Speed External (LSE) crystal.
AnnaBridge	172:65be27845400	1503	* @rmtoll BDCR LSEON LL_RCC_LSE_Disable
AnnaBridge	172:65be27845400	1504	* @retval None
AnnaBridge	172:65be27845400	1505	*/
AnnaBridge	172:65be27845400	1506	__STATIC_INLINE void LL_RCC_LSE_Disable(void)
AnnaBridge	172:65be27845400	1507	{
AnnaBridge	172:65be27845400	1508	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
AnnaBridge	172:65be27845400	1509	}
AnnaBridge	172:65be27845400	1510
AnnaBridge	172:65be27845400	1511	/**
AnnaBridge	172:65be27845400	1512	* @brief Enable external clock source (LSE bypass).
AnnaBridge	172:65be27845400	1513	* @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
AnnaBridge	172:65be27845400	1514	* @retval None
AnnaBridge	172:65be27845400	1515	*/
AnnaBridge	172:65be27845400	1516	__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
AnnaBridge	172:65be27845400	1517	{
AnnaBridge	172:65be27845400	1518	SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
AnnaBridge	172:65be27845400	1519	}
AnnaBridge	172:65be27845400	1520
AnnaBridge	172:65be27845400	1521	/**
AnnaBridge	172:65be27845400	1522	* @brief Disable external clock source (LSE bypass).
AnnaBridge	172:65be27845400	1523	* @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
AnnaBridge	172:65be27845400	1524	* @retval None
AnnaBridge	172:65be27845400	1525	*/
AnnaBridge	172:65be27845400	1526	__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
AnnaBridge	172:65be27845400	1527	{
AnnaBridge	172:65be27845400	1528	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
AnnaBridge	172:65be27845400	1529	}
AnnaBridge	172:65be27845400	1530
AnnaBridge	172:65be27845400	1531	/**
AnnaBridge	172:65be27845400	1532	* @brief Set LSE oscillator drive capability
AnnaBridge	172:65be27845400	1533	* @note The oscillator is in Xtal mode when it is not in bypass mode.
AnnaBridge	172:65be27845400	1534	* @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
AnnaBridge	172:65be27845400	1535	* @param LSEDrive This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1536	* @arg @ref LL_RCC_LSEDRIVE_LOW
AnnaBridge	172:65be27845400	1537	* @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
AnnaBridge	172:65be27845400	1538	* @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
AnnaBridge	172:65be27845400	1539	* @arg @ref LL_RCC_LSEDRIVE_HIGH
AnnaBridge	172:65be27845400	1540	* @retval None
AnnaBridge	172:65be27845400	1541	*/
AnnaBridge	172:65be27845400	1542	__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
AnnaBridge	172:65be27845400	1543	{
AnnaBridge	172:65be27845400	1544	MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
AnnaBridge	172:65be27845400	1545	}
AnnaBridge	172:65be27845400	1546
AnnaBridge	172:65be27845400	1547	/**
AnnaBridge	172:65be27845400	1548	* @brief Get LSE oscillator drive capability
AnnaBridge	172:65be27845400	1549	* @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
AnnaBridge	172:65be27845400	1550	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1551	* @arg @ref LL_RCC_LSEDRIVE_LOW
AnnaBridge	172:65be27845400	1552	* @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
AnnaBridge	172:65be27845400	1553	* @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
AnnaBridge	172:65be27845400	1554	* @arg @ref LL_RCC_LSEDRIVE_HIGH
AnnaBridge	172:65be27845400	1555	*/
AnnaBridge	172:65be27845400	1556	__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
AnnaBridge	172:65be27845400	1557	{
AnnaBridge	172:65be27845400	1558	return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
AnnaBridge	172:65be27845400	1559	}
AnnaBridge	172:65be27845400	1560
AnnaBridge	172:65be27845400	1561	/**
AnnaBridge	172:65be27845400	1562	* @brief Check if LSE oscillator Ready
AnnaBridge	172:65be27845400	1563	* @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
AnnaBridge	172:65be27845400	1564	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1565	*/
AnnaBridge	172:65be27845400	1566	__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
AnnaBridge	172:65be27845400	1567	{
AnnaBridge	172:65be27845400	1568	return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY))?1UL:0UL);
AnnaBridge	172:65be27845400	1569	}
AnnaBridge	172:65be27845400	1570
AnnaBridge	172:65be27845400	1571	/**
AnnaBridge	172:65be27845400	1572	* @}
AnnaBridge	172:65be27845400	1573	*/
AnnaBridge	172:65be27845400	1574
AnnaBridge	172:65be27845400	1575	/** @defgroup RCC_LL_EF_LSI LSI
AnnaBridge	172:65be27845400	1576	* @{
AnnaBridge	172:65be27845400	1577	*/
AnnaBridge	172:65be27845400	1578
AnnaBridge	172:65be27845400	1579	/**
AnnaBridge	172:65be27845400	1580	* @brief Enable LSI Oscillator
AnnaBridge	172:65be27845400	1581	* @rmtoll CSR LSION LL_RCC_LSI_Enable
AnnaBridge	172:65be27845400	1582	* @retval None
AnnaBridge	172:65be27845400	1583	*/
AnnaBridge	172:65be27845400	1584	__STATIC_INLINE void LL_RCC_LSI_Enable(void)
AnnaBridge	172:65be27845400	1585	{
AnnaBridge	172:65be27845400	1586	SET_BIT(RCC->CSR, RCC_CSR_LSION);
AnnaBridge	172:65be27845400	1587	}
AnnaBridge	172:65be27845400	1588
AnnaBridge	172:65be27845400	1589	/**
AnnaBridge	172:65be27845400	1590	* @brief Disable LSI Oscillator
AnnaBridge	172:65be27845400	1591	* @rmtoll CSR LSION LL_RCC_LSI_Disable
AnnaBridge	172:65be27845400	1592	* @retval None
AnnaBridge	172:65be27845400	1593	*/
AnnaBridge	172:65be27845400	1594	__STATIC_INLINE void LL_RCC_LSI_Disable(void)
AnnaBridge	172:65be27845400	1595	{
AnnaBridge	172:65be27845400	1596	CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
AnnaBridge	172:65be27845400	1597	}
AnnaBridge	172:65be27845400	1598
AnnaBridge	172:65be27845400	1599	/**
AnnaBridge	172:65be27845400	1600	* @brief Check if LSI is Ready
AnnaBridge	172:65be27845400	1601	* @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
AnnaBridge	172:65be27845400	1602	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1603	*/
AnnaBridge	172:65be27845400	1604	__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
AnnaBridge	172:65be27845400	1605	{
AnnaBridge	172:65be27845400	1606	return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY))?1UL:0UL);
AnnaBridge	172:65be27845400	1607	}
AnnaBridge	172:65be27845400	1608
AnnaBridge	172:65be27845400	1609	/**
AnnaBridge	172:65be27845400	1610	* @}
AnnaBridge	172:65be27845400	1611	*/
AnnaBridge	172:65be27845400	1612
AnnaBridge	172:65be27845400	1613	/** @defgroup RCC_LL_EF_System System
AnnaBridge	172:65be27845400	1614	* @{
AnnaBridge	172:65be27845400	1615	*/
AnnaBridge	172:65be27845400	1616
AnnaBridge	172:65be27845400	1617	/**
AnnaBridge	172:65be27845400	1618	* @brief Configure the system clock source
AnnaBridge	172:65be27845400	1619	* @rmtoll CFGR SW LL_RCC_SetSysClkSource
AnnaBridge	172:65be27845400	1620	* @param Source This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1621	* @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
AnnaBridge	172:65be27845400	1622	* @arg @ref LL_RCC_SYS_CLKSOURCE_CSI
AnnaBridge	172:65be27845400	1623	* @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
AnnaBridge	172:65be27845400	1624	* @arg @ref LL_RCC_SYS_CLKSOURCE_PLL1
AnnaBridge	172:65be27845400	1625	* @retval None
AnnaBridge	172:65be27845400	1626	*/
AnnaBridge	172:65be27845400	1627	__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
AnnaBridge	172:65be27845400	1628	{
AnnaBridge	172:65be27845400	1629	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
AnnaBridge	172:65be27845400	1630	}
AnnaBridge	172:65be27845400	1631
AnnaBridge	172:65be27845400	1632	/**
AnnaBridge	172:65be27845400	1633	* @brief Get the system clock source
AnnaBridge	172:65be27845400	1634	* @rmtoll CFGR SWS LL_RCC_GetSysClkSource
AnnaBridge	172:65be27845400	1635	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1636	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
AnnaBridge	172:65be27845400	1637	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_CSI
AnnaBridge	172:65be27845400	1638	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
AnnaBridge	172:65be27845400	1639	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL1
AnnaBridge	172:65be27845400	1640	*/
AnnaBridge	172:65be27845400	1641	__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
AnnaBridge	172:65be27845400	1642	{
AnnaBridge	172:65be27845400	1643	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
AnnaBridge	172:65be27845400	1644	}
AnnaBridge	172:65be27845400	1645
AnnaBridge	172:65be27845400	1646	/**
AnnaBridge	172:65be27845400	1647	* @brief Configure the system wakeup clock source
AnnaBridge	172:65be27845400	1648	* @rmtoll CFGR STOPWUCK LL_RCC_SetSysWakeUpClkSource
AnnaBridge	172:65be27845400	1649	* @param Source This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1650	* @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_HSI
AnnaBridge	172:65be27845400	1651	* @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_CSI
AnnaBridge	172:65be27845400	1652	* @retval None
AnnaBridge	172:65be27845400	1653	*/
AnnaBridge	172:65be27845400	1654	__STATIC_INLINE void LL_RCC_SetSysWakeUpClkSource(uint32_t Source)
AnnaBridge	172:65be27845400	1655	{
AnnaBridge	172:65be27845400	1656	MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Source);
AnnaBridge	172:65be27845400	1657	}
AnnaBridge	172:65be27845400	1658
AnnaBridge	172:65be27845400	1659	/**
AnnaBridge	172:65be27845400	1660	* @brief Get the system wakeup clock source
AnnaBridge	172:65be27845400	1661	* @rmtoll CFGR STOPWUCK LL_RCC_GetSysWakeUpClkSource
AnnaBridge	172:65be27845400	1662	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1663	* @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_HSI
AnnaBridge	172:65be27845400	1664	* @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_CSI
AnnaBridge	172:65be27845400	1665	*/
AnnaBridge	172:65be27845400	1666	__STATIC_INLINE uint32_t LL_RCC_GetSysWakeUpClkSource(void)
AnnaBridge	172:65be27845400	1667	{
AnnaBridge	172:65be27845400	1668	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK));
AnnaBridge	172:65be27845400	1669	}
AnnaBridge	172:65be27845400	1670
AnnaBridge	172:65be27845400	1671	/**
AnnaBridge	172:65be27845400	1672	* @brief Configure the kernel wakeup clock source
AnnaBridge	172:65be27845400	1673	* @rmtoll CFGR STOPKERWUCK LL_RCC_SetKerWakeUpClkSource
AnnaBridge	172:65be27845400	1674	* @param Source This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1675	* @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_HSI
AnnaBridge	172:65be27845400	1676	* @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_CSI
AnnaBridge	172:65be27845400	1677	* @retval None
AnnaBridge	172:65be27845400	1678	*/
AnnaBridge	172:65be27845400	1679	__STATIC_INLINE void LL_RCC_SetKerWakeUpClkSource(uint32_t Source)
AnnaBridge	172:65be27845400	1680	{
AnnaBridge	172:65be27845400	1681	MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, Source);
AnnaBridge	172:65be27845400	1682	}
AnnaBridge	172:65be27845400	1683
AnnaBridge	172:65be27845400	1684	/**
AnnaBridge	172:65be27845400	1685	* @brief Get the kernel wakeup clock source
AnnaBridge	172:65be27845400	1686	* @rmtoll CFGR STOPKERWUCK LL_RCC_GetKerWakeUpClkSource
AnnaBridge	172:65be27845400	1687	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1688	* @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_HSI
AnnaBridge	172:65be27845400	1689	* @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_CSI
AnnaBridge	172:65be27845400	1690	*/
AnnaBridge	172:65be27845400	1691	__STATIC_INLINE uint32_t LL_RCC_GetKerWakeUpClkSource(void)
AnnaBridge	172:65be27845400	1692	{
AnnaBridge	172:65be27845400	1693	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPKERWUCK));
AnnaBridge	172:65be27845400	1694	}
AnnaBridge	172:65be27845400	1695
AnnaBridge	172:65be27845400	1696	/**
AnnaBridge	172:65be27845400	1697	* @brief Set System prescaler
AnnaBridge	172:65be27845400	1698	* @rmtoll D1CFGR D1CPRE LL_RCC_SetSysPrescaler
AnnaBridge	172:65be27845400	1699	* @param Prescaler This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1700	* @arg @ref LL_RCC_SYSCLK_DIV_1
AnnaBridge	172:65be27845400	1701	* @arg @ref LL_RCC_SYSCLK_DIV_2
AnnaBridge	172:65be27845400	1702	* @arg @ref LL_RCC_SYSCLK_DIV_4
AnnaBridge	172:65be27845400	1703	* @arg @ref LL_RCC_SYSCLK_DIV_8
AnnaBridge	172:65be27845400	1704	* @arg @ref LL_RCC_SYSCLK_DIV_16
AnnaBridge	172:65be27845400	1705	* @arg @ref LL_RCC_SYSCLK_DIV_64
AnnaBridge	172:65be27845400	1706	* @arg @ref LL_RCC_SYSCLK_DIV_128
AnnaBridge	172:65be27845400	1707	* @arg @ref LL_RCC_SYSCLK_DIV_256
AnnaBridge	172:65be27845400	1708	* @arg @ref LL_RCC_SYSCLK_DIV_512
AnnaBridge	172:65be27845400	1709	* @retval None
AnnaBridge	172:65be27845400	1710	*/
AnnaBridge	172:65be27845400	1711	__STATIC_INLINE void LL_RCC_SetSysPrescaler(uint32_t Prescaler)
AnnaBridge	172:65be27845400	1712	{
AnnaBridge	172:65be27845400	1713	MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, Prescaler);
AnnaBridge	172:65be27845400	1714	}
AnnaBridge	172:65be27845400	1715
AnnaBridge	172:65be27845400	1716	/**
AnnaBridge	172:65be27845400	1717	* @brief Set AHB prescaler
AnnaBridge	172:65be27845400	1718	* @rmtoll D1CFGR HPRE LL_RCC_SetAHBPrescaler
AnnaBridge	172:65be27845400	1719	* @param Prescaler This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1720	* @arg @ref LL_RCC_AHB_DIV_1
AnnaBridge	172:65be27845400	1721	* @arg @ref LL_RCC_AHB_DIV_2
AnnaBridge	172:65be27845400	1722	* @arg @ref LL_RCC_AHB_DIV_4
AnnaBridge	172:65be27845400	1723	* @arg @ref LL_RCC_AHB_DIV_8
AnnaBridge	172:65be27845400	1724	* @arg @ref LL_RCC_AHB_DIV_16
AnnaBridge	172:65be27845400	1725	* @arg @ref LL_RCC_AHB_DIV_64
AnnaBridge	172:65be27845400	1726	* @arg @ref LL_RCC_AHB_DIV_128
AnnaBridge	172:65be27845400	1727	* @arg @ref LL_RCC_AHB_DIV_256
AnnaBridge	172:65be27845400	1728	* @arg @ref LL_RCC_AHB_DIV_512
AnnaBridge	172:65be27845400	1729	* @retval None
AnnaBridge	172:65be27845400	1730	*/
AnnaBridge	172:65be27845400	1731	__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
AnnaBridge	172:65be27845400	1732	{
AnnaBridge	172:65be27845400	1733	MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, Prescaler);
AnnaBridge	172:65be27845400	1734	}
AnnaBridge	172:65be27845400	1735
AnnaBridge	172:65be27845400	1736	/**
AnnaBridge	172:65be27845400	1737	* @brief Set APB1 prescaler
AnnaBridge	172:65be27845400	1738	* @rmtoll D2CFGR D2PPRE1 LL_RCC_SetAPB1Prescaler
AnnaBridge	172:65be27845400	1739	* @param Prescaler This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1740	* @arg @ref LL_RCC_APB1_DIV_1
AnnaBridge	172:65be27845400	1741	* @arg @ref LL_RCC_APB1_DIV_2
AnnaBridge	172:65be27845400	1742	* @arg @ref LL_RCC_APB1_DIV_4
AnnaBridge	172:65be27845400	1743	* @arg @ref LL_RCC_APB1_DIV_8
AnnaBridge	172:65be27845400	1744	* @arg @ref LL_RCC_APB1_DIV_16
AnnaBridge	172:65be27845400	1745	* @retval None
AnnaBridge	172:65be27845400	1746	*/
AnnaBridge	172:65be27845400	1747	__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
AnnaBridge	172:65be27845400	1748	{
AnnaBridge	172:65be27845400	1749	MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, Prescaler);
AnnaBridge	172:65be27845400	1750	}
AnnaBridge	172:65be27845400	1751
AnnaBridge	172:65be27845400	1752	/**
AnnaBridge	172:65be27845400	1753	* @brief Set APB2 prescaler
AnnaBridge	172:65be27845400	1754	* @rmtoll D2CFGR D2PPRE2 LL_RCC_SetAPB2Prescaler
AnnaBridge	172:65be27845400	1755	* @param Prescaler This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1756	* @arg @ref LL_RCC_APB2_DIV_1
AnnaBridge	172:65be27845400	1757	* @arg @ref LL_RCC_APB2_DIV_2
AnnaBridge	172:65be27845400	1758	* @arg @ref LL_RCC_APB2_DIV_4
AnnaBridge	172:65be27845400	1759	* @arg @ref LL_RCC_APB2_DIV_8
AnnaBridge	172:65be27845400	1760	* @arg @ref LL_RCC_APB2_DIV_16
AnnaBridge	172:65be27845400	1761	* @retval None
AnnaBridge	172:65be27845400	1762	*/
AnnaBridge	172:65be27845400	1763	__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
AnnaBridge	172:65be27845400	1764	{
AnnaBridge	172:65be27845400	1765	MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, Prescaler);
AnnaBridge	172:65be27845400	1766	}
AnnaBridge	172:65be27845400	1767
AnnaBridge	172:65be27845400	1768	/**
AnnaBridge	172:65be27845400	1769	* @brief Set APB3 prescaler
AnnaBridge	172:65be27845400	1770	* @rmtoll D1CFGR D1PPRE LL_RCC_SetAPB3Prescaler
AnnaBridge	172:65be27845400	1771	* @param Prescaler This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1772	* @arg @ref LL_RCC_APB3_DIV_1
AnnaBridge	172:65be27845400	1773	* @arg @ref LL_RCC_APB3_DIV_2
AnnaBridge	172:65be27845400	1774	* @arg @ref LL_RCC_APB3_DIV_4
AnnaBridge	172:65be27845400	1775	* @arg @ref LL_RCC_APB3_DIV_8
AnnaBridge	172:65be27845400	1776	* @arg @ref LL_RCC_APB3_DIV_16
AnnaBridge	172:65be27845400	1777	* @retval None
AnnaBridge	172:65be27845400	1778	*/
AnnaBridge	172:65be27845400	1779	__STATIC_INLINE void LL_RCC_SetAPB3Prescaler(uint32_t Prescaler)
AnnaBridge	172:65be27845400	1780	{
AnnaBridge	172:65be27845400	1781	MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, Prescaler);
AnnaBridge	172:65be27845400	1782	}
AnnaBridge	172:65be27845400	1783
AnnaBridge	172:65be27845400	1784	/**
AnnaBridge	172:65be27845400	1785	* @brief Set APB4 prescaler
AnnaBridge	172:65be27845400	1786	* @rmtoll D3CFGR D3PPRE LL_RCC_SetAPB4Prescaler
AnnaBridge	172:65be27845400	1787	* @param Prescaler This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1788	* @arg @ref LL_RCC_APB4_DIV_1
AnnaBridge	172:65be27845400	1789	* @arg @ref LL_RCC_APB4_DIV_2
AnnaBridge	172:65be27845400	1790	* @arg @ref LL_RCC_APB4_DIV_4
AnnaBridge	172:65be27845400	1791	* @arg @ref LL_RCC_APB4_DIV_8
AnnaBridge	172:65be27845400	1792	* @arg @ref LL_RCC_APB4_DIV_16
AnnaBridge	172:65be27845400	1793	* @retval None
AnnaBridge	172:65be27845400	1794	*/
AnnaBridge	172:65be27845400	1795	__STATIC_INLINE void LL_RCC_SetAPB4Prescaler(uint32_t Prescaler)
AnnaBridge	172:65be27845400	1796	{
AnnaBridge	172:65be27845400	1797	MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, Prescaler);
AnnaBridge	172:65be27845400	1798	}
AnnaBridge	172:65be27845400	1799
AnnaBridge	172:65be27845400	1800	/**
AnnaBridge	172:65be27845400	1801	* @brief Get System prescaler
AnnaBridge	172:65be27845400	1802	* @rmtoll D1CFGR D1CPRE LL_RCC_GetSysPrescaler
AnnaBridge	172:65be27845400	1803	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1804	* @arg @ref LL_RCC_SYSCLK_DIV_1
AnnaBridge	172:65be27845400	1805	* @arg @ref LL_RCC_SYSCLK_DIV_2
AnnaBridge	172:65be27845400	1806	* @arg @ref LL_RCC_SYSCLK_DIV_4
AnnaBridge	172:65be27845400	1807	* @arg @ref LL_RCC_SYSCLK_DIV_8
AnnaBridge	172:65be27845400	1808	* @arg @ref LL_RCC_SYSCLK_DIV_16
AnnaBridge	172:65be27845400	1809	* @arg @ref LL_RCC_SYSCLK_DIV_64
AnnaBridge	172:65be27845400	1810	* @arg @ref LL_RCC_SYSCLK_DIV_128
AnnaBridge	172:65be27845400	1811	* @arg @ref LL_RCC_SYSCLK_DIV_256
AnnaBridge	172:65be27845400	1812	* @arg @ref LL_RCC_SYSCLK_DIV_512
AnnaBridge	172:65be27845400	1813	*/
AnnaBridge	172:65be27845400	1814	__STATIC_INLINE uint32_t LL_RCC_GetSysPrescaler(void)
AnnaBridge	172:65be27845400	1815	{
AnnaBridge	172:65be27845400	1816	return (uint32_t)(READ_BIT(RCC->D1CFGR, RCC_D1CFGR_D1CPRE));
AnnaBridge	172:65be27845400	1817	}
AnnaBridge	172:65be27845400	1818
AnnaBridge	172:65be27845400	1819	/**
AnnaBridge	172:65be27845400	1820	* @brief Get AHB prescaler
AnnaBridge	172:65be27845400	1821	* @rmtoll D1CFGR HPRE LL_RCC_GetAHBPrescaler
AnnaBridge	172:65be27845400	1822	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1823	* @arg @ref LL_RCC_AHB_DIV_1
AnnaBridge	172:65be27845400	1824	* @arg @ref LL_RCC_AHB_DIV_2
AnnaBridge	172:65be27845400	1825	* @arg @ref LL_RCC_AHB_DIV_4
AnnaBridge	172:65be27845400	1826	* @arg @ref LL_RCC_AHB_DIV_8
AnnaBridge	172:65be27845400	1827	* @arg @ref LL_RCC_AHB_DIV_16
AnnaBridge	172:65be27845400	1828	* @arg @ref LL_RCC_AHB_DIV_64
AnnaBridge	172:65be27845400	1829	* @arg @ref LL_RCC_AHB_DIV_128
AnnaBridge	172:65be27845400	1830	* @arg @ref LL_RCC_AHB_DIV_256
AnnaBridge	172:65be27845400	1831	* @arg @ref LL_RCC_AHB_DIV_512
AnnaBridge	172:65be27845400	1832	*/
AnnaBridge	172:65be27845400	1833	__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
AnnaBridge	172:65be27845400	1834	{
AnnaBridge	172:65be27845400	1835	return (uint32_t)(READ_BIT(RCC->D1CFGR, RCC_D1CFGR_HPRE));
AnnaBridge	172:65be27845400	1836	}
AnnaBridge	172:65be27845400	1837
AnnaBridge	172:65be27845400	1838	/**
AnnaBridge	172:65be27845400	1839	* @brief Get APB1 prescaler
AnnaBridge	172:65be27845400	1840	* @rmtoll D2CFGR D2PPRE1 LL_RCC_GetAPB1Prescaler
AnnaBridge	172:65be27845400	1841	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1842	* @arg @ref LL_RCC_APB1_DIV_1
AnnaBridge	172:65be27845400	1843	* @arg @ref LL_RCC_APB1_DIV_2
AnnaBridge	172:65be27845400	1844	* @arg @ref LL_RCC_APB1_DIV_4
AnnaBridge	172:65be27845400	1845	* @arg @ref LL_RCC_APB1_DIV_8
AnnaBridge	172:65be27845400	1846	* @arg @ref LL_RCC_APB1_DIV_16
AnnaBridge	172:65be27845400	1847	*/
AnnaBridge	172:65be27845400	1848	__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
AnnaBridge	172:65be27845400	1849	{
AnnaBridge	172:65be27845400	1850	return (uint32_t)(READ_BIT(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1));
AnnaBridge	172:65be27845400	1851	}
AnnaBridge	172:65be27845400	1852
AnnaBridge	172:65be27845400	1853	/**
AnnaBridge	172:65be27845400	1854	* @brief Get APB2 prescaler
AnnaBridge	172:65be27845400	1855	* @rmtoll D2CFGR D2PPRE2 LL_RCC_GetAPB2Prescaler
AnnaBridge	172:65be27845400	1856	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1857	* @arg @ref LL_RCC_APB2_DIV_1
AnnaBridge	172:65be27845400	1858	* @arg @ref LL_RCC_APB2_DIV_2
AnnaBridge	172:65be27845400	1859	* @arg @ref LL_RCC_APB2_DIV_4
AnnaBridge	172:65be27845400	1860	* @arg @ref LL_RCC_APB2_DIV_8
AnnaBridge	172:65be27845400	1861	* @arg @ref LL_RCC_APB2_DIV_16
AnnaBridge	172:65be27845400	1862	*/
AnnaBridge	172:65be27845400	1863	__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
AnnaBridge	172:65be27845400	1864	{
AnnaBridge	172:65be27845400	1865	return (uint32_t)(READ_BIT(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2));
AnnaBridge	172:65be27845400	1866	}
AnnaBridge	172:65be27845400	1867
AnnaBridge	172:65be27845400	1868	/**
AnnaBridge	172:65be27845400	1869	* @brief Get APB3 prescaler
AnnaBridge	172:65be27845400	1870	* @rmtoll D1CFGR D1PPRE LL_RCC_GetAPB3Prescaler
AnnaBridge	172:65be27845400	1871	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1872	* @arg @ref LL_RCC_APB3_DIV_1
AnnaBridge	172:65be27845400	1873	* @arg @ref LL_RCC_APB3_DIV_2
AnnaBridge	172:65be27845400	1874	* @arg @ref LL_RCC_APB3_DIV_4
AnnaBridge	172:65be27845400	1875	* @arg @ref LL_RCC_APB3_DIV_8
AnnaBridge	172:65be27845400	1876	* @arg @ref LL_RCC_APB3_DIV_16
AnnaBridge	172:65be27845400	1877	*/
AnnaBridge	172:65be27845400	1878	__STATIC_INLINE uint32_t LL_RCC_GetAPB3Prescaler(void)
AnnaBridge	172:65be27845400	1879	{
AnnaBridge	172:65be27845400	1880	return (uint32_t)(READ_BIT(RCC->D1CFGR, RCC_D1CFGR_D1PPRE));
AnnaBridge	172:65be27845400	1881	}
AnnaBridge	172:65be27845400	1882
AnnaBridge	172:65be27845400	1883	/**
AnnaBridge	172:65be27845400	1884	* @brief Get APB4 prescaler
AnnaBridge	172:65be27845400	1885	* @rmtoll D3CFGR D3PPRE LL_RCC_GetAPB4Prescaler
AnnaBridge	172:65be27845400	1886	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1887	* @arg @ref LL_RCC_APB4_DIV_1
AnnaBridge	172:65be27845400	1888	* @arg @ref LL_RCC_APB4_DIV_2
AnnaBridge	172:65be27845400	1889	* @arg @ref LL_RCC_APB4_DIV_4
AnnaBridge	172:65be27845400	1890	* @arg @ref LL_RCC_APB4_DIV_8
AnnaBridge	172:65be27845400	1891	* @arg @ref LL_RCC_APB4_DIV_16
AnnaBridge	172:65be27845400	1892	*/
AnnaBridge	172:65be27845400	1893	__STATIC_INLINE uint32_t LL_RCC_GetAPB4Prescaler(void)
AnnaBridge	172:65be27845400	1894	{
AnnaBridge	172:65be27845400	1895	return (uint32_t)(READ_BIT(RCC->D3CFGR, RCC_D3CFGR_D3PPRE));
AnnaBridge	172:65be27845400	1896	}
AnnaBridge	172:65be27845400	1897
AnnaBridge	172:65be27845400	1898	/**
AnnaBridge	172:65be27845400	1899	* @}
AnnaBridge	172:65be27845400	1900	*/
AnnaBridge	172:65be27845400	1901
AnnaBridge	172:65be27845400	1902	/** @defgroup RCC_LL_EF_MCO MCO
AnnaBridge	172:65be27845400	1903	* @{
AnnaBridge	172:65be27845400	1904	*/
AnnaBridge	172:65be27845400	1905
AnnaBridge	172:65be27845400	1906	/**
AnnaBridge	172:65be27845400	1907	* @brief Configure MCOx
AnnaBridge	172:65be27845400	1908	* @rmtoll CFGR MCO1 LL_RCC_ConfigMCO\n
AnnaBridge	172:65be27845400	1909	* CFGR MCO1PRE LL_RCC_ConfigMCO\n
AnnaBridge	172:65be27845400	1910	* CFGR MCO2 LL_RCC_ConfigMCO\n
AnnaBridge	172:65be27845400	1911	* CFGR MCO2PRE LL_RCC_ConfigMCO
AnnaBridge	172:65be27845400	1912	* @param MCOxSource This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1913	* @arg @ref LL_RCC_MCO1SOURCE_HSI
AnnaBridge	172:65be27845400	1914	* @arg @ref LL_RCC_MCO1SOURCE_LSE
AnnaBridge	172:65be27845400	1915	* @arg @ref LL_RCC_MCO1SOURCE_HSE
AnnaBridge	172:65be27845400	1916	* @arg @ref LL_RCC_MCO1SOURCE_PLL1QCLK
AnnaBridge	172:65be27845400	1917	* @arg @ref LL_RCC_MCO1SOURCE_HSI48
AnnaBridge	172:65be27845400	1918	* @arg @ref LL_RCC_MCO2SOURCE_SYSCLK
AnnaBridge	172:65be27845400	1919	* @arg @ref LL_RCC_MCO2SOURCE_PLL2PCLK
AnnaBridge	172:65be27845400	1920	* @arg @ref LL_RCC_MCO2SOURCE_HSE
AnnaBridge	172:65be27845400	1921	* @arg @ref LL_RCC_MCO2SOURCE_PLL1PCLK
AnnaBridge	172:65be27845400	1922	* @arg @ref LL_RCC_MCO2SOURCE_CSI
AnnaBridge	172:65be27845400	1923	* @arg @ref LL_RCC_MCO2SOURCE_LSI
AnnaBridge	172:65be27845400	1924	* @param MCOxPrescaler This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1925	* @arg @ref LL_RCC_MCO1_DIV_1
AnnaBridge	172:65be27845400	1926	* @arg @ref LL_RCC_MCO1_DIV_2
AnnaBridge	172:65be27845400	1927	* @arg @ref LL_RCC_MCO1_DIV_3
AnnaBridge	172:65be27845400	1928	* @arg @ref LL_RCC_MCO1_DIV_4
AnnaBridge	172:65be27845400	1929	* @arg @ref LL_RCC_MCO1_DIV_5
AnnaBridge	172:65be27845400	1930	* @arg @ref LL_RCC_MCO1_DIV_6
AnnaBridge	172:65be27845400	1931	* @arg @ref LL_RCC_MCO1_DIV_7
AnnaBridge	172:65be27845400	1932	* @arg @ref LL_RCC_MCO1_DIV_8
AnnaBridge	172:65be27845400	1933	* @arg @ref LL_RCC_MCO1_DIV_9
AnnaBridge	172:65be27845400	1934	* @arg @ref LL_RCC_MCO1_DIV_10
AnnaBridge	172:65be27845400	1935	* @arg @ref LL_RCC_MCO1_DIV_11
AnnaBridge	172:65be27845400	1936	* @arg @ref LL_RCC_MCO1_DIV_12
AnnaBridge	172:65be27845400	1937	* @arg @ref LL_RCC_MCO1_DIV_13
AnnaBridge	172:65be27845400	1938	* @arg @ref LL_RCC_MCO1_DIV_14
AnnaBridge	172:65be27845400	1939	* @arg @ref LL_RCC_MCO1_DIV_15
AnnaBridge	172:65be27845400	1940	* @arg @ref LL_RCC_MCO2_DIV_1
AnnaBridge	172:65be27845400	1941	* @arg @ref LL_RCC_MCO2_DIV_2
AnnaBridge	172:65be27845400	1942	* @arg @ref LL_RCC_MCO2_DIV_3
AnnaBridge	172:65be27845400	1943	* @arg @ref LL_RCC_MCO2_DIV_4
AnnaBridge	172:65be27845400	1944	* @arg @ref LL_RCC_MCO2_DIV_5
AnnaBridge	172:65be27845400	1945	* @arg @ref LL_RCC_MCO2_DIV_6
AnnaBridge	172:65be27845400	1946	* @arg @ref LL_RCC_MCO2_DIV_7
AnnaBridge	172:65be27845400	1947	* @arg @ref LL_RCC_MCO2_DIV_8
AnnaBridge	172:65be27845400	1948	* @arg @ref LL_RCC_MCO2_DIV_9
AnnaBridge	172:65be27845400	1949	* @arg @ref LL_RCC_MCO2_DIV_10
AnnaBridge	172:65be27845400	1950	* @arg @ref LL_RCC_MCO2_DIV_11
AnnaBridge	172:65be27845400	1951	* @arg @ref LL_RCC_MCO2_DIV_12
AnnaBridge	172:65be27845400	1952	* @arg @ref LL_RCC_MCO2_DIV_13
AnnaBridge	172:65be27845400	1953	* @arg @ref LL_RCC_MCO2_DIV_14
AnnaBridge	172:65be27845400	1954	* @arg @ref LL_RCC_MCO2_DIV_15
AnnaBridge	172:65be27845400	1955	* @retval None
AnnaBridge	172:65be27845400	1956	*/
AnnaBridge	172:65be27845400	1957	__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
AnnaBridge	172:65be27845400	1958	{
AnnaBridge	172:65be27845400	1959	MODIFY_REG(RCC->CFGR, (MCOxSource << 16U) \| (MCOxPrescaler << 16U), (MCOxSource & 0xFFFF0000U) \| (MCOxPrescaler & 0xFFFF0000U));
AnnaBridge	172:65be27845400	1960	}
AnnaBridge	172:65be27845400	1961
AnnaBridge	172:65be27845400	1962	/**
AnnaBridge	172:65be27845400	1963	* @}
AnnaBridge	172:65be27845400	1964	*/
AnnaBridge	172:65be27845400	1965
AnnaBridge	172:65be27845400	1966	/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
AnnaBridge	172:65be27845400	1967	* @{
AnnaBridge	172:65be27845400	1968	*/
AnnaBridge	172:65be27845400	1969
AnnaBridge	172:65be27845400	1970	/**
AnnaBridge	172:65be27845400	1971	* @brief Configure periph clock source
AnnaBridge	172:65be27845400	1972	* @rmtoll D2CCIP1R * LL_RCC_SetClockSource\n
AnnaBridge	172:65be27845400	1973	* D2CCIP2R * LL_RCC_SetClockSource\n
AnnaBridge	172:65be27845400	1974	* D3CCIPR * LL_RCC_SetClockSource
AnnaBridge	172:65be27845400	1975	* @param ClkSource This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1976	* @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2
AnnaBridge	172:65be27845400	1977	* @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q
AnnaBridge	172:65be27845400	1978	* @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q
AnnaBridge	172:65be27845400	1979	* @arg @ref LL_RCC_USART16_CLKSOURCE_HSI
AnnaBridge	172:65be27845400	1980	* @arg @ref LL_RCC_USART16_CLKSOURCE_CSI
AnnaBridge	172:65be27845400	1981	* @arg @ref LL_RCC_USART16_CLKSOURCE_LSE
AnnaBridge	172:65be27845400	1982	* @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1
AnnaBridge	172:65be27845400	1983	* @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q
AnnaBridge	172:65be27845400	1984	* @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q
AnnaBridge	172:65be27845400	1985	* @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI
AnnaBridge	172:65be27845400	1986	* @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI
AnnaBridge	172:65be27845400	1987	* @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE
AnnaBridge	172:65be27845400	1988	* @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1
AnnaBridge	172:65be27845400	1989	* @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R
AnnaBridge	172:65be27845400	1990	* @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI
AnnaBridge	172:65be27845400	1991	* @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI
AnnaBridge	172:65be27845400	1992	* @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4
AnnaBridge	172:65be27845400	1993	* @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R
AnnaBridge	172:65be27845400	1994	* @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
AnnaBridge	172:65be27845400	1995	* @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI
AnnaBridge	172:65be27845400	1996	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
AnnaBridge	172:65be27845400	1997	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
AnnaBridge	172:65be27845400	1998	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R
AnnaBridge	172:65be27845400	1999	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
AnnaBridge	172:65be27845400	2000	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
AnnaBridge	172:65be27845400	2001	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
AnnaBridge	172:65be27845400	2002	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4
AnnaBridge	172:65be27845400	2003	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P
AnnaBridge	172:65be27845400	2004	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R
AnnaBridge	172:65be27845400	2005	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
AnnaBridge	172:65be27845400	2006	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
AnnaBridge	172:65be27845400	2007	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
AnnaBridge	172:65be27845400	2008	* @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4
AnnaBridge	172:65be27845400	2009	* @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P
AnnaBridge	172:65be27845400	2010	* @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R
AnnaBridge	172:65be27845400	2011	* @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE
AnnaBridge	172:65be27845400	2012	* @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI
AnnaBridge	172:65be27845400	2013	* @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP
AnnaBridge	172:65be27845400	2014	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q
AnnaBridge	172:65be27845400	2015	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P
AnnaBridge	172:65be27845400	2016	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
AnnaBridge	172:65be27845400	2017	* @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
AnnaBridge	172:65be27845400	2018	* @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
AnnaBridge	172:65be27845400	2019	* @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q
AnnaBridge	172:65be27845400	2020	* @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P
AnnaBridge	172:65be27845400	2021	* @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P
AnnaBridge	172:65be27845400	2022	* @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN
AnnaBridge	172:65be27845400	2023	* @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP
AnnaBridge	172:65be27845400	2024	* @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q
AnnaBridge	172:65be27845400	2025	* @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P
AnnaBridge	172:65be27845400	2026	* @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P
AnnaBridge	172:65be27845400	2027	* @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN
AnnaBridge	172:65be27845400	2028	* @arg @ref LL_RCC_SAI4A_CLKSOURCE_CLKP
AnnaBridge	172:65be27845400	2029	* @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q
AnnaBridge	172:65be27845400	2030	* @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P
AnnaBridge	172:65be27845400	2031	* @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P
AnnaBridge	172:65be27845400	2032	* @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN
AnnaBridge	172:65be27845400	2033	* @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP
AnnaBridge	172:65be27845400	2034	* @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q
AnnaBridge	172:65be27845400	2035	* @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P
AnnaBridge	172:65be27845400	2036	* @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P
AnnaBridge	172:65be27845400	2037	* @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN
AnnaBridge	172:65be27845400	2038	* @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP
AnnaBridge	172:65be27845400	2039	* @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2
AnnaBridge	172:65be27845400	2040	* @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q
AnnaBridge	172:65be27845400	2041	* @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q
AnnaBridge	172:65be27845400	2042	* @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI
AnnaBridge	172:65be27845400	2043	* @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI
AnnaBridge	172:65be27845400	2044	* @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE
AnnaBridge	172:65be27845400	2045	* @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
AnnaBridge	172:65be27845400	2046	* @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q
AnnaBridge	172:65be27845400	2047	* @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q
AnnaBridge	172:65be27845400	2048	* @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
AnnaBridge	172:65be27845400	2049	* @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI
AnnaBridge	172:65be27845400	2050	* @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE
AnnaBridge	172:65be27845400	2051	* @retval None
AnnaBridge	172:65be27845400	2052	*/
AnnaBridge	172:65be27845400	2053	__STATIC_INLINE void LL_RCC_SetClockSource(uint32_t ClkSource)
AnnaBridge	172:65be27845400	2054	{
AnnaBridge	172:65be27845400	2055	register uint32_t * pReg = (uint32_t *)((uint32_t)&RCC->D1CCIPR + LL_CLKSOURCE_REG(ClkSource));
AnnaBridge	172:65be27845400	2056
AnnaBridge	172:65be27845400	2057	MODIFY_REG(*pReg, LL_CLKSOURCE_MASK(ClkSource), LL_CLKSOURCE_CONFIG(ClkSource));
AnnaBridge	172:65be27845400	2058	}
AnnaBridge	172:65be27845400	2059
AnnaBridge	172:65be27845400	2060	/**
AnnaBridge	172:65be27845400	2061	* @brief Configure USARTx clock source
AnnaBridge	172:65be27845400	2062	* @rmtoll D2CCIP2R USART16SEL LL_RCC_SetUSARTClockSource\n
AnnaBridge	172:65be27845400	2063	* D2CCIP2R USART28SEL LL_RCC_SetUSARTClockSource
AnnaBridge	172:65be27845400	2064	* @param ClkSource This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2065	* @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2
AnnaBridge	172:65be27845400	2066	* @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q
AnnaBridge	172:65be27845400	2067	* @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q
AnnaBridge	172:65be27845400	2068	* @arg @ref LL_RCC_USART16_CLKSOURCE_HSI
AnnaBridge	172:65be27845400	2069	* @arg @ref LL_RCC_USART16_CLKSOURCE_CSI
AnnaBridge	172:65be27845400	2070	* @arg @ref LL_RCC_USART16_CLKSOURCE_LSE
AnnaBridge	172:65be27845400	2071	* @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1
AnnaBridge	172:65be27845400	2072	* @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q
AnnaBridge	172:65be27845400	2073	* @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q
AnnaBridge	172:65be27845400	2074	* @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI
AnnaBridge	172:65be27845400	2075	* @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI
AnnaBridge	172:65be27845400	2076	* @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE
AnnaBridge	172:65be27845400	2077	* @retval None
AnnaBridge	172:65be27845400	2078	*/
AnnaBridge	172:65be27845400	2079	__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t ClkSource)
AnnaBridge	172:65be27845400	2080	{
AnnaBridge	172:65be27845400	2081	LL_RCC_SetClockSource(ClkSource);
AnnaBridge	172:65be27845400	2082	}
AnnaBridge	172:65be27845400	2083
AnnaBridge	172:65be27845400	2084	/**
AnnaBridge	172:65be27845400	2085	* @brief Configure LPUARTx clock source
AnnaBridge	172:65be27845400	2086	* @rmtoll D3CCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource
AnnaBridge	172:65be27845400	2087	* @param ClkSource This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2088	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK4
AnnaBridge	172:65be27845400	2089	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL2Q
AnnaBridge	172:65be27845400	2090	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL3Q
AnnaBridge	172:65be27845400	2091	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
AnnaBridge	172:65be27845400	2092	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_CSI
AnnaBridge	172:65be27845400	2093	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
AnnaBridge	172:65be27845400	2094	* @retval None
AnnaBridge	172:65be27845400	2095	*/
AnnaBridge	172:65be27845400	2096	__STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t ClkSource)
AnnaBridge	172:65be27845400	2097	{
AnnaBridge	172:65be27845400	2098	MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL, ClkSource);
AnnaBridge	172:65be27845400	2099	}
AnnaBridge	172:65be27845400	2100
AnnaBridge	172:65be27845400	2101	/**
AnnaBridge	172:65be27845400	2102	* @brief Configure I2Cx clock source
AnnaBridge	172:65be27845400	2103	* @rmtoll D2CCIP2R I2C123SEL LL_RCC_SetI2CClockSource\n
AnnaBridge	172:65be27845400	2104	* D3CCIPR I2C4SEL LL_RCC_SetI2CClockSource
AnnaBridge	172:65be27845400	2105	* @param ClkSource This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2106	* @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1
AnnaBridge	172:65be27845400	2107	* @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R
AnnaBridge	172:65be27845400	2108	* @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI
AnnaBridge	172:65be27845400	2109	* @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI
AnnaBridge	172:65be27845400	2110	* @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4
AnnaBridge	172:65be27845400	2111	* @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R
AnnaBridge	172:65be27845400	2112	* @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
AnnaBridge	172:65be27845400	2113	* @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI
AnnaBridge	172:65be27845400	2114	* @retval None
AnnaBridge	172:65be27845400	2115	*/
AnnaBridge	172:65be27845400	2116	__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t ClkSource)
AnnaBridge	172:65be27845400	2117	{
AnnaBridge	172:65be27845400	2118	LL_RCC_SetClockSource(ClkSource);
AnnaBridge	172:65be27845400	2119	}
AnnaBridge	172:65be27845400	2120
AnnaBridge	172:65be27845400	2121	/**
AnnaBridge	172:65be27845400	2122	* @brief Configure LPTIMx clock source
AnnaBridge	172:65be27845400	2123	* @rmtoll D2CCIP2R LPTIM1SEL LL_RCC_SetLPTIMClockSource
AnnaBridge	172:65be27845400	2124	* D3CCIPR LPTIM2SEL LL_RCC_SetLPTIMClockSource\n
AnnaBridge	172:65be27845400	2125	* D3CCIPR LPTIM345SEL LL_RCC_SetLPTIMClockSource
AnnaBridge	172:65be27845400	2126	* @param ClkSource This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2127	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
AnnaBridge	172:65be27845400	2128	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
AnnaBridge	172:65be27845400	2129	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R
AnnaBridge	172:65be27845400	2130	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
AnnaBridge	172:65be27845400	2131	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
AnnaBridge	172:65be27845400	2132	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
AnnaBridge	172:65be27845400	2133	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4
AnnaBridge	172:65be27845400	2134	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P
AnnaBridge	172:65be27845400	2135	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R
AnnaBridge	172:65be27845400	2136	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
AnnaBridge	172:65be27845400	2137	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
AnnaBridge	172:65be27845400	2138	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
AnnaBridge	172:65be27845400	2139	* @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4
AnnaBridge	172:65be27845400	2140	* @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P
AnnaBridge	172:65be27845400	2141	* @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R
AnnaBridge	172:65be27845400	2142	* @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE
AnnaBridge	172:65be27845400	2143	* @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI
AnnaBridge	172:65be27845400	2144	* @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP
AnnaBridge	172:65be27845400	2145	* @retval None
AnnaBridge	172:65be27845400	2146	*/
AnnaBridge	172:65be27845400	2147	__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t ClkSource)
AnnaBridge	172:65be27845400	2148	{
AnnaBridge	172:65be27845400	2149	LL_RCC_SetClockSource(ClkSource);
AnnaBridge	172:65be27845400	2150	}
AnnaBridge	172:65be27845400	2151
AnnaBridge	172:65be27845400	2152	/**
AnnaBridge	172:65be27845400	2153	* @brief Configure SAIx clock source
AnnaBridge	172:65be27845400	2154	* @rmtoll D2CCIP1R SAI1SEL LL_RCC_SetSAIClockSource\n
AnnaBridge	172:65be27845400	2155	* D2CCIP1R SAI23SEL LL_RCC_SetSAIClockSource
AnnaBridge	172:65be27845400	2156	* D3CCIPR SAI4ASEL LL_RCC_SetSAI4xClockSource\n
AnnaBridge	172:65be27845400	2157	* D3CCIPR SAI4BSEL LL_RCC_SetSAI4xClockSource
AnnaBridge	172:65be27845400	2158	* @param ClkSource This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2159	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q
AnnaBridge	172:65be27845400	2160	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P
AnnaBridge	172:65be27845400	2161	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
AnnaBridge	172:65be27845400	2162	* @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
AnnaBridge	172:65be27845400	2163	* @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
AnnaBridge	172:65be27845400	2164	* @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q
AnnaBridge	172:65be27845400	2165	* @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P
AnnaBridge	172:65be27845400	2166	* @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P
AnnaBridge	172:65be27845400	2167	* @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN
AnnaBridge	172:65be27845400	2168	* @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP
AnnaBridge	172:65be27845400	2169	* @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q
AnnaBridge	172:65be27845400	2170	* @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P
AnnaBridge	172:65be27845400	2171	* @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P
AnnaBridge	172:65be27845400	2172	* @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN
AnnaBridge	172:65be27845400	2173	* @arg @ref LL_RCC_SAI4A_CLKSOURCE_CLKP
AnnaBridge	172:65be27845400	2174	* @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q
AnnaBridge	172:65be27845400	2175	* @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P
AnnaBridge	172:65be27845400	2176	* @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P
AnnaBridge	172:65be27845400	2177	* @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN
AnnaBridge	172:65be27845400	2178	* @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP
AnnaBridge	172:65be27845400	2179	* @retval None
AnnaBridge	172:65be27845400	2180	*/
AnnaBridge	172:65be27845400	2181	__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t ClkSource)
AnnaBridge	172:65be27845400	2182	{
AnnaBridge	172:65be27845400	2183	LL_RCC_SetClockSource(ClkSource);
AnnaBridge	172:65be27845400	2184	}
AnnaBridge	172:65be27845400	2185
AnnaBridge	172:65be27845400	2186	/**
AnnaBridge	172:65be27845400	2187	* @brief Configure SDMMCx clock source
AnnaBridge	172:65be27845400	2188	* @rmtoll D1CCIPR SDMMCSEL LL_RCC_SetSDMMCClockSource
AnnaBridge	172:65be27845400	2189	* @param ClkSource This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2190	* @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL1Q
AnnaBridge	172:65be27845400	2191	* @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL2R
AnnaBridge	172:65be27845400	2192	* @retval None
AnnaBridge	172:65be27845400	2193	*/
AnnaBridge	172:65be27845400	2194	__STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t ClkSource)
AnnaBridge	172:65be27845400	2195	{
AnnaBridge	172:65be27845400	2196	MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL, ClkSource);
AnnaBridge	172:65be27845400	2197	}
AnnaBridge	172:65be27845400	2198
AnnaBridge	172:65be27845400	2199	/**
AnnaBridge	172:65be27845400	2200	* @brief Configure RNGx clock source
AnnaBridge	172:65be27845400	2201	* @rmtoll D2CCIP2R RNGSEL LL_RCC_SetRNGClockSource
AnnaBridge	172:65be27845400	2202	* @param ClkSource This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2203	* @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
AnnaBridge	172:65be27845400	2204	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLL1Q
AnnaBridge	172:65be27845400	2205	* @arg @ref LL_RCC_RNG_CLKSOURCE_LSE
AnnaBridge	172:65be27845400	2206	* @arg @ref LL_RCC_RNG_CLKSOURCE_LSI
AnnaBridge	172:65be27845400	2207	* @retval None
AnnaBridge	172:65be27845400	2208	*/
AnnaBridge	172:65be27845400	2209	__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t ClkSource)
AnnaBridge	172:65be27845400	2210	{
AnnaBridge	172:65be27845400	2211	MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL, ClkSource);
AnnaBridge	172:65be27845400	2212	}
AnnaBridge	172:65be27845400	2213
AnnaBridge	172:65be27845400	2214	/**
AnnaBridge	172:65be27845400	2215	* @brief Configure USBx clock source
AnnaBridge	172:65be27845400	2216	* @rmtoll D2CCIP2R USBSEL LL_RCC_SetUSBClockSource
AnnaBridge	172:65be27845400	2217	* @param ClkSource This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2218	* @arg @ref LL_RCC_USB_CLKSOURCE_DISABLE
AnnaBridge	172:65be27845400	2219	* @arg @ref LL_RCC_USB_CLKSOURCE_PLL1Q
AnnaBridge	172:65be27845400	2220	* @arg @ref LL_RCC_USB_CLKSOURCE_PLL3Q
AnnaBridge	172:65be27845400	2221	* @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
AnnaBridge	172:65be27845400	2222	* @retval None
AnnaBridge	172:65be27845400	2223	*/
AnnaBridge	172:65be27845400	2224	__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t ClkSource)
AnnaBridge	172:65be27845400	2225	{
AnnaBridge	172:65be27845400	2226	MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL, ClkSource);
AnnaBridge	172:65be27845400	2227	}
AnnaBridge	172:65be27845400	2228
AnnaBridge	172:65be27845400	2229	/**
AnnaBridge	172:65be27845400	2230	* @brief Configure CECx clock source
AnnaBridge	172:65be27845400	2231	* @rmtoll D2CCIP2R CECSEL LL_RCC_SetCECClockSource
AnnaBridge	172:65be27845400	2232	* @param ClkSource This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2233	* @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
AnnaBridge	172:65be27845400	2234	* @arg @ref LL_RCC_CEC_CLKSOURCE_LSI
AnnaBridge	172:65be27845400	2235	* @arg @ref LL_RCC_CEC_CLKSOURCE_CSI_DIV122
AnnaBridge	172:65be27845400	2236	* @retval None
AnnaBridge	172:65be27845400	2237	*/
AnnaBridge	172:65be27845400	2238	__STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t ClkSource)
AnnaBridge	172:65be27845400	2239	{
AnnaBridge	172:65be27845400	2240	MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL, ClkSource);
AnnaBridge	172:65be27845400	2241	}
AnnaBridge	172:65be27845400	2242
AnnaBridge	172:65be27845400	2243	/**
AnnaBridge	172:65be27845400	2244	* @brief Configure DFSDMx Kernel clock source
AnnaBridge	172:65be27845400	2245	* @rmtoll D2CCIP1R DFSDM1SEL LL_RCC_SetDFSDMClockSource
AnnaBridge	172:65be27845400	2246	* @param ClkSource This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2247	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
AnnaBridge	172:65be27845400	2248	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
AnnaBridge	172:65be27845400	2249	* @retval None
AnnaBridge	172:65be27845400	2250	*/
AnnaBridge	172:65be27845400	2251	__STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t ClkSource)
AnnaBridge	172:65be27845400	2252	{
AnnaBridge	172:65be27845400	2253	MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, ClkSource);
AnnaBridge	172:65be27845400	2254	}
AnnaBridge	172:65be27845400	2255
AnnaBridge	172:65be27845400	2256	/**
AnnaBridge	172:65be27845400	2257	* @brief Configure FMCx Kernel clock source
AnnaBridge	172:65be27845400	2258	* @rmtoll D1CCIPR FMCSEL LL_RCC_SetFMCClockSource
AnnaBridge	172:65be27845400	2259	* @param ClkSource This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2260	* @arg @ref LL_RCC_FMC_CLKSOURCE_HCLK
AnnaBridge	172:65be27845400	2261	* @arg @ref LL_RCC_FMC_CLKSOURCE_PLL1Q
AnnaBridge	172:65be27845400	2262	* @arg @ref LL_RCC_FMC_CLKSOURCE_PLL2R
AnnaBridge	172:65be27845400	2263	* @arg @ref LL_RCC_FMC_CLKSOURCE_CLKP
AnnaBridge	172:65be27845400	2264	* @retval None
AnnaBridge	172:65be27845400	2265	*/
AnnaBridge	172:65be27845400	2266	__STATIC_INLINE void LL_RCC_SetFMCClockSource(uint32_t ClkSource)
AnnaBridge	172:65be27845400	2267	{
AnnaBridge	172:65be27845400	2268	MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL, ClkSource);
AnnaBridge	172:65be27845400	2269	}
AnnaBridge	172:65be27845400	2270
AnnaBridge	172:65be27845400	2271	/**
AnnaBridge	172:65be27845400	2272	* @brief Configure QSPIx Kernel clock source
AnnaBridge	172:65be27845400	2273	* @rmtoll D1CCIPR QSPISEL LL_RCC_SetQSPIClockSource
AnnaBridge	172:65be27845400	2274	* @param ClkSource This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2275	* @arg @ref LL_RCC_QSPI_CLKSOURCE_HCLK
AnnaBridge	172:65be27845400	2276	* @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL1Q
AnnaBridge	172:65be27845400	2277	* @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL2R
AnnaBridge	172:65be27845400	2278	* @arg @ref LL_RCC_QSPI_CLKSOURCE_CLKP
AnnaBridge	172:65be27845400	2279	* @retval None
AnnaBridge	172:65be27845400	2280	*/
AnnaBridge	172:65be27845400	2281	__STATIC_INLINE void LL_RCC_SetQSPIClockSource(uint32_t ClkSource)
AnnaBridge	172:65be27845400	2282	{
AnnaBridge	172:65be27845400	2283	MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL, ClkSource);
AnnaBridge	172:65be27845400	2284	}
AnnaBridge	172:65be27845400	2285
AnnaBridge	172:65be27845400	2286	/**
AnnaBridge	172:65be27845400	2287	* @brief Configure CLKP Kernel clock source
AnnaBridge	172:65be27845400	2288	* @rmtoll D1CCIPR CKPERSEL LL_RCC_SetCLKPClockSource
AnnaBridge	172:65be27845400	2289	* @param ClkSource This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2290	* @arg @ref LL_RCC_CLKP_CLKSOURCE_HSI
AnnaBridge	172:65be27845400	2291	* @arg @ref LL_RCC_CLKP_CLKSOURCE_CSI
AnnaBridge	172:65be27845400	2292	* @arg @ref LL_RCC_CLKP_CLKSOURCE_HSE
AnnaBridge	172:65be27845400	2293	* @retval None
AnnaBridge	172:65be27845400	2294	*/
AnnaBridge	172:65be27845400	2295	__STATIC_INLINE void LL_RCC_SetCLKPClockSource(uint32_t ClkSource)
AnnaBridge	172:65be27845400	2296	{
AnnaBridge	172:65be27845400	2297	MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL, ClkSource);
AnnaBridge	172:65be27845400	2298	}
AnnaBridge	172:65be27845400	2299
AnnaBridge	172:65be27845400	2300	/**
AnnaBridge	172:65be27845400	2301	* @brief Configure SPIx Kernel clock source
AnnaBridge	172:65be27845400	2302	* @rmtoll D2CCIP1R SPI123SEL LL_RCC_SetSPIClockSource\n
AnnaBridge	172:65be27845400	2303	* D2CCIP1R SPI45SEL LL_RCC_SetSPIClockSource\n
AnnaBridge	172:65be27845400	2304	* D3CCIPR SPI6SEL LL_RCC_SetSPIClockSource
AnnaBridge	172:65be27845400	2305	* @param ClkSource This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2306	* @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q
AnnaBridge	172:65be27845400	2307	* @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P
AnnaBridge	172:65be27845400	2308	* @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P
AnnaBridge	172:65be27845400	2309	* @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN
AnnaBridge	172:65be27845400	2310	* @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP
AnnaBridge	172:65be27845400	2311	* @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2
AnnaBridge	172:65be27845400	2312	* @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q
AnnaBridge	172:65be27845400	2313	* @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q
AnnaBridge	172:65be27845400	2314	* @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI
AnnaBridge	172:65be27845400	2315	* @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI
AnnaBridge	172:65be27845400	2316	* @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE
AnnaBridge	172:65be27845400	2317	* @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
AnnaBridge	172:65be27845400	2318	* @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q
AnnaBridge	172:65be27845400	2319	* @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q
AnnaBridge	172:65be27845400	2320	* @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
AnnaBridge	172:65be27845400	2321	* @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI
AnnaBridge	172:65be27845400	2322	* @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE
AnnaBridge	172:65be27845400	2323	* @retval None
AnnaBridge	172:65be27845400	2324	*/
AnnaBridge	172:65be27845400	2325	__STATIC_INLINE void LL_RCC_SetSPIClockSource(uint32_t ClkSource)
AnnaBridge	172:65be27845400	2326	{
AnnaBridge	172:65be27845400	2327	LL_RCC_SetClockSource(ClkSource);
AnnaBridge	172:65be27845400	2328	}
AnnaBridge	172:65be27845400	2329
AnnaBridge	172:65be27845400	2330	/**
AnnaBridge	172:65be27845400	2331	* @brief Configure SPDIFx Kernel clock source
AnnaBridge	172:65be27845400	2332	* @rmtoll D2CCIP1R SPDIFSEL LL_RCC_SetSPDIFClockSource
AnnaBridge	172:65be27845400	2333	* @param ClkSource This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2334	* @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL1Q
AnnaBridge	172:65be27845400	2335	* @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL2R
AnnaBridge	172:65be27845400	2336	* @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL3R
AnnaBridge	172:65be27845400	2337	* @arg @ref LL_RCC_SPDIF_CLKSOURCE_HSI
AnnaBridge	172:65be27845400	2338	* @retval None
AnnaBridge	172:65be27845400	2339	*/
AnnaBridge	172:65be27845400	2340	__STATIC_INLINE void LL_RCC_SetSPDIFClockSource(uint32_t ClkSource)
AnnaBridge	172:65be27845400	2341	{
AnnaBridge	172:65be27845400	2342	MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL, ClkSource);
AnnaBridge	172:65be27845400	2343	}
AnnaBridge	172:65be27845400	2344
AnnaBridge	172:65be27845400	2345	/**
AnnaBridge	172:65be27845400	2346	* @brief Configure FDCANx Kernel clock source
AnnaBridge	172:65be27845400	2347	* @rmtoll D2CCIP1R FDCANSEL LL_RCC_SetFDCANClockSource
AnnaBridge	172:65be27845400	2348	* @param ClkSource This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2349	* @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
AnnaBridge	172:65be27845400	2350	* @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL1Q
AnnaBridge	172:65be27845400	2351	* @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL2Q
AnnaBridge	172:65be27845400	2352	* @retval None
AnnaBridge	172:65be27845400	2353	*/
AnnaBridge	172:65be27845400	2354	__STATIC_INLINE void LL_RCC_SetFDCANClockSource(uint32_t ClkSource)
AnnaBridge	172:65be27845400	2355	{
AnnaBridge	172:65be27845400	2356	MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL, ClkSource);
AnnaBridge	172:65be27845400	2357	}
AnnaBridge	172:65be27845400	2358
AnnaBridge	172:65be27845400	2359	/**
AnnaBridge	172:65be27845400	2360	* @brief Configure SWPx Kernel clock source
AnnaBridge	172:65be27845400	2361	* @rmtoll D2CCIP1R SWPSEL LL_RCC_SetSWPClockSource
AnnaBridge	172:65be27845400	2362	* @param ClkSource This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2363	* @arg @ref LL_RCC_SWP_CLKSOURCE_PCLK1
AnnaBridge	172:65be27845400	2364	* @arg @ref LL_RCC_SWP_CLKSOURCE_HSI
AnnaBridge	172:65be27845400	2365	* @retval None
AnnaBridge	172:65be27845400	2366	*/
AnnaBridge	172:65be27845400	2367	__STATIC_INLINE void LL_RCC_SetSWPClockSource(uint32_t ClkSource)
AnnaBridge	172:65be27845400	2368	{
AnnaBridge	172:65be27845400	2369	MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL, ClkSource);
AnnaBridge	172:65be27845400	2370	}
AnnaBridge	172:65be27845400	2371
AnnaBridge	172:65be27845400	2372	/**
AnnaBridge	172:65be27845400	2373	* @brief Configure ADCx Kernel clock source
AnnaBridge	172:65be27845400	2374	* @rmtoll D3CCIPR ADCSEL LL_RCC_SetADCClockSource
AnnaBridge	172:65be27845400	2375	* @param ClkSource This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2376	* @arg @ref LL_RCC_ADC_CLKSOURCE_PLL2P
AnnaBridge	172:65be27845400	2377	* @arg @ref LL_RCC_ADC_CLKSOURCE_PLL3R
AnnaBridge	172:65be27845400	2378	* @arg @ref LL_RCC_ADC_CLKSOURCE_CLKP
AnnaBridge	172:65be27845400	2379	* @retval None
AnnaBridge	172:65be27845400	2380	*/
AnnaBridge	172:65be27845400	2381	__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ClkSource)
AnnaBridge	172:65be27845400	2382	{
AnnaBridge	172:65be27845400	2383	MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL, ClkSource);
AnnaBridge	172:65be27845400	2384	}
AnnaBridge	172:65be27845400	2385
AnnaBridge	172:65be27845400	2386	/**
AnnaBridge	172:65be27845400	2387	* @brief Get periph clock source
AnnaBridge	172:65be27845400	2388	* @rmtoll D1CCIPR * LL_RCC_GetClockSource\n
AnnaBridge	172:65be27845400	2389	* D2CCIP1R * LL_RCC_GetClockSource\n
AnnaBridge	172:65be27845400	2390	* D2CCIP2R * LL_RCC_GetClockSource\n
AnnaBridge	172:65be27845400	2391	* D3CCIPR * LL_RCC_GetClockSource
AnnaBridge	172:65be27845400	2392	* @param Periph This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2393	* @arg @ref LL_RCC_USART16_CLKSOURCE
AnnaBridge	172:65be27845400	2394	* @arg @ref LL_RCC_USART234578_CLKSOURCE
AnnaBridge	172:65be27845400	2395	* @arg @ref LL_RCC_I2C123_CLKSOURCE
AnnaBridge	172:65be27845400	2396	* @arg @ref LL_RCC_I2C4_CLKSOURCE
AnnaBridge	172:65be27845400	2397	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE
AnnaBridge	172:65be27845400	2398	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE
AnnaBridge	172:65be27845400	2399	* @arg @ref LL_RCC_LPTIM345_CLKSOURCE
AnnaBridge	172:65be27845400	2400	* @arg @ref LL_RCC_SAI1_CLKSOURCE
AnnaBridge	172:65be27845400	2401	* @arg @ref LL_RCC_SAI23_CLKSOURCE
AnnaBridge	172:65be27845400	2402	* @arg @ref LL_RCC_SAI4A_CLKSOURCE
AnnaBridge	172:65be27845400	2403	* @arg @ref LL_RCC_SAI4B_CLKSOURCE
AnnaBridge	172:65be27845400	2404	* @arg @ref LL_RCC_SPI123_CLKSOURCE
AnnaBridge	172:65be27845400	2405	* @arg @ref LL_RCC_SPI45_CLKSOURCE
AnnaBridge	172:65be27845400	2406	* @arg @ref LL_RCC_SPI6_CLKSOURCE
AnnaBridge	172:65be27845400	2407	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	2408	* @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2
AnnaBridge	172:65be27845400	2409	* @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q
AnnaBridge	172:65be27845400	2410	* @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q
AnnaBridge	172:65be27845400	2411	* @arg @ref LL_RCC_USART16_CLKSOURCE_HSI
AnnaBridge	172:65be27845400	2412	* @arg @ref LL_RCC_USART16_CLKSOURCE_CSI
AnnaBridge	172:65be27845400	2413	* @arg @ref LL_RCC_USART16_CLKSOURCE_LSE
AnnaBridge	172:65be27845400	2414	* @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1
AnnaBridge	172:65be27845400	2415	* @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q
AnnaBridge	172:65be27845400	2416	* @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q
AnnaBridge	172:65be27845400	2417	* @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI
AnnaBridge	172:65be27845400	2418	* @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI
AnnaBridge	172:65be27845400	2419	* @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE
AnnaBridge	172:65be27845400	2420	* @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1
AnnaBridge	172:65be27845400	2421	* @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R
AnnaBridge	172:65be27845400	2422	* @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI
AnnaBridge	172:65be27845400	2423	* @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI
AnnaBridge	172:65be27845400	2424	* @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4
AnnaBridge	172:65be27845400	2425	* @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R
AnnaBridge	172:65be27845400	2426	* @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
AnnaBridge	172:65be27845400	2427	* @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI
AnnaBridge	172:65be27845400	2428	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
AnnaBridge	172:65be27845400	2429	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
AnnaBridge	172:65be27845400	2430	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R
AnnaBridge	172:65be27845400	2431	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
AnnaBridge	172:65be27845400	2432	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
AnnaBridge	172:65be27845400	2433	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
AnnaBridge	172:65be27845400	2434	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4
AnnaBridge	172:65be27845400	2435	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P
AnnaBridge	172:65be27845400	2436	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R
AnnaBridge	172:65be27845400	2437	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
AnnaBridge	172:65be27845400	2438	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
AnnaBridge	172:65be27845400	2439	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
AnnaBridge	172:65be27845400	2440	* @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4
AnnaBridge	172:65be27845400	2441	* @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P
AnnaBridge	172:65be27845400	2442	* @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R
AnnaBridge	172:65be27845400	2443	* @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE
AnnaBridge	172:65be27845400	2444	* @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI
AnnaBridge	172:65be27845400	2445	* @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP
AnnaBridge	172:65be27845400	2446	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q
AnnaBridge	172:65be27845400	2447	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P
AnnaBridge	172:65be27845400	2448	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
AnnaBridge	172:65be27845400	2449	* @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
AnnaBridge	172:65be27845400	2450	* @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
AnnaBridge	172:65be27845400	2451	* @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q
AnnaBridge	172:65be27845400	2452	* @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P
AnnaBridge	172:65be27845400	2453	* @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P
AnnaBridge	172:65be27845400	2454	* @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN
AnnaBridge	172:65be27845400	2455	* @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP
AnnaBridge	172:65be27845400	2456	* @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q
AnnaBridge	172:65be27845400	2457	* @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P
AnnaBridge	172:65be27845400	2458	* @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P
AnnaBridge	172:65be27845400	2459	* @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN
AnnaBridge	172:65be27845400	2460	* @arg @ref LL_RCC_SAI4A_CLKSOURCE_CLKP
AnnaBridge	172:65be27845400	2461	* @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q
AnnaBridge	172:65be27845400	2462	* @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P
AnnaBridge	172:65be27845400	2463	* @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P
AnnaBridge	172:65be27845400	2464	* @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN
AnnaBridge	172:65be27845400	2465	* @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP
AnnaBridge	172:65be27845400	2466	* @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q
AnnaBridge	172:65be27845400	2467	* @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P
AnnaBridge	172:65be27845400	2468	* @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P
AnnaBridge	172:65be27845400	2469	* @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN
AnnaBridge	172:65be27845400	2470	* @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP
AnnaBridge	172:65be27845400	2471	* @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2
AnnaBridge	172:65be27845400	2472	* @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q
AnnaBridge	172:65be27845400	2473	* @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q
AnnaBridge	172:65be27845400	2474	* @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI
AnnaBridge	172:65be27845400	2475	* @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI
AnnaBridge	172:65be27845400	2476	* @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE
AnnaBridge	172:65be27845400	2477	* @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
AnnaBridge	172:65be27845400	2478	* @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q
AnnaBridge	172:65be27845400	2479	* @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q
AnnaBridge	172:65be27845400	2480	* @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
AnnaBridge	172:65be27845400	2481	* @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI
AnnaBridge	172:65be27845400	2482	* @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE
AnnaBridge	172:65be27845400	2483	* @retval None
AnnaBridge	172:65be27845400	2484	*/
AnnaBridge	172:65be27845400	2485	__STATIC_INLINE uint32_t LL_RCC_GetClockSource(uint32_t Periph)
AnnaBridge	172:65be27845400	2486	{
AnnaBridge	172:65be27845400	2487	register const uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&RCC->D1CCIPR) + LL_CLKSOURCE_REG(Periph)));
AnnaBridge	172:65be27845400	2488
AnnaBridge	172:65be27845400	2489	return (uint32_t) (Periph \| (((READ_BIT(*pReg, LL_CLKSOURCE_MASK(Periph))) >> LL_CLKSOURCE_SHIFT(Periph)) << CONFIG_SHIFT) );
AnnaBridge	172:65be27845400	2490	}
AnnaBridge	172:65be27845400	2491
AnnaBridge	172:65be27845400	2492	/**
AnnaBridge	172:65be27845400	2493	* @brief Get USARTx clock source
AnnaBridge	172:65be27845400	2494	* @rmtoll D2CCIP2R USART16SEL LL_RCC_GetUSARTClockSource\n
AnnaBridge	172:65be27845400	2495	* D2CCIP2R USART28SEL LL_RCC_GetUSARTClockSource
AnnaBridge	172:65be27845400	2496	* @param Periph This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2497	* @arg @ref LL_RCC_USART16_CLKSOURCE
AnnaBridge	172:65be27845400	2498	* @arg @ref LL_RCC_USART234578_CLKSOURCE
AnnaBridge	172:65be27845400	2499	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	2500	* @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2
AnnaBridge	172:65be27845400	2501	* @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q
AnnaBridge	172:65be27845400	2502	* @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q
AnnaBridge	172:65be27845400	2503	* @arg @ref LL_RCC_USART16_CLKSOURCE_HSI
AnnaBridge	172:65be27845400	2504	* @arg @ref LL_RCC_USART16_CLKSOURCE_CSI
AnnaBridge	172:65be27845400	2505	* @arg @ref LL_RCC_USART16_CLKSOURCE_LSE
AnnaBridge	172:65be27845400	2506	* @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1
AnnaBridge	172:65be27845400	2507	* @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q
AnnaBridge	172:65be27845400	2508	* @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q
AnnaBridge	172:65be27845400	2509	* @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI
AnnaBridge	172:65be27845400	2510	* @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI
AnnaBridge	172:65be27845400	2511	* @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE
AnnaBridge	172:65be27845400	2512	*/
AnnaBridge	172:65be27845400	2513	__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t Periph)
AnnaBridge	172:65be27845400	2514	{
AnnaBridge	172:65be27845400	2515	return LL_RCC_GetClockSource(Periph);
AnnaBridge	172:65be27845400	2516	}
AnnaBridge	172:65be27845400	2517
AnnaBridge	172:65be27845400	2518	/**
AnnaBridge	172:65be27845400	2519	* @brief Get LPUART clock source
AnnaBridge	172:65be27845400	2520	* @rmtoll D3CCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource
AnnaBridge	172:65be27845400	2521	* @param Periph This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2522	* @arg @ref LL_RCC_LPUART1_CLKSOURCE
AnnaBridge	172:65be27845400	2523	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	2524	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK4
AnnaBridge	172:65be27845400	2525	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL2Q
AnnaBridge	172:65be27845400	2526	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL3Q
AnnaBridge	172:65be27845400	2527	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
AnnaBridge	172:65be27845400	2528	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_CSI
AnnaBridge	172:65be27845400	2529	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
AnnaBridge	172:65be27845400	2530	*/
AnnaBridge	172:65be27845400	2531	__STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t Periph)
AnnaBridge	172:65be27845400	2532	{
AnnaBridge	172:65be27845400	2533	UNUSED(Periph);
AnnaBridge	172:65be27845400	2534	return (uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL));
AnnaBridge	172:65be27845400	2535	}
AnnaBridge	172:65be27845400	2536
AnnaBridge	172:65be27845400	2537	/**
AnnaBridge	172:65be27845400	2538	* @brief Get I2Cx clock source
AnnaBridge	172:65be27845400	2539	* @rmtoll D2CCIP2R I2C123SEL LL_RCC_GetI2CClockSource\n
AnnaBridge	172:65be27845400	2540	* D3CCIPR I2C4SEL LL_RCC_GetI2CClockSource
AnnaBridge	172:65be27845400	2541	* @param Periph This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2542	* @arg @ref LL_RCC_I2C123_CLKSOURCE
AnnaBridge	172:65be27845400	2543	* @arg @ref LL_RCC_I2C4_CLKSOURCE
AnnaBridge	172:65be27845400	2544	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	2545	* @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1
AnnaBridge	172:65be27845400	2546	* @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R
AnnaBridge	172:65be27845400	2547	* @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI
AnnaBridge	172:65be27845400	2548	* @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI
AnnaBridge	172:65be27845400	2549	* @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4
AnnaBridge	172:65be27845400	2550	* @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R
AnnaBridge	172:65be27845400	2551	* @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
AnnaBridge	172:65be27845400	2552	* @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI
AnnaBridge	172:65be27845400	2553	*/
AnnaBridge	172:65be27845400	2554	__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t Periph)
AnnaBridge	172:65be27845400	2555	{
AnnaBridge	172:65be27845400	2556	return LL_RCC_GetClockSource(Periph);
AnnaBridge	172:65be27845400	2557	}
AnnaBridge	172:65be27845400	2558
AnnaBridge	172:65be27845400	2559	/**
AnnaBridge	172:65be27845400	2560	* @brief Get LPTIM clock source
AnnaBridge	172:65be27845400	2561	* @rmtoll D2CCIP2R LPTIM1SEL LL_RCC_GetLPTIMClockSource\n
AnnaBridge	172:65be27845400	2562	* D3CCIPR LPTIM2SEL LL_RCC_GetLPTIMClockSource\n
AnnaBridge	172:65be27845400	2563	* D3CCIPR LPTIM345SEL LL_RCC_GetLPTIMClockSource
AnnaBridge	172:65be27845400	2564	* @param Periph This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2565	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE
AnnaBridge	172:65be27845400	2566	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE
AnnaBridge	172:65be27845400	2567	* @arg @ref LL_RCC_LPTIM345_CLKSOURCE
AnnaBridge	172:65be27845400	2568	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	2569	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
AnnaBridge	172:65be27845400	2570	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
AnnaBridge	172:65be27845400	2571	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R
AnnaBridge	172:65be27845400	2572	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
AnnaBridge	172:65be27845400	2573	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
AnnaBridge	172:65be27845400	2574	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
AnnaBridge	172:65be27845400	2575	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4
AnnaBridge	172:65be27845400	2576	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P
AnnaBridge	172:65be27845400	2577	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R
AnnaBridge	172:65be27845400	2578	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
AnnaBridge	172:65be27845400	2579	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
AnnaBridge	172:65be27845400	2580	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
AnnaBridge	172:65be27845400	2581	* @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4
AnnaBridge	172:65be27845400	2582	* @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P
AnnaBridge	172:65be27845400	2583	* @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R
AnnaBridge	172:65be27845400	2584	* @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE
AnnaBridge	172:65be27845400	2585	* @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI
AnnaBridge	172:65be27845400	2586	* @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP
AnnaBridge	172:65be27845400	2587	* @retval None
AnnaBridge	172:65be27845400	2588	*/
AnnaBridge	172:65be27845400	2589	__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t Periph)
AnnaBridge	172:65be27845400	2590	{
AnnaBridge	172:65be27845400	2591	return LL_RCC_GetClockSource(Periph);
AnnaBridge	172:65be27845400	2592	}
AnnaBridge	172:65be27845400	2593
AnnaBridge	172:65be27845400	2594	/**
AnnaBridge	172:65be27845400	2595	* @brief Get SAIx clock source
AnnaBridge	172:65be27845400	2596	* @rmtoll D2CCIP1R SAI1SEL LL_RCC_GetSAIClockSource\n
AnnaBridge	172:65be27845400	2597	* D2CCIP1R SAI23SEL LL_RCC_GetSAIClockSource
AnnaBridge	172:65be27845400	2598	* D3CCIPR SAI4ASEL LL_RCC_GetSAIClockSource\n
AnnaBridge	172:65be27845400	2599	* D3CCIPR SAI4BSEL LL_RCC_GetSAIClockSource
AnnaBridge	172:65be27845400	2600	* @param Periph This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2601	* @arg @ref LL_RCC_SAI1_CLKSOURCE
AnnaBridge	172:65be27845400	2602	* @arg @ref LL_RCC_SAI23_CLKSOURCE
AnnaBridge	172:65be27845400	2603	* @arg @ref LL_RCC_SAI4A_CLKSOURCE
AnnaBridge	172:65be27845400	2604	* @arg @ref LL_RCC_SAI4B_CLKSOURCE
AnnaBridge	172:65be27845400	2605	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	2606	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q
AnnaBridge	172:65be27845400	2607	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P
AnnaBridge	172:65be27845400	2608	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
AnnaBridge	172:65be27845400	2609	* @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
AnnaBridge	172:65be27845400	2610	* @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
AnnaBridge	172:65be27845400	2611	* @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q
AnnaBridge	172:65be27845400	2612	* @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P
AnnaBridge	172:65be27845400	2613	* @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P
AnnaBridge	172:65be27845400	2614	* @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN
AnnaBridge	172:65be27845400	2615	* @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP
AnnaBridge	172:65be27845400	2616	* @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q
AnnaBridge	172:65be27845400	2617	* @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P
AnnaBridge	172:65be27845400	2618	* @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P
AnnaBridge	172:65be27845400	2619	* @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN
AnnaBridge	172:65be27845400	2620	* @arg @ref LL_RCC_SAI4A_CLKSOURCE_CLKP
AnnaBridge	172:65be27845400	2621	* @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q
AnnaBridge	172:65be27845400	2622	* @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P
AnnaBridge	172:65be27845400	2623	* @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P
AnnaBridge	172:65be27845400	2624	* @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN
AnnaBridge	172:65be27845400	2625	* @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP
AnnaBridge	172:65be27845400	2626	*/
AnnaBridge	172:65be27845400	2627	__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t Periph)
AnnaBridge	172:65be27845400	2628	{
AnnaBridge	172:65be27845400	2629	return LL_RCC_GetClockSource(Periph);
AnnaBridge	172:65be27845400	2630	}
AnnaBridge	172:65be27845400	2631
AnnaBridge	172:65be27845400	2632	/**
AnnaBridge	172:65be27845400	2633	* @brief Get SDMMC clock source
AnnaBridge	172:65be27845400	2634	* @rmtoll D1CCIPR SDMMCSEL LL_RCC_GetSDMMCClockSource
AnnaBridge	172:65be27845400	2635	* @param Periph This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2636	* @arg @ref LL_RCC_SDMMC_CLKSOURCE
AnnaBridge	172:65be27845400	2637	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	2638	* @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL1Q
AnnaBridge	172:65be27845400	2639	* @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL2R
AnnaBridge	172:65be27845400	2640	*/
AnnaBridge	172:65be27845400	2641	__STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t Periph)
AnnaBridge	172:65be27845400	2642	{
AnnaBridge	172:65be27845400	2643	UNUSED(Periph);
AnnaBridge	172:65be27845400	2644	return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL));
AnnaBridge	172:65be27845400	2645	}
AnnaBridge	172:65be27845400	2646
AnnaBridge	172:65be27845400	2647	/**
AnnaBridge	172:65be27845400	2648	* @brief Get RNG clock source
AnnaBridge	172:65be27845400	2649	* @rmtoll D2CCIP2R RNGSEL LL_RCC_GetRNGClockSource
AnnaBridge	172:65be27845400	2650	* @param Periph This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2651	* @arg @ref LL_RCC_RNG_CLKSOURCE
AnnaBridge	172:65be27845400	2652	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	2653	* @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
AnnaBridge	172:65be27845400	2654	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLL1Q
AnnaBridge	172:65be27845400	2655	* @arg @ref LL_RCC_RNG_CLKSOURCE_LSE
AnnaBridge	172:65be27845400	2656	* @arg @ref LL_RCC_RNG_CLKSOURCE_LSI
AnnaBridge	172:65be27845400	2657	*/
AnnaBridge	172:65be27845400	2658	__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t Periph)
AnnaBridge	172:65be27845400	2659	{
AnnaBridge	172:65be27845400	2660	UNUSED(Periph);
AnnaBridge	172:65be27845400	2661	return (uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL));
AnnaBridge	172:65be27845400	2662	}
AnnaBridge	172:65be27845400	2663
AnnaBridge	172:65be27845400	2664	/**
AnnaBridge	172:65be27845400	2665	* @brief Get USB clock source
AnnaBridge	172:65be27845400	2666	* @rmtoll D2CCIP2R USBSEL LL_RCC_GetUSBClockSource
AnnaBridge	172:65be27845400	2667	* @param Periph This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2668	* @arg @ref LL_RCC_USB_CLKSOURCE
AnnaBridge	172:65be27845400	2669	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	2670	* @arg @ref LL_RCC_USB_CLKSOURCE_DISABLE
AnnaBridge	172:65be27845400	2671	* @arg @ref LL_RCC_USB_CLKSOURCE_PLL1Q
AnnaBridge	172:65be27845400	2672	* @arg @ref LL_RCC_USB_CLKSOURCE_PLL3Q
AnnaBridge	172:65be27845400	2673	* @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
AnnaBridge	172:65be27845400	2674	*/
AnnaBridge	172:65be27845400	2675	__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t Periph)
AnnaBridge	172:65be27845400	2676	{
AnnaBridge	172:65be27845400	2677	UNUSED(Periph);
AnnaBridge	172:65be27845400	2678	return (uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL));
AnnaBridge	172:65be27845400	2679	}
AnnaBridge	172:65be27845400	2680
AnnaBridge	172:65be27845400	2681	/**
AnnaBridge	172:65be27845400	2682	* @brief Get CEC clock source
AnnaBridge	172:65be27845400	2683	* @rmtoll D2CCIP2R CECSEL LL_RCC_GetCECClockSource
AnnaBridge	172:65be27845400	2684	* @param Periph This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2685	* @arg @ref LL_RCC_CEC_CLKSOURCE
AnnaBridge	172:65be27845400	2686	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	2687	* @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
AnnaBridge	172:65be27845400	2688	* @arg @ref LL_RCC_CEC_CLKSOURCE_LSI
AnnaBridge	172:65be27845400	2689	* @arg @ref LL_RCC_CEC_CLKSOURCE_CSI_DIV122
AnnaBridge	172:65be27845400	2690	*/
AnnaBridge	172:65be27845400	2691	__STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t Periph)
AnnaBridge	172:65be27845400	2692	{
AnnaBridge	172:65be27845400	2693	UNUSED(Periph);
AnnaBridge	172:65be27845400	2694	return (uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL));
AnnaBridge	172:65be27845400	2695	}
AnnaBridge	172:65be27845400	2696
AnnaBridge	172:65be27845400	2697	/**
AnnaBridge	172:65be27845400	2698	* @brief Get DFSDM Kernel clock source
AnnaBridge	172:65be27845400	2699	* @rmtoll D2CCIP1R DFSDM1SEL LL_RCC_GetDFSDMClockSource
AnnaBridge	172:65be27845400	2700	* @param Periph This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2701	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE
AnnaBridge	172:65be27845400	2702	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	2703	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
AnnaBridge	172:65be27845400	2704	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
AnnaBridge	172:65be27845400	2705	*/
AnnaBridge	172:65be27845400	2706	__STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t Periph)
AnnaBridge	172:65be27845400	2707	{
AnnaBridge	172:65be27845400	2708	UNUSED(Periph);
AnnaBridge	172:65be27845400	2709	return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL));
AnnaBridge	172:65be27845400	2710	}
AnnaBridge	172:65be27845400	2711
AnnaBridge	172:65be27845400	2712	/**
AnnaBridge	172:65be27845400	2713	* @brief Get FMC Kernel clock source
AnnaBridge	172:65be27845400	2714	* @rmtoll D1CCIPR FMCSEL LL_RCC_GetFMCClockSource
AnnaBridge	172:65be27845400	2715	* @param Periph This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2716	* @arg @ref LL_RCC_FMC_CLKSOURCE
AnnaBridge	172:65be27845400	2717	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	2718	* @arg @ref LL_RCC_FMC_CLKSOURCE_HCLK
AnnaBridge	172:65be27845400	2719	* @arg @ref LL_RCC_FMC_CLKSOURCE_PLL1Q
AnnaBridge	172:65be27845400	2720	* @arg @ref LL_RCC_FMC_CLKSOURCE_PLL2R
AnnaBridge	172:65be27845400	2721	* @arg @ref LL_RCC_FMC_CLKSOURCE_CLKP
AnnaBridge	172:65be27845400	2722	*/
AnnaBridge	172:65be27845400	2723	__STATIC_INLINE uint32_t LL_RCC_GetFMCClockSource(uint32_t Periph)
AnnaBridge	172:65be27845400	2724	{
AnnaBridge	172:65be27845400	2725	UNUSED(Periph);
AnnaBridge	172:65be27845400	2726	return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL));
AnnaBridge	172:65be27845400	2727	}
AnnaBridge	172:65be27845400	2728
AnnaBridge	172:65be27845400	2729	/**
AnnaBridge	172:65be27845400	2730	* @brief Get QSPI Kernel clock source
AnnaBridge	172:65be27845400	2731	* @rmtoll D1CCIPR QSPISEL LL_RCC_GetQSPIClockSource
AnnaBridge	172:65be27845400	2732	* @param Periph This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2733	* @arg @ref LL_RCC_QSPI_CLKSOURCE
AnnaBridge	172:65be27845400	2734	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	2735	* @arg @ref LL_RCC_QSPI_CLKSOURCE_HCLK
AnnaBridge	172:65be27845400	2736	* @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL1Q
AnnaBridge	172:65be27845400	2737	* @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL2R
AnnaBridge	172:65be27845400	2738	* @arg @ref LL_RCC_QSPI_CLKSOURCE_CLKP
AnnaBridge	172:65be27845400	2739	*/
AnnaBridge	172:65be27845400	2740	__STATIC_INLINE uint32_t LL_RCC_GetQSPIClockSource(uint32_t Periph)
AnnaBridge	172:65be27845400	2741	{
AnnaBridge	172:65be27845400	2742	UNUSED(Periph);
AnnaBridge	172:65be27845400	2743	return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL));
AnnaBridge	172:65be27845400	2744	}
AnnaBridge	172:65be27845400	2745
AnnaBridge	172:65be27845400	2746	/**
AnnaBridge	172:65be27845400	2747	* @brief Get CLKP Kernel clock source
AnnaBridge	172:65be27845400	2748	* @rmtoll D1CCIPR CKPERSEL LL_RCC_GetCLKPClockSource
AnnaBridge	172:65be27845400	2749	* @param Periph This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2750	* @arg @ref LL_RCC_CLKP_CLKSOURCE
AnnaBridge	172:65be27845400	2751	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	2752	* @arg @ref LL_RCC_CLKP_CLKSOURCE_HSI
AnnaBridge	172:65be27845400	2753	* @arg @ref LL_RCC_CLKP_CLKSOURCE_CSI
AnnaBridge	172:65be27845400	2754	* @arg @ref LL_RCC_CLKP_CLKSOURCE_HSE
AnnaBridge	172:65be27845400	2755	*/
AnnaBridge	172:65be27845400	2756	__STATIC_INLINE uint32_t LL_RCC_GetCLKPClockSource(uint32_t Periph)
AnnaBridge	172:65be27845400	2757	{
AnnaBridge	172:65be27845400	2758	UNUSED(Periph);
AnnaBridge	172:65be27845400	2759	return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL));
AnnaBridge	172:65be27845400	2760	}
AnnaBridge	172:65be27845400	2761
AnnaBridge	172:65be27845400	2762	/**
AnnaBridge	172:65be27845400	2763	* @brief Get SPIx Kernel clock source
AnnaBridge	172:65be27845400	2764	* @rmtoll D2CCIP1R SPI123SEL LL_RCC_GetSPIClockSource\n
AnnaBridge	172:65be27845400	2765	* D2CCIP1R SPI45SEL LL_RCC_GetSPIClockSource\n
AnnaBridge	172:65be27845400	2766	* D3CCIPR SPI6SEL LL_RCC_GetSPIClockSource
AnnaBridge	172:65be27845400	2767	* @param Periph This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2768	* @arg @ref LL_RCC_SPI123_CLKSOURCE
AnnaBridge	172:65be27845400	2769	* @arg @ref LL_RCC_SPI45_CLKSOURCE
AnnaBridge	172:65be27845400	2770	* @arg @ref LL_RCC_SPI6_CLKSOURCE
AnnaBridge	172:65be27845400	2771	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	2772	* @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q
AnnaBridge	172:65be27845400	2773	* @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P
AnnaBridge	172:65be27845400	2774	* @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P
AnnaBridge	172:65be27845400	2775	* @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN
AnnaBridge	172:65be27845400	2776	* @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP
AnnaBridge	172:65be27845400	2777	* @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2
AnnaBridge	172:65be27845400	2778	* @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q
AnnaBridge	172:65be27845400	2779	* @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q
AnnaBridge	172:65be27845400	2780	* @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI
AnnaBridge	172:65be27845400	2781	* @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI
AnnaBridge	172:65be27845400	2782	* @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE
AnnaBridge	172:65be27845400	2783	* @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
AnnaBridge	172:65be27845400	2784	* @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q
AnnaBridge	172:65be27845400	2785	* @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q
AnnaBridge	172:65be27845400	2786	* @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
AnnaBridge	172:65be27845400	2787	* @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI
AnnaBridge	172:65be27845400	2788	* @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE
AnnaBridge	172:65be27845400	2789	*/
AnnaBridge	172:65be27845400	2790	__STATIC_INLINE uint32_t LL_RCC_GetSPIClockSource(uint32_t Periph)
AnnaBridge	172:65be27845400	2791	{
AnnaBridge	172:65be27845400	2792	return LL_RCC_GetClockSource(Periph);
AnnaBridge	172:65be27845400	2793	}
AnnaBridge	172:65be27845400	2794
AnnaBridge	172:65be27845400	2795	/**
AnnaBridge	172:65be27845400	2796	* @brief Get SPDIF Kernel clock source
AnnaBridge	172:65be27845400	2797	* @rmtoll D2CCIP1R SPDIFSEL LL_RCC_GetSPDIFClockSource
AnnaBridge	172:65be27845400	2798	* @param Periph This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2799	* @arg @ref LL_RCC_SPDIF_CLKSOURCE
AnnaBridge	172:65be27845400	2800	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	2801	* @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL1Q
AnnaBridge	172:65be27845400	2802	* @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL2R
AnnaBridge	172:65be27845400	2803	* @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL3R
AnnaBridge	172:65be27845400	2804	* @arg @ref LL_RCC_SPDIF_CLKSOURCE_HSI
AnnaBridge	172:65be27845400	2805	*/
AnnaBridge	172:65be27845400	2806	__STATIC_INLINE uint32_t LL_RCC_GetSPDIFClockSource(uint32_t Periph)
AnnaBridge	172:65be27845400	2807	{
AnnaBridge	172:65be27845400	2808	UNUSED(Periph);
AnnaBridge	172:65be27845400	2809	return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL));
AnnaBridge	172:65be27845400	2810	}
AnnaBridge	172:65be27845400	2811
AnnaBridge	172:65be27845400	2812	/**
AnnaBridge	172:65be27845400	2813	* @brief Get FDCAN Kernel clock source
AnnaBridge	172:65be27845400	2814	* @rmtoll D2CCIP1R FDCANSEL LL_RCC_GetFDCANClockSource
AnnaBridge	172:65be27845400	2815	* @param Periph This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2816	* @arg @ref LL_RCC_FDCAN_CLKSOURCE
AnnaBridge	172:65be27845400	2817	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	2818	* @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
AnnaBridge	172:65be27845400	2819	* @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL1Q
AnnaBridge	172:65be27845400	2820	* @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL2Q
AnnaBridge	172:65be27845400	2821	*/
AnnaBridge	172:65be27845400	2822	__STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t Periph)
AnnaBridge	172:65be27845400	2823	{
AnnaBridge	172:65be27845400	2824	UNUSED(Periph);
AnnaBridge	172:65be27845400	2825	return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL));
AnnaBridge	172:65be27845400	2826	}
AnnaBridge	172:65be27845400	2827
AnnaBridge	172:65be27845400	2828	/**
AnnaBridge	172:65be27845400	2829	* @brief Get SWP Kernel clock source
AnnaBridge	172:65be27845400	2830	* @rmtoll D2CCIP1R SWPSEL LL_RCC_GetSWPClockSource
AnnaBridge	172:65be27845400	2831	* @param Periph This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2832	* @arg @ref LL_RCC_SWP_CLKSOURCE
AnnaBridge	172:65be27845400	2833	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	2834	* @arg @ref LL_RCC_SWP_CLKSOURCE_PCLK1
AnnaBridge	172:65be27845400	2835	* @arg @ref LL_RCC_SWP_CLKSOURCE_HSI
AnnaBridge	172:65be27845400	2836	*/
AnnaBridge	172:65be27845400	2837	__STATIC_INLINE uint32_t LL_RCC_GetSWPClockSource(uint32_t Periph)
AnnaBridge	172:65be27845400	2838	{
AnnaBridge	172:65be27845400	2839	UNUSED(Periph);
AnnaBridge	172:65be27845400	2840	return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL));
AnnaBridge	172:65be27845400	2841	}
AnnaBridge	172:65be27845400	2842
AnnaBridge	172:65be27845400	2843	/**
AnnaBridge	172:65be27845400	2844	* @brief Get ADC Kernel clock source
AnnaBridge	172:65be27845400	2845	* @rmtoll D3CCIPR ADCSEL LL_RCC_GetADCClockSolurce
AnnaBridge	172:65be27845400	2846	* @param Periph This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2847	* @arg @ref LL_RCC_ADC_CLKSOURCE
AnnaBridge	172:65be27845400	2848	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	2849	* @arg @ref LL_RCC_ADC_CLKSOURCE_PLL2P
AnnaBridge	172:65be27845400	2850	* @arg @ref LL_RCC_ADC_CLKSOURCE_PLL3R
AnnaBridge	172:65be27845400	2851	* @arg @ref LL_RCC_ADC_CLKSOURCE_CLKP
AnnaBridge	172:65be27845400	2852	*/
AnnaBridge	172:65be27845400	2853	__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t Periph)
AnnaBridge	172:65be27845400	2854	{
AnnaBridge	172:65be27845400	2855	UNUSED(Periph);
AnnaBridge	172:65be27845400	2856	return (uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL));
AnnaBridge	172:65be27845400	2857	}
AnnaBridge	172:65be27845400	2858
AnnaBridge	172:65be27845400	2859	/**
AnnaBridge	172:65be27845400	2860	* @}
AnnaBridge	172:65be27845400	2861	*/
AnnaBridge	172:65be27845400	2862
AnnaBridge	172:65be27845400	2863	/** @defgroup RCC_LL_EF_RTC RTC
AnnaBridge	172:65be27845400	2864	* @{
AnnaBridge	172:65be27845400	2865	*/
AnnaBridge	172:65be27845400	2866
AnnaBridge	172:65be27845400	2867	/**
AnnaBridge	172:65be27845400	2868	* @brief Set RTC Clock Source
AnnaBridge	172:65be27845400	2869	* @note Once the RTC clock source has been selected, it cannot be changed anymore unless
AnnaBridge	172:65be27845400	2870	* the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
AnnaBridge	172:65be27845400	2871	* set). The BDRST bit can be used to reset them.
AnnaBridge	172:65be27845400	2872	* @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
AnnaBridge	172:65be27845400	2873	* @param Source This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2874	* @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
AnnaBridge	172:65be27845400	2875	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
AnnaBridge	172:65be27845400	2876	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
AnnaBridge	172:65be27845400	2877	* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
AnnaBridge	172:65be27845400	2878	* @retval None
AnnaBridge	172:65be27845400	2879	*/
AnnaBridge	172:65be27845400	2880	__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
AnnaBridge	172:65be27845400	2881	{
AnnaBridge	172:65be27845400	2882	MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
AnnaBridge	172:65be27845400	2883	}
AnnaBridge	172:65be27845400	2884
AnnaBridge	172:65be27845400	2885	/**
AnnaBridge	172:65be27845400	2886	* @brief Get RTC Clock Source
AnnaBridge	172:65be27845400	2887	* @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
AnnaBridge	172:65be27845400	2888	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	2889	* @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
AnnaBridge	172:65be27845400	2890	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
AnnaBridge	172:65be27845400	2891	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
AnnaBridge	172:65be27845400	2892	* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
AnnaBridge	172:65be27845400	2893	*/
AnnaBridge	172:65be27845400	2894	__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
AnnaBridge	172:65be27845400	2895	{
AnnaBridge	172:65be27845400	2896	return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
AnnaBridge	172:65be27845400	2897	}
AnnaBridge	172:65be27845400	2898
AnnaBridge	172:65be27845400	2899	/**
AnnaBridge	172:65be27845400	2900	* @brief Enable RTC
AnnaBridge	172:65be27845400	2901	* @rmtoll BDCR RTCEN LL_RCC_EnableRTC
AnnaBridge	172:65be27845400	2902	* @retval None
AnnaBridge	172:65be27845400	2903	*/
AnnaBridge	172:65be27845400	2904	__STATIC_INLINE void LL_RCC_EnableRTC(void)
AnnaBridge	172:65be27845400	2905	{
AnnaBridge	172:65be27845400	2906	SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
AnnaBridge	172:65be27845400	2907	}
AnnaBridge	172:65be27845400	2908
AnnaBridge	172:65be27845400	2909	/**
AnnaBridge	172:65be27845400	2910	* @brief Disable RTC
AnnaBridge	172:65be27845400	2911	* @rmtoll BDCR RTCEN LL_RCC_DisableRTC
AnnaBridge	172:65be27845400	2912	* @retval None
AnnaBridge	172:65be27845400	2913	*/
AnnaBridge	172:65be27845400	2914	__STATIC_INLINE void LL_RCC_DisableRTC(void)
AnnaBridge	172:65be27845400	2915	{
AnnaBridge	172:65be27845400	2916	CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
AnnaBridge	172:65be27845400	2917	}
AnnaBridge	172:65be27845400	2918
AnnaBridge	172:65be27845400	2919	/**
AnnaBridge	172:65be27845400	2920	* @brief Check if RTC has been enabled or not
AnnaBridge	172:65be27845400	2921	* @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
AnnaBridge	172:65be27845400	2922	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	2923	*/
AnnaBridge	172:65be27845400	2924	__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
AnnaBridge	172:65be27845400	2925	{
AnnaBridge	172:65be27845400	2926	return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN))?1UL:0UL);
AnnaBridge	172:65be27845400	2927	}
AnnaBridge	172:65be27845400	2928
AnnaBridge	172:65be27845400	2929	/**
AnnaBridge	172:65be27845400	2930	* @brief Force the Backup domain reset
AnnaBridge	172:65be27845400	2931	* @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
AnnaBridge	172:65be27845400	2932	* @retval None
AnnaBridge	172:65be27845400	2933	*/
AnnaBridge	172:65be27845400	2934	__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
AnnaBridge	172:65be27845400	2935	{
AnnaBridge	172:65be27845400	2936	SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
AnnaBridge	172:65be27845400	2937	}
AnnaBridge	172:65be27845400	2938
AnnaBridge	172:65be27845400	2939	/**
AnnaBridge	172:65be27845400	2940	* @brief Release the Backup domain reset
AnnaBridge	172:65be27845400	2941	* @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
AnnaBridge	172:65be27845400	2942	* @retval None
AnnaBridge	172:65be27845400	2943	*/
AnnaBridge	172:65be27845400	2944	__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
AnnaBridge	172:65be27845400	2945	{
AnnaBridge	172:65be27845400	2946	CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
AnnaBridge	172:65be27845400	2947	}
AnnaBridge	172:65be27845400	2948
AnnaBridge	172:65be27845400	2949	/**
AnnaBridge	172:65be27845400	2950	* @brief Set HSE Prescalers for RTC Clock
AnnaBridge	172:65be27845400	2951	* @rmtoll CFGR RTCPRE LL_RCC_SetRTC_HSEPrescaler
AnnaBridge	172:65be27845400	2952	* @param Prescaler This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2953	* @arg @ref LL_RCC_RTC_NOCLOCK
AnnaBridge	172:65be27845400	2954	* @arg @ref LL_RCC_RTC_HSE_DIV_2
AnnaBridge	172:65be27845400	2955	* @arg @ref LL_RCC_RTC_HSE_DIV_3
AnnaBridge	172:65be27845400	2956	* @arg @ref LL_RCC_RTC_HSE_DIV_4
AnnaBridge	172:65be27845400	2957	* @arg @ref LL_RCC_RTC_HSE_DIV_5
AnnaBridge	172:65be27845400	2958	* @arg @ref LL_RCC_RTC_HSE_DIV_6
AnnaBridge	172:65be27845400	2959	* @arg @ref LL_RCC_RTC_HSE_DIV_7
AnnaBridge	172:65be27845400	2960	* @arg @ref LL_RCC_RTC_HSE_DIV_8
AnnaBridge	172:65be27845400	2961	* @arg @ref LL_RCC_RTC_HSE_DIV_9
AnnaBridge	172:65be27845400	2962	* @arg @ref LL_RCC_RTC_HSE_DIV_10
AnnaBridge	172:65be27845400	2963	* @arg @ref LL_RCC_RTC_HSE_DIV_11
AnnaBridge	172:65be27845400	2964	* @arg @ref LL_RCC_RTC_HSE_DIV_12
AnnaBridge	172:65be27845400	2965	* @arg @ref LL_RCC_RTC_HSE_DIV_13
AnnaBridge	172:65be27845400	2966	* @arg @ref LL_RCC_RTC_HSE_DIV_14
AnnaBridge	172:65be27845400	2967	* @arg @ref LL_RCC_RTC_HSE_DIV_15
AnnaBridge	172:65be27845400	2968	* @arg @ref LL_RCC_RTC_HSE_DIV_16
AnnaBridge	172:65be27845400	2969	* @arg @ref LL_RCC_RTC_HSE_DIV_17
AnnaBridge	172:65be27845400	2970	* @arg @ref LL_RCC_RTC_HSE_DIV_18
AnnaBridge	172:65be27845400	2971	* @arg @ref LL_RCC_RTC_HSE_DIV_19
AnnaBridge	172:65be27845400	2972	* @arg @ref LL_RCC_RTC_HSE_DIV_20
AnnaBridge	172:65be27845400	2973	* @arg @ref LL_RCC_RTC_HSE_DIV_21
AnnaBridge	172:65be27845400	2974	* @arg @ref LL_RCC_RTC_HSE_DIV_22
AnnaBridge	172:65be27845400	2975	* @arg @ref LL_RCC_RTC_HSE_DIV_23
AnnaBridge	172:65be27845400	2976	* @arg @ref LL_RCC_RTC_HSE_DIV_24
AnnaBridge	172:65be27845400	2977	* @arg @ref LL_RCC_RTC_HSE_DIV_25
AnnaBridge	172:65be27845400	2978	* @arg @ref LL_RCC_RTC_HSE_DIV_26
AnnaBridge	172:65be27845400	2979	* @arg @ref LL_RCC_RTC_HSE_DIV_27
AnnaBridge	172:65be27845400	2980	* @arg @ref LL_RCC_RTC_HSE_DIV_28
AnnaBridge	172:65be27845400	2981	* @arg @ref LL_RCC_RTC_HSE_DIV_29
AnnaBridge	172:65be27845400	2982	* @arg @ref LL_RCC_RTC_HSE_DIV_30
AnnaBridge	172:65be27845400	2983	* @arg @ref LL_RCC_RTC_HSE_DIV_31
AnnaBridge	172:65be27845400	2984	* @arg @ref LL_RCC_RTC_HSE_DIV_32
AnnaBridge	172:65be27845400	2985	* @arg @ref LL_RCC_RTC_HSE_DIV_33
AnnaBridge	172:65be27845400	2986	* @arg @ref LL_RCC_RTC_HSE_DIV_34
AnnaBridge	172:65be27845400	2987	* @arg @ref LL_RCC_RTC_HSE_DIV_35
AnnaBridge	172:65be27845400	2988	* @arg @ref LL_RCC_RTC_HSE_DIV_36
AnnaBridge	172:65be27845400	2989	* @arg @ref LL_RCC_RTC_HSE_DIV_37
AnnaBridge	172:65be27845400	2990	* @arg @ref LL_RCC_RTC_HSE_DIV_38
AnnaBridge	172:65be27845400	2991	* @arg @ref LL_RCC_RTC_HSE_DIV_39
AnnaBridge	172:65be27845400	2992	* @arg @ref LL_RCC_RTC_HSE_DIV_40
AnnaBridge	172:65be27845400	2993	* @arg @ref LL_RCC_RTC_HSE_DIV_41
AnnaBridge	172:65be27845400	2994	* @arg @ref LL_RCC_RTC_HSE_DIV_42
AnnaBridge	172:65be27845400	2995	* @arg @ref LL_RCC_RTC_HSE_DIV_43
AnnaBridge	172:65be27845400	2996	* @arg @ref LL_RCC_RTC_HSE_DIV_44
AnnaBridge	172:65be27845400	2997	* @arg @ref LL_RCC_RTC_HSE_DIV_45
AnnaBridge	172:65be27845400	2998	* @arg @ref LL_RCC_RTC_HSE_DIV_46
AnnaBridge	172:65be27845400	2999	* @arg @ref LL_RCC_RTC_HSE_DIV_47
AnnaBridge	172:65be27845400	3000	* @arg @ref LL_RCC_RTC_HSE_DIV_48
AnnaBridge	172:65be27845400	3001	* @arg @ref LL_RCC_RTC_HSE_DIV_49
AnnaBridge	172:65be27845400	3002	* @arg @ref LL_RCC_RTC_HSE_DIV_50
AnnaBridge	172:65be27845400	3003	* @arg @ref LL_RCC_RTC_HSE_DIV_51
AnnaBridge	172:65be27845400	3004	* @arg @ref LL_RCC_RTC_HSE_DIV_52
AnnaBridge	172:65be27845400	3005	* @arg @ref LL_RCC_RTC_HSE_DIV_53
AnnaBridge	172:65be27845400	3006	* @arg @ref LL_RCC_RTC_HSE_DIV_54
AnnaBridge	172:65be27845400	3007	* @arg @ref LL_RCC_RTC_HSE_DIV_55
AnnaBridge	172:65be27845400	3008	* @arg @ref LL_RCC_RTC_HSE_DIV_56
AnnaBridge	172:65be27845400	3009	* @arg @ref LL_RCC_RTC_HSE_DIV_57
AnnaBridge	172:65be27845400	3010	* @arg @ref LL_RCC_RTC_HSE_DIV_58
AnnaBridge	172:65be27845400	3011	* @arg @ref LL_RCC_RTC_HSE_DIV_59
AnnaBridge	172:65be27845400	3012	* @arg @ref LL_RCC_RTC_HSE_DIV_60
AnnaBridge	172:65be27845400	3013	* @arg @ref LL_RCC_RTC_HSE_DIV_61
AnnaBridge	172:65be27845400	3014	* @arg @ref LL_RCC_RTC_HSE_DIV_62
AnnaBridge	172:65be27845400	3015	* @arg @ref LL_RCC_RTC_HSE_DIV_63
AnnaBridge	172:65be27845400	3016	* @retval None
AnnaBridge	172:65be27845400	3017	*/
AnnaBridge	172:65be27845400	3018	__STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)
AnnaBridge	172:65be27845400	3019	{
AnnaBridge	172:65be27845400	3020	MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler);
AnnaBridge	172:65be27845400	3021	}
AnnaBridge	172:65be27845400	3022
AnnaBridge	172:65be27845400	3023	/**
AnnaBridge	172:65be27845400	3024	* @brief Get HSE Prescalers for RTC Clock
AnnaBridge	172:65be27845400	3025	* @rmtoll CFGR RTCPRE LL_RCC_GetRTC_HSEPrescaler
AnnaBridge	172:65be27845400	3026	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	3027	* @arg @ref LL_RCC_RTC_NOCLOCK
AnnaBridge	172:65be27845400	3028	* @arg @ref LL_RCC_RTC_HSE_DIV_2
AnnaBridge	172:65be27845400	3029	* @arg @ref LL_RCC_RTC_HSE_DIV_3
AnnaBridge	172:65be27845400	3030	* @arg @ref LL_RCC_RTC_HSE_DIV_4
AnnaBridge	172:65be27845400	3031	* @arg @ref LL_RCC_RTC_HSE_DIV_5
AnnaBridge	172:65be27845400	3032	* @arg @ref LL_RCC_RTC_HSE_DIV_6
AnnaBridge	172:65be27845400	3033	* @arg @ref LL_RCC_RTC_HSE_DIV_7
AnnaBridge	172:65be27845400	3034	* @arg @ref LL_RCC_RTC_HSE_DIV_8
AnnaBridge	172:65be27845400	3035	* @arg @ref LL_RCC_RTC_HSE_DIV_9
AnnaBridge	172:65be27845400	3036	* @arg @ref LL_RCC_RTC_HSE_DIV_10
AnnaBridge	172:65be27845400	3037	* @arg @ref LL_RCC_RTC_HSE_DIV_11
AnnaBridge	172:65be27845400	3038	* @arg @ref LL_RCC_RTC_HSE_DIV_12
AnnaBridge	172:65be27845400	3039	* @arg @ref LL_RCC_RTC_HSE_DIV_13
AnnaBridge	172:65be27845400	3040	* @arg @ref LL_RCC_RTC_HSE_DIV_14
AnnaBridge	172:65be27845400	3041	* @arg @ref LL_RCC_RTC_HSE_DIV_15
AnnaBridge	172:65be27845400	3042	* @arg @ref LL_RCC_RTC_HSE_DIV_16
AnnaBridge	172:65be27845400	3043	* @arg @ref LL_RCC_RTC_HSE_DIV_17
AnnaBridge	172:65be27845400	3044	* @arg @ref LL_RCC_RTC_HSE_DIV_18
AnnaBridge	172:65be27845400	3045	* @arg @ref LL_RCC_RTC_HSE_DIV_19
AnnaBridge	172:65be27845400	3046	* @arg @ref LL_RCC_RTC_HSE_DIV_20
AnnaBridge	172:65be27845400	3047	* @arg @ref LL_RCC_RTC_HSE_DIV_21
AnnaBridge	172:65be27845400	3048	* @arg @ref LL_RCC_RTC_HSE_DIV_22
AnnaBridge	172:65be27845400	3049	* @arg @ref LL_RCC_RTC_HSE_DIV_23
AnnaBridge	172:65be27845400	3050	* @arg @ref LL_RCC_RTC_HSE_DIV_24
AnnaBridge	172:65be27845400	3051	* @arg @ref LL_RCC_RTC_HSE_DIV_25
AnnaBridge	172:65be27845400	3052	* @arg @ref LL_RCC_RTC_HSE_DIV_26
AnnaBridge	172:65be27845400	3053	* @arg @ref LL_RCC_RTC_HSE_DIV_27
AnnaBridge	172:65be27845400	3054	* @arg @ref LL_RCC_RTC_HSE_DIV_28
AnnaBridge	172:65be27845400	3055	* @arg @ref LL_RCC_RTC_HSE_DIV_29
AnnaBridge	172:65be27845400	3056	* @arg @ref LL_RCC_RTC_HSE_DIV_30
AnnaBridge	172:65be27845400	3057	* @arg @ref LL_RCC_RTC_HSE_DIV_31
AnnaBridge	172:65be27845400	3058	* @arg @ref LL_RCC_RTC_HSE_DIV_32
AnnaBridge	172:65be27845400	3059	* @arg @ref LL_RCC_RTC_HSE_DIV_33
AnnaBridge	172:65be27845400	3060	* @arg @ref LL_RCC_RTC_HSE_DIV_34
AnnaBridge	172:65be27845400	3061	* @arg @ref LL_RCC_RTC_HSE_DIV_35
AnnaBridge	172:65be27845400	3062	* @arg @ref LL_RCC_RTC_HSE_DIV_36
AnnaBridge	172:65be27845400	3063	* @arg @ref LL_RCC_RTC_HSE_DIV_37
AnnaBridge	172:65be27845400	3064	* @arg @ref LL_RCC_RTC_HSE_DIV_38
AnnaBridge	172:65be27845400	3065	* @arg @ref LL_RCC_RTC_HSE_DIV_39
AnnaBridge	172:65be27845400	3066	* @arg @ref LL_RCC_RTC_HSE_DIV_40
AnnaBridge	172:65be27845400	3067	* @arg @ref LL_RCC_RTC_HSE_DIV_41
AnnaBridge	172:65be27845400	3068	* @arg @ref LL_RCC_RTC_HSE_DIV_42
AnnaBridge	172:65be27845400	3069	* @arg @ref LL_RCC_RTC_HSE_DIV_43
AnnaBridge	172:65be27845400	3070	* @arg @ref LL_RCC_RTC_HSE_DIV_44
AnnaBridge	172:65be27845400	3071	* @arg @ref LL_RCC_RTC_HSE_DIV_45
AnnaBridge	172:65be27845400	3072	* @arg @ref LL_RCC_RTC_HSE_DIV_46
AnnaBridge	172:65be27845400	3073	* @arg @ref LL_RCC_RTC_HSE_DIV_47
AnnaBridge	172:65be27845400	3074	* @arg @ref LL_RCC_RTC_HSE_DIV_48
AnnaBridge	172:65be27845400	3075	* @arg @ref LL_RCC_RTC_HSE_DIV_49
AnnaBridge	172:65be27845400	3076	* @arg @ref LL_RCC_RTC_HSE_DIV_50
AnnaBridge	172:65be27845400	3077	* @arg @ref LL_RCC_RTC_HSE_DIV_51
AnnaBridge	172:65be27845400	3078	* @arg @ref LL_RCC_RTC_HSE_DIV_52
AnnaBridge	172:65be27845400	3079	* @arg @ref LL_RCC_RTC_HSE_DIV_53
AnnaBridge	172:65be27845400	3080	* @arg @ref LL_RCC_RTC_HSE_DIV_54
AnnaBridge	172:65be27845400	3081	* @arg @ref LL_RCC_RTC_HSE_DIV_55
AnnaBridge	172:65be27845400	3082	* @arg @ref LL_RCC_RTC_HSE_DIV_56
AnnaBridge	172:65be27845400	3083	* @arg @ref LL_RCC_RTC_HSE_DIV_57
AnnaBridge	172:65be27845400	3084	* @arg @ref LL_RCC_RTC_HSE_DIV_58
AnnaBridge	172:65be27845400	3085	* @arg @ref LL_RCC_RTC_HSE_DIV_59
AnnaBridge	172:65be27845400	3086	* @arg @ref LL_RCC_RTC_HSE_DIV_60
AnnaBridge	172:65be27845400	3087	* @arg @ref LL_RCC_RTC_HSE_DIV_61
AnnaBridge	172:65be27845400	3088	* @arg @ref LL_RCC_RTC_HSE_DIV_62
AnnaBridge	172:65be27845400	3089	* @arg @ref LL_RCC_RTC_HSE_DIV_63
AnnaBridge	172:65be27845400	3090	*/
AnnaBridge	172:65be27845400	3091	__STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
AnnaBridge	172:65be27845400	3092	{
AnnaBridge	172:65be27845400	3093	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE));
AnnaBridge	172:65be27845400	3094	}
AnnaBridge	172:65be27845400	3095
AnnaBridge	172:65be27845400	3096	/**
AnnaBridge	172:65be27845400	3097	* @}
AnnaBridge	172:65be27845400	3098	*/
AnnaBridge	172:65be27845400	3099
AnnaBridge	172:65be27845400	3100	/** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM
AnnaBridge	172:65be27845400	3101	* @{
AnnaBridge	172:65be27845400	3102	*/
AnnaBridge	172:65be27845400	3103
AnnaBridge	172:65be27845400	3104	/**
AnnaBridge	172:65be27845400	3105	* @brief Set Timers Clock Prescalers
AnnaBridge	172:65be27845400	3106	* @rmtoll CFGR TIMPRE LL_RCC_SetTIMPrescaler
AnnaBridge	172:65be27845400	3107	* @param Prescaler This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3108	* @arg @ref LL_RCC_TIM_PRESCALER_TWICE
AnnaBridge	172:65be27845400	3109	* @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
AnnaBridge	172:65be27845400	3110	* @retval None
AnnaBridge	172:65be27845400	3111	*/
AnnaBridge	172:65be27845400	3112	__STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler)
AnnaBridge	172:65be27845400	3113	{
AnnaBridge	172:65be27845400	3114	MODIFY_REG(RCC->CFGR, RCC_CFGR_TIMPRE, Prescaler);
AnnaBridge	172:65be27845400	3115	}
AnnaBridge	172:65be27845400	3116
AnnaBridge	172:65be27845400	3117	/**
AnnaBridge	172:65be27845400	3118	* @brief Get Timers Clock Prescalers
AnnaBridge	172:65be27845400	3119	* @rmtoll CFGR TIMPRE LL_RCC_GetTIMPrescaler
AnnaBridge	172:65be27845400	3120	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	3121	* @arg @ref LL_RCC_TIM_PRESCALER_TWICE
AnnaBridge	172:65be27845400	3122	* @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
AnnaBridge	172:65be27845400	3123	*/
AnnaBridge	172:65be27845400	3124	__STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void)
AnnaBridge	172:65be27845400	3125	{
AnnaBridge	172:65be27845400	3126	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_TIMPRE));
AnnaBridge	172:65be27845400	3127	}
AnnaBridge	172:65be27845400	3128
AnnaBridge	172:65be27845400	3129	/**
AnnaBridge	172:65be27845400	3130	* @}
AnnaBridge	172:65be27845400	3131	*/
AnnaBridge	172:65be27845400	3132
AnnaBridge	172:65be27845400	3133	/** @defgroup RCC_LL_EF_HRTIM_SET_CLOCK_SOURCE HRTIM
AnnaBridge	172:65be27845400	3134	* @{
AnnaBridge	172:65be27845400	3135	*/
AnnaBridge	172:65be27845400	3136
AnnaBridge	172:65be27845400	3137	/**
AnnaBridge	172:65be27845400	3138	* @brief Set High Resolution Timers Clock Source
AnnaBridge	172:65be27845400	3139	* @rmtoll CFGR HRTIMSEL LL_RCC_SetHRTIMClockSource
AnnaBridge	172:65be27845400	3140	* @param Prescaler This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3141	* @arg @ref LL_RCC_HRTIM_CLKSOURCE_TIM
AnnaBridge	172:65be27845400	3142	* @arg @ref LL_RCC_HRTIM_CLKSOURCE_CPU
AnnaBridge	172:65be27845400	3143	* @retval None
AnnaBridge	172:65be27845400	3144	*/
AnnaBridge	172:65be27845400	3145	__STATIC_INLINE void LL_RCC_SetHRTIMClockSource(uint32_t Prescaler)
AnnaBridge	172:65be27845400	3146	{
AnnaBridge	172:65be27845400	3147	MODIFY_REG(RCC->CFGR, RCC_CFGR_HRTIMSEL, Prescaler);
AnnaBridge	172:65be27845400	3148	}
AnnaBridge	172:65be27845400	3149
AnnaBridge	172:65be27845400	3150	/**
AnnaBridge	172:65be27845400	3151	* @brief Get High Resolution Timers Clock Source
AnnaBridge	172:65be27845400	3152	* @rmtoll CFGR HRTIMSEL LL_RCC_GetHRTIMClockSource
AnnaBridge	172:65be27845400	3153	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	3154	* @arg @ref LL_RCC_HRTIM_CLKSOURCE_TIM
AnnaBridge	172:65be27845400	3155	* @arg @ref LL_RCC_HRTIM_CLKSOURCE_CPU
AnnaBridge	172:65be27845400	3156	*/
AnnaBridge	172:65be27845400	3157	__STATIC_INLINE uint32_t LL_RCC_GetHRTIMClockSource(void)
AnnaBridge	172:65be27845400	3158	{
AnnaBridge	172:65be27845400	3159	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HRTIMSEL));
AnnaBridge	172:65be27845400	3160	}
AnnaBridge	172:65be27845400	3161
AnnaBridge	172:65be27845400	3162	/**
AnnaBridge	172:65be27845400	3163	* @}
AnnaBridge	172:65be27845400	3164	*/
AnnaBridge	172:65be27845400	3165
AnnaBridge	172:65be27845400	3166	/** @defgroup RCC_LL_EF_PLL PLL
AnnaBridge	172:65be27845400	3167	* @{
AnnaBridge	172:65be27845400	3168	*/
AnnaBridge	172:65be27845400	3169
AnnaBridge	172:65be27845400	3170	/**
AnnaBridge	172:65be27845400	3171	* @brief Set the oscillator used as PLL clock source.
AnnaBridge	172:65be27845400	3172	* @note PLLSRC can be written only when All PLLs are disabled.
AnnaBridge	172:65be27845400	3173	* @rmtoll PLLCKSELR PLLSRC LL_RCC_PLL_SetSource
AnnaBridge	172:65be27845400	3174	* @param PLLSource parameter can be one of the following values:
AnnaBridge	172:65be27845400	3175	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	172:65be27845400	3176	* @arg @ref LL_RCC_PLLSOURCE_CSI
AnnaBridge	172:65be27845400	3177	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	172:65be27845400	3178	* @arg @ref LL_RCC_PLLSOURCE_NONE
AnnaBridge	172:65be27845400	3179	* @retval None
AnnaBridge	172:65be27845400	3180	*/
AnnaBridge	172:65be27845400	3181	__STATIC_INLINE void LL_RCC_PLL_SetSource(uint32_t PLLSource)
AnnaBridge	172:65be27845400	3182	{
AnnaBridge	172:65be27845400	3183	MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, PLLSource);
AnnaBridge	172:65be27845400	3184	}
AnnaBridge	172:65be27845400	3185
AnnaBridge	172:65be27845400	3186	/**
AnnaBridge	172:65be27845400	3187	* @brief Get the oscillator used as PLL clock source.
AnnaBridge	172:65be27845400	3188	* @rmtoll PLLCKSELR PLLSRC LL_RCC_PLL_GetSource
AnnaBridge	172:65be27845400	3189	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	3190	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	172:65be27845400	3191	* @arg @ref LL_RCC_PLLSOURCE_CSI
AnnaBridge	172:65be27845400	3192	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	172:65be27845400	3193	* @arg @ref LL_RCC_PLLSOURCE_NONE
AnnaBridge	172:65be27845400	3194	*/
AnnaBridge	172:65be27845400	3195	__STATIC_INLINE uint32_t LL_RCC_PLL_GetSource(void)
AnnaBridge	172:65be27845400	3196	{
AnnaBridge	172:65be27845400	3197	return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC));
AnnaBridge	172:65be27845400	3198	}
AnnaBridge	172:65be27845400	3199
AnnaBridge	172:65be27845400	3200	/**
AnnaBridge	172:65be27845400	3201	* @brief Enable PLL1
AnnaBridge	172:65be27845400	3202	* @rmtoll CR PLL1ON LL_RCC_PLL1_Enable
AnnaBridge	172:65be27845400	3203	* @retval None
AnnaBridge	172:65be27845400	3204	*/
AnnaBridge	172:65be27845400	3205	__STATIC_INLINE void LL_RCC_PLL1_Enable(void)
AnnaBridge	172:65be27845400	3206	{
AnnaBridge	172:65be27845400	3207	SET_BIT(RCC->CR, RCC_CR_PLL1ON);
AnnaBridge	172:65be27845400	3208	}
AnnaBridge	172:65be27845400	3209
AnnaBridge	172:65be27845400	3210	/**
AnnaBridge	172:65be27845400	3211	* @brief Disable PLL1
AnnaBridge	172:65be27845400	3212	* @note Cannot be disabled if the PLL1 clock is used as the system clock
AnnaBridge	172:65be27845400	3213	* @rmtoll CR PLL1ON LL_RCC_PLL1_Disable
AnnaBridge	172:65be27845400	3214	* @retval None
AnnaBridge	172:65be27845400	3215	*/
AnnaBridge	172:65be27845400	3216	__STATIC_INLINE void LL_RCC_PLL1_Disable(void)
AnnaBridge	172:65be27845400	3217	{
AnnaBridge	172:65be27845400	3218	CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON);
AnnaBridge	172:65be27845400	3219	}
AnnaBridge	172:65be27845400	3220
AnnaBridge	172:65be27845400	3221	/**
AnnaBridge	172:65be27845400	3222	* @brief Check if PLL1 Ready
AnnaBridge	172:65be27845400	3223	* @rmtoll CR PLL1RDY LL_RCC_PLL1_IsReady
AnnaBridge	172:65be27845400	3224	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	3225	*/
AnnaBridge	172:65be27845400	3226	__STATIC_INLINE uint32_t LL_RCC_PLL1_IsReady(void)
AnnaBridge	172:65be27845400	3227	{
AnnaBridge	172:65be27845400	3228	return ((READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == (RCC_CR_PLL1RDY))?1UL:0UL);
AnnaBridge	172:65be27845400	3229	}
AnnaBridge	172:65be27845400	3230
AnnaBridge	172:65be27845400	3231	/**
AnnaBridge	172:65be27845400	3232	* @brief Enable PLL1P
AnnaBridge	172:65be27845400	3233	* @note This API shall be called only when PLL1 is disabled.
AnnaBridge	172:65be27845400	3234	* @rmtoll PLLCFGR DIVP1EN LL_RCC_PLL1P_Enable
AnnaBridge	172:65be27845400	3235	* @retval None
AnnaBridge	172:65be27845400	3236	*/
AnnaBridge	172:65be27845400	3237	__STATIC_INLINE void LL_RCC_PLL1P_Enable(void)
AnnaBridge	172:65be27845400	3238	{
AnnaBridge	172:65be27845400	3239	SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN);
AnnaBridge	172:65be27845400	3240	}
AnnaBridge	172:65be27845400	3241
AnnaBridge	172:65be27845400	3242	/**
AnnaBridge	172:65be27845400	3243	* @brief Enable PLL1Q
AnnaBridge	172:65be27845400	3244	* @note This API shall be called only when PLL1 is disabled.
AnnaBridge	172:65be27845400	3245	* @rmtoll PLLCFGR DIVQ1EN LL_RCC_PLL1Q_Enable
AnnaBridge	172:65be27845400	3246	* @retval None
AnnaBridge	172:65be27845400	3247	*/
AnnaBridge	172:65be27845400	3248	__STATIC_INLINE void LL_RCC_PLL1Q_Enable(void)
AnnaBridge	172:65be27845400	3249	{
AnnaBridge	172:65be27845400	3250	SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN);
AnnaBridge	172:65be27845400	3251	}
AnnaBridge	172:65be27845400	3252
AnnaBridge	172:65be27845400	3253	/**
AnnaBridge	172:65be27845400	3254	* @brief Enable PLL1R
AnnaBridge	172:65be27845400	3255	* @note This API shall be called only when PLL1 is disabled.
AnnaBridge	172:65be27845400	3256	* @rmtoll PLLCFGR DIVR1EN LL_RCC_PLL1R_Enable
AnnaBridge	172:65be27845400	3257	* @retval None
AnnaBridge	172:65be27845400	3258	*/
AnnaBridge	172:65be27845400	3259	__STATIC_INLINE void LL_RCC_PLL1R_Enable(void)
AnnaBridge	172:65be27845400	3260	{
AnnaBridge	172:65be27845400	3261	SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN);
AnnaBridge	172:65be27845400	3262	}
AnnaBridge	172:65be27845400	3263
AnnaBridge	172:65be27845400	3264	/**
AnnaBridge	172:65be27845400	3265	* @brief Enable PLL1 FRACN
AnnaBridge	172:65be27845400	3266	* @rmtoll PLLCFGR PLL1FRACEN LL_RCC_PLL1FRACN_Enable
AnnaBridge	172:65be27845400	3267	* @retval None
AnnaBridge	172:65be27845400	3268	*/
AnnaBridge	172:65be27845400	3269	__STATIC_INLINE void LL_RCC_PLL1FRACN_Enable(void)
AnnaBridge	172:65be27845400	3270	{
AnnaBridge	172:65be27845400	3271	SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN);
AnnaBridge	172:65be27845400	3272	}
AnnaBridge	172:65be27845400	3273
AnnaBridge	172:65be27845400	3274	/**
AnnaBridge	172:65be27845400	3275	* @brief Check if PLL1 P is enabled
AnnaBridge	172:65be27845400	3276	* @rmtoll PLLCFGR DIVP1EN LL_RCC_PLL1P_IsEnabled
AnnaBridge	172:65be27845400	3277	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	3278	*/
AnnaBridge	172:65be27845400	3279	__STATIC_INLINE uint32_t LL_RCC_PLL1P_IsEnabled(void)
AnnaBridge	172:65be27845400	3280	{
AnnaBridge	172:65be27845400	3281	return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN) == RCC_PLLCFGR_DIVP1EN)?1UL:0UL);
AnnaBridge	172:65be27845400	3282	}
AnnaBridge	172:65be27845400	3283
AnnaBridge	172:65be27845400	3284	/**
AnnaBridge	172:65be27845400	3285	* @brief Check if PLL1 Q is enabled
AnnaBridge	172:65be27845400	3286	* @rmtoll PLLCFGR DIVQ1EN LL_RCC_PLL1Q_IsEnabled
AnnaBridge	172:65be27845400	3287	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	3288	*/
AnnaBridge	172:65be27845400	3289	__STATIC_INLINE uint32_t LL_RCC_PLL1Q_IsEnabled(void)
AnnaBridge	172:65be27845400	3290	{
AnnaBridge	172:65be27845400	3291	return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN) == RCC_PLLCFGR_DIVQ1EN)?1UL:0UL);
AnnaBridge	172:65be27845400	3292	}
AnnaBridge	172:65be27845400	3293
AnnaBridge	172:65be27845400	3294	/**
AnnaBridge	172:65be27845400	3295	* @brief Check if PLL1 R is enabled
AnnaBridge	172:65be27845400	3296	* @rmtoll PLLCFGR DIVR1EN LL_RCC_PLL1R_IsEnabled
AnnaBridge	172:65be27845400	3297	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	3298	*/
AnnaBridge	172:65be27845400	3299	__STATIC_INLINE uint32_t LL_RCC_PLL1R_IsEnabled(void)
AnnaBridge	172:65be27845400	3300	{
AnnaBridge	172:65be27845400	3301	return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN) == RCC_PLLCFGR_DIVR1EN)?1UL:0UL);
AnnaBridge	172:65be27845400	3302	}
AnnaBridge	172:65be27845400	3303
AnnaBridge	172:65be27845400	3304	/**
AnnaBridge	172:65be27845400	3305	* @brief Check if PLL1 FRACN is enabled
AnnaBridge	172:65be27845400	3306	* @rmtoll PLLCFGR PLL1FRACEN LL_RCC_PLL1FRACN_IsEnabled
AnnaBridge	172:65be27845400	3307	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	3308	*/
AnnaBridge	172:65be27845400	3309	__STATIC_INLINE uint32_t LL_RCC_PLL1FRACN_IsEnabled(void)
AnnaBridge	172:65be27845400	3310	{
AnnaBridge	172:65be27845400	3311	return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN) == RCC_PLLCFGR_PLL1FRACEN)?1UL:0UL);
AnnaBridge	172:65be27845400	3312	}
AnnaBridge	172:65be27845400	3313
AnnaBridge	172:65be27845400	3314	/**
AnnaBridge	172:65be27845400	3315	* @brief Disable PLL1P
AnnaBridge	172:65be27845400	3316	* @note This API shall be called only when PLL1 is disabled.
AnnaBridge	172:65be27845400	3317	* @rmtoll PLLCFGR DIVP1EN LL_RCC_PLL1P_Disable
AnnaBridge	172:65be27845400	3318	* @retval None
AnnaBridge	172:65be27845400	3319	*/
AnnaBridge	172:65be27845400	3320	__STATIC_INLINE void LL_RCC_PLL1P_Disable(void)
AnnaBridge	172:65be27845400	3321	{
AnnaBridge	172:65be27845400	3322	CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN);
AnnaBridge	172:65be27845400	3323	}
AnnaBridge	172:65be27845400	3324
AnnaBridge	172:65be27845400	3325	/**
AnnaBridge	172:65be27845400	3326	* @brief Disable PLL1Q
AnnaBridge	172:65be27845400	3327	* @note This API shall be called only when PLL1 is disabled.
AnnaBridge	172:65be27845400	3328	* @rmtoll PLLCFGR DIVQ1EN LL_RCC_PLL1Q_Disable
AnnaBridge	172:65be27845400	3329	* @retval None
AnnaBridge	172:65be27845400	3330	*/
AnnaBridge	172:65be27845400	3331	__STATIC_INLINE void LL_RCC_PLL1Q_Disable(void)
AnnaBridge	172:65be27845400	3332	{
AnnaBridge	172:65be27845400	3333	CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN);
AnnaBridge	172:65be27845400	3334	}
AnnaBridge	172:65be27845400	3335
AnnaBridge	172:65be27845400	3336	/**
AnnaBridge	172:65be27845400	3337	* @brief Disable PLL1R
AnnaBridge	172:65be27845400	3338	* @note This API shall be called only when PLL1 is disabled.
AnnaBridge	172:65be27845400	3339	* @rmtoll PLLCFGR DIVR1EN LL_RCC_PLL1R_Disable
AnnaBridge	172:65be27845400	3340	* @retval None
AnnaBridge	172:65be27845400	3341	*/
AnnaBridge	172:65be27845400	3342	__STATIC_INLINE void LL_RCC_PLL1R_Disable(void)
AnnaBridge	172:65be27845400	3343	{
AnnaBridge	172:65be27845400	3344	CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN);
AnnaBridge	172:65be27845400	3345	}
AnnaBridge	172:65be27845400	3346
AnnaBridge	172:65be27845400	3347	/**
AnnaBridge	172:65be27845400	3348	* @brief Disable PLL1 FRACN
AnnaBridge	172:65be27845400	3349	* @rmtoll PLLCFGR PLL1FRACEN LL_RCC_PLL1FRACN_Enable
AnnaBridge	172:65be27845400	3350	* @retval None
AnnaBridge	172:65be27845400	3351	*/
AnnaBridge	172:65be27845400	3352	__STATIC_INLINE void LL_RCC_PLL1FRACN_Disable(void)
AnnaBridge	172:65be27845400	3353	{
AnnaBridge	172:65be27845400	3354	CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN);
AnnaBridge	172:65be27845400	3355	}
AnnaBridge	172:65be27845400	3356
AnnaBridge	172:65be27845400	3357	/**
AnnaBridge	172:65be27845400	3358	* @brief Set PLL1 VCO OutputRange
AnnaBridge	172:65be27845400	3359	* @note This API shall be called only when PLL1 is disabled.
AnnaBridge	172:65be27845400	3360	* @rmtoll PLLCFGR PLL1VCOSEL LL_RCC_PLL1_SetVCOOuputRange
AnnaBridge	172:65be27845400	3361	* @param VCORange This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3362	* @arg @ref LL_RCC_PLLVCORANGE_WIDE
AnnaBridge	172:65be27845400	3363	* @arg @ref LL_RCC_PLLVCORANGE_MEDIUM
AnnaBridge	172:65be27845400	3364	* @retval None
AnnaBridge	172:65be27845400	3365	*/
AnnaBridge	172:65be27845400	3366	__STATIC_INLINE void LL_RCC_PLL1_SetVCOOutputRange(uint32_t VCORange)
AnnaBridge	172:65be27845400	3367	{
AnnaBridge	172:65be27845400	3368	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, VCORange << RCC_PLLCFGR_PLL1VCOSEL_Pos);
AnnaBridge	172:65be27845400	3369	}
AnnaBridge	172:65be27845400	3370
AnnaBridge	172:65be27845400	3371	/**
AnnaBridge	172:65be27845400	3372	* @brief Set PLL1 VCO Input Range
AnnaBridge	172:65be27845400	3373	* @note This API shall be called only when PLL1 is disabled.
AnnaBridge	172:65be27845400	3374	* @rmtoll PLLCFGR PLL1RGE LL_RCC_PLL1_SetVCOInputRange
AnnaBridge	172:65be27845400	3375	* @param InputRange This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3376	* @arg @ref LL_RCC_PLLINPUTRANGE_1_2
AnnaBridge	172:65be27845400	3377	* @arg @ref LL_RCC_PLLINPUTRANGE_2_4
AnnaBridge	172:65be27845400	3378	* @arg @ref LL_RCC_PLLINPUTRANGE_4_8
AnnaBridge	172:65be27845400	3379	* @arg @ref LL_RCC_PLLINPUTRANGE_8_16
AnnaBridge	172:65be27845400	3380	* @retval None
AnnaBridge	172:65be27845400	3381	*/
AnnaBridge	172:65be27845400	3382	__STATIC_INLINE void LL_RCC_PLL1_SetVCOInputRange(uint32_t InputRange)
AnnaBridge	172:65be27845400	3383	{
AnnaBridge	172:65be27845400	3384	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, InputRange << RCC_PLLCFGR_PLL1RGE_Pos);
AnnaBridge	172:65be27845400	3385	}
AnnaBridge	172:65be27845400	3386
AnnaBridge	172:65be27845400	3387	/**
AnnaBridge	172:65be27845400	3388	* @brief Get PLL1 N Coefficient
AnnaBridge	172:65be27845400	3389	* @rmtoll PLL1DIVR N1 LL_RCC_PLL1_GetN
AnnaBridge	172:65be27845400	3390	* @retval A value between 4 and 512
AnnaBridge	172:65be27845400	3391	*/
AnnaBridge	172:65be27845400	3392	__STATIC_INLINE uint32_t LL_RCC_PLL1_GetN(void)
AnnaBridge	172:65be27845400	3393	{
AnnaBridge	172:65be27845400	3394	return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_N1) >> RCC_PLL1DIVR_N1_Pos) + 1UL);
AnnaBridge	172:65be27845400	3395	}
AnnaBridge	172:65be27845400	3396
AnnaBridge	172:65be27845400	3397	/**
AnnaBridge	172:65be27845400	3398	* @brief Get PLL1 M Coefficient
AnnaBridge	172:65be27845400	3399	* @rmtoll PLLCKSELR DIVM1 LL_RCC_PLL1_GetM
AnnaBridge	172:65be27845400	3400	* @retval A value between 0 and 63
AnnaBridge	172:65be27845400	3401	*/
AnnaBridge	172:65be27845400	3402	__STATIC_INLINE uint32_t LL_RCC_PLL1_GetM(void)
AnnaBridge	172:65be27845400	3403	{
AnnaBridge	172:65be27845400	3404	return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos);
AnnaBridge	172:65be27845400	3405	}
AnnaBridge	172:65be27845400	3406
AnnaBridge	172:65be27845400	3407	/**
AnnaBridge	172:65be27845400	3408	* @brief Get PLL1 P Coefficient
AnnaBridge	172:65be27845400	3409	* @rmtoll PLL1DIVR P1 LL_RCC_PLL1_GetP
AnnaBridge	172:65be27845400	3410	* @retval A value between 2 and 128
AnnaBridge	172:65be27845400	3411	*/
AnnaBridge	172:65be27845400	3412	__STATIC_INLINE uint32_t LL_RCC_PLL1_GetP(void)
AnnaBridge	172:65be27845400	3413	{
AnnaBridge	172:65be27845400	3414	return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) + 1UL);
AnnaBridge	172:65be27845400	3415	}
AnnaBridge	172:65be27845400	3416
AnnaBridge	172:65be27845400	3417	/**
AnnaBridge	172:65be27845400	3418	* @brief Get PLL1 Q Coefficient
AnnaBridge	172:65be27845400	3419	* @rmtoll PLL1DIVR Q1 LL_RCC_PLL1_GetQ
AnnaBridge	172:65be27845400	3420	* @retval A value between 1 and 128
AnnaBridge	172:65be27845400	3421	*/
AnnaBridge	172:65be27845400	3422	__STATIC_INLINE uint32_t LL_RCC_PLL1_GetQ(void)
AnnaBridge	172:65be27845400	3423	{
AnnaBridge	172:65be27845400	3424	return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) + 1UL);
AnnaBridge	172:65be27845400	3425	}
AnnaBridge	172:65be27845400	3426
AnnaBridge	172:65be27845400	3427	/**
AnnaBridge	172:65be27845400	3428	* @brief Get PLL1 R Coefficient
AnnaBridge	172:65be27845400	3429	* @rmtoll PLL1DIVR R1 LL_RCC_PLL1_GetR
AnnaBridge	172:65be27845400	3430	* @retval A value between 1 and 128
AnnaBridge	172:65be27845400	3431	*/
AnnaBridge	172:65be27845400	3432	__STATIC_INLINE uint32_t LL_RCC_PLL1_GetR(void)
AnnaBridge	172:65be27845400	3433	{
AnnaBridge	172:65be27845400	3434	return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) + 1UL);
AnnaBridge	172:65be27845400	3435	}
AnnaBridge	172:65be27845400	3436
AnnaBridge	172:65be27845400	3437	/**
AnnaBridge	172:65be27845400	3438	* @brief Get PLL1 FRACN Coefficient
AnnaBridge	172:65be27845400	3439	* @rmtoll PLL1FRACR FRACN1 LL_RCC_PLL1_GetFRACN
AnnaBridge	172:65be27845400	3440	* @retval A value between 0 and 8191 (0x1FFF)
AnnaBridge	172:65be27845400	3441	*/
AnnaBridge	172:65be27845400	3442	__STATIC_INLINE uint32_t LL_RCC_PLL1_GetFRACN(void)
AnnaBridge	172:65be27845400	3443	{
AnnaBridge	172:65be27845400	3444	return (uint32_t)(READ_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos);
AnnaBridge	172:65be27845400	3445	}
AnnaBridge	172:65be27845400	3446
AnnaBridge	172:65be27845400	3447	/**
AnnaBridge	172:65be27845400	3448	* @brief Set PLL1 N Coefficient
AnnaBridge	172:65be27845400	3449	* @note This API shall be called only when PLL1 is disabled.
AnnaBridge	172:65be27845400	3450	* @rmtoll PLL1DIVR N1 LL_RCC_PLL1_SetN
AnnaBridge	172:65be27845400	3451	* @param N parameter can be a value between 4 and 512
AnnaBridge	172:65be27845400	3452	*/
AnnaBridge	172:65be27845400	3453	__STATIC_INLINE void LL_RCC_PLL1_SetN(uint32_t N)
AnnaBridge	172:65be27845400	3454	{
AnnaBridge	172:65be27845400	3455	MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_N1, (N-1UL) << RCC_PLL1DIVR_N1_Pos);
AnnaBridge	172:65be27845400	3456	}
AnnaBridge	172:65be27845400	3457
AnnaBridge	172:65be27845400	3458	/**
AnnaBridge	172:65be27845400	3459	* @brief Set PLL1 M Coefficient
AnnaBridge	172:65be27845400	3460	* @note This API shall be called only when PLL1 is disabled.
AnnaBridge	172:65be27845400	3461	* @rmtoll PLLCKSELR DIVM1 LL_RCC_PLL1_SetM
AnnaBridge	172:65be27845400	3462	* @param M parameter can be a value between 0 and 63
AnnaBridge	172:65be27845400	3463	*/
AnnaBridge	172:65be27845400	3464	__STATIC_INLINE void LL_RCC_PLL1_SetM(uint32_t M)
AnnaBridge	172:65be27845400	3465	{
AnnaBridge	172:65be27845400	3466	MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM1, M << RCC_PLLCKSELR_DIVM1_Pos);
AnnaBridge	172:65be27845400	3467	}
AnnaBridge	172:65be27845400	3468
AnnaBridge	172:65be27845400	3469	/**
AnnaBridge	172:65be27845400	3470	* @brief Set PLL1 P Coefficient
AnnaBridge	172:65be27845400	3471	* @note This API shall be called only when PLL1 is disabled.
AnnaBridge	172:65be27845400	3472	* @rmtoll PLL1DIVR P1 LL_RCC_PLL1_SetP
AnnaBridge	172:65be27845400	3473	* @param P parameter can be a value between 2 and 128 (ODD division factor not supportted)
AnnaBridge	172:65be27845400	3474	*/
AnnaBridge	172:65be27845400	3475	__STATIC_INLINE void LL_RCC_PLL1_SetP(uint32_t P)
AnnaBridge	172:65be27845400	3476	{
AnnaBridge	172:65be27845400	3477	MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_P1, (P-1UL) << RCC_PLL1DIVR_P1_Pos);
AnnaBridge	172:65be27845400	3478	}
AnnaBridge	172:65be27845400	3479
AnnaBridge	172:65be27845400	3480	/**
AnnaBridge	172:65be27845400	3481	* @brief Set PLL1 Q Coefficient
AnnaBridge	172:65be27845400	3482	* @note This API shall be called only when PLL1 is disabled.
AnnaBridge	172:65be27845400	3483	* @rmtoll PLL1DIVR Q1 LL_RCC_PLL1_SetQ
AnnaBridge	172:65be27845400	3484	* @param Q parameter can be a value between 1 and 128
AnnaBridge	172:65be27845400	3485	*/
AnnaBridge	172:65be27845400	3486	__STATIC_INLINE void LL_RCC_PLL1_SetQ(uint32_t Q)
AnnaBridge	172:65be27845400	3487	{
AnnaBridge	172:65be27845400	3488	MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_Q1, (Q-1UL) << RCC_PLL1DIVR_Q1_Pos);
AnnaBridge	172:65be27845400	3489	}
AnnaBridge	172:65be27845400	3490
AnnaBridge	172:65be27845400	3491	/**
AnnaBridge	172:65be27845400	3492	* @brief Set PLL1 R Coefficient
AnnaBridge	172:65be27845400	3493	* @note This API shall be called only when PLL1 is disabled.
AnnaBridge	172:65be27845400	3494	* @rmtoll PLL1DIVR R1 LL_RCC_PLL1_SetR
AnnaBridge	172:65be27845400	3495	* @param R parameter can be a value between 1 and 128
AnnaBridge	172:65be27845400	3496	*/
AnnaBridge	172:65be27845400	3497	__STATIC_INLINE void LL_RCC_PLL1_SetR(uint32_t R)
AnnaBridge	172:65be27845400	3498	{
AnnaBridge	172:65be27845400	3499	MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_R1, (R-1UL) << RCC_PLL1DIVR_R1_Pos);
AnnaBridge	172:65be27845400	3500	}
AnnaBridge	172:65be27845400	3501
AnnaBridge	172:65be27845400	3502	/**
AnnaBridge	172:65be27845400	3503	* @brief Set PLL1 FRACN Coefficient
AnnaBridge	172:65be27845400	3504	* @rmtoll PLL1FRACR FRACN1 LL_RCC_PLL1_SetFRACN
AnnaBridge	172:65be27845400	3505	* @param FRACN parameter can be a value between 0 and 8191 (0x1FFF)
AnnaBridge	172:65be27845400	3506	*/
AnnaBridge	172:65be27845400	3507	__STATIC_INLINE void LL_RCC_PLL1_SetFRACN(uint32_t FRACN)
AnnaBridge	172:65be27845400	3508	{
AnnaBridge	172:65be27845400	3509	MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1, FRACN << RCC_PLL1FRACR_FRACN1_Pos);
AnnaBridge	172:65be27845400	3510	}
AnnaBridge	172:65be27845400	3511
AnnaBridge	172:65be27845400	3512	/**
AnnaBridge	172:65be27845400	3513	* @brief Enable PLL2
AnnaBridge	172:65be27845400	3514	* @rmtoll CR PLL2ON LL_RCC_PLL2_Enable
AnnaBridge	172:65be27845400	3515	* @retval None
AnnaBridge	172:65be27845400	3516	*/
AnnaBridge	172:65be27845400	3517	__STATIC_INLINE void LL_RCC_PLL2_Enable(void)
AnnaBridge	172:65be27845400	3518	{
AnnaBridge	172:65be27845400	3519	SET_BIT(RCC->CR, RCC_CR_PLL2ON);
AnnaBridge	172:65be27845400	3520	}
AnnaBridge	172:65be27845400	3521
AnnaBridge	172:65be27845400	3522	/**
AnnaBridge	172:65be27845400	3523	* @brief Disable PLL2
AnnaBridge	172:65be27845400	3524	* @note Cannot be disabled if the PLL2 clock is used as the system clock
AnnaBridge	172:65be27845400	3525	* @rmtoll CR PLL2ON LL_RCC_PLL2_Disable
AnnaBridge	172:65be27845400	3526	* @retval None
AnnaBridge	172:65be27845400	3527	*/
AnnaBridge	172:65be27845400	3528	__STATIC_INLINE void LL_RCC_PLL2_Disable(void)
AnnaBridge	172:65be27845400	3529	{
AnnaBridge	172:65be27845400	3530	CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);
AnnaBridge	172:65be27845400	3531	}
AnnaBridge	172:65be27845400	3532
AnnaBridge	172:65be27845400	3533	/**
AnnaBridge	172:65be27845400	3534	* @brief Check if PLL2 Ready
AnnaBridge	172:65be27845400	3535	* @rmtoll CR PLL2RDY LL_RCC_PLL2_IsReady
AnnaBridge	172:65be27845400	3536	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	3537	*/
AnnaBridge	172:65be27845400	3538	__STATIC_INLINE uint32_t LL_RCC_PLL2_IsReady(void)
AnnaBridge	172:65be27845400	3539	{
AnnaBridge	172:65be27845400	3540	return ((READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == (RCC_CR_PLL2RDY))?1UL:0UL);
AnnaBridge	172:65be27845400	3541	}
AnnaBridge	172:65be27845400	3542
AnnaBridge	172:65be27845400	3543	/**
AnnaBridge	172:65be27845400	3544	* @brief Enable PLL2P
AnnaBridge	172:65be27845400	3545	* @note This API shall be called only when PLL2 is disabled.
AnnaBridge	172:65be27845400	3546	* @rmtoll PLLCFGR DIVP2EN LL_RCC_PLL2P_Enable
AnnaBridge	172:65be27845400	3547	* @retval None
AnnaBridge	172:65be27845400	3548	*/
AnnaBridge	172:65be27845400	3549	__STATIC_INLINE void LL_RCC_PLL2P_Enable(void)
AnnaBridge	172:65be27845400	3550	{
AnnaBridge	172:65be27845400	3551	SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN);
AnnaBridge	172:65be27845400	3552	}
AnnaBridge	172:65be27845400	3553
AnnaBridge	172:65be27845400	3554	/**
AnnaBridge	172:65be27845400	3555	* @brief Enable PLL2Q
AnnaBridge	172:65be27845400	3556	* @note This API shall be called only when PLL2 is disabled.
AnnaBridge	172:65be27845400	3557	* @rmtoll PLLCFGR DIVQ2EN LL_RCC_PLL2Q_Enable
AnnaBridge	172:65be27845400	3558	* @retval None
AnnaBridge	172:65be27845400	3559	*/
AnnaBridge	172:65be27845400	3560	__STATIC_INLINE void LL_RCC_PLL2Q_Enable(void)
AnnaBridge	172:65be27845400	3561	{
AnnaBridge	172:65be27845400	3562	SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN);
AnnaBridge	172:65be27845400	3563	}
AnnaBridge	172:65be27845400	3564
AnnaBridge	172:65be27845400	3565	/**
AnnaBridge	172:65be27845400	3566	* @brief Enable PLL2R
AnnaBridge	172:65be27845400	3567	* @note This API shall be called only when PLL2 is disabled.
AnnaBridge	172:65be27845400	3568	* @rmtoll PLLCFGR DIVR2EN LL_RCC_PLL2R_Enable
AnnaBridge	172:65be27845400	3569	* @retval None
AnnaBridge	172:65be27845400	3570	*/
AnnaBridge	172:65be27845400	3571	__STATIC_INLINE void LL_RCC_PLL2R_Enable(void)
AnnaBridge	172:65be27845400	3572	{
AnnaBridge	172:65be27845400	3573	SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN);
AnnaBridge	172:65be27845400	3574	}
AnnaBridge	172:65be27845400	3575
AnnaBridge	172:65be27845400	3576	/**
AnnaBridge	172:65be27845400	3577	* @brief Enable PLL2 FRACN
AnnaBridge	172:65be27845400	3578	* @rmtoll PLLCFGR PLL2FRACEN LL_RCC_PLL2FRACN_Enable
AnnaBridge	172:65be27845400	3579	* @retval None
AnnaBridge	172:65be27845400	3580	*/
AnnaBridge	172:65be27845400	3581	__STATIC_INLINE void LL_RCC_PLL2FRACN_Enable(void)
AnnaBridge	172:65be27845400	3582	{
AnnaBridge	172:65be27845400	3583	SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN);
AnnaBridge	172:65be27845400	3584	}
AnnaBridge	172:65be27845400	3585
AnnaBridge	172:65be27845400	3586	/**
AnnaBridge	172:65be27845400	3587	* @brief Check if PLL2 P is enabled
AnnaBridge	172:65be27845400	3588	* @rmtoll PLLCFGR DIVP2EN LL_RCC_PLL2P_IsEnabled
AnnaBridge	172:65be27845400	3589	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	3590	*/
AnnaBridge	172:65be27845400	3591	__STATIC_INLINE uint32_t LL_RCC_PLL2P_IsEnabled(void)
AnnaBridge	172:65be27845400	3592	{
AnnaBridge	172:65be27845400	3593	return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN) == RCC_PLLCFGR_DIVP2EN)?1UL:0UL);
AnnaBridge	172:65be27845400	3594	}
AnnaBridge	172:65be27845400	3595
AnnaBridge	172:65be27845400	3596	/**
AnnaBridge	172:65be27845400	3597	* @brief Check if PLL2 Q is enabled
AnnaBridge	172:65be27845400	3598	* @rmtoll PLLCFGR DIVQ2EN LL_RCC_PLL2Q_IsEnabled
AnnaBridge	172:65be27845400	3599	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	3600	*/
AnnaBridge	172:65be27845400	3601	__STATIC_INLINE uint32_t LL_RCC_PLL2Q_IsEnabled(void)
AnnaBridge	172:65be27845400	3602	{
AnnaBridge	172:65be27845400	3603	return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN) == RCC_PLLCFGR_DIVQ2EN)?1UL:0UL);
AnnaBridge	172:65be27845400	3604	}
AnnaBridge	172:65be27845400	3605
AnnaBridge	172:65be27845400	3606	/**
AnnaBridge	172:65be27845400	3607	* @brief Check if PLL2 R is enabled
AnnaBridge	172:65be27845400	3608	* @rmtoll PLLCFGR DIVR2EN LL_RCC_PLL2R_IsEnabled
AnnaBridge	172:65be27845400	3609	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	3610	*/
AnnaBridge	172:65be27845400	3611	__STATIC_INLINE uint32_t LL_RCC_PLL2R_IsEnabled(void)
AnnaBridge	172:65be27845400	3612	{
AnnaBridge	172:65be27845400	3613	return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN) == RCC_PLLCFGR_DIVR2EN)?1UL:0UL);
AnnaBridge	172:65be27845400	3614	}
AnnaBridge	172:65be27845400	3615
AnnaBridge	172:65be27845400	3616	/**
AnnaBridge	172:65be27845400	3617	* @brief Check if PLL2 FRACN is enabled
AnnaBridge	172:65be27845400	3618	* @rmtoll PLLCFGR PLL2FRACEN LL_RCC_PLL2FRACN_IsEnabled
AnnaBridge	172:65be27845400	3619	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	3620	*/
AnnaBridge	172:65be27845400	3621	__STATIC_INLINE uint32_t LL_RCC_PLL2FRACN_IsEnabled(void)
AnnaBridge	172:65be27845400	3622	{
AnnaBridge	172:65be27845400	3623	return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) == RCC_PLLCFGR_PLL2FRACEN)?1UL:0UL);
AnnaBridge	172:65be27845400	3624	}
AnnaBridge	172:65be27845400	3625
AnnaBridge	172:65be27845400	3626	/**
AnnaBridge	172:65be27845400	3627	* @brief Disable PLL2P
AnnaBridge	172:65be27845400	3628	* @note This API shall be called only when PLL2 is disabled.
AnnaBridge	172:65be27845400	3629	* @rmtoll PLLCFGR DIVP2EN LL_RCC_PLL2P_Disable
AnnaBridge	172:65be27845400	3630	* @retval None
AnnaBridge	172:65be27845400	3631	*/
AnnaBridge	172:65be27845400	3632	__STATIC_INLINE void LL_RCC_PLL2P_Disable(void)
AnnaBridge	172:65be27845400	3633	{
AnnaBridge	172:65be27845400	3634	CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN);
AnnaBridge	172:65be27845400	3635	}
AnnaBridge	172:65be27845400	3636
AnnaBridge	172:65be27845400	3637	/**
AnnaBridge	172:65be27845400	3638	* @brief Disable PLL2Q
AnnaBridge	172:65be27845400	3639	* @note This API shall be called only when PLL2 is disabled.
AnnaBridge	172:65be27845400	3640	* @rmtoll PLLCFGR DIVQ2EN LL_RCC_PLL2Q_Disable
AnnaBridge	172:65be27845400	3641	* @retval None
AnnaBridge	172:65be27845400	3642	*/
AnnaBridge	172:65be27845400	3643	__STATIC_INLINE void LL_RCC_PLL2Q_Disable(void)
AnnaBridge	172:65be27845400	3644	{
AnnaBridge	172:65be27845400	3645	CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN);
AnnaBridge	172:65be27845400	3646	}
AnnaBridge	172:65be27845400	3647
AnnaBridge	172:65be27845400	3648	/**
AnnaBridge	172:65be27845400	3649	* @brief Disable PLL2R
AnnaBridge	172:65be27845400	3650	* @note This API shall be called only when PLL2 is disabled.
AnnaBridge	172:65be27845400	3651	* @rmtoll PLLCFGR DIVR2EN LL_RCC_PLL2R_Disable
AnnaBridge	172:65be27845400	3652	* @retval None
AnnaBridge	172:65be27845400	3653	*/
AnnaBridge	172:65be27845400	3654	__STATIC_INLINE void LL_RCC_PLL2R_Disable(void)
AnnaBridge	172:65be27845400	3655	{
AnnaBridge	172:65be27845400	3656	CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN);
AnnaBridge	172:65be27845400	3657	}
AnnaBridge	172:65be27845400	3658
AnnaBridge	172:65be27845400	3659	/**
AnnaBridge	172:65be27845400	3660	* @brief Disable PLL2 FRACN
AnnaBridge	172:65be27845400	3661	* @rmtoll PLLCFGR PLL2FRACEN LL_RCC_PLL2FRACN_Enable
AnnaBridge	172:65be27845400	3662	* @retval None
AnnaBridge	172:65be27845400	3663	*/
AnnaBridge	172:65be27845400	3664	__STATIC_INLINE void LL_RCC_PLL2FRACN_Disable(void)
AnnaBridge	172:65be27845400	3665	{
AnnaBridge	172:65be27845400	3666	CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN);
AnnaBridge	172:65be27845400	3667	}
AnnaBridge	172:65be27845400	3668
AnnaBridge	172:65be27845400	3669	/**
AnnaBridge	172:65be27845400	3670	* @brief Set PLL2 VCO OutputRange
AnnaBridge	172:65be27845400	3671	* @note This API shall be called only when PLL2 is disabled.
AnnaBridge	172:65be27845400	3672	* @rmtoll PLLCFGR PLL2VCOSEL LL_RCC_PLL2_SetVCOOuputRange
AnnaBridge	172:65be27845400	3673	* @param VCORange This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3674	* @arg @ref LL_RCC_PLLVCORANGE_WIDE
AnnaBridge	172:65be27845400	3675	* @arg @ref LL_RCC_PLLVCORANGE_MEDIUM
AnnaBridge	172:65be27845400	3676	* @retval None
AnnaBridge	172:65be27845400	3677	*/
AnnaBridge	172:65be27845400	3678	__STATIC_INLINE void LL_RCC_PLL2_SetVCOOutputRange(uint32_t VCORange)
AnnaBridge	172:65be27845400	3679	{
AnnaBridge	172:65be27845400	3680	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, VCORange << RCC_PLLCFGR_PLL2VCOSEL_Pos);
AnnaBridge	172:65be27845400	3681	}
AnnaBridge	172:65be27845400	3682
AnnaBridge	172:65be27845400	3683	/**
AnnaBridge	172:65be27845400	3684	* @brief Set PLL2 VCO Input Range
AnnaBridge	172:65be27845400	3685	* @note This API shall be called only when PLL2 is disabled.
AnnaBridge	172:65be27845400	3686	* @rmtoll PLLCFGR PLL2RGE LL_RCC_PLL2_SetVCOInputRange
AnnaBridge	172:65be27845400	3687	* @param InputRange This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3688	* @arg @ref LL_RCC_PLLINPUTRANGE_1_2
AnnaBridge	172:65be27845400	3689	* @arg @ref LL_RCC_PLLINPUTRANGE_2_4
AnnaBridge	172:65be27845400	3690	* @arg @ref LL_RCC_PLLINPUTRANGE_4_8
AnnaBridge	172:65be27845400	3691	* @arg @ref LL_RCC_PLLINPUTRANGE_8_16
AnnaBridge	172:65be27845400	3692	* @retval None
AnnaBridge	172:65be27845400	3693	*/
AnnaBridge	172:65be27845400	3694	__STATIC_INLINE void LL_RCC_PLL2_SetVCOInputRange(uint32_t InputRange)
AnnaBridge	172:65be27845400	3695	{
AnnaBridge	172:65be27845400	3696	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, InputRange << RCC_PLLCFGR_PLL2RGE_Pos);
AnnaBridge	172:65be27845400	3697	}
AnnaBridge	172:65be27845400	3698
AnnaBridge	172:65be27845400	3699	/**
AnnaBridge	172:65be27845400	3700	* @brief Get PLL2 N Coefficient
AnnaBridge	172:65be27845400	3701	* @rmtoll PLL2DIVR N2 LL_RCC_PLL2_GetN
AnnaBridge	172:65be27845400	3702	* @retval A value between 4 and 512
AnnaBridge	172:65be27845400	3703	*/
AnnaBridge	172:65be27845400	3704	__STATIC_INLINE uint32_t LL_RCC_PLL2_GetN(void)
AnnaBridge	172:65be27845400	3705	{
AnnaBridge	172:65be27845400	3706	return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_N2) >> RCC_PLL2DIVR_N2_Pos) + 1UL);
AnnaBridge	172:65be27845400	3707	}
AnnaBridge	172:65be27845400	3708
AnnaBridge	172:65be27845400	3709	/**
AnnaBridge	172:65be27845400	3710	* @brief Get PLL2 M Coefficient
AnnaBridge	172:65be27845400	3711	* @rmtoll PLLCKSELR DIVM2 LL_RCC_PLL2_GetM
AnnaBridge	172:65be27845400	3712	* @retval A value between 0 and 63
AnnaBridge	172:65be27845400	3713	*/
AnnaBridge	172:65be27845400	3714	__STATIC_INLINE uint32_t LL_RCC_PLL2_GetM(void)
AnnaBridge	172:65be27845400	3715	{
AnnaBridge	172:65be27845400	3716	return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM2) >> RCC_PLLCKSELR_DIVM2_Pos);
AnnaBridge	172:65be27845400	3717	}
AnnaBridge	172:65be27845400	3718
AnnaBridge	172:65be27845400	3719	/**
AnnaBridge	172:65be27845400	3720	* @brief Get PLL2 P Coefficient
AnnaBridge	172:65be27845400	3721	* @rmtoll PLL2DIVR P2 LL_RCC_PLL2_GetP
AnnaBridge	172:65be27845400	3722	* @retval A value between 1 and 128
AnnaBridge	172:65be27845400	3723	*/
AnnaBridge	172:65be27845400	3724	__STATIC_INLINE uint32_t LL_RCC_PLL2_GetP(void)
AnnaBridge	172:65be27845400	3725	{
AnnaBridge	172:65be27845400	3726	return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_P2) >> RCC_PLL2DIVR_P2_Pos) + 1UL);
AnnaBridge	172:65be27845400	3727	}
AnnaBridge	172:65be27845400	3728
AnnaBridge	172:65be27845400	3729	/**
AnnaBridge	172:65be27845400	3730	* @brief Get PLL2 Q Coefficient
AnnaBridge	172:65be27845400	3731	* @rmtoll PLL2DIVR Q2 LL_RCC_PLL2_GetQ
AnnaBridge	172:65be27845400	3732	* @retval A value between 1 and 128
AnnaBridge	172:65be27845400	3733	*/
AnnaBridge	172:65be27845400	3734	__STATIC_INLINE uint32_t LL_RCC_PLL2_GetQ(void)
AnnaBridge	172:65be27845400	3735	{
AnnaBridge	172:65be27845400	3736	return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_Q2) >> RCC_PLL2DIVR_Q2_Pos) + 1UL);
AnnaBridge	172:65be27845400	3737	}
AnnaBridge	172:65be27845400	3738
AnnaBridge	172:65be27845400	3739	/**
AnnaBridge	172:65be27845400	3740	* @brief Get PLL2 R Coefficient
AnnaBridge	172:65be27845400	3741	* @rmtoll PLL2DIVR R2 LL_RCC_PLL2_GetR
AnnaBridge	172:65be27845400	3742	* @retval A value between 1 and 128
AnnaBridge	172:65be27845400	3743	*/
AnnaBridge	172:65be27845400	3744	__STATIC_INLINE uint32_t LL_RCC_PLL2_GetR(void)
AnnaBridge	172:65be27845400	3745	{
AnnaBridge	172:65be27845400	3746	return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_R2) >> RCC_PLL2DIVR_R2_Pos) + 1UL);
AnnaBridge	172:65be27845400	3747	}
AnnaBridge	172:65be27845400	3748
AnnaBridge	172:65be27845400	3749	/**
AnnaBridge	172:65be27845400	3750	* @brief Get PLL2 FRACN Coefficient
AnnaBridge	172:65be27845400	3751	* @rmtoll PLL2FRACR FRACN2 LL_RCC_PLL2_GetFRACN
AnnaBridge	172:65be27845400	3752	* @retval A value between 0 and 8191 (0x1FFF)
AnnaBridge	172:65be27845400	3753	*/
AnnaBridge	172:65be27845400	3754	__STATIC_INLINE uint32_t LL_RCC_PLL2_GetFRACN(void)
AnnaBridge	172:65be27845400	3755	{
AnnaBridge	172:65be27845400	3756	return (uint32_t)(READ_BIT(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2) >> RCC_PLL2FRACR_FRACN2_Pos);
AnnaBridge	172:65be27845400	3757	}
AnnaBridge	172:65be27845400	3758
AnnaBridge	172:65be27845400	3759	/**
AnnaBridge	172:65be27845400	3760	* @brief Set PLL2 N Coefficient
AnnaBridge	172:65be27845400	3761	* @note This API shall be called only when PLL2 is disabled.
AnnaBridge	172:65be27845400	3762	* @rmtoll PLL2DIVR N2 LL_RCC_PLL2_SetN
AnnaBridge	172:65be27845400	3763	* @param N parameter can be a value between 4 and 512
AnnaBridge	172:65be27845400	3764	*/
AnnaBridge	172:65be27845400	3765	__STATIC_INLINE void LL_RCC_PLL2_SetN(uint32_t N)
AnnaBridge	172:65be27845400	3766	{
AnnaBridge	172:65be27845400	3767	MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_N2, (N-1UL) << RCC_PLL2DIVR_N2_Pos);
AnnaBridge	172:65be27845400	3768	}
AnnaBridge	172:65be27845400	3769
AnnaBridge	172:65be27845400	3770	/**
AnnaBridge	172:65be27845400	3771	* @brief Set PLL2 M Coefficient
AnnaBridge	172:65be27845400	3772	* @note This API shall be called only when PLL2 is disabled.
AnnaBridge	172:65be27845400	3773	* @rmtoll PLLCKSELR DIVM2 LL_RCC_PLL2_SetM
AnnaBridge	172:65be27845400	3774	* @param M parameter can be a value between 0 and 63
AnnaBridge	172:65be27845400	3775	*/
AnnaBridge	172:65be27845400	3776	__STATIC_INLINE void LL_RCC_PLL2_SetM(uint32_t M)
AnnaBridge	172:65be27845400	3777	{
AnnaBridge	172:65be27845400	3778	MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM2, M << RCC_PLLCKSELR_DIVM2_Pos);
AnnaBridge	172:65be27845400	3779	}
AnnaBridge	172:65be27845400	3780
AnnaBridge	172:65be27845400	3781	/**
AnnaBridge	172:65be27845400	3782	* @brief Set PLL2 P Coefficient
AnnaBridge	172:65be27845400	3783	* @note This API shall be called only when PLL2 is disabled.
AnnaBridge	172:65be27845400	3784	* @rmtoll PLL2DIVR P2 LL_RCC_PLL2_SetP
AnnaBridge	172:65be27845400	3785	* @param P parameter can be a value between 1 and 128
AnnaBridge	172:65be27845400	3786	*/
AnnaBridge	172:65be27845400	3787	__STATIC_INLINE void LL_RCC_PLL2_SetP(uint32_t P)
AnnaBridge	172:65be27845400	3788	{
AnnaBridge	172:65be27845400	3789	MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_P2, (P-1UL) << RCC_PLL2DIVR_P2_Pos);
AnnaBridge	172:65be27845400	3790	}
AnnaBridge	172:65be27845400	3791
AnnaBridge	172:65be27845400	3792	/**
AnnaBridge	172:65be27845400	3793	* @brief Set PLL2 Q Coefficient
AnnaBridge	172:65be27845400	3794	* @note This API shall be called only when PLL2 is disabled.
AnnaBridge	172:65be27845400	3795	* @rmtoll PLL2DIVR Q2 LL_RCC_PLL2_SetQ
AnnaBridge	172:65be27845400	3796	* @param Q parameter can be a value between 1 and 128
AnnaBridge	172:65be27845400	3797	*/
AnnaBridge	172:65be27845400	3798	__STATIC_INLINE void LL_RCC_PLL2_SetQ(uint32_t Q)
AnnaBridge	172:65be27845400	3799	{
AnnaBridge	172:65be27845400	3800	MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_Q2, (Q-1UL) << RCC_PLL2DIVR_Q2_Pos);
AnnaBridge	172:65be27845400	3801	}
AnnaBridge	172:65be27845400	3802
AnnaBridge	172:65be27845400	3803	/**
AnnaBridge	172:65be27845400	3804	* @brief Set PLL2 R Coefficient
AnnaBridge	172:65be27845400	3805	* @note This API shall be called only when PLL2 is disabled.
AnnaBridge	172:65be27845400	3806	* @rmtoll PLL2DIVR R2 LL_RCC_PLL2_SetR
AnnaBridge	172:65be27845400	3807	* @param R parameter can be a value between 1 and 128
AnnaBridge	172:65be27845400	3808	*/
AnnaBridge	172:65be27845400	3809	__STATIC_INLINE void LL_RCC_PLL2_SetR(uint32_t R)
AnnaBridge	172:65be27845400	3810	{
AnnaBridge	172:65be27845400	3811	MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_R2, (R-1UL) << RCC_PLL2DIVR_R2_Pos);
AnnaBridge	172:65be27845400	3812	}
AnnaBridge	172:65be27845400	3813
AnnaBridge	172:65be27845400	3814	/**
AnnaBridge	172:65be27845400	3815	* @brief Set PLL2 FRACN Coefficient
AnnaBridge	172:65be27845400	3816	* @rmtoll PLL2FRACR FRACN2 LL_RCC_PLL2_SetFRACN
AnnaBridge	172:65be27845400	3817	* @param FRACN parameter can be a value between 0 and 8191 (0x1FFF)
AnnaBridge	172:65be27845400	3818	*/
AnnaBridge	172:65be27845400	3819	__STATIC_INLINE void LL_RCC_PLL2_SetFRACN(uint32_t FRACN)
AnnaBridge	172:65be27845400	3820	{
AnnaBridge	172:65be27845400	3821	MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2, FRACN << RCC_PLL2FRACR_FRACN2_Pos);
AnnaBridge	172:65be27845400	3822	}
AnnaBridge	172:65be27845400	3823
AnnaBridge	172:65be27845400	3824	/**
AnnaBridge	172:65be27845400	3825	* @brief Enable PLL3
AnnaBridge	172:65be27845400	3826	* @rmtoll CR PLL3ON LL_RCC_PLL3_Enable
AnnaBridge	172:65be27845400	3827	* @retval None
AnnaBridge	172:65be27845400	3828	*/
AnnaBridge	172:65be27845400	3829	__STATIC_INLINE void LL_RCC_PLL3_Enable(void)
AnnaBridge	172:65be27845400	3830	{
AnnaBridge	172:65be27845400	3831	SET_BIT(RCC->CR, RCC_CR_PLL3ON);
AnnaBridge	172:65be27845400	3832	}
AnnaBridge	172:65be27845400	3833
AnnaBridge	172:65be27845400	3834	/**
AnnaBridge	172:65be27845400	3835	* @brief Disable PLL3
AnnaBridge	172:65be27845400	3836	* @note Cannot be disabled if the PLL3 clock is used as the system clock
AnnaBridge	172:65be27845400	3837	* @rmtoll CR PLL3ON LL_RCC_PLL3_Disable
AnnaBridge	172:65be27845400	3838	* @retval None
AnnaBridge	172:65be27845400	3839	*/
AnnaBridge	172:65be27845400	3840	__STATIC_INLINE void LL_RCC_PLL3_Disable(void)
AnnaBridge	172:65be27845400	3841	{
AnnaBridge	172:65be27845400	3842	CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);
AnnaBridge	172:65be27845400	3843	}
AnnaBridge	172:65be27845400	3844
AnnaBridge	172:65be27845400	3845	/**
AnnaBridge	172:65be27845400	3846	* @brief Check if PLL3 Ready
AnnaBridge	172:65be27845400	3847	* @rmtoll CR PLL3RDY LL_RCC_PLL3_IsReady
AnnaBridge	172:65be27845400	3848	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	3849	*/
AnnaBridge	172:65be27845400	3850	__STATIC_INLINE uint32_t LL_RCC_PLL3_IsReady(void)
AnnaBridge	172:65be27845400	3851	{
AnnaBridge	172:65be27845400	3852	return ((READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == (RCC_CR_PLL3RDY))?1UL:0UL);
AnnaBridge	172:65be27845400	3853	}
AnnaBridge	172:65be27845400	3854
AnnaBridge	172:65be27845400	3855	/**
AnnaBridge	172:65be27845400	3856	* @brief Enable PLL3P
AnnaBridge	172:65be27845400	3857	* @note This API shall be called only when PLL3 is disabled.
AnnaBridge	172:65be27845400	3858	* @rmtoll PLLCFGR DIVP3EN LL_RCC_PLL3P_Enable
AnnaBridge	172:65be27845400	3859	* @retval None
AnnaBridge	172:65be27845400	3860	*/
AnnaBridge	172:65be27845400	3861	__STATIC_INLINE void LL_RCC_PLL3P_Enable(void)
AnnaBridge	172:65be27845400	3862	{
AnnaBridge	172:65be27845400	3863	SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN);
AnnaBridge	172:65be27845400	3864	}
AnnaBridge	172:65be27845400	3865
AnnaBridge	172:65be27845400	3866	/**
AnnaBridge	172:65be27845400	3867	* @brief Enable PLL3Q
AnnaBridge	172:65be27845400	3868	* @note This API shall be called only when PLL3 is disabled.
AnnaBridge	172:65be27845400	3869	* @rmtoll PLLCFGR DIVQ3EN LL_RCC_PLL3Q_Enable
AnnaBridge	172:65be27845400	3870	* @retval None
AnnaBridge	172:65be27845400	3871	*/
AnnaBridge	172:65be27845400	3872	__STATIC_INLINE void LL_RCC_PLL3Q_Enable(void)
AnnaBridge	172:65be27845400	3873	{
AnnaBridge	172:65be27845400	3874	SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN);
AnnaBridge	172:65be27845400	3875	}
AnnaBridge	172:65be27845400	3876
AnnaBridge	172:65be27845400	3877	/**
AnnaBridge	172:65be27845400	3878	* @brief Enable PLL3R
AnnaBridge	172:65be27845400	3879	* @note This API shall be called only when PLL3 is disabled.
AnnaBridge	172:65be27845400	3880	* @rmtoll PLLCFGR DIVR3EN LL_RCC_PLL3R_Enable
AnnaBridge	172:65be27845400	3881	* @retval None
AnnaBridge	172:65be27845400	3882	*/
AnnaBridge	172:65be27845400	3883	__STATIC_INLINE void LL_RCC_PLL3R_Enable(void)
AnnaBridge	172:65be27845400	3884	{
AnnaBridge	172:65be27845400	3885	SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN);
AnnaBridge	172:65be27845400	3886	}
AnnaBridge	172:65be27845400	3887
AnnaBridge	172:65be27845400	3888	/**
AnnaBridge	172:65be27845400	3889	* @brief Enable PLL3 FRACN
AnnaBridge	172:65be27845400	3890	* @rmtoll PLLCFGR PLL3FRACEN LL_RCC_PLL3FRACN_Enable
AnnaBridge	172:65be27845400	3891	* @retval None
AnnaBridge	172:65be27845400	3892	*/
AnnaBridge	172:65be27845400	3893	__STATIC_INLINE void LL_RCC_PLL3FRACN_Enable(void)
AnnaBridge	172:65be27845400	3894	{
AnnaBridge	172:65be27845400	3895	SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN);
AnnaBridge	172:65be27845400	3896	}
AnnaBridge	172:65be27845400	3897
AnnaBridge	172:65be27845400	3898	/**
AnnaBridge	172:65be27845400	3899	* @brief Check if PLL3 P is enabled
AnnaBridge	172:65be27845400	3900	* @rmtoll PLLCFGR DIVP3EN LL_RCC_PLL3P_IsEnabled
AnnaBridge	172:65be27845400	3901	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	3902	*/
AnnaBridge	172:65be27845400	3903	__STATIC_INLINE uint32_t LL_RCC_PLL3P_IsEnabled(void)
AnnaBridge	172:65be27845400	3904	{
AnnaBridge	172:65be27845400	3905	return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN) == RCC_PLLCFGR_DIVP3EN)?1UL:0UL);
AnnaBridge	172:65be27845400	3906	}
AnnaBridge	172:65be27845400	3907
AnnaBridge	172:65be27845400	3908	/**
AnnaBridge	172:65be27845400	3909	* @brief Check if PLL3 Q is enabled
AnnaBridge	172:65be27845400	3910	* @rmtoll PLLCFGR DIVQ3EN LL_RCC_PLL3Q_IsEnabled
AnnaBridge	172:65be27845400	3911	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	3912	*/
AnnaBridge	172:65be27845400	3913	__STATIC_INLINE uint32_t LL_RCC_PLL3Q_IsEnabled(void)
AnnaBridge	172:65be27845400	3914	{
AnnaBridge	172:65be27845400	3915	return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN) == RCC_PLLCFGR_DIVQ3EN)?1UL:0UL);
AnnaBridge	172:65be27845400	3916	}
AnnaBridge	172:65be27845400	3917
AnnaBridge	172:65be27845400	3918	/**
AnnaBridge	172:65be27845400	3919	* @brief Check if PLL3 R is enabled
AnnaBridge	172:65be27845400	3920	* @rmtoll PLLCFGR DIVR3EN LL_RCC_PLL3R_IsEnabled
AnnaBridge	172:65be27845400	3921	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	3922	*/
AnnaBridge	172:65be27845400	3923	__STATIC_INLINE uint32_t LL_RCC_PLL3R_IsEnabled(void)
AnnaBridge	172:65be27845400	3924	{
AnnaBridge	172:65be27845400	3925	return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN) == RCC_PLLCFGR_DIVR3EN)?1UL:0UL);
AnnaBridge	172:65be27845400	3926	}
AnnaBridge	172:65be27845400	3927
AnnaBridge	172:65be27845400	3928	/**
AnnaBridge	172:65be27845400	3929	* @brief Check if PLL3 FRACN is enabled
AnnaBridge	172:65be27845400	3930	* @rmtoll PLLCFGR PLL3FRACEN LL_RCC_PLL3FRACN_IsEnabled
AnnaBridge	172:65be27845400	3931	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	3932	*/
AnnaBridge	172:65be27845400	3933	__STATIC_INLINE uint32_t LL_RCC_PLL3FRACN_IsEnabled(void)
AnnaBridge	172:65be27845400	3934	{
AnnaBridge	172:65be27845400	3935	return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) == RCC_PLLCFGR_PLL3FRACEN)?1UL:0UL);
AnnaBridge	172:65be27845400	3936	}
AnnaBridge	172:65be27845400	3937
AnnaBridge	172:65be27845400	3938	/**
AnnaBridge	172:65be27845400	3939	* @brief Disable PLL3P
AnnaBridge	172:65be27845400	3940	* @note This API shall be called only when PLL3 is disabled.
AnnaBridge	172:65be27845400	3941	* @rmtoll PLLCFGR DIVP2EN LL_RCC_PLL3P_Disable
AnnaBridge	172:65be27845400	3942	* @retval None
AnnaBridge	172:65be27845400	3943	*/
AnnaBridge	172:65be27845400	3944	__STATIC_INLINE void LL_RCC_PLL3P_Disable(void)
AnnaBridge	172:65be27845400	3945	{
AnnaBridge	172:65be27845400	3946	CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN);
AnnaBridge	172:65be27845400	3947	}
AnnaBridge	172:65be27845400	3948
AnnaBridge	172:65be27845400	3949	/**
AnnaBridge	172:65be27845400	3950	* @brief Disable PLL3Q
AnnaBridge	172:65be27845400	3951	* @note This API shall be called only when PLL3 is disabled.
AnnaBridge	172:65be27845400	3952	* @rmtoll PLLCFGR DIVQ3EN LL_RCC_PLL3Q_Disable
AnnaBridge	172:65be27845400	3953	* @retval None
AnnaBridge	172:65be27845400	3954	*/
AnnaBridge	172:65be27845400	3955	__STATIC_INLINE void LL_RCC_PLL3Q_Disable(void)
AnnaBridge	172:65be27845400	3956	{
AnnaBridge	172:65be27845400	3957	CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN);
AnnaBridge	172:65be27845400	3958	}
AnnaBridge	172:65be27845400	3959
AnnaBridge	172:65be27845400	3960	/**
AnnaBridge	172:65be27845400	3961	* @brief Disable PLL3R
AnnaBridge	172:65be27845400	3962	* @note This API shall be called only when PLL3 is disabled.
AnnaBridge	172:65be27845400	3963	* @rmtoll PLLCFGR DIVR3EN LL_RCC_PLL3R_Disable
AnnaBridge	172:65be27845400	3964	* @retval None
AnnaBridge	172:65be27845400	3965	*/
AnnaBridge	172:65be27845400	3966	__STATIC_INLINE void LL_RCC_PLL3R_Disable(void)
AnnaBridge	172:65be27845400	3967	{
AnnaBridge	172:65be27845400	3968	CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN);
AnnaBridge	172:65be27845400	3969	}
AnnaBridge	172:65be27845400	3970
AnnaBridge	172:65be27845400	3971	/**
AnnaBridge	172:65be27845400	3972	* @brief Disable PLL3 FRACN
AnnaBridge	172:65be27845400	3973	* @rmtoll PLLCFGR PLL3FRACEN LL_RCC_PLL3FRACN_Enable
AnnaBridge	172:65be27845400	3974	* @retval None
AnnaBridge	172:65be27845400	3975	*/
AnnaBridge	172:65be27845400	3976	__STATIC_INLINE void LL_RCC_PLL3FRACN_Disable(void)
AnnaBridge	172:65be27845400	3977	{
AnnaBridge	172:65be27845400	3978	CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN);
AnnaBridge	172:65be27845400	3979	}
AnnaBridge	172:65be27845400	3980
AnnaBridge	172:65be27845400	3981	/**
AnnaBridge	172:65be27845400	3982	* @brief Set PLL3 VCO OutputRange
AnnaBridge	172:65be27845400	3983	* @note This API shall be called only when PLL3 is disabled.
AnnaBridge	172:65be27845400	3984	* @rmtoll PLLCFGR PLL3VCOSEL LL_RCC_PLL3_SetVCOOuputRange
AnnaBridge	172:65be27845400	3985	* @param VCORange This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3986	* @arg @ref LL_RCC_PLLVCORANGE_WIDE
AnnaBridge	172:65be27845400	3987	* @arg @ref LL_RCC_PLLVCORANGE_MEDIUM
AnnaBridge	172:65be27845400	3988	* @retval None
AnnaBridge	172:65be27845400	3989	*/
AnnaBridge	172:65be27845400	3990	__STATIC_INLINE void LL_RCC_PLL3_SetVCOOutputRange(uint32_t VCORange)
AnnaBridge	172:65be27845400	3991	{
AnnaBridge	172:65be27845400	3992	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, VCORange << RCC_PLLCFGR_PLL3VCOSEL_Pos);
AnnaBridge	172:65be27845400	3993	}
AnnaBridge	172:65be27845400	3994
AnnaBridge	172:65be27845400	3995	/**
AnnaBridge	172:65be27845400	3996	* @brief Set PLL3 VCO Input Range
AnnaBridge	172:65be27845400	3997	* @note This API shall be called only when PLL3 is disabled.
AnnaBridge	172:65be27845400	3998	* @rmtoll PLLCFGR PLL3RGE LL_RCC_PLL3_SetVCOInputRange
AnnaBridge	172:65be27845400	3999	* @param InputRange This parameter can be one of the following values:
AnnaBridge	172:65be27845400	4000	* @arg @ref LL_RCC_PLLINPUTRANGE_1_2
AnnaBridge	172:65be27845400	4001	* @arg @ref LL_RCC_PLLINPUTRANGE_2_4
AnnaBridge	172:65be27845400	4002	* @arg @ref LL_RCC_PLLINPUTRANGE_4_8
AnnaBridge	172:65be27845400	4003	* @arg @ref LL_RCC_PLLINPUTRANGE_8_16
AnnaBridge	172:65be27845400	4004	* @retval None
AnnaBridge	172:65be27845400	4005	*/
AnnaBridge	172:65be27845400	4006	__STATIC_INLINE void LL_RCC_PLL3_SetVCOInputRange(uint32_t InputRange)
AnnaBridge	172:65be27845400	4007	{
AnnaBridge	172:65be27845400	4008	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, InputRange << RCC_PLLCFGR_PLL3RGE_Pos);
AnnaBridge	172:65be27845400	4009	}
AnnaBridge	172:65be27845400	4010
AnnaBridge	172:65be27845400	4011	/**
AnnaBridge	172:65be27845400	4012	* @brief Get PLL3 N Coefficient
AnnaBridge	172:65be27845400	4013	* @rmtoll PLL3DIVR N3 LL_RCC_PLL3_GetN
AnnaBridge	172:65be27845400	4014	* @retval A value between 4 and 512
AnnaBridge	172:65be27845400	4015	*/
AnnaBridge	172:65be27845400	4016	__STATIC_INLINE uint32_t LL_RCC_PLL3_GetN(void)
AnnaBridge	172:65be27845400	4017	{
AnnaBridge	172:65be27845400	4018	return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_N3) >> RCC_PLL3DIVR_N3_Pos) + 1UL);
AnnaBridge	172:65be27845400	4019	}
AnnaBridge	172:65be27845400	4020
AnnaBridge	172:65be27845400	4021	/**
AnnaBridge	172:65be27845400	4022	* @brief Get PLL3 M Coefficient
AnnaBridge	172:65be27845400	4023	* @rmtoll PLLCKSELR DIVM3 LL_RCC_PLL3_GetM
AnnaBridge	172:65be27845400	4024	* @retval A value between 0 and 63
AnnaBridge	172:65be27845400	4025	*/
AnnaBridge	172:65be27845400	4026	__STATIC_INLINE uint32_t LL_RCC_PLL3_GetM(void)
AnnaBridge	172:65be27845400	4027	{
AnnaBridge	172:65be27845400	4028	return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM3) >> RCC_PLLCKSELR_DIVM3_Pos);
AnnaBridge	172:65be27845400	4029	}
AnnaBridge	172:65be27845400	4030
AnnaBridge	172:65be27845400	4031	/**
AnnaBridge	172:65be27845400	4032	* @brief Get PLL3 P Coefficient
AnnaBridge	172:65be27845400	4033	* @rmtoll PLL3DIVR P3 LL_RCC_PLL3_GetP
AnnaBridge	172:65be27845400	4034	* @retval A value between 1 and 128
AnnaBridge	172:65be27845400	4035	*/
AnnaBridge	172:65be27845400	4036	__STATIC_INLINE uint32_t LL_RCC_PLL3_GetP(void)
AnnaBridge	172:65be27845400	4037	{
AnnaBridge	172:65be27845400	4038	return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_P3) >> RCC_PLL3DIVR_P3_Pos) + 1UL);
AnnaBridge	172:65be27845400	4039	}
AnnaBridge	172:65be27845400	4040
AnnaBridge	172:65be27845400	4041	/**
AnnaBridge	172:65be27845400	4042	* @brief Get PLL3 Q Coefficient
AnnaBridge	172:65be27845400	4043	* @rmtoll PLL3DIVR Q3 LL_RCC_PLL3_GetQ
AnnaBridge	172:65be27845400	4044	* @retval A value between 1 and 128
AnnaBridge	172:65be27845400	4045	*/
AnnaBridge	172:65be27845400	4046	__STATIC_INLINE uint32_t LL_RCC_PLL3_GetQ(void)
AnnaBridge	172:65be27845400	4047	{
AnnaBridge	172:65be27845400	4048	return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_Q3) >> RCC_PLL3DIVR_Q3_Pos) + 1UL);
AnnaBridge	172:65be27845400	4049	}
AnnaBridge	172:65be27845400	4050
AnnaBridge	172:65be27845400	4051	/**
AnnaBridge	172:65be27845400	4052	* @brief Get PLL3 R Coefficient
AnnaBridge	172:65be27845400	4053	* @rmtoll PLL3DIVR R3 LL_RCC_PLL3_GetR
AnnaBridge	172:65be27845400	4054	* @retval A value between 1 and 128
AnnaBridge	172:65be27845400	4055	*/
AnnaBridge	172:65be27845400	4056	__STATIC_INLINE uint32_t LL_RCC_PLL3_GetR(void)
AnnaBridge	172:65be27845400	4057	{
AnnaBridge	172:65be27845400	4058	return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_R3) >> RCC_PLL3DIVR_R3_Pos) + 1UL);
AnnaBridge	172:65be27845400	4059	}
AnnaBridge	172:65be27845400	4060
AnnaBridge	172:65be27845400	4061	/**
AnnaBridge	172:65be27845400	4062	* @brief Get PLL3 FRACN Coefficient
AnnaBridge	172:65be27845400	4063	* @rmtoll PLL3FRACR FRACN3 LL_RCC_PLL3_GetFRACN
AnnaBridge	172:65be27845400	4064	* @retval A value between 0 and 8191 (0x1FFF)
AnnaBridge	172:65be27845400	4065	*/
AnnaBridge	172:65be27845400	4066	__STATIC_INLINE uint32_t LL_RCC_PLL3_GetFRACN(void)
AnnaBridge	172:65be27845400	4067	{
AnnaBridge	172:65be27845400	4068	return (uint32_t)(READ_BIT(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3) >> RCC_PLL3FRACR_FRACN3_Pos);
AnnaBridge	172:65be27845400	4069	}
AnnaBridge	172:65be27845400	4070
AnnaBridge	172:65be27845400	4071	/**
AnnaBridge	172:65be27845400	4072	* @brief Set PLL3 N Coefficient
AnnaBridge	172:65be27845400	4073	* @note This API shall be called only when PLL3 is disabled.
AnnaBridge	172:65be27845400	4074	* @rmtoll PLL3DIVR N3 LL_RCC_PLL3_SetN
AnnaBridge	172:65be27845400	4075	* @param N parameter can be a value between 4 and 512
AnnaBridge	172:65be27845400	4076	*/
AnnaBridge	172:65be27845400	4077	__STATIC_INLINE void LL_RCC_PLL3_SetN(uint32_t N)
AnnaBridge	172:65be27845400	4078	{
AnnaBridge	172:65be27845400	4079	MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_N3, (N-1UL) << RCC_PLL3DIVR_N3_Pos);
AnnaBridge	172:65be27845400	4080	}
AnnaBridge	172:65be27845400	4081
AnnaBridge	172:65be27845400	4082	/**
AnnaBridge	172:65be27845400	4083	* @brief Set PLL3 M Coefficient
AnnaBridge	172:65be27845400	4084	* @note This API shall be called only when PLL3 is disabled.
AnnaBridge	172:65be27845400	4085	* @rmtoll PLLCKSELR DIVM3 LL_RCC_PLL3_SetM
AnnaBridge	172:65be27845400	4086	* @param M parameter can be a value between 0 and 63
AnnaBridge	172:65be27845400	4087	*/
AnnaBridge	172:65be27845400	4088	__STATIC_INLINE void LL_RCC_PLL3_SetM(uint32_t M)
AnnaBridge	172:65be27845400	4089	{
AnnaBridge	172:65be27845400	4090	MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM3, M << RCC_PLLCKSELR_DIVM3_Pos);
AnnaBridge	172:65be27845400	4091	}
AnnaBridge	172:65be27845400	4092
AnnaBridge	172:65be27845400	4093	/**
AnnaBridge	172:65be27845400	4094	* @brief Set PLL3 P Coefficient
AnnaBridge	172:65be27845400	4095	* @note This API shall be called only when PLL3 is disabled.
AnnaBridge	172:65be27845400	4096	* @rmtoll PLL3DIVR P3 LL_RCC_PLL3_SetP
AnnaBridge	172:65be27845400	4097	* @param P parameter can be a value between 1 and 128
AnnaBridge	172:65be27845400	4098	*/
AnnaBridge	172:65be27845400	4099	__STATIC_INLINE void LL_RCC_PLL3_SetP(uint32_t P)
AnnaBridge	172:65be27845400	4100	{
AnnaBridge	172:65be27845400	4101	MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_P3, (P-1UL) << RCC_PLL3DIVR_P3_Pos);
AnnaBridge	172:65be27845400	4102	}
AnnaBridge	172:65be27845400	4103
AnnaBridge	172:65be27845400	4104	/**
AnnaBridge	172:65be27845400	4105	* @brief Set PLL3 Q Coefficient
AnnaBridge	172:65be27845400	4106	* @note This API shall be called only when PLL3 is disabled.
AnnaBridge	172:65be27845400	4107	* @rmtoll PLL3DIVR Q3 LL_RCC_PLL3_SetQ
AnnaBridge	172:65be27845400	4108	* @param Q parameter can be a value between 1 and 128
AnnaBridge	172:65be27845400	4109	*/
AnnaBridge	172:65be27845400	4110	__STATIC_INLINE void LL_RCC_PLL3_SetQ(uint32_t Q)
AnnaBridge	172:65be27845400	4111	{
AnnaBridge	172:65be27845400	4112	MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_Q3, (Q-1UL) << RCC_PLL3DIVR_Q3_Pos);
AnnaBridge	172:65be27845400	4113	}
AnnaBridge	172:65be27845400	4114
AnnaBridge	172:65be27845400	4115	/**
AnnaBridge	172:65be27845400	4116	* @brief Set PLL3 R Coefficient
AnnaBridge	172:65be27845400	4117	* @note This API shall be called only when PLL3 is disabled.
AnnaBridge	172:65be27845400	4118	* @rmtoll PLL3DIVR R3 LL_RCC_PLL3_SetR
AnnaBridge	172:65be27845400	4119	* @param R parameter can be a value between 1 and 128
AnnaBridge	172:65be27845400	4120	*/
AnnaBridge	172:65be27845400	4121	__STATIC_INLINE void LL_RCC_PLL3_SetR(uint32_t R)
AnnaBridge	172:65be27845400	4122	{
AnnaBridge	172:65be27845400	4123	MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_R3, (R-1UL) << RCC_PLL3DIVR_R3_Pos);
AnnaBridge	172:65be27845400	4124	}
AnnaBridge	172:65be27845400	4125
AnnaBridge	172:65be27845400	4126	/**
AnnaBridge	172:65be27845400	4127	* @brief Set PLL3 FRACN Coefficient
AnnaBridge	172:65be27845400	4128	* @rmtoll PLL3FRACR FRACN3 LL_RCC_PLL3_SetFRACN
AnnaBridge	172:65be27845400	4129	* @param FRACN parameter can be a value between 0 and 8191 (0x1FFF)
AnnaBridge	172:65be27845400	4130	*/
AnnaBridge	172:65be27845400	4131	__STATIC_INLINE void LL_RCC_PLL3_SetFRACN(uint32_t FRACN)
AnnaBridge	172:65be27845400	4132	{
AnnaBridge	172:65be27845400	4133	MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, FRACN << RCC_PLL3FRACR_FRACN3_Pos);
AnnaBridge	172:65be27845400	4134	}
AnnaBridge	172:65be27845400	4135
AnnaBridge	172:65be27845400	4136
AnnaBridge	172:65be27845400	4137	/**
AnnaBridge	172:65be27845400	4138	* @}
AnnaBridge	172:65be27845400	4139	*/
AnnaBridge	172:65be27845400	4140
AnnaBridge	172:65be27845400	4141
AnnaBridge	172:65be27845400	4142	/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
AnnaBridge	172:65be27845400	4143	* @{
AnnaBridge	172:65be27845400	4144	*/
AnnaBridge	172:65be27845400	4145
AnnaBridge	172:65be27845400	4146	/**
AnnaBridge	172:65be27845400	4147	* @brief Clear LSI ready interrupt flag
AnnaBridge	172:65be27845400	4148	* @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY
AnnaBridge	172:65be27845400	4149	* @retval None
AnnaBridge	172:65be27845400	4150	*/
AnnaBridge	172:65be27845400	4151	__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
AnnaBridge	172:65be27845400	4152	{
AnnaBridge	172:65be27845400	4153	SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);
AnnaBridge	172:65be27845400	4154	}
AnnaBridge	172:65be27845400	4155
AnnaBridge	172:65be27845400	4156	/**
AnnaBridge	172:65be27845400	4157	* @brief Clear LSE ready interrupt flag
AnnaBridge	172:65be27845400	4158	* @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY
AnnaBridge	172:65be27845400	4159	* @retval None
AnnaBridge	172:65be27845400	4160	*/
AnnaBridge	172:65be27845400	4161	__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
AnnaBridge	172:65be27845400	4162	{
AnnaBridge	172:65be27845400	4163	SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
AnnaBridge	172:65be27845400	4164	}
AnnaBridge	172:65be27845400	4165
AnnaBridge	172:65be27845400	4166	/**
AnnaBridge	172:65be27845400	4167	* @brief Clear HSI ready interrupt flag
AnnaBridge	172:65be27845400	4168	* @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY
AnnaBridge	172:65be27845400	4169	* @retval None
AnnaBridge	172:65be27845400	4170	*/
AnnaBridge	172:65be27845400	4171	__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
AnnaBridge	172:65be27845400	4172	{
AnnaBridge	172:65be27845400	4173	SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
AnnaBridge	172:65be27845400	4174	}
AnnaBridge	172:65be27845400	4175
AnnaBridge	172:65be27845400	4176	/**
AnnaBridge	172:65be27845400	4177	* @brief Clear HSE ready interrupt flag
AnnaBridge	172:65be27845400	4178	* @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY
AnnaBridge	172:65be27845400	4179	* @retval None
AnnaBridge	172:65be27845400	4180	*/
AnnaBridge	172:65be27845400	4181	__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
AnnaBridge	172:65be27845400	4182	{
AnnaBridge	172:65be27845400	4183	SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
AnnaBridge	172:65be27845400	4184	}
AnnaBridge	172:65be27845400	4185
AnnaBridge	172:65be27845400	4186	/**
AnnaBridge	172:65be27845400	4187	* @brief Clear CSI ready interrupt flag
AnnaBridge	172:65be27845400	4188	* @rmtoll CICR CSIRDYC LL_RCC_ClearFlag_CSIRDY
AnnaBridge	172:65be27845400	4189	* @retval None
AnnaBridge	172:65be27845400	4190	*/
AnnaBridge	172:65be27845400	4191	__STATIC_INLINE void LL_RCC_ClearFlag_CSIRDY(void)
AnnaBridge	172:65be27845400	4192	{
AnnaBridge	172:65be27845400	4193	SET_BIT(RCC->CICR, RCC_CICR_CSIRDYC);
AnnaBridge	172:65be27845400	4194	}
AnnaBridge	172:65be27845400	4195
AnnaBridge	172:65be27845400	4196	/**
AnnaBridge	172:65be27845400	4197	* @brief Clear HSI48 ready interrupt flag
AnnaBridge	172:65be27845400	4198	* @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY
AnnaBridge	172:65be27845400	4199	* @retval None
AnnaBridge	172:65be27845400	4200	*/
AnnaBridge	172:65be27845400	4201	__STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
AnnaBridge	172:65be27845400	4202	{
AnnaBridge	172:65be27845400	4203	SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);
AnnaBridge	172:65be27845400	4204	}
AnnaBridge	172:65be27845400	4205
AnnaBridge	172:65be27845400	4206	/**
AnnaBridge	172:65be27845400	4207	* @brief Clear PLL1 ready interrupt flag
AnnaBridge	172:65be27845400	4208	* @rmtoll CICR PLL1RDYC LL_RCC_ClearFlag_PLL1RDY
AnnaBridge	172:65be27845400	4209	* @retval None
AnnaBridge	172:65be27845400	4210	*/
AnnaBridge	172:65be27845400	4211	__STATIC_INLINE void LL_RCC_ClearFlag_PLL1RDY(void)
AnnaBridge	172:65be27845400	4212	{
AnnaBridge	172:65be27845400	4213	SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);
AnnaBridge	172:65be27845400	4214	}
AnnaBridge	172:65be27845400	4215
AnnaBridge	172:65be27845400	4216	/**
AnnaBridge	172:65be27845400	4217	* @brief Clear PLL2 ready interrupt flag
AnnaBridge	172:65be27845400	4218	* @rmtoll CICR PLL2RDYC LL_RCC_ClearFlag_PLL2RDY
AnnaBridge	172:65be27845400	4219	* @retval None
AnnaBridge	172:65be27845400	4220	*/
AnnaBridge	172:65be27845400	4221	__STATIC_INLINE void LL_RCC_ClearFlag_PLL2RDY(void)
AnnaBridge	172:65be27845400	4222	{
AnnaBridge	172:65be27845400	4223	SET_BIT(RCC->CICR, RCC_CICR_PLL2RDYC);
AnnaBridge	172:65be27845400	4224	}
AnnaBridge	172:65be27845400	4225
AnnaBridge	172:65be27845400	4226	/**
AnnaBridge	172:65be27845400	4227	* @brief Clear PLL3 ready interrupt flag
AnnaBridge	172:65be27845400	4228	* @rmtoll CICR PLL3RDYC LL_RCC_ClearFlag_PLL3RDY
AnnaBridge	172:65be27845400	4229	* @retval None
AnnaBridge	172:65be27845400	4230	*/
AnnaBridge	172:65be27845400	4231	__STATIC_INLINE void LL_RCC_ClearFlag_PLL3RDY(void)
AnnaBridge	172:65be27845400	4232	{
AnnaBridge	172:65be27845400	4233	SET_BIT(RCC->CICR, RCC_CICR_PLL3RDYC);
AnnaBridge	172:65be27845400	4234	}
AnnaBridge	172:65be27845400	4235
AnnaBridge	172:65be27845400	4236	/**
AnnaBridge	172:65be27845400	4237	* @brief Clear LSE Clock security system interrupt flag
AnnaBridge	172:65be27845400	4238	* @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS
AnnaBridge	172:65be27845400	4239	* @retval None
AnnaBridge	172:65be27845400	4240	*/
AnnaBridge	172:65be27845400	4241	__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
AnnaBridge	172:65be27845400	4242	{
AnnaBridge	172:65be27845400	4243	SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);
AnnaBridge	172:65be27845400	4244	}
AnnaBridge	172:65be27845400	4245
AnnaBridge	172:65be27845400	4246	/**
AnnaBridge	172:65be27845400	4247	* @brief Clear HSE Clock security system interrupt flag
AnnaBridge	172:65be27845400	4248	* @rmtoll CICR HSECSSC LL_RCC_ClearFlag_HSECSS
AnnaBridge	172:65be27845400	4249	* @retval None
AnnaBridge	172:65be27845400	4250	*/
AnnaBridge	172:65be27845400	4251	__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
AnnaBridge	172:65be27845400	4252	{
AnnaBridge	172:65be27845400	4253	SET_BIT(RCC->CICR, RCC_CICR_HSECSSC);
AnnaBridge	172:65be27845400	4254	}
AnnaBridge	172:65be27845400	4255
AnnaBridge	172:65be27845400	4256	/**
AnnaBridge	172:65be27845400	4257	* @brief Check if LSI ready interrupt occurred or not
AnnaBridge	172:65be27845400	4258	* @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
AnnaBridge	172:65be27845400	4259	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4260	*/
AnnaBridge	172:65be27845400	4261	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
AnnaBridge	172:65be27845400	4262	{
AnnaBridge	172:65be27845400	4263	return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF))?1UL:0UL);
AnnaBridge	172:65be27845400	4264	}
AnnaBridge	172:65be27845400	4265
AnnaBridge	172:65be27845400	4266	/**
AnnaBridge	172:65be27845400	4267	* @brief Check if LSE ready interrupt occurred or not
AnnaBridge	172:65be27845400	4268	* @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY
AnnaBridge	172:65be27845400	4269	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4270	*/
AnnaBridge	172:65be27845400	4271	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
AnnaBridge	172:65be27845400	4272	{
AnnaBridge	172:65be27845400	4273	return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF))?1UL:0UL);
AnnaBridge	172:65be27845400	4274	}
AnnaBridge	172:65be27845400	4275
AnnaBridge	172:65be27845400	4276	/**
AnnaBridge	172:65be27845400	4277	* @brief Check if HSI ready interrupt occurred or not
AnnaBridge	172:65be27845400	4278	* @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
AnnaBridge	172:65be27845400	4279	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4280	*/
AnnaBridge	172:65be27845400	4281	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
AnnaBridge	172:65be27845400	4282	{
AnnaBridge	172:65be27845400	4283	return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF))?1UL:0UL);
AnnaBridge	172:65be27845400	4284	}
AnnaBridge	172:65be27845400	4285
AnnaBridge	172:65be27845400	4286	/**
AnnaBridge	172:65be27845400	4287	* @brief Check if HSE ready interrupt occurred or not
AnnaBridge	172:65be27845400	4288	* @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY
AnnaBridge	172:65be27845400	4289	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4290	*/
AnnaBridge	172:65be27845400	4291	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
AnnaBridge	172:65be27845400	4292	{
AnnaBridge	172:65be27845400	4293	return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF))?1UL:0UL);
AnnaBridge	172:65be27845400	4294	}
AnnaBridge	172:65be27845400	4295
AnnaBridge	172:65be27845400	4296	/**
AnnaBridge	172:65be27845400	4297	* @brief Check if CSI ready interrupt occurred or not
AnnaBridge	172:65be27845400	4298	* @rmtoll CIFR CSIRDYF LL_RCC_IsActiveFlag_CSIRDY
AnnaBridge	172:65be27845400	4299	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4300	*/
AnnaBridge	172:65be27845400	4301	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CSIRDY(void)
AnnaBridge	172:65be27845400	4302	{
AnnaBridge	172:65be27845400	4303	return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSIRDYF) == (RCC_CIFR_CSIRDYF))?1UL:0UL);
AnnaBridge	172:65be27845400	4304	}
AnnaBridge	172:65be27845400	4305
AnnaBridge	172:65be27845400	4306	/**
AnnaBridge	172:65be27845400	4307	* @brief Check if HSI48 ready interrupt occurred or not
AnnaBridge	172:65be27845400	4308	* @rmtoll CIFR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY
AnnaBridge	172:65be27845400	4309	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4310	*/
AnnaBridge	172:65be27845400	4311	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
AnnaBridge	172:65be27845400	4312	{
AnnaBridge	172:65be27845400	4313	return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF))?1UL:0UL);
AnnaBridge	172:65be27845400	4314	}
AnnaBridge	172:65be27845400	4315
AnnaBridge	172:65be27845400	4316	/**
AnnaBridge	172:65be27845400	4317	* @brief Check if PLL1 ready interrupt occurred or not
AnnaBridge	172:65be27845400	4318	* @rmtoll CIFR PLLRDYF LL_RCC_IsActiveFlag_PLL1RDY
AnnaBridge	172:65be27845400	4319	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4320	*/
AnnaBridge	172:65be27845400	4321	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL1RDY(void)
AnnaBridge	172:65be27845400	4322	{
AnnaBridge	172:65be27845400	4323	return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF))?1UL:0UL);
AnnaBridge	172:65be27845400	4324	}
AnnaBridge	172:65be27845400	4325
AnnaBridge	172:65be27845400	4326	/**
AnnaBridge	172:65be27845400	4327	* @brief Check if PLL2 ready interrupt occurred or not
AnnaBridge	172:65be27845400	4328	* @rmtoll CIFR PLL2RDYF LL_RCC_IsActiveFlag_PLL2RDY
AnnaBridge	172:65be27845400	4329	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4330	*/
AnnaBridge	172:65be27845400	4331	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL2RDY(void)
AnnaBridge	172:65be27845400	4332	{
AnnaBridge	172:65be27845400	4333	return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL2RDYF) == (RCC_CIFR_PLL2RDYF))?1UL:0UL);
AnnaBridge	172:65be27845400	4334	}
AnnaBridge	172:65be27845400	4335
AnnaBridge	172:65be27845400	4336	/**
AnnaBridge	172:65be27845400	4337	* @brief Check if PLL3 ready interrupt occurred or not
AnnaBridge	172:65be27845400	4338	* @rmtoll CIFR PLL3RDYF LL_RCC_IsActiveFlag_PLL3RDY
AnnaBridge	172:65be27845400	4339	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4340	*/
AnnaBridge	172:65be27845400	4341	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL3RDY(void)
AnnaBridge	172:65be27845400	4342	{
AnnaBridge	172:65be27845400	4343	return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL3RDYF) == (RCC_CIFR_PLL3RDYF))?1UL:0UL);
AnnaBridge	172:65be27845400	4344	}
AnnaBridge	172:65be27845400	4345
AnnaBridge	172:65be27845400	4346	/**
AnnaBridge	172:65be27845400	4347	* @brief Check if LSE Clock security system interrupt occurred or not
AnnaBridge	172:65be27845400	4348	* @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS
AnnaBridge	172:65be27845400	4349	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4350	*/
AnnaBridge	172:65be27845400	4351	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
AnnaBridge	172:65be27845400	4352	{
AnnaBridge	172:65be27845400	4353	return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF))?1UL:0UL);
AnnaBridge	172:65be27845400	4354	}
AnnaBridge	172:65be27845400	4355
AnnaBridge	172:65be27845400	4356	/**
AnnaBridge	172:65be27845400	4357	* @brief Check if HSE Clock security system interrupt occurred or not
AnnaBridge	172:65be27845400	4358	* @rmtoll CIFR HSECSSF LL_RCC_IsActiveFlag_HSECSS
AnnaBridge	172:65be27845400	4359	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4360	*/
AnnaBridge	172:65be27845400	4361	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
AnnaBridge	172:65be27845400	4362	{
AnnaBridge	172:65be27845400	4363	return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSECSSF) == (RCC_CIFR_HSECSSF))?1UL:0UL);
AnnaBridge	172:65be27845400	4364	}
AnnaBridge	172:65be27845400	4365
AnnaBridge	172:65be27845400	4366	/**
AnnaBridge	172:65be27845400	4367	* @brief Check if RCC flag Low Power D1 reset is set or not.
AnnaBridge	172:65be27845400	4368	* @rmtoll RSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST (*)\n
AnnaBridge	172:65be27845400	4369	* RSR LPWR1RSTF LL_RCC_IsActiveFlag_LPWRRST (**)
AnnaBridge	172:65be27845400	4370	*
AnnaBridge	172:65be27845400	4371	* (*) Only available for single core devices
AnnaBridge	172:65be27845400	4372	* (**) Only available for Dual core devices
AnnaBridge	172:65be27845400	4373	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4374	*/
AnnaBridge	172:65be27845400	4375	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
AnnaBridge	172:65be27845400	4376	{
AnnaBridge	172:65be27845400	4377	return ((READ_BIT(RCC->RSR, RCC_RSR_LPWRRSTF) == (RCC_RSR_LPWRRSTF))?1UL:0UL);
AnnaBridge	172:65be27845400	4378	}
AnnaBridge	172:65be27845400	4379
AnnaBridge	172:65be27845400	4380
AnnaBridge	172:65be27845400	4381	/**
AnnaBridge	172:65be27845400	4382	* @brief Check if RCC flag Window Watchdog 1 reset is set or not.
AnnaBridge	172:65be27845400	4383	* @rmtoll RSR WWDG1RSTF LL_RCC_IsActiveFlag_WWDG1RST
AnnaBridge	172:65be27845400	4384	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4385	*/
AnnaBridge	172:65be27845400	4386	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDG1RST(void)
AnnaBridge	172:65be27845400	4387	{
AnnaBridge	172:65be27845400	4388	return ((READ_BIT(RCC->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF))?1UL:0UL);
AnnaBridge	172:65be27845400	4389	}
AnnaBridge	172:65be27845400	4390
AnnaBridge	172:65be27845400	4391
AnnaBridge	172:65be27845400	4392	/**
AnnaBridge	172:65be27845400	4393	* @brief Check if RCC flag Independent Watchdog 1 reset is set or not.
AnnaBridge	172:65be27845400	4394	* @rmtoll RSR IWDG1RSTF LL_RCC_IsActiveFlag_IWDG1RST
AnnaBridge	172:65be27845400	4395	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4396	*/
AnnaBridge	172:65be27845400	4397	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDG1RST(void)
AnnaBridge	172:65be27845400	4398	{
AnnaBridge	172:65be27845400	4399	return ((READ_BIT(RCC->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF))?1UL:0UL);
AnnaBridge	172:65be27845400	4400	}
AnnaBridge	172:65be27845400	4401
AnnaBridge	172:65be27845400	4402	/**
AnnaBridge	172:65be27845400	4403	* @brief Check if RCC flag Software reset is set or not.
AnnaBridge	172:65be27845400	4404	* @rmtoll RSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST (*)\n
AnnaBridge	172:65be27845400	4405	* RSR SFT1RSTF LL_RCC_IsActiveFlag_SFTRST (**)
AnnaBridge	172:65be27845400	4406	*
AnnaBridge	172:65be27845400	4407	* (*) Only available for single core devices
AnnaBridge	172:65be27845400	4408	* (**) Only available for Dual core devices
AnnaBridge	172:65be27845400	4409	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4410	*/
AnnaBridge	172:65be27845400	4411	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
AnnaBridge	172:65be27845400	4412	{
AnnaBridge	172:65be27845400	4413	return ((READ_BIT(RCC->RSR, RCC_RSR_SFTRSTF) == (RCC_RSR_SFTRSTF))?1UL:0UL);
AnnaBridge	172:65be27845400	4414	}
AnnaBridge	172:65be27845400	4415
AnnaBridge	172:65be27845400	4416
AnnaBridge	172:65be27845400	4417	/**
AnnaBridge	172:65be27845400	4418	* @brief Check if RCC flag POR/PDR reset is set or not.
AnnaBridge	172:65be27845400	4419	* @rmtoll RSR PORRSTF LL_RCC_IsActiveFlag_PORRST
AnnaBridge	172:65be27845400	4420	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4421	*/
AnnaBridge	172:65be27845400	4422	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
AnnaBridge	172:65be27845400	4423	{
AnnaBridge	172:65be27845400	4424	return ((READ_BIT(RCC->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF))?1UL:0UL);
AnnaBridge	172:65be27845400	4425	}
AnnaBridge	172:65be27845400	4426
AnnaBridge	172:65be27845400	4427	/**
AnnaBridge	172:65be27845400	4428	* @brief Check if RCC flag Pin reset is set or not.
AnnaBridge	172:65be27845400	4429	* @rmtoll RSR PINRSTF LL_RCC_IsActiveFlag_PINRST
AnnaBridge	172:65be27845400	4430	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4431	*/
AnnaBridge	172:65be27845400	4432	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
AnnaBridge	172:65be27845400	4433	{
AnnaBridge	172:65be27845400	4434	return ((READ_BIT(RCC->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF))?1UL:0UL);
AnnaBridge	172:65be27845400	4435	}
AnnaBridge	172:65be27845400	4436
AnnaBridge	172:65be27845400	4437	/**
AnnaBridge	172:65be27845400	4438	* @brief Check if RCC flag BOR reset is set or not.
AnnaBridge	172:65be27845400	4439	* @rmtoll RSR BORRSTF LL_RCC_IsActiveFlag_BORRST
AnnaBridge	172:65be27845400	4440	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4441	*/
AnnaBridge	172:65be27845400	4442	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
AnnaBridge	172:65be27845400	4443	{
AnnaBridge	172:65be27845400	4444	return ((READ_BIT(RCC->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF))?1UL:0UL);
AnnaBridge	172:65be27845400	4445	}
AnnaBridge	172:65be27845400	4446
AnnaBridge	172:65be27845400	4447	/**
AnnaBridge	172:65be27845400	4448	* @brief Check if RCC flag D1 reset is set or not.
AnnaBridge	172:65be27845400	4449	* @rmtoll RSR D1RSTF LL_RCC_IsActiveFlag_D1RST
AnnaBridge	172:65be27845400	4450	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4451	*/
AnnaBridge	172:65be27845400	4452	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_D1RST(void)
AnnaBridge	172:65be27845400	4453	{
AnnaBridge	172:65be27845400	4454	return ((READ_BIT(RCC->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF))?1UL:0UL);
AnnaBridge	172:65be27845400	4455	}
AnnaBridge	172:65be27845400	4456
AnnaBridge	172:65be27845400	4457	/**
AnnaBridge	172:65be27845400	4458	* @brief Check if RCC flag D2 reset is set or not.
AnnaBridge	172:65be27845400	4459	* @rmtoll RSR D2RSTF LL_RCC_IsActiveFlag_D2RST
AnnaBridge	172:65be27845400	4460	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4461	*/
AnnaBridge	172:65be27845400	4462	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_D2RST(void)
AnnaBridge	172:65be27845400	4463	{
AnnaBridge	172:65be27845400	4464	return ((READ_BIT(RCC->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF))?1UL:0UL);
AnnaBridge	172:65be27845400	4465	}
AnnaBridge	172:65be27845400	4466
AnnaBridge	172:65be27845400	4467	/**
AnnaBridge	172:65be27845400	4468	* @brief Check if RCC flag CPU reset is set or not.
AnnaBridge	172:65be27845400	4469	* @rmtoll RSR CPURSTF LL_RCC_IsActiveFlag_CPURST (*)\n
AnnaBridge	172:65be27845400	4470	* RSR C1RSTF LL_RCC_IsActiveFlag_CPURST (**)
AnnaBridge	172:65be27845400	4471	*
AnnaBridge	172:65be27845400	4472	* (*) Only available for single core devices
AnnaBridge	172:65be27845400	4473	* (**) Only available for Dual core devices
AnnaBridge	172:65be27845400	4474	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4475	*/
AnnaBridge	172:65be27845400	4476	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CPURST(void)
AnnaBridge	172:65be27845400	4477	{
AnnaBridge	172:65be27845400	4478	return ((READ_BIT(RCC->RSR, RCC_RSR_CPURSTF) == (RCC_RSR_CPURSTF))?1UL:0UL);
AnnaBridge	172:65be27845400	4479	}
AnnaBridge	172:65be27845400	4480
AnnaBridge	172:65be27845400	4481
AnnaBridge	172:65be27845400	4482	/**
AnnaBridge	172:65be27845400	4483	* @brief Set RMVF bit to clear all reset flags.
AnnaBridge	172:65be27845400	4484	* @rmtoll RSR RMVF LL_RCC_ClearResetFlags
AnnaBridge	172:65be27845400	4485	* @retval None
AnnaBridge	172:65be27845400	4486	*/
AnnaBridge	172:65be27845400	4487	__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
AnnaBridge	172:65be27845400	4488	{
AnnaBridge	172:65be27845400	4489	SET_BIT(RCC->RSR, RCC_RSR_RMVF);
AnnaBridge	172:65be27845400	4490	}
AnnaBridge	172:65be27845400	4491
AnnaBridge	172:65be27845400	4492	/**
AnnaBridge	172:65be27845400	4493	* @}
AnnaBridge	172:65be27845400	4494	*/
AnnaBridge	172:65be27845400	4495
AnnaBridge	172:65be27845400	4496	/** @defgroup RCC_LL_EF_IT_Management IT Management
AnnaBridge	172:65be27845400	4497	* @{
AnnaBridge	172:65be27845400	4498	*/
AnnaBridge	172:65be27845400	4499
AnnaBridge	172:65be27845400	4500	/**
AnnaBridge	172:65be27845400	4501	* @brief Enable LSI ready interrupt
AnnaBridge	172:65be27845400	4502	* @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY
AnnaBridge	172:65be27845400	4503	* @retval None
AnnaBridge	172:65be27845400	4504	*/
AnnaBridge	172:65be27845400	4505	__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
AnnaBridge	172:65be27845400	4506	{
AnnaBridge	172:65be27845400	4507	SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
AnnaBridge	172:65be27845400	4508	}
AnnaBridge	172:65be27845400	4509
AnnaBridge	172:65be27845400	4510	/**
AnnaBridge	172:65be27845400	4511	* @brief Enable LSE ready interrupt
AnnaBridge	172:65be27845400	4512	* @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY
AnnaBridge	172:65be27845400	4513	* @retval None
AnnaBridge	172:65be27845400	4514	*/
AnnaBridge	172:65be27845400	4515	__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
AnnaBridge	172:65be27845400	4516	{
AnnaBridge	172:65be27845400	4517	SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
AnnaBridge	172:65be27845400	4518	}
AnnaBridge	172:65be27845400	4519
AnnaBridge	172:65be27845400	4520	/**
AnnaBridge	172:65be27845400	4521	* @brief Enable HSI ready interrupt
AnnaBridge	172:65be27845400	4522	* @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY
AnnaBridge	172:65be27845400	4523	* @retval None
AnnaBridge	172:65be27845400	4524	*/
AnnaBridge	172:65be27845400	4525	__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
AnnaBridge	172:65be27845400	4526	{
AnnaBridge	172:65be27845400	4527	SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
AnnaBridge	172:65be27845400	4528	}
AnnaBridge	172:65be27845400	4529
AnnaBridge	172:65be27845400	4530	/**
AnnaBridge	172:65be27845400	4531	* @brief Enable HSE ready interrupt
AnnaBridge	172:65be27845400	4532	* @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY
AnnaBridge	172:65be27845400	4533	* @retval None
AnnaBridge	172:65be27845400	4534	*/
AnnaBridge	172:65be27845400	4535	__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
AnnaBridge	172:65be27845400	4536	{
AnnaBridge	172:65be27845400	4537	SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
AnnaBridge	172:65be27845400	4538	}
AnnaBridge	172:65be27845400	4539
AnnaBridge	172:65be27845400	4540	/**
AnnaBridge	172:65be27845400	4541	* @brief Enable CSI ready interrupt
AnnaBridge	172:65be27845400	4542	* @rmtoll CIER CSIRDYIE LL_RCC_EnableIT_CSIRDY
AnnaBridge	172:65be27845400	4543	* @retval None
AnnaBridge	172:65be27845400	4544	*/
AnnaBridge	172:65be27845400	4545	__STATIC_INLINE void LL_RCC_EnableIT_CSIRDY(void)
AnnaBridge	172:65be27845400	4546	{
AnnaBridge	172:65be27845400	4547	SET_BIT(RCC->CIER, RCC_CIER_CSIRDYIE);
AnnaBridge	172:65be27845400	4548	}
AnnaBridge	172:65be27845400	4549
AnnaBridge	172:65be27845400	4550	/**
AnnaBridge	172:65be27845400	4551	* @brief Enable HSI48 ready interrupt
AnnaBridge	172:65be27845400	4552	* @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY
AnnaBridge	172:65be27845400	4553	* @retval None
AnnaBridge	172:65be27845400	4554	*/
AnnaBridge	172:65be27845400	4555	__STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
AnnaBridge	172:65be27845400	4556	{
AnnaBridge	172:65be27845400	4557	SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
AnnaBridge	172:65be27845400	4558	}
AnnaBridge	172:65be27845400	4559
AnnaBridge	172:65be27845400	4560	/**
AnnaBridge	172:65be27845400	4561	* @brief Enable PLL1 ready interrupt
AnnaBridge	172:65be27845400	4562	* @rmtoll CIER PLL1RDYIE LL_RCC_EnableIT_PLL1RDY
AnnaBridge	172:65be27845400	4563	* @retval None
AnnaBridge	172:65be27845400	4564	*/
AnnaBridge	172:65be27845400	4565	__STATIC_INLINE void LL_RCC_EnableIT_PLL1RDY(void)
AnnaBridge	172:65be27845400	4566	{
AnnaBridge	172:65be27845400	4567	SET_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE);
AnnaBridge	172:65be27845400	4568	}
AnnaBridge	172:65be27845400	4569
AnnaBridge	172:65be27845400	4570	/**
AnnaBridge	172:65be27845400	4571	* @brief Enable PLL2 ready interrupt
AnnaBridge	172:65be27845400	4572	* @rmtoll CIER PLL2RDYIE LL_RCC_EnableIT_PLL2RDY
AnnaBridge	172:65be27845400	4573	* @retval None
AnnaBridge	172:65be27845400	4574	*/
AnnaBridge	172:65be27845400	4575	__STATIC_INLINE void LL_RCC_EnableIT_PLL2RDY(void)
AnnaBridge	172:65be27845400	4576	{
AnnaBridge	172:65be27845400	4577	SET_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE);
AnnaBridge	172:65be27845400	4578	}
AnnaBridge	172:65be27845400	4579
AnnaBridge	172:65be27845400	4580	/**
AnnaBridge	172:65be27845400	4581	* @brief Enable PLL3 ready interrupt
AnnaBridge	172:65be27845400	4582	* @rmtoll CIER PLL3RDYIE LL_RCC_EnableIT_PLL3RDY
AnnaBridge	172:65be27845400	4583	* @retval None
AnnaBridge	172:65be27845400	4584	*/
AnnaBridge	172:65be27845400	4585	__STATIC_INLINE void LL_RCC_EnableIT_PLL3RDY(void)
AnnaBridge	172:65be27845400	4586	{
AnnaBridge	172:65be27845400	4587	SET_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE);
AnnaBridge	172:65be27845400	4588	}
AnnaBridge	172:65be27845400	4589
AnnaBridge	172:65be27845400	4590	/**
AnnaBridge	172:65be27845400	4591	* @brief Enable LSECSS interrupt
AnnaBridge	172:65be27845400	4592	* @rmtoll CIER LSECSSIE LL_RCC_EnableIT_LSECSS
AnnaBridge	172:65be27845400	4593	* @retval None
AnnaBridge	172:65be27845400	4594	*/
AnnaBridge	172:65be27845400	4595	__STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
AnnaBridge	172:65be27845400	4596	{
AnnaBridge	172:65be27845400	4597	SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
AnnaBridge	172:65be27845400	4598	}
AnnaBridge	172:65be27845400	4599
AnnaBridge	172:65be27845400	4600	/**
AnnaBridge	172:65be27845400	4601	* @brief Disable LSI ready interrupt
AnnaBridge	172:65be27845400	4602	* @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY
AnnaBridge	172:65be27845400	4603	* @retval None
AnnaBridge	172:65be27845400	4604	*/
AnnaBridge	172:65be27845400	4605	__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
AnnaBridge	172:65be27845400	4606	{
AnnaBridge	172:65be27845400	4607	CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
AnnaBridge	172:65be27845400	4608	}
AnnaBridge	172:65be27845400	4609
AnnaBridge	172:65be27845400	4610	/**
AnnaBridge	172:65be27845400	4611	* @brief Disable LSE ready interrupt
AnnaBridge	172:65be27845400	4612	* @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY
AnnaBridge	172:65be27845400	4613	* @retval None
AnnaBridge	172:65be27845400	4614	*/
AnnaBridge	172:65be27845400	4615	__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
AnnaBridge	172:65be27845400	4616	{
AnnaBridge	172:65be27845400	4617	CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
AnnaBridge	172:65be27845400	4618	}
AnnaBridge	172:65be27845400	4619
AnnaBridge	172:65be27845400	4620	/**
AnnaBridge	172:65be27845400	4621	* @brief Disable HSI ready interrupt
AnnaBridge	172:65be27845400	4622	* @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY
AnnaBridge	172:65be27845400	4623	* @retval None
AnnaBridge	172:65be27845400	4624	*/
AnnaBridge	172:65be27845400	4625	__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
AnnaBridge	172:65be27845400	4626	{
AnnaBridge	172:65be27845400	4627	CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
AnnaBridge	172:65be27845400	4628	}
AnnaBridge	172:65be27845400	4629
AnnaBridge	172:65be27845400	4630	/**
AnnaBridge	172:65be27845400	4631	* @brief Disable HSE ready interrupt
AnnaBridge	172:65be27845400	4632	* @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY
AnnaBridge	172:65be27845400	4633	* @retval None
AnnaBridge	172:65be27845400	4634	*/
AnnaBridge	172:65be27845400	4635	__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
AnnaBridge	172:65be27845400	4636	{
AnnaBridge	172:65be27845400	4637	CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
AnnaBridge	172:65be27845400	4638	}
AnnaBridge	172:65be27845400	4639
AnnaBridge	172:65be27845400	4640	/**
AnnaBridge	172:65be27845400	4641	* @brief Disable CSI ready interrupt
AnnaBridge	172:65be27845400	4642	* @rmtoll CIER CSIRDYIE LL_RCC_DisableIT_CSIRDY
AnnaBridge	172:65be27845400	4643	* @retval None
AnnaBridge	172:65be27845400	4644	*/
AnnaBridge	172:65be27845400	4645	__STATIC_INLINE void LL_RCC_DisableIT_CSIRDY(void)
AnnaBridge	172:65be27845400	4646	{
AnnaBridge	172:65be27845400	4647	CLEAR_BIT(RCC->CIER, RCC_CIER_CSIRDYIE);
AnnaBridge	172:65be27845400	4648	}
AnnaBridge	172:65be27845400	4649
AnnaBridge	172:65be27845400	4650	/**
AnnaBridge	172:65be27845400	4651	* @brief Disable HSI48 ready interrupt
AnnaBridge	172:65be27845400	4652	* @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY
AnnaBridge	172:65be27845400	4653	* @retval None
AnnaBridge	172:65be27845400	4654	*/
AnnaBridge	172:65be27845400	4655	__STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
AnnaBridge	172:65be27845400	4656	{
AnnaBridge	172:65be27845400	4657	CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
AnnaBridge	172:65be27845400	4658	}
AnnaBridge	172:65be27845400	4659
AnnaBridge	172:65be27845400	4660	/**
AnnaBridge	172:65be27845400	4661	* @brief Disable PLL1 ready interrupt
AnnaBridge	172:65be27845400	4662	* @rmtoll CIER PLL1RDYIE LL_RCC_DisableIT_PLL1RDY
AnnaBridge	172:65be27845400	4663	* @retval None
AnnaBridge	172:65be27845400	4664	*/
AnnaBridge	172:65be27845400	4665	__STATIC_INLINE void LL_RCC_DisableIT_PLL1RDY(void)
AnnaBridge	172:65be27845400	4666	{
AnnaBridge	172:65be27845400	4667	CLEAR_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE);
AnnaBridge	172:65be27845400	4668	}
AnnaBridge	172:65be27845400	4669
AnnaBridge	172:65be27845400	4670	/**
AnnaBridge	172:65be27845400	4671	* @brief Disable PLL2 ready interrupt
AnnaBridge	172:65be27845400	4672	* @rmtoll CIER PLL2RDYIE LL_RCC_DisableIT_PLL2RDY
AnnaBridge	172:65be27845400	4673	* @retval None
AnnaBridge	172:65be27845400	4674	*/
AnnaBridge	172:65be27845400	4675	__STATIC_INLINE void LL_RCC_DisableIT_PLL2RDY(void)
AnnaBridge	172:65be27845400	4676	{
AnnaBridge	172:65be27845400	4677	CLEAR_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE);
AnnaBridge	172:65be27845400	4678	}
AnnaBridge	172:65be27845400	4679
AnnaBridge	172:65be27845400	4680	/**
AnnaBridge	172:65be27845400	4681	* @brief Disable PLL3 ready interrupt
AnnaBridge	172:65be27845400	4682	* @rmtoll CIER PLL3RDYIE LL_RCC_DisableIT_PLL3RDY
AnnaBridge	172:65be27845400	4683	* @retval None
AnnaBridge	172:65be27845400	4684	*/
AnnaBridge	172:65be27845400	4685	__STATIC_INLINE void LL_RCC_DisableIT_PLL3RDY(void)
AnnaBridge	172:65be27845400	4686	{
AnnaBridge	172:65be27845400	4687	CLEAR_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE);
AnnaBridge	172:65be27845400	4688	}
AnnaBridge	172:65be27845400	4689
AnnaBridge	172:65be27845400	4690	/**
AnnaBridge	172:65be27845400	4691	* @brief Disable LSECSS interrupt
AnnaBridge	172:65be27845400	4692	* @rmtoll CIER LSECSSIE LL_RCC_DisableIT_LSECSS
AnnaBridge	172:65be27845400	4693	* @retval None
AnnaBridge	172:65be27845400	4694	*/
AnnaBridge	172:65be27845400	4695	__STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
AnnaBridge	172:65be27845400	4696	{
AnnaBridge	172:65be27845400	4697	CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
AnnaBridge	172:65be27845400	4698	}
AnnaBridge	172:65be27845400	4699
AnnaBridge	172:65be27845400	4700	/**
AnnaBridge	172:65be27845400	4701	* @brief Checks if LSI ready interrupt source is enabled or disabled.
AnnaBridge	172:65be27845400	4702	* @rmtoll CIER LSIRDYIE LL_RCC_IsEnableIT_LSIRDY
AnnaBridge	172:65be27845400	4703	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4704	*/
AnnaBridge	172:65be27845400	4705	__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSIRDY(void)
AnnaBridge	172:65be27845400	4706	{
AnnaBridge	172:65be27845400	4707	return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == RCC_CIER_LSIRDYIE)?1UL:0UL);
AnnaBridge	172:65be27845400	4708	}
AnnaBridge	172:65be27845400	4709
AnnaBridge	172:65be27845400	4710	/**
AnnaBridge	172:65be27845400	4711	* @brief Checks if LSE ready interrupt source is enabled or disabled.
AnnaBridge	172:65be27845400	4712	* @rmtoll CIER LSERDYIE LL_RCC_IsEnableIT_LSERDY
AnnaBridge	172:65be27845400	4713	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4714	*/
AnnaBridge	172:65be27845400	4715	__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSERDY(void)
AnnaBridge	172:65be27845400	4716	{
AnnaBridge	172:65be27845400	4717	return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == RCC_CIER_LSERDYIE)?1UL:0UL);
AnnaBridge	172:65be27845400	4718	}
AnnaBridge	172:65be27845400	4719
AnnaBridge	172:65be27845400	4720	/**
AnnaBridge	172:65be27845400	4721	* @brief Checks if HSI ready interrupt source is enabled or disabled.
AnnaBridge	172:65be27845400	4722	* @rmtoll CIER HSIRDYIE LL_RCC_IsEnableIT_HSIRDY
AnnaBridge	172:65be27845400	4723	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4724	*/
AnnaBridge	172:65be27845400	4725	__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSIRDY(void)
AnnaBridge	172:65be27845400	4726	{
AnnaBridge	172:65be27845400	4727	return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == RCC_CIER_HSIRDYIE)?1UL:0UL);
AnnaBridge	172:65be27845400	4728	}
AnnaBridge	172:65be27845400	4729
AnnaBridge	172:65be27845400	4730	/**
AnnaBridge	172:65be27845400	4731	* @brief Checks if HSE ready interrupt source is enabled or disabled.
AnnaBridge	172:65be27845400	4732	* @rmtoll CIER HSERDYIE LL_RCC_IsEnableIT_HSERDY
AnnaBridge	172:65be27845400	4733	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4734	*/
AnnaBridge	172:65be27845400	4735	__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSERDY(void)
AnnaBridge	172:65be27845400	4736	{
AnnaBridge	172:65be27845400	4737	return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == RCC_CIER_HSERDYIE)?1UL:0UL);
AnnaBridge	172:65be27845400	4738	}
AnnaBridge	172:65be27845400	4739
AnnaBridge	172:65be27845400	4740	/**
AnnaBridge	172:65be27845400	4741	* @brief Checks if CSI ready interrupt source is enabled or disabled.
AnnaBridge	172:65be27845400	4742	* @rmtoll CIER CSIRDYIE LL_RCC_IsEnableIT_CSIRDY
AnnaBridge	172:65be27845400	4743	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4744	*/
AnnaBridge	172:65be27845400	4745	__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_CSIRDY(void)
AnnaBridge	172:65be27845400	4746	{
AnnaBridge	172:65be27845400	4747	return ((READ_BIT(RCC->CIER, RCC_CIER_CSIRDYIE) == RCC_CIER_CSIRDYIE)?1UL:0UL);
AnnaBridge	172:65be27845400	4748	}
AnnaBridge	172:65be27845400	4749
AnnaBridge	172:65be27845400	4750	/**
AnnaBridge	172:65be27845400	4751	* @brief Checks if HSI48 ready interrupt source is enabled or disabled.
AnnaBridge	172:65be27845400	4752	* @rmtoll CIER HSI48RDYIE LL_RCC_IsEnableIT_HSI48RDY
AnnaBridge	172:65be27845400	4753	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4754	*/
AnnaBridge	172:65be27845400	4755	__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSI48RDY(void)
AnnaBridge	172:65be27845400	4756	{
AnnaBridge	172:65be27845400	4757	return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == RCC_CIER_HSI48RDYIE)?1UL:0UL);
AnnaBridge	172:65be27845400	4758	}
AnnaBridge	172:65be27845400	4759
AnnaBridge	172:65be27845400	4760	/**
AnnaBridge	172:65be27845400	4761	* @brief Checks if PLL1 ready interrupt source is enabled or disabled.
AnnaBridge	172:65be27845400	4762	* @rmtoll CIER PLL1RDYIE LL_RCC_IsEnableIT_PLL1RDY
AnnaBridge	172:65be27845400	4763	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4764	*/
AnnaBridge	172:65be27845400	4765	__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL1RDY(void)
AnnaBridge	172:65be27845400	4766	{
AnnaBridge	172:65be27845400	4767	return ((READ_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE) == RCC_CIER_PLL1RDYIE)?1UL:0UL);
AnnaBridge	172:65be27845400	4768	}
AnnaBridge	172:65be27845400	4769
AnnaBridge	172:65be27845400	4770	/**
AnnaBridge	172:65be27845400	4771	* @brief Checks if PLL2 ready interrupt source is enabled or disabled.
AnnaBridge	172:65be27845400	4772	* @rmtoll CIER PLL2RDYIE LL_RCC_IsEnableIT_PLL2RDY
AnnaBridge	172:65be27845400	4773	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4774	*/
AnnaBridge	172:65be27845400	4775	__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL2RDY(void)
AnnaBridge	172:65be27845400	4776	{
AnnaBridge	172:65be27845400	4777	return ((READ_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE) == RCC_CIER_PLL2RDYIE)?1UL:0UL);
AnnaBridge	172:65be27845400	4778	}
AnnaBridge	172:65be27845400	4779
AnnaBridge	172:65be27845400	4780	/**
AnnaBridge	172:65be27845400	4781	* @brief Checks if PLL3 ready interrupt source is enabled or disabled.
AnnaBridge	172:65be27845400	4782	* @rmtoll CIER PLL3RDYIE LL_RCC_IsEnableIT_PLL3RDY
AnnaBridge	172:65be27845400	4783	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4784	*/
AnnaBridge	172:65be27845400	4785	__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL3RDY(void)
AnnaBridge	172:65be27845400	4786	{
AnnaBridge	172:65be27845400	4787	return ((READ_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE) == RCC_CIER_PLL3RDYIE)?1UL:0UL);
AnnaBridge	172:65be27845400	4788	}
AnnaBridge	172:65be27845400	4789
AnnaBridge	172:65be27845400	4790	/**
AnnaBridge	172:65be27845400	4791	* @brief Checks if LSECSS interrupt source is enabled or disabled.
AnnaBridge	172:65be27845400	4792	* @rmtoll CIER LSECSSIE LL_RCC_IsEnableIT_LSECSS
AnnaBridge	172:65be27845400	4793	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4794	*/
AnnaBridge	172:65be27845400	4795	__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSECSS(void)
AnnaBridge	172:65be27845400	4796	{
AnnaBridge	172:65be27845400	4797	return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == RCC_CIER_LSECSSIE)?1UL:0UL);
AnnaBridge	172:65be27845400	4798	}
AnnaBridge	172:65be27845400	4799	/**
AnnaBridge	172:65be27845400	4800	* @}
AnnaBridge	172:65be27845400	4801	*/
AnnaBridge	172:65be27845400	4802
AnnaBridge	172:65be27845400	4803	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	172:65be27845400	4804	/** @defgroup RCC_LL_EF_Init De-initialization function
AnnaBridge	172:65be27845400	4805	* @{
AnnaBridge	172:65be27845400	4806	*/
AnnaBridge	172:65be27845400	4807	void LL_RCC_DeInit(void);
AnnaBridge	172:65be27845400	4808	/**
AnnaBridge	172:65be27845400	4809	* @}
AnnaBridge	172:65be27845400	4810	*/
AnnaBridge	172:65be27845400	4811
AnnaBridge	172:65be27845400	4812	/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
AnnaBridge	172:65be27845400	4813	* @{
AnnaBridge	172:65be27845400	4814	*/
AnnaBridge	172:65be27845400	4815	uint32_t LL_RCC_CalcPLLClockFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACN, uint32_t PQR);
AnnaBridge	172:65be27845400	4816
AnnaBridge	172:65be27845400	4817	void LL_RCC_GetPLL1ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks);
AnnaBridge	172:65be27845400	4818	void LL_RCC_GetPLL2ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks);
AnnaBridge	172:65be27845400	4819	void LL_RCC_GetPLL3ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks);
AnnaBridge	172:65be27845400	4820	void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
AnnaBridge	172:65be27845400	4821
AnnaBridge	172:65be27845400	4822	uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
AnnaBridge	172:65be27845400	4823	uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
AnnaBridge	172:65be27845400	4824	uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
AnnaBridge	172:65be27845400	4825	uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
AnnaBridge	172:65be27845400	4826	uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
AnnaBridge	172:65be27845400	4827	uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
AnnaBridge	172:65be27845400	4828	uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource);
AnnaBridge	172:65be27845400	4829	uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
AnnaBridge	172:65be27845400	4830	uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource);
AnnaBridge	172:65be27845400	4831	uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
AnnaBridge	172:65be27845400	4832	uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);
AnnaBridge	172:65be27845400	4833	uint32_t LL_RCC_GetSPDIFClockFreq(uint32_t SPDIFxSource);
AnnaBridge	172:65be27845400	4834	uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource);
AnnaBridge	172:65be27845400	4835	uint32_t LL_RCC_GetSWPClockFreq(uint32_t SWPxSource);
AnnaBridge	172:65be27845400	4836	uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource);
AnnaBridge	172:65be27845400	4837	uint32_t LL_RCC_GetFMCClockFreq(uint32_t FMCxSource);
AnnaBridge	172:65be27845400	4838	uint32_t LL_RCC_GetQSPIClockFreq(uint32_t QSPIxSource);
AnnaBridge	172:65be27845400	4839	uint32_t LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource);
AnnaBridge	172:65be27845400	4840
AnnaBridge	172:65be27845400	4841
AnnaBridge	172:65be27845400	4842	/**
AnnaBridge	172:65be27845400	4843	* @}
AnnaBridge	172:65be27845400	4844	*/
AnnaBridge	172:65be27845400	4845	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	172:65be27845400	4846
AnnaBridge	172:65be27845400	4847	/**
AnnaBridge	172:65be27845400	4848	* @}
AnnaBridge	172:65be27845400	4849	*/
AnnaBridge	172:65be27845400	4850
AnnaBridge	172:65be27845400	4851	/**
AnnaBridge	172:65be27845400	4852	* @}
AnnaBridge	172:65be27845400	4853	*/
AnnaBridge	172:65be27845400	4854
AnnaBridge	172:65be27845400	4855	/**
AnnaBridge	172:65be27845400	4856	* @}
AnnaBridge	172:65be27845400	4857	*/
AnnaBridge	172:65be27845400	4858	#endif /* defined(RCC) */
AnnaBridge	172:65be27845400	4859
AnnaBridge	172:65be27845400	4860	/**
AnnaBridge	172:65be27845400	4861	* @}
AnnaBridge	172:65be27845400	4862	*/
AnnaBridge	172:65be27845400	4863
AnnaBridge	172:65be27845400	4864	#ifdef __cplusplus
AnnaBridge	172:65be27845400	4865	}
AnnaBridge	172:65be27845400	4866	#endif
AnnaBridge	172:65be27845400	4867
AnnaBridge	172:65be27845400	4868	#endif /* STM32H7xx_LL_RCC_H */
AnnaBridge	172:65be27845400	4869
AnnaBridge	172:65be27845400	4870	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/