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TARGET_NUCLEO_H743ZI/TOOLCHAIN_ARM_STD/stm32h7xx_ll_dma.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	172:65be27845400	1	/**
AnnaBridge	172:65be27845400	2	******************************************************************************
AnnaBridge	172:65be27845400	3	* @file stm32h7xx_ll_dma.h
AnnaBridge	172:65be27845400	4	* @author MCD Application Team
AnnaBridge	172:65be27845400	5	* @brief Header file of DMA LL module.
AnnaBridge	172:65be27845400	6	******************************************************************************
AnnaBridge	172:65be27845400	7	* @attention
AnnaBridge	172:65be27845400	8	*
AnnaBridge	172:65be27845400	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
AnnaBridge	172:65be27845400	10	* All rights reserved.</center></h2>
AnnaBridge	172:65be27845400	11	*
AnnaBridge	172:65be27845400	12	* This software component is licensed by ST under BSD 3-Clause license,
AnnaBridge	172:65be27845400	13	* the "License"; You may not use this file except in compliance with the
AnnaBridge	172:65be27845400	14	* License. You may obtain a copy of the License at:
AnnaBridge	172:65be27845400	15	* opensource.org/licenses/BSD-3-Clause
AnnaBridge	172:65be27845400	16	*
AnnaBridge	172:65be27845400	17	******************************************************************************
AnnaBridge	172:65be27845400	18	*/
AnnaBridge	172:65be27845400	19
AnnaBridge	172:65be27845400	20	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	172:65be27845400	21	#ifndef STM32H7xx_LL_DMA_H
AnnaBridge	172:65be27845400	22	#define STM32H7xx_LL_DMA_H
AnnaBridge	172:65be27845400	23
AnnaBridge	172:65be27845400	24	#ifdef __cplusplus
AnnaBridge	172:65be27845400	25	extern "C" {
AnnaBridge	172:65be27845400	26	#endif
AnnaBridge	172:65be27845400	27
AnnaBridge	172:65be27845400	28	/* Includes ------------------------------------------------------------------*/
AnnaBridge	172:65be27845400	29	#include "stm32h7xx.h"
AnnaBridge	172:65be27845400	30	#include "stm32h7xx_ll_dmamux.h"
AnnaBridge	172:65be27845400	31	/** @addtogroup STM32H7xx_LL_Driver
AnnaBridge	172:65be27845400	32	* @{
AnnaBridge	172:65be27845400	33	*/
AnnaBridge	172:65be27845400	34
AnnaBridge	172:65be27845400	35	#if defined (DMA1) \|\| defined (DMA2)
AnnaBridge	172:65be27845400	36
AnnaBridge	172:65be27845400	37	/** @defgroup DMA_LL DMA
AnnaBridge	172:65be27845400	38	* @{
AnnaBridge	172:65be27845400	39	*/
AnnaBridge	172:65be27845400	40
AnnaBridge	172:65be27845400	41	/* Private types -------------------------------------------------------------*/
AnnaBridge	172:65be27845400	42	/* Private variables ---------------------------------------------------------*/
AnnaBridge	172:65be27845400	43	/** @defgroup DMA_LL_Private_Variables DMA Private Variables
AnnaBridge	172:65be27845400	44	* @{
AnnaBridge	172:65be27845400	45	*/
AnnaBridge	172:65be27845400	46	/* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */
AnnaBridge	172:65be27845400	47	static const uint8_t LL_DMA_STR_OFFSET_TAB[] =
AnnaBridge	172:65be27845400	48	{
AnnaBridge	172:65be27845400	49	(uint8_t)(DMA1_Stream0_BASE - DMA1_BASE),
AnnaBridge	172:65be27845400	50	(uint8_t)(DMA1_Stream1_BASE - DMA1_BASE),
AnnaBridge	172:65be27845400	51	(uint8_t)(DMA1_Stream2_BASE - DMA1_BASE),
AnnaBridge	172:65be27845400	52	(uint8_t)(DMA1_Stream3_BASE - DMA1_BASE),
AnnaBridge	172:65be27845400	53	(uint8_t)(DMA1_Stream4_BASE - DMA1_BASE),
AnnaBridge	172:65be27845400	54	(uint8_t)(DMA1_Stream5_BASE - DMA1_BASE),
AnnaBridge	172:65be27845400	55	(uint8_t)(DMA1_Stream6_BASE - DMA1_BASE),
AnnaBridge	172:65be27845400	56	(uint8_t)(DMA1_Stream7_BASE - DMA1_BASE)
AnnaBridge	172:65be27845400	57	};
AnnaBridge	172:65be27845400	58
AnnaBridge	172:65be27845400	59
AnnaBridge	172:65be27845400	60	/**
AnnaBridge	172:65be27845400	61	* @}
AnnaBridge	172:65be27845400	62	*/
AnnaBridge	172:65be27845400	63
AnnaBridge	172:65be27845400	64	/* Private macros ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	65
AnnaBridge	172:65be27845400	66	/**
AnnaBridge	172:65be27845400	67	* @brief Helper macro to convert DMA Instance DMAx into DMAMUX channel
AnnaBridge	172:65be27845400	68	* @note DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7.
AnnaBridge	172:65be27845400	69	* DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7.
AnnaBridge	172:65be27845400	70	* @param __DMA_INSTANCE__ DMAx
AnnaBridge	172:65be27845400	71	* @retval Channel_Offset (LL_DMAMUX_CHANNEL_8 or 0).
AnnaBridge	172:65be27845400	72	*/
AnnaBridge	172:65be27845400	73	#define LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(__DMA_INSTANCE__) \
AnnaBridge	172:65be27845400	74	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) ? 0UL : 8UL)
AnnaBridge	172:65be27845400	75
AnnaBridge	172:65be27845400	76	/* Exported types ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	77	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	172:65be27845400	78	/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
AnnaBridge	172:65be27845400	79	* @{
AnnaBridge	172:65be27845400	80	*/
AnnaBridge	172:65be27845400	81	typedef struct
AnnaBridge	172:65be27845400	82	{
AnnaBridge	172:65be27845400	83	uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
AnnaBridge	172:65be27845400	84	or as Source base address in case of memory to memory transfer direction.
AnnaBridge	172:65be27845400	85
AnnaBridge	172:65be27845400	86	This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
AnnaBridge	172:65be27845400	87
AnnaBridge	172:65be27845400	88	uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
AnnaBridge	172:65be27845400	89	or as Destination base address in case of memory to memory transfer direction.
AnnaBridge	172:65be27845400	90
AnnaBridge	172:65be27845400	91	This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
AnnaBridge	172:65be27845400	92
AnnaBridge	172:65be27845400	93	uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
AnnaBridge	172:65be27845400	94	from memory to memory or from peripheral to memory.
AnnaBridge	172:65be27845400	95	This parameter can be a value of @ref DMA_LL_EC_DIRECTION
AnnaBridge	172:65be27845400	96
AnnaBridge	172:65be27845400	97	This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
AnnaBridge	172:65be27845400	98
AnnaBridge	172:65be27845400	99	uint32_t Mode; /*!< Specifies the normal or circular operation mode.
AnnaBridge	172:65be27845400	100	This parameter can be a value of @ref DMA_LL_EC_MODE
AnnaBridge	172:65be27845400	101	@note The circular buffer mode cannot be used if the memory to memory
AnnaBridge	172:65be27845400	102	data transfer direction is configured on the selected Stream
AnnaBridge	172:65be27845400	103
AnnaBridge	172:65be27845400	104	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
AnnaBridge	172:65be27845400	105
AnnaBridge	172:65be27845400	106	uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
AnnaBridge	172:65be27845400	107	is incremented or not.
AnnaBridge	172:65be27845400	108	This parameter can be a value of @ref DMA_LL_EC_PERIPH
AnnaBridge	172:65be27845400	109
AnnaBridge	172:65be27845400	110	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
AnnaBridge	172:65be27845400	111
AnnaBridge	172:65be27845400	112	uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
AnnaBridge	172:65be27845400	113	is incremented or not.
AnnaBridge	172:65be27845400	114	This parameter can be a value of @ref DMA_LL_EC_MEMORY
AnnaBridge	172:65be27845400	115
AnnaBridge	172:65be27845400	116	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
AnnaBridge	172:65be27845400	117
AnnaBridge	172:65be27845400	118	uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
AnnaBridge	172:65be27845400	119	in case of memory to memory transfer direction.
AnnaBridge	172:65be27845400	120	This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
AnnaBridge	172:65be27845400	121
AnnaBridge	172:65be27845400	122	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
AnnaBridge	172:65be27845400	123
AnnaBridge	172:65be27845400	124	uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
AnnaBridge	172:65be27845400	125	in case of memory to memory transfer direction.
AnnaBridge	172:65be27845400	126	This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
AnnaBridge	172:65be27845400	127
AnnaBridge	172:65be27845400	128	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
AnnaBridge	172:65be27845400	129
AnnaBridge	172:65be27845400	130	uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
AnnaBridge	172:65be27845400	131	The data unit is equal to the source buffer configuration set in PeripheralSize
AnnaBridge	172:65be27845400	132	or MemorySize parameters depending in the transfer direction.
AnnaBridge	172:65be27845400	133	This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
AnnaBridge	172:65be27845400	134
AnnaBridge	172:65be27845400	135	This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
AnnaBridge	172:65be27845400	136
AnnaBridge	172:65be27845400	137	uint32_t PeriphRequest; /*!< Specifies the peripheral request.
AnnaBridge	172:65be27845400	138	This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST
AnnaBridge	172:65be27845400	139
AnnaBridge	172:65be27845400	140	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
AnnaBridge	172:65be27845400	141
AnnaBridge	172:65be27845400	142	uint32_t Priority; /*!< Specifies the channel priority level.
AnnaBridge	172:65be27845400	143	This parameter can be a value of @ref DMA_LL_EC_PRIORITY
AnnaBridge	172:65be27845400	144
AnnaBridge	172:65be27845400	145	This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */
AnnaBridge	172:65be27845400	146
AnnaBridge	172:65be27845400	147	uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
AnnaBridge	172:65be27845400	148	This parameter can be a value of @ref DMA_LL_FIFOMODE
AnnaBridge	172:65be27845400	149	@note The Direct mode (FIFO mode disabled) cannot be used if the
AnnaBridge	172:65be27845400	150	memory-to-memory data transfer is configured on the selected stream
AnnaBridge	172:65be27845400	151
AnnaBridge	172:65be27845400	152	This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */
AnnaBridge	172:65be27845400	153
AnnaBridge	172:65be27845400	154	uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
AnnaBridge	172:65be27845400	155	This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD
AnnaBridge	172:65be27845400	156
AnnaBridge	172:65be27845400	157	This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */
AnnaBridge	172:65be27845400	158
AnnaBridge	172:65be27845400	159	uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
AnnaBridge	172:65be27845400	160	It specifies the amount of data to be transferred in a single non interruptible
AnnaBridge	172:65be27845400	161	transaction.
AnnaBridge	172:65be27845400	162	This parameter can be a value of @ref DMA_LL_EC_MBURST
AnnaBridge	172:65be27845400	163	@note The burst mode is possible only if the address Increment mode is enabled.
AnnaBridge	172:65be27845400	164
AnnaBridge	172:65be27845400	165	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */
AnnaBridge	172:65be27845400	166
AnnaBridge	172:65be27845400	167	uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
AnnaBridge	172:65be27845400	168	It specifies the amount of data to be transferred in a single non interruptible
AnnaBridge	172:65be27845400	169	transaction.
AnnaBridge	172:65be27845400	170	This parameter can be a value of @ref DMA_LL_EC_PBURST
AnnaBridge	172:65be27845400	171	@note The burst mode is possible only if the address Increment mode is enabled.
AnnaBridge	172:65be27845400	172
AnnaBridge	172:65be27845400	173	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */
AnnaBridge	172:65be27845400	174
AnnaBridge	172:65be27845400	175	} LL_DMA_InitTypeDef;
AnnaBridge	172:65be27845400	176	/**
AnnaBridge	172:65be27845400	177	* @}
AnnaBridge	172:65be27845400	178	*/
AnnaBridge	172:65be27845400	179	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	172:65be27845400	180	/* Exported constants --------------------------------------------------------*/
AnnaBridge	172:65be27845400	181	/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
AnnaBridge	172:65be27845400	182	* @{
AnnaBridge	172:65be27845400	183	*/
AnnaBridge	172:65be27845400	184
AnnaBridge	172:65be27845400	185	/** @defgroup DMA_LL_EC_STREAM STREAM
AnnaBridge	172:65be27845400	186	* @{
AnnaBridge	172:65be27845400	187	*/
AnnaBridge	172:65be27845400	188	#define LL_DMA_STREAM_0 0x00000000U
AnnaBridge	172:65be27845400	189	#define LL_DMA_STREAM_1 0x00000001U
AnnaBridge	172:65be27845400	190	#define LL_DMA_STREAM_2 0x00000002U
AnnaBridge	172:65be27845400	191	#define LL_DMA_STREAM_3 0x00000003U
AnnaBridge	172:65be27845400	192	#define LL_DMA_STREAM_4 0x00000004U
AnnaBridge	172:65be27845400	193	#define LL_DMA_STREAM_5 0x00000005U
AnnaBridge	172:65be27845400	194	#define LL_DMA_STREAM_6 0x00000006U
AnnaBridge	172:65be27845400	195	#define LL_DMA_STREAM_7 0x00000007U
AnnaBridge	172:65be27845400	196	#define LL_DMA_STREAM_ALL 0xFFFF0000U
AnnaBridge	172:65be27845400	197	/**
AnnaBridge	172:65be27845400	198	* @}
AnnaBridge	172:65be27845400	199	*/
AnnaBridge	172:65be27845400	200
AnnaBridge	172:65be27845400	201
AnnaBridge	172:65be27845400	202	/** @defgroup DMA_LL_EC_DIRECTION DIRECTION
AnnaBridge	172:65be27845400	203	* @{
AnnaBridge	172:65be27845400	204	*/
AnnaBridge	172:65be27845400	205	#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /!< Peripheral to memory direction /
AnnaBridge	172:65be27845400	206	#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /!< Memory to peripheral direction /
AnnaBridge	172:65be27845400	207	#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /!< Memory to memory direction /
AnnaBridge	172:65be27845400	208	/**
AnnaBridge	172:65be27845400	209	* @}
AnnaBridge	172:65be27845400	210	*/
AnnaBridge	172:65be27845400	211
AnnaBridge	172:65be27845400	212	/** @defgroup DMA_LL_EC_MODE MODE
AnnaBridge	172:65be27845400	213	* @{
AnnaBridge	172:65be27845400	214	*/
AnnaBridge	172:65be27845400	215	#define LL_DMA_MODE_NORMAL 0x00000000U /!< Normal Mode /
AnnaBridge	172:65be27845400	216	#define LL_DMA_MODE_CIRCULAR DMA_SxCR_CIRC /!< Circular Mode /
AnnaBridge	172:65be27845400	217	#define LL_DMA_MODE_PFCTRL DMA_SxCR_PFCTRL /!< Peripheral flow control mode /
AnnaBridge	172:65be27845400	218	/**
AnnaBridge	172:65be27845400	219	* @}
AnnaBridge	172:65be27845400	220	*/
AnnaBridge	172:65be27845400	221
AnnaBridge	172:65be27845400	222	/** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE
AnnaBridge	172:65be27845400	223	* @{
AnnaBridge	172:65be27845400	224	*/
AnnaBridge	172:65be27845400	225	#define LL_DMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /!< Disable double buffering mode /
AnnaBridge	172:65be27845400	226	#define LL_DMA_DOUBLEBUFFER_MODE_ENABLE DMA_SxCR_DBM /!< Enable double buffering mode /
AnnaBridge	172:65be27845400	227	/**
AnnaBridge	172:65be27845400	228	* @}
AnnaBridge	172:65be27845400	229	*/
AnnaBridge	172:65be27845400	230
AnnaBridge	172:65be27845400	231	/** @defgroup DMA_LL_EC_PERIPH PERIPH
AnnaBridge	172:65be27845400	232	* @{
AnnaBridge	172:65be27845400	233	*/
AnnaBridge	172:65be27845400	234	#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /!< Peripheral increment mode Disable /
AnnaBridge	172:65be27845400	235	#define LL_DMA_PERIPH_INCREMENT DMA_SxCR_PINC /!< Peripheral increment mode Enable /
AnnaBridge	172:65be27845400	236	/**
AnnaBridge	172:65be27845400	237	* @}
AnnaBridge	172:65be27845400	238	*/
AnnaBridge	172:65be27845400	239
AnnaBridge	172:65be27845400	240	/** @defgroup DMA_LL_EC_MEMORY MEMORY
AnnaBridge	172:65be27845400	241	* @{
AnnaBridge	172:65be27845400	242	*/
AnnaBridge	172:65be27845400	243	#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /!< Memory increment mode Disable /
AnnaBridge	172:65be27845400	244	#define LL_DMA_MEMORY_INCREMENT DMA_SxCR_MINC /!< Memory increment mode Enable /
AnnaBridge	172:65be27845400	245	/**
AnnaBridge	172:65be27845400	246	* @}
AnnaBridge	172:65be27845400	247	*/
AnnaBridge	172:65be27845400	248
AnnaBridge	172:65be27845400	249	/** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN
AnnaBridge	172:65be27845400	250	* @{
AnnaBridge	172:65be27845400	251	*/
AnnaBridge	172:65be27845400	252	#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /!< Peripheral data alignment : Byte /
AnnaBridge	172:65be27845400	253	#define LL_DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /!< Peripheral data alignment : HalfWord /
AnnaBridge	172:65be27845400	254	#define LL_DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /!< Peripheral data alignment : Word /
AnnaBridge	172:65be27845400	255	/**
AnnaBridge	172:65be27845400	256	* @}
AnnaBridge	172:65be27845400	257	*/
AnnaBridge	172:65be27845400	258
AnnaBridge	172:65be27845400	259	/** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN
AnnaBridge	172:65be27845400	260	* @{
AnnaBridge	172:65be27845400	261	*/
AnnaBridge	172:65be27845400	262	#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /!< Memory data alignment : Byte /
AnnaBridge	172:65be27845400	263	#define LL_DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /!< Memory data alignment : HalfWord /
AnnaBridge	172:65be27845400	264	#define LL_DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /!< Memory data alignment : Word /
AnnaBridge	172:65be27845400	265	/**
AnnaBridge	172:65be27845400	266	* @}
AnnaBridge	172:65be27845400	267	*/
AnnaBridge	172:65be27845400	268
AnnaBridge	172:65be27845400	269	/** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE
AnnaBridge	172:65be27845400	270	* @{
AnnaBridge	172:65be27845400	271	*/
AnnaBridge	172:65be27845400	272	#define LL_DMA_OFFSETSIZE_PSIZE 0x00000000U /!< Peripheral increment offset size is linked to the PSIZE /
AnnaBridge	172:65be27845400	273	#define LL_DMA_OFFSETSIZE_FIXEDTO4 DMA_SxCR_PINCOS /!< Peripheral increment offset size is fixed to 4 (32-bit alignment) /
AnnaBridge	172:65be27845400	274	/**
AnnaBridge	172:65be27845400	275	* @}
AnnaBridge	172:65be27845400	276	*/
AnnaBridge	172:65be27845400	277
AnnaBridge	172:65be27845400	278	/** @defgroup DMA_LL_EC_PRIORITY PRIORITY
AnnaBridge	172:65be27845400	279	* @{
AnnaBridge	172:65be27845400	280	*/
AnnaBridge	172:65be27845400	281	#define LL_DMA_PRIORITY_LOW 0x00000000U /!< Priority level : Low /
AnnaBridge	172:65be27845400	282	#define LL_DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /!< Priority level : Medium /
AnnaBridge	172:65be27845400	283	#define LL_DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /!< Priority level : High /
AnnaBridge	172:65be27845400	284	#define LL_DMA_PRIORITY_VERYHIGH DMA_SxCR_PL /!< Priority level : Very_High /
AnnaBridge	172:65be27845400	285	/**
AnnaBridge	172:65be27845400	286	* @}
AnnaBridge	172:65be27845400	287	*/
AnnaBridge	172:65be27845400	288
AnnaBridge	172:65be27845400	289
AnnaBridge	172:65be27845400	290	/** @defgroup DMA_LL_EC_MBURST MBURST
AnnaBridge	172:65be27845400	291	* @{
AnnaBridge	172:65be27845400	292	*/
AnnaBridge	172:65be27845400	293	#define LL_DMA_MBURST_SINGLE 0x00000000U /!< Memory burst single transfer configuration /
AnnaBridge	172:65be27845400	294	#define LL_DMA_MBURST_INC4 DMA_SxCR_MBURST_0 /!< Memory burst of 4 beats transfer configuration /
AnnaBridge	172:65be27845400	295	#define LL_DMA_MBURST_INC8 DMA_SxCR_MBURST_1 /!< Memory burst of 8 beats transfer configuration /
AnnaBridge	172:65be27845400	296	#define LL_DMA_MBURST_INC16 (DMA_SxCR_MBURST_0 \| DMA_SxCR_MBURST_1) /!< Memory burst of 16 beats transfer configuration /
AnnaBridge	172:65be27845400	297	/**
AnnaBridge	172:65be27845400	298	* @}
AnnaBridge	172:65be27845400	299	*/
AnnaBridge	172:65be27845400	300
AnnaBridge	172:65be27845400	301	/** @defgroup DMA_LL_EC_PBURST PBURST
AnnaBridge	172:65be27845400	302	* @{
AnnaBridge	172:65be27845400	303	*/
AnnaBridge	172:65be27845400	304	#define LL_DMA_PBURST_SINGLE 0x00000000U /!< Peripheral burst single transfer configuration /
AnnaBridge	172:65be27845400	305	#define LL_DMA_PBURST_INC4 DMA_SxCR_PBURST_0 /!< Peripheral burst of 4 beats transfer configuration /
AnnaBridge	172:65be27845400	306	#define LL_DMA_PBURST_INC8 DMA_SxCR_PBURST_1 /!< Peripheral burst of 8 beats transfer configuration /
AnnaBridge	172:65be27845400	307	#define LL_DMA_PBURST_INC16 (DMA_SxCR_PBURST_0 \| DMA_SxCR_PBURST_1) /!< Peripheral burst of 16 beats transfer configuration /
AnnaBridge	172:65be27845400	308	/**
AnnaBridge	172:65be27845400	309	* @}
AnnaBridge	172:65be27845400	310	*/
AnnaBridge	172:65be27845400	311
AnnaBridge	172:65be27845400	312	/** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE
AnnaBridge	172:65be27845400	313	* @{
AnnaBridge	172:65be27845400	314	*/
AnnaBridge	172:65be27845400	315	#define LL_DMA_FIFOMODE_DISABLE 0x00000000U /!< FIFO mode disable (direct mode is enabled) /
AnnaBridge	172:65be27845400	316	#define LL_DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /!< FIFO mode enable /
AnnaBridge	172:65be27845400	317	/**
AnnaBridge	172:65be27845400	318	* @}
AnnaBridge	172:65be27845400	319	*/
AnnaBridge	172:65be27845400	320
AnnaBridge	172:65be27845400	321	/** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0
AnnaBridge	172:65be27845400	322	* @{
AnnaBridge	172:65be27845400	323	*/
AnnaBridge	172:65be27845400	324	#define LL_DMA_FIFOSTATUS_0_25 0x00000000U /!< 0 < fifo_level < 1/4 /
AnnaBridge	172:65be27845400	325	#define LL_DMA_FIFOSTATUS_25_50 DMA_SxFCR_FS_0 /!< 1/4 < fifo_level < 1/2 /
AnnaBridge	172:65be27845400	326	#define LL_DMA_FIFOSTATUS_50_75 DMA_SxFCR_FS_1 /!< 1/2 < fifo_level < 3/4 /
AnnaBridge	172:65be27845400	327	#define LL_DMA_FIFOSTATUS_75_100 (DMA_SxFCR_FS_1 \| DMA_SxFCR_FS_0) /!< 3/4 < fifo_level < full /
AnnaBridge	172:65be27845400	328	#define LL_DMA_FIFOSTATUS_EMPTY DMA_SxFCR_FS_2 /!< FIFO is empty /
AnnaBridge	172:65be27845400	329	#define LL_DMA_FIFOSTATUS_FULL (DMA_SxFCR_FS_2 \| DMA_SxFCR_FS_0) /!< FIFO is full /
AnnaBridge	172:65be27845400	330	/**
AnnaBridge	172:65be27845400	331	* @}
AnnaBridge	172:65be27845400	332	*/
AnnaBridge	172:65be27845400	333
AnnaBridge	172:65be27845400	334	/** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD
AnnaBridge	172:65be27845400	335	* @{
AnnaBridge	172:65be27845400	336	*/
AnnaBridge	172:65be27845400	337	#define LL_DMA_FIFOTHRESHOLD_1_4 0x00000000U /!< FIFO threshold 1 quart full configuration /
AnnaBridge	172:65be27845400	338	#define LL_DMA_FIFOTHRESHOLD_1_2 DMA_SxFCR_FTH_0 /!< FIFO threshold half full configuration /
AnnaBridge	172:65be27845400	339	#define LL_DMA_FIFOTHRESHOLD_3_4 DMA_SxFCR_FTH_1 /!< FIFO threshold 3 quarts full configuration /
AnnaBridge	172:65be27845400	340	#define LL_DMA_FIFOTHRESHOLD_FULL DMA_SxFCR_FTH /!< FIFO threshold full configuration /
AnnaBridge	172:65be27845400	341	/**
AnnaBridge	172:65be27845400	342	* @}
AnnaBridge	172:65be27845400	343	*/
AnnaBridge	172:65be27845400	344
AnnaBridge	172:65be27845400	345	/** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
AnnaBridge	172:65be27845400	346	* @{
AnnaBridge	172:65be27845400	347	*/
AnnaBridge	172:65be27845400	348	#define LL_DMA_CURRENTTARGETMEM0 0x00000000U /!< Set CurrentTarget Memory to Memory 0 /
AnnaBridge	172:65be27845400	349	#define LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT /!< Set CurrentTarget Memory to Memory 1 /
AnnaBridge	172:65be27845400	350	/**
AnnaBridge	172:65be27845400	351	* @}
AnnaBridge	172:65be27845400	352	*/
AnnaBridge	172:65be27845400	353
AnnaBridge	172:65be27845400	354	/**
AnnaBridge	172:65be27845400	355	* @}
AnnaBridge	172:65be27845400	356	*/
AnnaBridge	172:65be27845400	357
AnnaBridge	172:65be27845400	358	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	359	/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
AnnaBridge	172:65be27845400	360	* @{
AnnaBridge	172:65be27845400	361	*/
AnnaBridge	172:65be27845400	362
AnnaBridge	172:65be27845400	363	/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
AnnaBridge	172:65be27845400	364	* @{
AnnaBridge	172:65be27845400	365	*/
AnnaBridge	172:65be27845400	366	/**
AnnaBridge	172:65be27845400	367	* @brief Write a value in DMA register
AnnaBridge	172:65be27845400	368	* @param __INSTANCE__ DMA Instance
AnnaBridge	172:65be27845400	369	* @param __REG__ Register to be written
AnnaBridge	172:65be27845400	370	* @param __VALUE__ Value to be written in the register
AnnaBridge	172:65be27845400	371	* @retval None
AnnaBridge	172:65be27845400	372	*/
AnnaBridge	172:65be27845400	373	#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
AnnaBridge	172:65be27845400	374
AnnaBridge	172:65be27845400	375	/**
AnnaBridge	172:65be27845400	376	* @brief Read a value in DMA register
AnnaBridge	172:65be27845400	377	* @param __INSTANCE__ DMA Instance
AnnaBridge	172:65be27845400	378	* @param __REG__ Register to be read
AnnaBridge	172:65be27845400	379	* @retval Register value
AnnaBridge	172:65be27845400	380	*/
AnnaBridge	172:65be27845400	381	#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge	172:65be27845400	382	/**
AnnaBridge	172:65be27845400	383	* @}
AnnaBridge	172:65be27845400	384	*/
AnnaBridge	172:65be27845400	385
AnnaBridge	172:65be27845400	386	/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy
AnnaBridge	172:65be27845400	387	* @{
AnnaBridge	172:65be27845400	388	*/
AnnaBridge	172:65be27845400	389	/**
AnnaBridge	172:65be27845400	390	* @brief Convert DMAx_Streamy into DMAx
AnnaBridge	172:65be27845400	391	* @param __STREAM_INSTANCE__ DMAx_Streamy
AnnaBridge	172:65be27845400	392	* @retval DMAx
AnnaBridge	172:65be27845400	393	*/
AnnaBridge	172:65be27845400	394	#define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__) \
AnnaBridge	172:65be27845400	395	(((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ? DMA2 : DMA1)
AnnaBridge	172:65be27845400	396
AnnaBridge	172:65be27845400	397	/**
AnnaBridge	172:65be27845400	398	* @brief Convert DMAx_Streamy into LL_DMA_STREAM_y
AnnaBridge	172:65be27845400	399	* @param __STREAM_INSTANCE__ DMAx_Streamy
AnnaBridge	172:65be27845400	400	* @retval LL_DMA_STREAM_y
AnnaBridge	172:65be27845400	401	*/
AnnaBridge	172:65be27845400	402	#define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__) \
AnnaBridge	172:65be27845400	403	(((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \
AnnaBridge	172:65be27845400	404	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \
AnnaBridge	172:65be27845400	405	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \
AnnaBridge	172:65be27845400	406	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \
AnnaBridge	172:65be27845400	407	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \
AnnaBridge	172:65be27845400	408	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \
AnnaBridge	172:65be27845400	409	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \
AnnaBridge	172:65be27845400	410	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \
AnnaBridge	172:65be27845400	411	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \
AnnaBridge	172:65be27845400	412	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \
AnnaBridge	172:65be27845400	413	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \
AnnaBridge	172:65be27845400	414	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \
AnnaBridge	172:65be27845400	415	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \
AnnaBridge	172:65be27845400	416	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \
AnnaBridge	172:65be27845400	417	LL_DMA_STREAM_7)
AnnaBridge	172:65be27845400	418
AnnaBridge	172:65be27845400	419	/**
AnnaBridge	172:65be27845400	420	* @brief Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy
AnnaBridge	172:65be27845400	421	* @param __DMA_INSTANCE__ DMAx
AnnaBridge	172:65be27845400	422	* @param __STREAM__ LL_DMA_STREAM_y
AnnaBridge	172:65be27845400	423	* @retval DMAx_Streamy
AnnaBridge	172:65be27845400	424	*/
AnnaBridge	172:65be27845400	425	#define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__) \
AnnaBridge	172:65be27845400	426	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : \
AnnaBridge	172:65be27845400	427	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : \
AnnaBridge	172:65be27845400	428	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : \
AnnaBridge	172:65be27845400	429	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : \
AnnaBridge	172:65be27845400	430	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : \
AnnaBridge	172:65be27845400	431	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : \
AnnaBridge	172:65be27845400	432	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : \
AnnaBridge	172:65be27845400	433	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : \
AnnaBridge	172:65be27845400	434	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : \
AnnaBridge	172:65be27845400	435	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : \
AnnaBridge	172:65be27845400	436	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \
AnnaBridge	172:65be27845400	437	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : \
AnnaBridge	172:65be27845400	438	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : \
AnnaBridge	172:65be27845400	439	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : \
AnnaBridge	172:65be27845400	440	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : \
AnnaBridge	172:65be27845400	441	DMA2_Stream7)
AnnaBridge	172:65be27845400	442
AnnaBridge	172:65be27845400	443	/**
AnnaBridge	172:65be27845400	444	* @}
AnnaBridge	172:65be27845400	445	*/
AnnaBridge	172:65be27845400	446
AnnaBridge	172:65be27845400	447	/**
AnnaBridge	172:65be27845400	448	* @}
AnnaBridge	172:65be27845400	449	*/
AnnaBridge	172:65be27845400	450
AnnaBridge	172:65be27845400	451
AnnaBridge	172:65be27845400	452	/* Exported functions --------------------------------------------------------*/
AnnaBridge	172:65be27845400	453	/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
AnnaBridge	172:65be27845400	454	* @{
AnnaBridge	172:65be27845400	455	*/
AnnaBridge	172:65be27845400	456
AnnaBridge	172:65be27845400	457	/** @defgroup DMA_LL_EF_Configuration Configuration
AnnaBridge	172:65be27845400	458	* @{
AnnaBridge	172:65be27845400	459	*/
AnnaBridge	172:65be27845400	460	/**
AnnaBridge	172:65be27845400	461	* @brief Enable DMA stream.
AnnaBridge	172:65be27845400	462	* @rmtoll CR EN LL_DMA_EnableStream
AnnaBridge	172:65be27845400	463	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	464	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	465	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	466	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	467	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	468	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	469	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	470	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	471	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	472	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	473	* @retval None
AnnaBridge	172:65be27845400	474	*/
AnnaBridge	172:65be27845400	475	__STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	172:65be27845400	476	{
AnnaBridge	172:65be27845400	477	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	478
AnnaBridge	172:65be27845400	479	SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN);
AnnaBridge	172:65be27845400	480	}
AnnaBridge	172:65be27845400	481
AnnaBridge	172:65be27845400	482	/**
AnnaBridge	172:65be27845400	483	* @brief Disable DMA stream.
AnnaBridge	172:65be27845400	484	* @rmtoll CR EN LL_DMA_DisableStream
AnnaBridge	172:65be27845400	485	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	486	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	487	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	488	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	489	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	490	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	491	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	492	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	493	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	494	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	495	* @retval None
AnnaBridge	172:65be27845400	496	*/
AnnaBridge	172:65be27845400	497	__STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	172:65be27845400	498	{
AnnaBridge	172:65be27845400	499	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	500
AnnaBridge	172:65be27845400	501	CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN);
AnnaBridge	172:65be27845400	502	}
AnnaBridge	172:65be27845400	503
AnnaBridge	172:65be27845400	504	/**
AnnaBridge	172:65be27845400	505	* @brief Check if DMA stream is enabled or disabled.
AnnaBridge	172:65be27845400	506	* @rmtoll CR EN LL_DMA_IsEnabledStream
AnnaBridge	172:65be27845400	507	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	508	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	509	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	510	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	511	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	512	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	513	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	514	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	515	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	516	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	517	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	518	*/
AnnaBridge	172:65be27845400	519	__STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	172:65be27845400	520	{
AnnaBridge	172:65be27845400	521	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	522
AnnaBridge	172:65be27845400	523	return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	524	}
AnnaBridge	172:65be27845400	525
AnnaBridge	172:65be27845400	526	/**
AnnaBridge	172:65be27845400	527	* @brief Configure all parameters linked to DMA transfer.
AnnaBridge	172:65be27845400	528	* @rmtoll CR DIR LL_DMA_ConfigTransfer\n
AnnaBridge	172:65be27845400	529	* CR CIRC LL_DMA_ConfigTransfer\n
AnnaBridge	172:65be27845400	530	* CR PINC LL_DMA_ConfigTransfer\n
AnnaBridge	172:65be27845400	531	* CR MINC LL_DMA_ConfigTransfer\n
AnnaBridge	172:65be27845400	532	* CR PSIZE LL_DMA_ConfigTransfer\n
AnnaBridge	172:65be27845400	533	* CR MSIZE LL_DMA_ConfigTransfer\n
AnnaBridge	172:65be27845400	534	* CR PL LL_DMA_ConfigTransfer\n
AnnaBridge	172:65be27845400	535	* CR PFCTRL LL_DMA_ConfigTransfer
AnnaBridge	172:65be27845400	536	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	537	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	538	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	539	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	540	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	541	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	542	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	543	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	544	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	545	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	546	* @param Configuration This parameter must be a combination of all the following values:
AnnaBridge	172:65be27845400	547	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge	172:65be27845400	548	* @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR or @ref LL_DMA_MODE_PFCTRL
AnnaBridge	172:65be27845400	549	* @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
AnnaBridge	172:65be27845400	550	* @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
AnnaBridge	172:65be27845400	551	* @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
AnnaBridge	172:65be27845400	552	* @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
AnnaBridge	172:65be27845400	553	* @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
AnnaBridge	172:65be27845400	554	*@retval None
AnnaBridge	172:65be27845400	555	*/
AnnaBridge	172:65be27845400	556	__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration)
AnnaBridge	172:65be27845400	557	{
AnnaBridge	172:65be27845400	558	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	559
AnnaBridge	172:65be27845400	560	MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR,
AnnaBridge	172:65be27845400	561	DMA_SxCR_DIR \| DMA_SxCR_CIRC \| DMA_SxCR_PINC \| DMA_SxCR_MINC \| DMA_SxCR_PSIZE \| DMA_SxCR_MSIZE \| DMA_SxCR_PL \| DMA_SxCR_PFCTRL,
AnnaBridge	172:65be27845400	562	Configuration);
AnnaBridge	172:65be27845400	563	}
AnnaBridge	172:65be27845400	564
AnnaBridge	172:65be27845400	565	/**
AnnaBridge	172:65be27845400	566	* @brief Set Data transfer direction (read from peripheral or from memory).
AnnaBridge	172:65be27845400	567	* @rmtoll CR DIR LL_DMA_SetDataTransferDirection
AnnaBridge	172:65be27845400	568	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	569	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	570	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	571	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	572	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	573	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	574	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	575	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	576	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	577	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	578	* @param Direction This parameter can be one of the following values:
AnnaBridge	172:65be27845400	579	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
AnnaBridge	172:65be27845400	580	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
AnnaBridge	172:65be27845400	581	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge	172:65be27845400	582	* @retval None
AnnaBridge	172:65be27845400	583	*/
AnnaBridge	172:65be27845400	584	__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction)
AnnaBridge	172:65be27845400	585	{
AnnaBridge	172:65be27845400	586	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	587
AnnaBridge	172:65be27845400	588	MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DIR, Direction);
AnnaBridge	172:65be27845400	589	}
AnnaBridge	172:65be27845400	590
AnnaBridge	172:65be27845400	591	/**
AnnaBridge	172:65be27845400	592	* @brief Get Data transfer direction (read from peripheral or from memory).
AnnaBridge	172:65be27845400	593	* @rmtoll CR DIR LL_DMA_GetDataTransferDirection
AnnaBridge	172:65be27845400	594	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	595	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	596	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	597	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	598	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	599	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	600	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	601	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	602	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	603	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	604	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	605	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
AnnaBridge	172:65be27845400	606	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
AnnaBridge	172:65be27845400	607	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge	172:65be27845400	608	*/
AnnaBridge	172:65be27845400	609	__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	172:65be27845400	610	{
AnnaBridge	172:65be27845400	611	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	612
AnnaBridge	172:65be27845400	613	return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DIR));
AnnaBridge	172:65be27845400	614	}
AnnaBridge	172:65be27845400	615
AnnaBridge	172:65be27845400	616	/**
AnnaBridge	172:65be27845400	617	* @brief Set DMA mode normal, circular or peripheral flow control.
AnnaBridge	172:65be27845400	618	* @rmtoll CR CIRC LL_DMA_SetMode\n
AnnaBridge	172:65be27845400	619	* CR PFCTRL LL_DMA_SetMode
AnnaBridge	172:65be27845400	620	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	621	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	622	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	623	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	624	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	625	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	626	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	627	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	628	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	629	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	630	* @param Mode This parameter can be one of the following values:
AnnaBridge	172:65be27845400	631	* @arg @ref LL_DMA_MODE_NORMAL
AnnaBridge	172:65be27845400	632	* @arg @ref LL_DMA_MODE_CIRCULAR
AnnaBridge	172:65be27845400	633	* @arg @ref LL_DMA_MODE_PFCTRL
AnnaBridge	172:65be27845400	634	* @retval None
AnnaBridge	172:65be27845400	635	*/
AnnaBridge	172:65be27845400	636	__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode)
AnnaBridge	172:65be27845400	637	{
AnnaBridge	172:65be27845400	638	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	639
AnnaBridge	172:65be27845400	640	MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CIRC \| DMA_SxCR_PFCTRL, Mode);
AnnaBridge	172:65be27845400	641	}
AnnaBridge	172:65be27845400	642
AnnaBridge	172:65be27845400	643	/**
AnnaBridge	172:65be27845400	644	* @brief Get DMA mode normal, circular or peripheral flow control.
AnnaBridge	172:65be27845400	645	* @rmtoll CR CIRC LL_DMA_GetMode\n
AnnaBridge	172:65be27845400	646	* CR PFCTRL LL_DMA_GetMode
AnnaBridge	172:65be27845400	647	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	648	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	649	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	650	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	651	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	652	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	653	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	654	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	655	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	656	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	657	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	658	* @arg @ref LL_DMA_MODE_NORMAL
AnnaBridge	172:65be27845400	659	* @arg @ref LL_DMA_MODE_CIRCULAR
AnnaBridge	172:65be27845400	660	* @arg @ref LL_DMA_MODE_PFCTRL
AnnaBridge	172:65be27845400	661	*/
AnnaBridge	172:65be27845400	662	__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	172:65be27845400	663	{
AnnaBridge	172:65be27845400	664	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	665
AnnaBridge	172:65be27845400	666	return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CIRC \| DMA_SxCR_PFCTRL));
AnnaBridge	172:65be27845400	667	}
AnnaBridge	172:65be27845400	668
AnnaBridge	172:65be27845400	669	/**
AnnaBridge	172:65be27845400	670	* @brief Set Peripheral increment mode.
AnnaBridge	172:65be27845400	671	* @rmtoll CR PINC LL_DMA_SetPeriphIncMode
AnnaBridge	172:65be27845400	672	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	673	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	674	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	675	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	676	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	677	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	678	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	679	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	680	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	681	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	682	* @param IncrementMode This parameter can be one of the following values:
AnnaBridge	172:65be27845400	683	* @arg @ref LL_DMA_PERIPH_NOINCREMENT
AnnaBridge	172:65be27845400	684	* @arg @ref LL_DMA_PERIPH_INCREMENT
AnnaBridge	172:65be27845400	685	* @retval None
AnnaBridge	172:65be27845400	686	*/
AnnaBridge	172:65be27845400	687	__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
AnnaBridge	172:65be27845400	688	{
AnnaBridge	172:65be27845400	689	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	690
AnnaBridge	172:65be27845400	691	MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINC, IncrementMode);
AnnaBridge	172:65be27845400	692	}
AnnaBridge	172:65be27845400	693
AnnaBridge	172:65be27845400	694	/**
AnnaBridge	172:65be27845400	695	* @brief Get Peripheral increment mode.
AnnaBridge	172:65be27845400	696	* @rmtoll CR PINC LL_DMA_GetPeriphIncMode
AnnaBridge	172:65be27845400	697	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	698	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	699	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	700	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	701	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	702	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	703	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	704	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	705	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	706	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	707	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	708	* @arg @ref LL_DMA_PERIPH_NOINCREMENT
AnnaBridge	172:65be27845400	709	* @arg @ref LL_DMA_PERIPH_INCREMENT
AnnaBridge	172:65be27845400	710	*/
AnnaBridge	172:65be27845400	711	__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	172:65be27845400	712	{
AnnaBridge	172:65be27845400	713	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	714
AnnaBridge	172:65be27845400	715	return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINC));
AnnaBridge	172:65be27845400	716	}
AnnaBridge	172:65be27845400	717
AnnaBridge	172:65be27845400	718	/**
AnnaBridge	172:65be27845400	719	* @brief Set Memory increment mode.
AnnaBridge	172:65be27845400	720	* @rmtoll CR MINC LL_DMA_SetMemoryIncMode
AnnaBridge	172:65be27845400	721	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	722	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	723	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	724	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	725	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	726	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	727	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	728	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	729	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	730	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	731	* @param IncrementMode This parameter can be one of the following values:
AnnaBridge	172:65be27845400	732	* @arg @ref LL_DMA_MEMORY_NOINCREMENT
AnnaBridge	172:65be27845400	733	* @arg @ref LL_DMA_MEMORY_INCREMENT
AnnaBridge	172:65be27845400	734	* @retval None
AnnaBridge	172:65be27845400	735	*/
AnnaBridge	172:65be27845400	736	__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
AnnaBridge	172:65be27845400	737	{
AnnaBridge	172:65be27845400	738	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	739
AnnaBridge	172:65be27845400	740	MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MINC, IncrementMode);
AnnaBridge	172:65be27845400	741	}
AnnaBridge	172:65be27845400	742
AnnaBridge	172:65be27845400	743	/**
AnnaBridge	172:65be27845400	744	* @brief Get Memory increment mode.
AnnaBridge	172:65be27845400	745	* @rmtoll CR MINC LL_DMA_GetMemoryIncMode
AnnaBridge	172:65be27845400	746	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	747	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	748	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	749	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	750	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	751	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	752	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	753	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	754	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	755	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	756	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	757	* @arg @ref LL_DMA_MEMORY_NOINCREMENT
AnnaBridge	172:65be27845400	758	* @arg @ref LL_DMA_MEMORY_INCREMENT
AnnaBridge	172:65be27845400	759	*/
AnnaBridge	172:65be27845400	760	__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	172:65be27845400	761	{
AnnaBridge	172:65be27845400	762	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	763
AnnaBridge	172:65be27845400	764	return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MINC));
AnnaBridge	172:65be27845400	765	}
AnnaBridge	172:65be27845400	766
AnnaBridge	172:65be27845400	767	/**
AnnaBridge	172:65be27845400	768	* @brief Set Peripheral size.
AnnaBridge	172:65be27845400	769	* @rmtoll CR PSIZE LL_DMA_SetPeriphSize
AnnaBridge	172:65be27845400	770	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	771	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	772	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	773	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	774	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	775	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	776	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	777	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	778	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	779	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	780	* @param Size This parameter can be one of the following values:
AnnaBridge	172:65be27845400	781	* @arg @ref LL_DMA_PDATAALIGN_BYTE
AnnaBridge	172:65be27845400	782	* @arg @ref LL_DMA_PDATAALIGN_HALFWORD
AnnaBridge	172:65be27845400	783	* @arg @ref LL_DMA_PDATAALIGN_WORD
AnnaBridge	172:65be27845400	784	* @retval None
AnnaBridge	172:65be27845400	785	*/
AnnaBridge	172:65be27845400	786	__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size)
AnnaBridge	172:65be27845400	787	{
AnnaBridge	172:65be27845400	788	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	789
AnnaBridge	172:65be27845400	790	MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PSIZE, Size);
AnnaBridge	172:65be27845400	791	}
AnnaBridge	172:65be27845400	792
AnnaBridge	172:65be27845400	793	/**
AnnaBridge	172:65be27845400	794	* @brief Get Peripheral size.
AnnaBridge	172:65be27845400	795	* @rmtoll CR PSIZE LL_DMA_GetPeriphSize
AnnaBridge	172:65be27845400	796	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	797	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	798	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	799	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	800	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	801	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	802	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	803	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	804	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	805	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	806	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	807	* @arg @ref LL_DMA_PDATAALIGN_BYTE
AnnaBridge	172:65be27845400	808	* @arg @ref LL_DMA_PDATAALIGN_HALFWORD
AnnaBridge	172:65be27845400	809	* @arg @ref LL_DMA_PDATAALIGN_WORD
AnnaBridge	172:65be27845400	810	*/
AnnaBridge	172:65be27845400	811	__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	172:65be27845400	812	{
AnnaBridge	172:65be27845400	813	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	814
AnnaBridge	172:65be27845400	815	return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PSIZE));
AnnaBridge	172:65be27845400	816	}
AnnaBridge	172:65be27845400	817
AnnaBridge	172:65be27845400	818	/**
AnnaBridge	172:65be27845400	819	* @brief Set Memory size.
AnnaBridge	172:65be27845400	820	* @rmtoll CR MSIZE LL_DMA_SetMemorySize
AnnaBridge	172:65be27845400	821	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	822	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	823	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	824	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	825	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	826	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	827	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	828	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	829	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	830	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	831	* @param Size This parameter can be one of the following values:
AnnaBridge	172:65be27845400	832	* @arg @ref LL_DMA_MDATAALIGN_BYTE
AnnaBridge	172:65be27845400	833	* @arg @ref LL_DMA_MDATAALIGN_HALFWORD
AnnaBridge	172:65be27845400	834	* @arg @ref LL_DMA_MDATAALIGN_WORD
AnnaBridge	172:65be27845400	835	* @retval None
AnnaBridge	172:65be27845400	836	*/
AnnaBridge	172:65be27845400	837	__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size)
AnnaBridge	172:65be27845400	838	{
AnnaBridge	172:65be27845400	839	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	840
AnnaBridge	172:65be27845400	841	MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MSIZE, Size);
AnnaBridge	172:65be27845400	842	}
AnnaBridge	172:65be27845400	843
AnnaBridge	172:65be27845400	844	/**
AnnaBridge	172:65be27845400	845	* @brief Get Memory size.
AnnaBridge	172:65be27845400	846	* @rmtoll CR MSIZE LL_DMA_GetMemorySize
AnnaBridge	172:65be27845400	847	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	848	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	849	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	850	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	851	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	852	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	853	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	854	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	855	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	856	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	857	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	858	* @arg @ref LL_DMA_MDATAALIGN_BYTE
AnnaBridge	172:65be27845400	859	* @arg @ref LL_DMA_MDATAALIGN_HALFWORD
AnnaBridge	172:65be27845400	860	* @arg @ref LL_DMA_MDATAALIGN_WORD
AnnaBridge	172:65be27845400	861	*/
AnnaBridge	172:65be27845400	862	__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	172:65be27845400	863	{
AnnaBridge	172:65be27845400	864	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	865
AnnaBridge	172:65be27845400	866	return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MSIZE));
AnnaBridge	172:65be27845400	867	}
AnnaBridge	172:65be27845400	868
AnnaBridge	172:65be27845400	869	/**
AnnaBridge	172:65be27845400	870	* @brief Set Peripheral increment offset size.
AnnaBridge	172:65be27845400	871	* @rmtoll CR PINCOS LL_DMA_SetIncOffsetSize
AnnaBridge	172:65be27845400	872	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	873	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	874	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	875	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	876	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	877	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	878	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	879	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	880	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	881	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	882	* @param OffsetSize This parameter can be one of the following values:
AnnaBridge	172:65be27845400	883	* @arg @ref LL_DMA_OFFSETSIZE_PSIZE
AnnaBridge	172:65be27845400	884	* @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
AnnaBridge	172:65be27845400	885	* @retval None
AnnaBridge	172:65be27845400	886	*/
AnnaBridge	172:65be27845400	887	__STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize)
AnnaBridge	172:65be27845400	888	{
AnnaBridge	172:65be27845400	889	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	890
AnnaBridge	172:65be27845400	891	MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINCOS, OffsetSize);
AnnaBridge	172:65be27845400	892	}
AnnaBridge	172:65be27845400	893
AnnaBridge	172:65be27845400	894	/**
AnnaBridge	172:65be27845400	895	* @brief Get Peripheral increment offset size.
AnnaBridge	172:65be27845400	896	* @rmtoll CR PINCOS LL_DMA_GetIncOffsetSize
AnnaBridge	172:65be27845400	897	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	898	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	899	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	900	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	901	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	902	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	903	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	904	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	905	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	906	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	907	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	908	* @arg @ref LL_DMA_OFFSETSIZE_PSIZE
AnnaBridge	172:65be27845400	909	* @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
AnnaBridge	172:65be27845400	910	*/
AnnaBridge	172:65be27845400	911	__STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	172:65be27845400	912	{
AnnaBridge	172:65be27845400	913	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	914
AnnaBridge	172:65be27845400	915	return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINCOS));
AnnaBridge	172:65be27845400	916	}
AnnaBridge	172:65be27845400	917
AnnaBridge	172:65be27845400	918	/**
AnnaBridge	172:65be27845400	919	* @brief Set Stream priority level.
AnnaBridge	172:65be27845400	920	* @rmtoll CR PL LL_DMA_SetStreamPriorityLevel
AnnaBridge	172:65be27845400	921	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	922	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	923	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	924	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	925	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	926	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	927	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	928	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	929	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	930	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	931	* @param Priority This parameter can be one of the following values:
AnnaBridge	172:65be27845400	932	* @arg @ref LL_DMA_PRIORITY_LOW
AnnaBridge	172:65be27845400	933	* @arg @ref LL_DMA_PRIORITY_MEDIUM
AnnaBridge	172:65be27845400	934	* @arg @ref LL_DMA_PRIORITY_HIGH
AnnaBridge	172:65be27845400	935	* @arg @ref LL_DMA_PRIORITY_VERYHIGH
AnnaBridge	172:65be27845400	936	* @retval None
AnnaBridge	172:65be27845400	937	*/
AnnaBridge	172:65be27845400	938	__STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority)
AnnaBridge	172:65be27845400	939	{
AnnaBridge	172:65be27845400	940	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	941
AnnaBridge	172:65be27845400	942	MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PL, Priority);
AnnaBridge	172:65be27845400	943	}
AnnaBridge	172:65be27845400	944
AnnaBridge	172:65be27845400	945	/**
AnnaBridge	172:65be27845400	946	* @brief Get Stream priority level.
AnnaBridge	172:65be27845400	947	* @rmtoll CR PL LL_DMA_GetStreamPriorityLevel
AnnaBridge	172:65be27845400	948	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	949	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	950	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	951	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	952	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	953	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	954	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	955	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	956	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	957	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	958	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	959	* @arg @ref LL_DMA_PRIORITY_LOW
AnnaBridge	172:65be27845400	960	* @arg @ref LL_DMA_PRIORITY_MEDIUM
AnnaBridge	172:65be27845400	961	* @arg @ref LL_DMA_PRIORITY_HIGH
AnnaBridge	172:65be27845400	962	* @arg @ref LL_DMA_PRIORITY_VERYHIGH
AnnaBridge	172:65be27845400	963	*/
AnnaBridge	172:65be27845400	964	__STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	172:65be27845400	965	{
AnnaBridge	172:65be27845400	966	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	967
AnnaBridge	172:65be27845400	968	return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PL));
AnnaBridge	172:65be27845400	969	}
AnnaBridge	172:65be27845400	970
AnnaBridge	172:65be27845400	971	/**
AnnaBridge	172:65be27845400	972	* @brief Set Number of data to transfer.
AnnaBridge	172:65be27845400	973	* @rmtoll NDTR NDT LL_DMA_SetDataLength
AnnaBridge	172:65be27845400	974	* @note This action has no effect if
AnnaBridge	172:65be27845400	975	* stream is enabled.
AnnaBridge	172:65be27845400	976	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	977	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	978	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	979	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	980	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	981	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	982	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	983	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	984	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	985	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	986	* @param NbData Between 0 to 0xFFFFFFFF
AnnaBridge	172:65be27845400	987	* @retval None
AnnaBridge	172:65be27845400	988	*/
AnnaBridge	172:65be27845400	989	__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t NbData)
AnnaBridge	172:65be27845400	990	{
AnnaBridge	172:65be27845400	991	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	992
AnnaBridge	172:65be27845400	993	MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->NDTR, DMA_SxNDT, NbData);
AnnaBridge	172:65be27845400	994	}
AnnaBridge	172:65be27845400	995
AnnaBridge	172:65be27845400	996	/**
AnnaBridge	172:65be27845400	997	* @brief Get Number of data to transfer.
AnnaBridge	172:65be27845400	998	* @rmtoll NDTR NDT LL_DMA_GetDataLength
AnnaBridge	172:65be27845400	999	* @note Once the stream is enabled, the return value indicate the
AnnaBridge	172:65be27845400	1000	* remaining bytes to be transmitted.
AnnaBridge	172:65be27845400	1001	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1002	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1003	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	1004	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	1005	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	1006	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	1007	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	1008	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	1009	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	1010	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	1011	* @retval Between 0 to 0xFFFFFFFF
AnnaBridge	172:65be27845400	1012	*/
AnnaBridge	172:65be27845400	1013	__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	172:65be27845400	1014	{
AnnaBridge	172:65be27845400	1015	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	1016
AnnaBridge	172:65be27845400	1017	return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->NDTR, DMA_SxNDT));
AnnaBridge	172:65be27845400	1018	}
AnnaBridge	172:65be27845400	1019	/**
AnnaBridge	172:65be27845400	1020	* @brief Set DMA request for DMA Streams on DMAMUX Channel x.
AnnaBridge	172:65be27845400	1021	* @note DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7.
AnnaBridge	172:65be27845400	1022	* DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7.
AnnaBridge	172:65be27845400	1023	* @rmtoll CxCR DMAREQ_ID LL_DMA_SetPeriphRequest
AnnaBridge	172:65be27845400	1024	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1025	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1026	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	1027	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	1028	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	1029	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	1030	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	1031	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	1032	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	1033	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	1034	* @param Request This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1035	* @arg @ref LL_DMAMUX1_REQ_MEM2MEM
AnnaBridge	172:65be27845400	1036	* @arg @ref LL_DMAMUX1_REQ_GENERATOR0
AnnaBridge	172:65be27845400	1037	* @arg @ref LL_DMAMUX1_REQ_GENERATOR1
AnnaBridge	172:65be27845400	1038	* @arg @ref LL_DMAMUX1_REQ_GENERATOR2
AnnaBridge	172:65be27845400	1039	* @arg @ref LL_DMAMUX1_REQ_GENERATOR3
AnnaBridge	172:65be27845400	1040	* @arg @ref LL_DMAMUX1_REQ_GENERATOR4
AnnaBridge	172:65be27845400	1041	* @arg @ref LL_DMAMUX1_REQ_GENERATOR5
AnnaBridge	172:65be27845400	1042	* @arg @ref LL_DMAMUX1_REQ_GENERATOR6
AnnaBridge	172:65be27845400	1043	* @arg @ref LL_DMAMUX1_REQ_GENERATOR7
AnnaBridge	172:65be27845400	1044	* @arg @ref LL_DMAMUX1_REQ_ADC1
AnnaBridge	172:65be27845400	1045	* @arg @ref LL_DMAMUX1_REQ_ADC2
AnnaBridge	172:65be27845400	1046	* @arg @ref LL_DMAMUX1_REQ_TIM1_CH1
AnnaBridge	172:65be27845400	1047	* @arg @ref LL_DMAMUX1_REQ_TIM1_CH2
AnnaBridge	172:65be27845400	1048	* @arg @ref LL_DMAMUX1_REQ_TIM1_CH3
AnnaBridge	172:65be27845400	1049	* @arg @ref LL_DMAMUX1_REQ_TIM1_CH4
AnnaBridge	172:65be27845400	1050	* @arg @ref LL_DMAMUX1_REQ_TIM1_UP
AnnaBridge	172:65be27845400	1051	* @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG
AnnaBridge	172:65be27845400	1052	* @arg @ref LL_DMAMUX1_REQ_TIM1_COM
AnnaBridge	172:65be27845400	1053	* @arg @ref LL_DMAMUX1_REQ_TIM2_CH1
AnnaBridge	172:65be27845400	1054	* @arg @ref LL_DMAMUX1_REQ_TIM2_CH2
AnnaBridge	172:65be27845400	1055	* @arg @ref LL_DMAMUX1_REQ_TIM2_CH3
AnnaBridge	172:65be27845400	1056	* @arg @ref LL_DMAMUX1_REQ_TIM2_CH4
AnnaBridge	172:65be27845400	1057	* @arg @ref LL_DMAMUX1_REQ_TIM2_UP
AnnaBridge	172:65be27845400	1058	* @arg @ref LL_DMAMUX1_REQ_TIM3_CH1
AnnaBridge	172:65be27845400	1059	* @arg @ref LL_DMAMUX1_REQ_TIM3_CH2
AnnaBridge	172:65be27845400	1060	* @arg @ref LL_DMAMUX1_REQ_TIM3_CH3
AnnaBridge	172:65be27845400	1061	* @arg @ref LL_DMAMUX1_REQ_TIM3_CH4
AnnaBridge	172:65be27845400	1062	* @arg @ref LL_DMAMUX1_REQ_TIM3_UP
AnnaBridge	172:65be27845400	1063	* @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG
AnnaBridge	172:65be27845400	1064	* @arg @ref LL_DMAMUX1_REQ_TIM4_CH1
AnnaBridge	172:65be27845400	1065	* @arg @ref LL_DMAMUX1_REQ_TIM4_CH2
AnnaBridge	172:65be27845400	1066	* @arg @ref LL_DMAMUX1_REQ_TIM4_CH3
AnnaBridge	172:65be27845400	1067	* @arg @ref LL_DMAMUX1_REQ_TIM4_UP
AnnaBridge	172:65be27845400	1068	* @arg @ref LL_DMAMUX1_REQ_I2C1_RX
AnnaBridge	172:65be27845400	1069	* @arg @ref LL_DMAMUX1_REQ_I2C1_TX
AnnaBridge	172:65be27845400	1070	* @arg @ref LL_DMAMUX1_REQ_I2C2_RX
AnnaBridge	172:65be27845400	1071	* @arg @ref LL_DMAMUX1_REQ_I2C2_TX
AnnaBridge	172:65be27845400	1072	* @arg @ref LL_DMAMUX1_REQ_SPI1_RX
AnnaBridge	172:65be27845400	1073	* @arg @ref LL_DMAMUX1_REQ_SPI1_TX
AnnaBridge	172:65be27845400	1074	* @arg @ref LL_DMAMUX1_REQ_SPI2_RX
AnnaBridge	172:65be27845400	1075	* @arg @ref LL_DMAMUX1_REQ_SPI2_TX
AnnaBridge	172:65be27845400	1076	* @arg @ref LL_DMAMUX1_REQ_USART1_RX
AnnaBridge	172:65be27845400	1077	* @arg @ref LL_DMAMUX1_REQ_USART1_TX
AnnaBridge	172:65be27845400	1078	* @arg @ref LL_DMAMUX1_REQ_USART2_RX
AnnaBridge	172:65be27845400	1079	* @arg @ref LL_DMAMUX1_REQ_USART2_TX
AnnaBridge	172:65be27845400	1080	* @arg @ref LL_DMAMUX1_REQ_USART3_RX
AnnaBridge	172:65be27845400	1081	* @arg @ref LL_DMAMUX1_REQ_USART3_TX
AnnaBridge	172:65be27845400	1082	* @arg @ref LL_DMAMUX1_REQ_TIM8_CH1
AnnaBridge	172:65be27845400	1083	* @arg @ref LL_DMAMUX1_REQ_TIM8_CH2
AnnaBridge	172:65be27845400	1084	* @arg @ref LL_DMAMUX1_REQ_TIM8_CH3
AnnaBridge	172:65be27845400	1085	* @arg @ref LL_DMAMUX1_REQ_TIM8_CH4
AnnaBridge	172:65be27845400	1086	* @arg @ref LL_DMAMUX1_REQ_TIM8_UP
AnnaBridge	172:65be27845400	1087	* @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG
AnnaBridge	172:65be27845400	1088	* @arg @ref LL_DMAMUX1_REQ_TIM8_COM
AnnaBridge	172:65be27845400	1089	* @arg @ref LL_DMAMUX1_REQ_TIM5_CH1
AnnaBridge	172:65be27845400	1090	* @arg @ref LL_DMAMUX1_REQ_TIM5_CH2
AnnaBridge	172:65be27845400	1091	* @arg @ref LL_DMAMUX1_REQ_TIM5_CH3
AnnaBridge	172:65be27845400	1092	* @arg @ref LL_DMAMUX1_REQ_TIM5_CH4
AnnaBridge	172:65be27845400	1093	* @arg @ref LL_DMAMUX1_REQ_TIM5_UP
AnnaBridge	172:65be27845400	1094	* @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG
AnnaBridge	172:65be27845400	1095	* @arg @ref LL_DMAMUX1_REQ_SPI3_RX
AnnaBridge	172:65be27845400	1096	* @arg @ref LL_DMAMUX1_REQ_SPI3_TX
AnnaBridge	172:65be27845400	1097	* @arg @ref LL_DMAMUX1_REQ_UART4_RX
AnnaBridge	172:65be27845400	1098	* @arg @ref LL_DMAMUX1_REQ_UART4_TX
AnnaBridge	172:65be27845400	1099	* @arg @ref LL_DMAMUX1_REQ_UART5_RX
AnnaBridge	172:65be27845400	1100	* @arg @ref LL_DMAMUX1_REQ_UART5_TX
AnnaBridge	172:65be27845400	1101	* @arg @ref LL_DMAMUX1_REQ_DAC1_CH1
AnnaBridge	172:65be27845400	1102	* @arg @ref LL_DMAMUX1_REQ_DAC1_CH2
AnnaBridge	172:65be27845400	1103	* @arg @ref LL_DMAMUX1_REQ_TIM6_UP
AnnaBridge	172:65be27845400	1104	* @arg @ref LL_DMAMUX1_REQ_TIM7_UP
AnnaBridge	172:65be27845400	1105	* @arg @ref LL_DMAMUX1_REQ_USART6_RX
AnnaBridge	172:65be27845400	1106	* @arg @ref LL_DMAMUX1_REQ_USART6_TX
AnnaBridge	172:65be27845400	1107	* @arg @ref LL_DMAMUX1_REQ_I2C3_RX
AnnaBridge	172:65be27845400	1108	* @arg @ref LL_DMAMUX1_REQ_I2C3_TX
AnnaBridge	172:65be27845400	1109	* @arg @ref LL_DMAMUX1_REQ_DCMI
AnnaBridge	172:65be27845400	1110	* @arg @ref LL_DMAMUX1_REQ_CRYP_IN
AnnaBridge	172:65be27845400	1111	* @arg @ref LL_DMAMUX1_REQ_CRYP_OUT
AnnaBridge	172:65be27845400	1112	* @arg @ref LL_DMAMUX1_REQ_HASH_IN
AnnaBridge	172:65be27845400	1113	* @arg @ref LL_DMAMUX1_REQ_UART7_RX
AnnaBridge	172:65be27845400	1114	* @arg @ref LL_DMAMUX1_REQ_UART7_TX
AnnaBridge	172:65be27845400	1115	* @arg @ref LL_DMAMUX1_REQ_UART8_RX
AnnaBridge	172:65be27845400	1116	* @arg @ref LL_DMAMUX1_REQ_UART8_TX
AnnaBridge	172:65be27845400	1117	* @arg @ref LL_DMAMUX1_REQ_SPI4_RX
AnnaBridge	172:65be27845400	1118	* @arg @ref LL_DMAMUX1_REQ_SPI4_TX
AnnaBridge	172:65be27845400	1119	* @arg @ref LL_DMAMUX1_REQ_SPI5_RX
AnnaBridge	172:65be27845400	1120	* @arg @ref LL_DMAMUX1_REQ_SPI5_TX
AnnaBridge	172:65be27845400	1121	* @arg @ref LL_DMAMUX1_REQ_SAI1_A
AnnaBridge	172:65be27845400	1122	* @arg @ref LL_DMAMUX1_REQ_SAI1_B
AnnaBridge	172:65be27845400	1123	* @arg @ref LL_DMAMUX1_REQ_SAI2_A
AnnaBridge	172:65be27845400	1124	* @arg @ref LL_DMAMUX1_REQ_SAI2_B
AnnaBridge	172:65be27845400	1125	* @arg @ref LL_DMAMUX1_REQ_SWPMI_RX
AnnaBridge	172:65be27845400	1126	* @arg @ref LL_DMAMUX1_REQ_SWPMI_TX
AnnaBridge	172:65be27845400	1127	* @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT
AnnaBridge	172:65be27845400	1128	* @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS
AnnaBridge	172:65be27845400	1129	* @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER
AnnaBridge	172:65be27845400	1130	* @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A
AnnaBridge	172:65be27845400	1131	* @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B
AnnaBridge	172:65be27845400	1132	* @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C
AnnaBridge	172:65be27845400	1133	* @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D
AnnaBridge	172:65be27845400	1134	* @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E
AnnaBridge	172:65be27845400	1135	* @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0
AnnaBridge	172:65be27845400	1136	* @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1
AnnaBridge	172:65be27845400	1137	* @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2
AnnaBridge	172:65be27845400	1138	* @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3
AnnaBridge	172:65be27845400	1139	* @arg @ref LL_DMAMUX1_REQ_TIM15_CH1
AnnaBridge	172:65be27845400	1140	* @arg @ref LL_DMAMUX1_REQ_TIM15_UP
AnnaBridge	172:65be27845400	1141	* @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG
AnnaBridge	172:65be27845400	1142	* @arg @ref LL_DMAMUX1_REQ_TIM15_COM
AnnaBridge	172:65be27845400	1143	* @arg @ref LL_DMAMUX1_REQ_TIM16_CH1
AnnaBridge	172:65be27845400	1144	* @arg @ref LL_DMAMUX1_REQ_TIM16_UP
AnnaBridge	172:65be27845400	1145	* @arg @ref LL_DMAMUX1_REQ_TIM17_CH1
AnnaBridge	172:65be27845400	1146	* @arg @ref LL_DMAMUX1_REQ_TIM17_UP
AnnaBridge	172:65be27845400	1147	* @arg @ref LL_DMAMUX1_REQ_SAI3_A
AnnaBridge	172:65be27845400	1148	* @arg @ref LL_DMAMUX1_REQ_SAI3_B
AnnaBridge	172:65be27845400	1149	* @arg @ref LL_DMAMUX1_REQ_ADC3
AnnaBridge	172:65be27845400	1150	* @retval None
AnnaBridge	172:65be27845400	1151	*/
AnnaBridge	172:65be27845400	1152	__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Request)
AnnaBridge	172:65be27845400	1153	{
AnnaBridge	172:65be27845400	1154	MODIFY_REG(((DMAMUX_Channel_TypeDef )(uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE (Stream)) + (uint32_t)(DMAMUX_CCR_SIZE * LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
AnnaBridge	172:65be27845400	1155	}
AnnaBridge	172:65be27845400	1156
AnnaBridge	172:65be27845400	1157	/**
AnnaBridge	172:65be27845400	1158	* @brief Get DMA request for DMA Channels on DMAMUX Channel x.
AnnaBridge	172:65be27845400	1159	* @note DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7.
AnnaBridge	172:65be27845400	1160	* DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7.
AnnaBridge	172:65be27845400	1161	* @rmtoll CxCR DMAREQ_ID LL_DMA_GetPeriphRequest
AnnaBridge	172:65be27845400	1162	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1163	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1164	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	1165	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	1166	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	1167	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	1168	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	1169	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	1170	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	1171	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	1172	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1173	* @arg @ref LL_DMAMUX1_REQ_MEM2MEM
AnnaBridge	172:65be27845400	1174	* @arg @ref LL_DMAMUX1_REQ_GENERATOR0
AnnaBridge	172:65be27845400	1175	* @arg @ref LL_DMAMUX1_REQ_GENERATOR1
AnnaBridge	172:65be27845400	1176	* @arg @ref LL_DMAMUX1_REQ_GENERATOR2
AnnaBridge	172:65be27845400	1177	* @arg @ref LL_DMAMUX1_REQ_GENERATOR3
AnnaBridge	172:65be27845400	1178	* @arg @ref LL_DMAMUX1_REQ_GENERATOR4
AnnaBridge	172:65be27845400	1179	* @arg @ref LL_DMAMUX1_REQ_GENERATOR5
AnnaBridge	172:65be27845400	1180	* @arg @ref LL_DMAMUX1_REQ_GENERATOR6
AnnaBridge	172:65be27845400	1181	* @arg @ref LL_DMAMUX1_REQ_GENERATOR7
AnnaBridge	172:65be27845400	1182	* @arg @ref LL_DMAMUX1_REQ_ADC1
AnnaBridge	172:65be27845400	1183	* @arg @ref LL_DMAMUX1_REQ_ADC2
AnnaBridge	172:65be27845400	1184	* @arg @ref LL_DMAMUX1_REQ_TIM1_CH1
AnnaBridge	172:65be27845400	1185	* @arg @ref LL_DMAMUX1_REQ_TIM1_CH2
AnnaBridge	172:65be27845400	1186	* @arg @ref LL_DMAMUX1_REQ_TIM1_CH3
AnnaBridge	172:65be27845400	1187	* @arg @ref LL_DMAMUX1_REQ_TIM1_CH4
AnnaBridge	172:65be27845400	1188	* @arg @ref LL_DMAMUX1_REQ_TIM1_UP
AnnaBridge	172:65be27845400	1189	* @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG
AnnaBridge	172:65be27845400	1190	* @arg @ref LL_DMAMUX1_REQ_TIM1_COM
AnnaBridge	172:65be27845400	1191	* @arg @ref LL_DMAMUX1_REQ_TIM2_CH1
AnnaBridge	172:65be27845400	1192	* @arg @ref LL_DMAMUX1_REQ_TIM2_CH2
AnnaBridge	172:65be27845400	1193	* @arg @ref LL_DMAMUX1_REQ_TIM2_CH3
AnnaBridge	172:65be27845400	1194	* @arg @ref LL_DMAMUX1_REQ_TIM2_CH4
AnnaBridge	172:65be27845400	1195	* @arg @ref LL_DMAMUX1_REQ_TIM2_UP
AnnaBridge	172:65be27845400	1196	* @arg @ref LL_DMAMUX1_REQ_TIM3_CH1
AnnaBridge	172:65be27845400	1197	* @arg @ref LL_DMAMUX1_REQ_TIM3_CH2
AnnaBridge	172:65be27845400	1198	* @arg @ref LL_DMAMUX1_REQ_TIM3_CH3
AnnaBridge	172:65be27845400	1199	* @arg @ref LL_DMAMUX1_REQ_TIM3_CH4
AnnaBridge	172:65be27845400	1200	* @arg @ref LL_DMAMUX1_REQ_TIM3_UP
AnnaBridge	172:65be27845400	1201	* @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG
AnnaBridge	172:65be27845400	1202	* @arg @ref LL_DMAMUX1_REQ_TIM4_CH1
AnnaBridge	172:65be27845400	1203	* @arg @ref LL_DMAMUX1_REQ_TIM4_CH2
AnnaBridge	172:65be27845400	1204	* @arg @ref LL_DMAMUX1_REQ_TIM4_CH3
AnnaBridge	172:65be27845400	1205	* @arg @ref LL_DMAMUX1_REQ_TIM4_UP
AnnaBridge	172:65be27845400	1206	* @arg @ref LL_DMAMUX1_REQ_I2C1_RX
AnnaBridge	172:65be27845400	1207	* @arg @ref LL_DMAMUX1_REQ_I2C1_TX
AnnaBridge	172:65be27845400	1208	* @arg @ref LL_DMAMUX1_REQ_I2C2_RX
AnnaBridge	172:65be27845400	1209	* @arg @ref LL_DMAMUX1_REQ_I2C2_TX
AnnaBridge	172:65be27845400	1210	* @arg @ref LL_DMAMUX1_REQ_SPI1_RX
AnnaBridge	172:65be27845400	1211	* @arg @ref LL_DMAMUX1_REQ_SPI1_TX
AnnaBridge	172:65be27845400	1212	* @arg @ref LL_DMAMUX1_REQ_SPI2_RX
AnnaBridge	172:65be27845400	1213	* @arg @ref LL_DMAMUX1_REQ_SPI2_TX
AnnaBridge	172:65be27845400	1214	* @arg @ref LL_DMAMUX1_REQ_USART1_RX
AnnaBridge	172:65be27845400	1215	* @arg @ref LL_DMAMUX1_REQ_USART1_TX
AnnaBridge	172:65be27845400	1216	* @arg @ref LL_DMAMUX1_REQ_USART2_RX
AnnaBridge	172:65be27845400	1217	* @arg @ref LL_DMAMUX1_REQ_USART2_TX
AnnaBridge	172:65be27845400	1218	* @arg @ref LL_DMAMUX1_REQ_USART3_RX
AnnaBridge	172:65be27845400	1219	* @arg @ref LL_DMAMUX1_REQ_USART3_TX
AnnaBridge	172:65be27845400	1220	* @arg @ref LL_DMAMUX1_REQ_TIM8_CH1
AnnaBridge	172:65be27845400	1221	* @arg @ref LL_DMAMUX1_REQ_TIM8_CH2
AnnaBridge	172:65be27845400	1222	* @arg @ref LL_DMAMUX1_REQ_TIM8_CH3
AnnaBridge	172:65be27845400	1223	* @arg @ref LL_DMAMUX1_REQ_TIM8_CH4
AnnaBridge	172:65be27845400	1224	* @arg @ref LL_DMAMUX1_REQ_TIM8_UP
AnnaBridge	172:65be27845400	1225	* @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG
AnnaBridge	172:65be27845400	1226	* @arg @ref LL_DMAMUX1_REQ_TIM8_COM
AnnaBridge	172:65be27845400	1227	* @arg @ref LL_DMAMUX1_REQ_TIM5_CH1
AnnaBridge	172:65be27845400	1228	* @arg @ref LL_DMAMUX1_REQ_TIM5_CH2
AnnaBridge	172:65be27845400	1229	* @arg @ref LL_DMAMUX1_REQ_TIM5_CH3
AnnaBridge	172:65be27845400	1230	* @arg @ref LL_DMAMUX1_REQ_TIM5_CH4
AnnaBridge	172:65be27845400	1231	* @arg @ref LL_DMAMUX1_REQ_TIM5_UP
AnnaBridge	172:65be27845400	1232	* @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG
AnnaBridge	172:65be27845400	1233	* @arg @ref LL_DMAMUX1_REQ_SPI3_RX
AnnaBridge	172:65be27845400	1234	* @arg @ref LL_DMAMUX1_REQ_SPI3_TX
AnnaBridge	172:65be27845400	1235	* @arg @ref LL_DMAMUX1_REQ_UART4_RX
AnnaBridge	172:65be27845400	1236	* @arg @ref LL_DMAMUX1_REQ_UART4_TX
AnnaBridge	172:65be27845400	1237	* @arg @ref LL_DMAMUX1_REQ_UART5_RX
AnnaBridge	172:65be27845400	1238	* @arg @ref LL_DMAMUX1_REQ_UART5_TX
AnnaBridge	172:65be27845400	1239	* @arg @ref LL_DMAMUX1_REQ_DAC1_CH1
AnnaBridge	172:65be27845400	1240	* @arg @ref LL_DMAMUX1_REQ_DAC1_CH2
AnnaBridge	172:65be27845400	1241	* @arg @ref LL_DMAMUX1_REQ_TIM6_UP
AnnaBridge	172:65be27845400	1242	* @arg @ref LL_DMAMUX1_REQ_TIM7_UP
AnnaBridge	172:65be27845400	1243	* @arg @ref LL_DMAMUX1_REQ_USART6_RX
AnnaBridge	172:65be27845400	1244	* @arg @ref LL_DMAMUX1_REQ_USART6_TX
AnnaBridge	172:65be27845400	1245	* @arg @ref LL_DMAMUX1_REQ_I2C3_RX
AnnaBridge	172:65be27845400	1246	* @arg @ref LL_DMAMUX1_REQ_I2C3_TX
AnnaBridge	172:65be27845400	1247	* @arg @ref LL_DMAMUX1_REQ_DCMI
AnnaBridge	172:65be27845400	1248	* @arg @ref LL_DMAMUX1_REQ_CRYP_IN
AnnaBridge	172:65be27845400	1249	* @arg @ref LL_DMAMUX1_REQ_CRYP_OUT
AnnaBridge	172:65be27845400	1250	* @arg @ref LL_DMAMUX1_REQ_HASH_IN
AnnaBridge	172:65be27845400	1251	* @arg @ref LL_DMAMUX1_REQ_UART7_RX
AnnaBridge	172:65be27845400	1252	* @arg @ref LL_DMAMUX1_REQ_UART7_TX
AnnaBridge	172:65be27845400	1253	* @arg @ref LL_DMAMUX1_REQ_UART8_RX
AnnaBridge	172:65be27845400	1254	* @arg @ref LL_DMAMUX1_REQ_UART8_TX
AnnaBridge	172:65be27845400	1255	* @arg @ref LL_DMAMUX1_REQ_SPI4_RX
AnnaBridge	172:65be27845400	1256	* @arg @ref LL_DMAMUX1_REQ_SPI4_TX
AnnaBridge	172:65be27845400	1257	* @arg @ref LL_DMAMUX1_REQ_SPI5_RX
AnnaBridge	172:65be27845400	1258	* @arg @ref LL_DMAMUX1_REQ_SPI5_TX
AnnaBridge	172:65be27845400	1259	* @arg @ref LL_DMAMUX1_REQ_SAI1_A
AnnaBridge	172:65be27845400	1260	* @arg @ref LL_DMAMUX1_REQ_SAI1_B
AnnaBridge	172:65be27845400	1261	* @arg @ref LL_DMAMUX1_REQ_SAI2_A
AnnaBridge	172:65be27845400	1262	* @arg @ref LL_DMAMUX1_REQ_SAI2_B
AnnaBridge	172:65be27845400	1263	* @arg @ref LL_DMAMUX1_REQ_SWPMI_RX
AnnaBridge	172:65be27845400	1264	* @arg @ref LL_DMAMUX1_REQ_SWPMI_TX
AnnaBridge	172:65be27845400	1265	* @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT
AnnaBridge	172:65be27845400	1266	* @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS
AnnaBridge	172:65be27845400	1267	* @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER
AnnaBridge	172:65be27845400	1268	* @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A
AnnaBridge	172:65be27845400	1269	* @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B
AnnaBridge	172:65be27845400	1270	* @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C
AnnaBridge	172:65be27845400	1271	* @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D
AnnaBridge	172:65be27845400	1272	* @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E
AnnaBridge	172:65be27845400	1273	* @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0
AnnaBridge	172:65be27845400	1274	* @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1
AnnaBridge	172:65be27845400	1275	* @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2
AnnaBridge	172:65be27845400	1276	* @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3
AnnaBridge	172:65be27845400	1277	* @arg @ref LL_DMAMUX1_REQ_TIM15_CH1
AnnaBridge	172:65be27845400	1278	* @arg @ref LL_DMAMUX1_REQ_TIM15_UP
AnnaBridge	172:65be27845400	1279	* @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG
AnnaBridge	172:65be27845400	1280	* @arg @ref LL_DMAMUX1_REQ_TIM15_COM
AnnaBridge	172:65be27845400	1281	* @arg @ref LL_DMAMUX1_REQ_TIM16_CH1
AnnaBridge	172:65be27845400	1282	* @arg @ref LL_DMAMUX1_REQ_TIM16_UP
AnnaBridge	172:65be27845400	1283	* @arg @ref LL_DMAMUX1_REQ_TIM17_CH1
AnnaBridge	172:65be27845400	1284	* @arg @ref LL_DMAMUX1_REQ_TIM17_UP
AnnaBridge	172:65be27845400	1285	* @arg @ref LL_DMAMUX1_REQ_SAI3_A
AnnaBridge	172:65be27845400	1286	* @arg @ref LL_DMAMUX1_REQ_SAI3_B
AnnaBridge	172:65be27845400	1287	* @arg @ref LL_DMAMUX1_REQ_ADC3
AnnaBridge	172:65be27845400	1288	*/
AnnaBridge	172:65be27845400	1289	__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	172:65be27845400	1290	{
AnnaBridge	172:65be27845400	1291	return (READ_BIT(((DMAMUX_Channel_TypeDef )((uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE (Stream)) + (uint32_t)(DMAMUX_CCR_SIZE * LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx)))))->CCR, DMAMUX_CxCR_DMAREQ_ID));
AnnaBridge	172:65be27845400	1292	}
AnnaBridge	172:65be27845400	1293	/**
AnnaBridge	172:65be27845400	1294	* @brief Set Memory burst transfer configuration.
AnnaBridge	172:65be27845400	1295	* @rmtoll CR MBURST LL_DMA_SetMemoryBurstxfer
AnnaBridge	172:65be27845400	1296	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1297	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1298	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	1299	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	1300	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	1301	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	1302	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	1303	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	1304	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	1305	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	1306	* @param Mburst This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1307	* @arg @ref LL_DMA_MBURST_SINGLE
AnnaBridge	172:65be27845400	1308	* @arg @ref LL_DMA_MBURST_INC4
AnnaBridge	172:65be27845400	1309	* @arg @ref LL_DMA_MBURST_INC8
AnnaBridge	172:65be27845400	1310	* @arg @ref LL_DMA_MBURST_INC16
AnnaBridge	172:65be27845400	1311	* @retval None
AnnaBridge	172:65be27845400	1312	*/
AnnaBridge	172:65be27845400	1313	__STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst)
AnnaBridge	172:65be27845400	1314	{
AnnaBridge	172:65be27845400	1315	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	1316
AnnaBridge	172:65be27845400	1317	MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MBURST, Mburst);
AnnaBridge	172:65be27845400	1318	}
AnnaBridge	172:65be27845400	1319
AnnaBridge	172:65be27845400	1320	/**
AnnaBridge	172:65be27845400	1321	* @brief Get Memory burst transfer configuration.
AnnaBridge	172:65be27845400	1322	* @rmtoll CR MBURST LL_DMA_GetMemoryBurstxfer
AnnaBridge	172:65be27845400	1323	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1324	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1325	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	1326	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	1327	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	1328	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	1329	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	1330	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	1331	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	1332	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	1333	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1334	* @arg @ref LL_DMA_MBURST_SINGLE
AnnaBridge	172:65be27845400	1335	* @arg @ref LL_DMA_MBURST_INC4
AnnaBridge	172:65be27845400	1336	* @arg @ref LL_DMA_MBURST_INC8
AnnaBridge	172:65be27845400	1337	* @arg @ref LL_DMA_MBURST_INC16
AnnaBridge	172:65be27845400	1338	*/
AnnaBridge	172:65be27845400	1339	__STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	172:65be27845400	1340	{
AnnaBridge	172:65be27845400	1341	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	1342
AnnaBridge	172:65be27845400	1343	return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MBURST));
AnnaBridge	172:65be27845400	1344	}
AnnaBridge	172:65be27845400	1345
AnnaBridge	172:65be27845400	1346	/**
AnnaBridge	172:65be27845400	1347	* @brief Set Peripheral burst transfer configuration.
AnnaBridge	172:65be27845400	1348	* @rmtoll CR PBURST LL_DMA_SetPeriphBurstxfer
AnnaBridge	172:65be27845400	1349	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1350	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1351	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	1352	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	1353	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	1354	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	1355	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	1356	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	1357	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	1358	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	1359	* @param Pburst This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1360	* @arg @ref LL_DMA_PBURST_SINGLE
AnnaBridge	172:65be27845400	1361	* @arg @ref LL_DMA_PBURST_INC4
AnnaBridge	172:65be27845400	1362	* @arg @ref LL_DMA_PBURST_INC8
AnnaBridge	172:65be27845400	1363	* @arg @ref LL_DMA_PBURST_INC16
AnnaBridge	172:65be27845400	1364	* @retval None
AnnaBridge	172:65be27845400	1365	*/
AnnaBridge	172:65be27845400	1366	__STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst)
AnnaBridge	172:65be27845400	1367	{
AnnaBridge	172:65be27845400	1368	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	1369
AnnaBridge	172:65be27845400	1370	MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PBURST, Pburst);
AnnaBridge	172:65be27845400	1371	}
AnnaBridge	172:65be27845400	1372
AnnaBridge	172:65be27845400	1373	/**
AnnaBridge	172:65be27845400	1374	* @brief Get Peripheral burst transfer configuration.
AnnaBridge	172:65be27845400	1375	* @rmtoll CR PBURST LL_DMA_GetPeriphBurstxfer
AnnaBridge	172:65be27845400	1376	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1377	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1378	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	1379	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	1380	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	1381	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	1382	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	1383	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	1384	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	1385	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	1386	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1387	* @arg @ref LL_DMA_PBURST_SINGLE
AnnaBridge	172:65be27845400	1388	* @arg @ref LL_DMA_PBURST_INC4
AnnaBridge	172:65be27845400	1389	* @arg @ref LL_DMA_PBURST_INC8
AnnaBridge	172:65be27845400	1390	* @arg @ref LL_DMA_PBURST_INC16
AnnaBridge	172:65be27845400	1391	*/
AnnaBridge	172:65be27845400	1392	__STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	172:65be27845400	1393	{
AnnaBridge	172:65be27845400	1394	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	1395
AnnaBridge	172:65be27845400	1396	return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PBURST));
AnnaBridge	172:65be27845400	1397	}
AnnaBridge	172:65be27845400	1398
AnnaBridge	172:65be27845400	1399	/**
AnnaBridge	172:65be27845400	1400	* @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
AnnaBridge	172:65be27845400	1401	* @rmtoll CR CT LL_DMA_SetCurrentTargetMem
AnnaBridge	172:65be27845400	1402	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1403	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1404	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	1405	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	1406	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	1407	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	1408	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	1409	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	1410	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	1411	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	1412	* @param CurrentMemory This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1413	* @arg @ref LL_DMA_CURRENTTARGETMEM0
AnnaBridge	172:65be27845400	1414	* @arg @ref LL_DMA_CURRENTTARGETMEM1
AnnaBridge	172:65be27845400	1415	* @retval None
AnnaBridge	172:65be27845400	1416	*/
AnnaBridge	172:65be27845400	1417	__STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory)
AnnaBridge	172:65be27845400	1418	{
AnnaBridge	172:65be27845400	1419	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	1420
AnnaBridge	172:65be27845400	1421	MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CT, CurrentMemory);
AnnaBridge	172:65be27845400	1422	}
AnnaBridge	172:65be27845400	1423
AnnaBridge	172:65be27845400	1424	/**
AnnaBridge	172:65be27845400	1425	* @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
AnnaBridge	172:65be27845400	1426	* @rmtoll CR CT LL_DMA_GetCurrentTargetMem
AnnaBridge	172:65be27845400	1427	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1428	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1429	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	1430	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	1431	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	1432	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	1433	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	1434	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	1435	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	1436	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	1437	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1438	* @arg @ref LL_DMA_CURRENTTARGETMEM0
AnnaBridge	172:65be27845400	1439	* @arg @ref LL_DMA_CURRENTTARGETMEM1
AnnaBridge	172:65be27845400	1440	*/
AnnaBridge	172:65be27845400	1441	__STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	172:65be27845400	1442	{
AnnaBridge	172:65be27845400	1443	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	1444
AnnaBridge	172:65be27845400	1445	return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CT));
AnnaBridge	172:65be27845400	1446	}
AnnaBridge	172:65be27845400	1447
AnnaBridge	172:65be27845400	1448	/**
AnnaBridge	172:65be27845400	1449	* @brief Enable the double buffer mode.
AnnaBridge	172:65be27845400	1450	* @rmtoll CR DBM LL_DMA_EnableDoubleBufferMode
AnnaBridge	172:65be27845400	1451	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1452	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1453	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	1454	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	1455	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	1456	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	1457	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	1458	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	1459	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	1460	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	1461	* @retval None
AnnaBridge	172:65be27845400	1462	*/
AnnaBridge	172:65be27845400	1463	__STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	172:65be27845400	1464	{
AnnaBridge	172:65be27845400	1465	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	1466
AnnaBridge	172:65be27845400	1467	SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM);
AnnaBridge	172:65be27845400	1468	}
AnnaBridge	172:65be27845400	1469
AnnaBridge	172:65be27845400	1470	/**
AnnaBridge	172:65be27845400	1471	* @brief Disable the double buffer mode.
AnnaBridge	172:65be27845400	1472	* @rmtoll CR DBM LL_DMA_DisableDoubleBufferMode
AnnaBridge	172:65be27845400	1473	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1474	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1475	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	1476	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	1477	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	1478	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	1479	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	1480	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	1481	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	1482	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	1483	* @retval None
AnnaBridge	172:65be27845400	1484	*/
AnnaBridge	172:65be27845400	1485	__STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	172:65be27845400	1486	{
AnnaBridge	172:65be27845400	1487	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	1488
AnnaBridge	172:65be27845400	1489	CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM);
AnnaBridge	172:65be27845400	1490	}
AnnaBridge	172:65be27845400	1491
AnnaBridge	172:65be27845400	1492	/**
AnnaBridge	172:65be27845400	1493	* @brief Get FIFO status.
AnnaBridge	172:65be27845400	1494	* @rmtoll FCR FS LL_DMA_GetFIFOStatus
AnnaBridge	172:65be27845400	1495	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1496	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1497	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	1498	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	1499	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	1500	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	1501	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	1502	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	1503	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	1504	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	1505	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1506	* @arg @ref LL_DMA_FIFOSTATUS_0_25
AnnaBridge	172:65be27845400	1507	* @arg @ref LL_DMA_FIFOSTATUS_25_50
AnnaBridge	172:65be27845400	1508	* @arg @ref LL_DMA_FIFOSTATUS_50_75
AnnaBridge	172:65be27845400	1509	* @arg @ref LL_DMA_FIFOSTATUS_75_100
AnnaBridge	172:65be27845400	1510	* @arg @ref LL_DMA_FIFOSTATUS_EMPTY
AnnaBridge	172:65be27845400	1511	* @arg @ref LL_DMA_FIFOSTATUS_FULL
AnnaBridge	172:65be27845400	1512	*/
AnnaBridge	172:65be27845400	1513	__STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	172:65be27845400	1514	{
AnnaBridge	172:65be27845400	1515	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	1516
AnnaBridge	172:65be27845400	1517	return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FS));
AnnaBridge	172:65be27845400	1518	}
AnnaBridge	172:65be27845400	1519
AnnaBridge	172:65be27845400	1520	/**
AnnaBridge	172:65be27845400	1521	* @brief Disable Fifo mode.
AnnaBridge	172:65be27845400	1522	* @rmtoll FCR DMDIS LL_DMA_DisableFifoMode
AnnaBridge	172:65be27845400	1523	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1524	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1525	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	1526	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	1527	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	1528	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	1529	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	1530	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	1531	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	1532	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	1533	* @retval None
AnnaBridge	172:65be27845400	1534	*/
AnnaBridge	172:65be27845400	1535	__STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	172:65be27845400	1536	{
AnnaBridge	172:65be27845400	1537	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	1538
AnnaBridge	172:65be27845400	1539	CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_DMDIS);
AnnaBridge	172:65be27845400	1540	}
AnnaBridge	172:65be27845400	1541
AnnaBridge	172:65be27845400	1542	/**
AnnaBridge	172:65be27845400	1543	* @brief Enable Fifo mode.
AnnaBridge	172:65be27845400	1544	* @rmtoll FCR DMDIS LL_DMA_EnableFifoMode
AnnaBridge	172:65be27845400	1545	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1546	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1547	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	1548	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	1549	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	1550	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	1551	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	1552	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	1553	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	1554	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	1555	* @retval None
AnnaBridge	172:65be27845400	1556	*/
AnnaBridge	172:65be27845400	1557	__STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	172:65be27845400	1558	{
AnnaBridge	172:65be27845400	1559	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	1560
AnnaBridge	172:65be27845400	1561	SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_DMDIS);
AnnaBridge	172:65be27845400	1562	}
AnnaBridge	172:65be27845400	1563
AnnaBridge	172:65be27845400	1564	/**
AnnaBridge	172:65be27845400	1565	* @brief Select FIFO threshold.
AnnaBridge	172:65be27845400	1566	* @rmtoll FCR FTH LL_DMA_SetFIFOThreshold
AnnaBridge	172:65be27845400	1567	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1568	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1569	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	1570	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	1571	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	1572	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	1573	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	1574	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	1575	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	1576	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	1577	* @param Threshold This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1578	* @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
AnnaBridge	172:65be27845400	1579	* @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
AnnaBridge	172:65be27845400	1580	* @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
AnnaBridge	172:65be27845400	1581	* @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
AnnaBridge	172:65be27845400	1582	* @retval None
AnnaBridge	172:65be27845400	1583	*/
AnnaBridge	172:65be27845400	1584	__STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold)
AnnaBridge	172:65be27845400	1585	{
AnnaBridge	172:65be27845400	1586	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	1587
AnnaBridge	172:65be27845400	1588	MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH, Threshold);
AnnaBridge	172:65be27845400	1589	}
AnnaBridge	172:65be27845400	1590
AnnaBridge	172:65be27845400	1591	/**
AnnaBridge	172:65be27845400	1592	* @brief Get FIFO threshold.
AnnaBridge	172:65be27845400	1593	* @rmtoll FCR FTH LL_DMA_GetFIFOThreshold
AnnaBridge	172:65be27845400	1594	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1595	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1596	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	1597	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	1598	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	1599	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	1600	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	1601	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	1602	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	1603	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	1604	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1605	* @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
AnnaBridge	172:65be27845400	1606	* @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
AnnaBridge	172:65be27845400	1607	* @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
AnnaBridge	172:65be27845400	1608	* @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
AnnaBridge	172:65be27845400	1609	*/
AnnaBridge	172:65be27845400	1610	__STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	172:65be27845400	1611	{
AnnaBridge	172:65be27845400	1612	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	1613
AnnaBridge	172:65be27845400	1614	return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH));
AnnaBridge	172:65be27845400	1615	}
AnnaBridge	172:65be27845400	1616
AnnaBridge	172:65be27845400	1617	/**
AnnaBridge	172:65be27845400	1618	* @brief Configure the FIFO .
AnnaBridge	172:65be27845400	1619	* @rmtoll FCR FTH LL_DMA_ConfigFifo\n
AnnaBridge	172:65be27845400	1620	* FCR DMDIS LL_DMA_ConfigFifo
AnnaBridge	172:65be27845400	1621	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1622	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1623	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	1624	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	1625	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	1626	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	1627	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	1628	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	1629	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	1630	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	1631	* @param FifoMode This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1632	* @arg @ref LL_DMA_FIFOMODE_ENABLE
AnnaBridge	172:65be27845400	1633	* @arg @ref LL_DMA_FIFOMODE_DISABLE
AnnaBridge	172:65be27845400	1634	* @param FifoThreshold This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1635	* @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
AnnaBridge	172:65be27845400	1636	* @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
AnnaBridge	172:65be27845400	1637	* @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
AnnaBridge	172:65be27845400	1638	* @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
AnnaBridge	172:65be27845400	1639	* @retval None
AnnaBridge	172:65be27845400	1640	*/
AnnaBridge	172:65be27845400	1641	__STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold)
AnnaBridge	172:65be27845400	1642	{
AnnaBridge	172:65be27845400	1643	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	1644
AnnaBridge	172:65be27845400	1645	MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH \| DMA_SxFCR_DMDIS, FifoMode \| FifoThreshold);
AnnaBridge	172:65be27845400	1646	}
AnnaBridge	172:65be27845400	1647
AnnaBridge	172:65be27845400	1648	/**
AnnaBridge	172:65be27845400	1649	* @brief Configure the Source and Destination addresses.
AnnaBridge	172:65be27845400	1650	* @note This API must not be called when the DMA stream is enabled.
AnnaBridge	172:65be27845400	1651	* @rmtoll M0AR M0A LL_DMA_ConfigAddresses\n
AnnaBridge	172:65be27845400	1652	* PAR PA LL_DMA_ConfigAddresses
AnnaBridge	172:65be27845400	1653	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1654	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1655	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	1656	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	1657	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	1658	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	1659	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	1660	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	1661	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	1662	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	1663	* @param SrcAddress Between 0 to 0xFFFFFFFF
AnnaBridge	172:65be27845400	1664	* @param DstAddress Between 0 to 0xFFFFFFFF
AnnaBridge	172:65be27845400	1665	* @param Direction This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1666	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
AnnaBridge	172:65be27845400	1667	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
AnnaBridge	172:65be27845400	1668	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge	172:65be27845400	1669	* @retval None
AnnaBridge	172:65be27845400	1670	*/
AnnaBridge	172:65be27845400	1671	__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)
AnnaBridge	172:65be27845400	1672	{
AnnaBridge	172:65be27845400	1673	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	1674
AnnaBridge	172:65be27845400	1675	/* Direction Memory to Periph */
AnnaBridge	172:65be27845400	1676	if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
AnnaBridge	172:65be27845400	1677	{
AnnaBridge	172:65be27845400	1678	WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, SrcAddress);
AnnaBridge	172:65be27845400	1679	WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, DstAddress);
AnnaBridge	172:65be27845400	1680	}
AnnaBridge	172:65be27845400	1681	/* Direction Periph to Memory and Memory to Memory */
AnnaBridge	172:65be27845400	1682	else
AnnaBridge	172:65be27845400	1683	{
AnnaBridge	172:65be27845400	1684	WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, SrcAddress);
AnnaBridge	172:65be27845400	1685	WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, DstAddress);
AnnaBridge	172:65be27845400	1686	}
AnnaBridge	172:65be27845400	1687	}
AnnaBridge	172:65be27845400	1688
AnnaBridge	172:65be27845400	1689	/**
AnnaBridge	172:65be27845400	1690	* @brief Set the Memory address.
AnnaBridge	172:65be27845400	1691	* @rmtoll M0AR M0A LL_DMA_SetMemoryAddress
AnnaBridge	172:65be27845400	1692	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge	172:65be27845400	1693	* @note This API must not be called when the DMA stream is enabled.
AnnaBridge	172:65be27845400	1694	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1695	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1696	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	1697	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	1698	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	1699	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	1700	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	1701	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	1702	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	1703	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	1704	* @param MemoryAddress Between 0 to 0xFFFFFFFF
AnnaBridge	172:65be27845400	1705	* @retval None
AnnaBridge	172:65be27845400	1706	*/
AnnaBridge	172:65be27845400	1707	__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress)
AnnaBridge	172:65be27845400	1708	{
AnnaBridge	172:65be27845400	1709	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	1710
AnnaBridge	172:65be27845400	1711	WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, MemoryAddress);
AnnaBridge	172:65be27845400	1712	}
AnnaBridge	172:65be27845400	1713
AnnaBridge	172:65be27845400	1714	/**
AnnaBridge	172:65be27845400	1715	* @brief Set the Peripheral address.
AnnaBridge	172:65be27845400	1716	* @rmtoll PAR PA LL_DMA_SetPeriphAddress
AnnaBridge	172:65be27845400	1717	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge	172:65be27845400	1718	* @note This API must not be called when the DMA stream is enabled.
AnnaBridge	172:65be27845400	1719	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1720	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1721	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	1722	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	1723	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	1724	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	1725	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	1726	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	1727	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	1728	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	1729	* @param PeriphAddress Between 0 to 0xFFFFFFFF
AnnaBridge	172:65be27845400	1730	* @retval None
AnnaBridge	172:65be27845400	1731	*/
AnnaBridge	172:65be27845400	1732	__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t PeriphAddress)
AnnaBridge	172:65be27845400	1733	{
AnnaBridge	172:65be27845400	1734	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	1735
AnnaBridge	172:65be27845400	1736	WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, PeriphAddress);
AnnaBridge	172:65be27845400	1737	}
AnnaBridge	172:65be27845400	1738
AnnaBridge	172:65be27845400	1739	/**
AnnaBridge	172:65be27845400	1740	* @brief Get the Memory address.
AnnaBridge	172:65be27845400	1741	* @rmtoll M0AR M0A LL_DMA_GetMemoryAddress
AnnaBridge	172:65be27845400	1742	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge	172:65be27845400	1743	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1744	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1745	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	1746	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	1747	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	1748	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	1749	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	1750	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	1751	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	1752	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	1753	* @retval Between 0 to 0xFFFFFFFF
AnnaBridge	172:65be27845400	1754	*/
AnnaBridge	172:65be27845400	1755	__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	172:65be27845400	1756	{
AnnaBridge	172:65be27845400	1757	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	1758
AnnaBridge	172:65be27845400	1759	return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR));
AnnaBridge	172:65be27845400	1760	}
AnnaBridge	172:65be27845400	1761
AnnaBridge	172:65be27845400	1762	/**
AnnaBridge	172:65be27845400	1763	* @brief Get the Peripheral address.
AnnaBridge	172:65be27845400	1764	* @rmtoll PAR PA LL_DMA_GetPeriphAddress
AnnaBridge	172:65be27845400	1765	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge	172:65be27845400	1766	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1767	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1768	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	1769	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	1770	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	1771	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	1772	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	1773	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	1774	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	1775	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	1776	* @retval Between 0 to 0xFFFFFFFF
AnnaBridge	172:65be27845400	1777	*/
AnnaBridge	172:65be27845400	1778	__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	172:65be27845400	1779	{
AnnaBridge	172:65be27845400	1780	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	1781
AnnaBridge	172:65be27845400	1782	return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR));
AnnaBridge	172:65be27845400	1783	}
AnnaBridge	172:65be27845400	1784
AnnaBridge	172:65be27845400	1785	/**
AnnaBridge	172:65be27845400	1786	* @brief Set the Memory to Memory Source address.
AnnaBridge	172:65be27845400	1787	* @rmtoll PAR PA LL_DMA_SetM2MSrcAddress
AnnaBridge	172:65be27845400	1788	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge	172:65be27845400	1789	* @note This API must not be called when the DMA stream is enabled.
AnnaBridge	172:65be27845400	1790	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1791	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1792	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	1793	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	1794	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	1795	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	1796	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	1797	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	1798	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	1799	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	1800	* @param MemoryAddress Between 0 to 0xFFFFFFFF
AnnaBridge	172:65be27845400	1801	* @retval None
AnnaBridge	172:65be27845400	1802	*/
AnnaBridge	172:65be27845400	1803	__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress)
AnnaBridge	172:65be27845400	1804	{
AnnaBridge	172:65be27845400	1805	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	1806
AnnaBridge	172:65be27845400	1807	WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, MemoryAddress);
AnnaBridge	172:65be27845400	1808	}
AnnaBridge	172:65be27845400	1809
AnnaBridge	172:65be27845400	1810	/**
AnnaBridge	172:65be27845400	1811	* @brief Set the Memory to Memory Destination address.
AnnaBridge	172:65be27845400	1812	* @rmtoll M0AR M0A LL_DMA_SetM2MDstAddress
AnnaBridge	172:65be27845400	1813	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge	172:65be27845400	1814	* @note This API must not be called when the DMA stream is enabled.
AnnaBridge	172:65be27845400	1815	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1816	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1817	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	1818	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	1819	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	1820	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	1821	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	1822	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	1823	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	1824	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	1825	* @param MemoryAddress Between 0 to 0xFFFFFFFF
AnnaBridge	172:65be27845400	1826	* @retval None
AnnaBridge	172:65be27845400	1827	*/
AnnaBridge	172:65be27845400	1828	__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress)
AnnaBridge	172:65be27845400	1829	{
AnnaBridge	172:65be27845400	1830	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	1831
AnnaBridge	172:65be27845400	1832	WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, MemoryAddress);
AnnaBridge	172:65be27845400	1833	}
AnnaBridge	172:65be27845400	1834
AnnaBridge	172:65be27845400	1835	/**
AnnaBridge	172:65be27845400	1836	* @brief Get the Memory to Memory Source address.
AnnaBridge	172:65be27845400	1837	* @rmtoll PAR PA LL_DMA_GetM2MSrcAddress
AnnaBridge	172:65be27845400	1838	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge	172:65be27845400	1839	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1840	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1841	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	1842	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	1843	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	1844	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	1845	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	1846	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	1847	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	1848	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	1849	* @retval Between 0 to 0xFFFFFFFF
AnnaBridge	172:65be27845400	1850	*/
AnnaBridge	172:65be27845400	1851	__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	172:65be27845400	1852	{
AnnaBridge	172:65be27845400	1853	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	1854
AnnaBridge	172:65be27845400	1855	return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR));
AnnaBridge	172:65be27845400	1856	}
AnnaBridge	172:65be27845400	1857
AnnaBridge	172:65be27845400	1858	/**
AnnaBridge	172:65be27845400	1859	* @brief Get the Memory to Memory Destination address.
AnnaBridge	172:65be27845400	1860	* @rmtoll M0AR M0A LL_DMA_GetM2MDstAddress
AnnaBridge	172:65be27845400	1861	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge	172:65be27845400	1862	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1863	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1864	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	1865	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	1866	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	1867	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	1868	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	1869	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	1870	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	1871	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	1872	* @retval Between 0 to 0xFFFFFFFF
AnnaBridge	172:65be27845400	1873	*/
AnnaBridge	172:65be27845400	1874	__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	172:65be27845400	1875	{
AnnaBridge	172:65be27845400	1876	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	1877
AnnaBridge	172:65be27845400	1878	return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR));
AnnaBridge	172:65be27845400	1879	}
AnnaBridge	172:65be27845400	1880
AnnaBridge	172:65be27845400	1881	/**
AnnaBridge	172:65be27845400	1882	* @brief Set Memory 1 address (used in case of Double buffer mode).
AnnaBridge	172:65be27845400	1883	* @rmtoll M1AR M1A LL_DMA_SetMemory1Address
AnnaBridge	172:65be27845400	1884	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1885	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1886	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	1887	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	1888	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	1889	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	1890	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	1891	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	1892	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	1893	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	1894	* @param Address Between 0 to 0xFFFFFFFF
AnnaBridge	172:65be27845400	1895	* @retval None
AnnaBridge	172:65be27845400	1896	*/
AnnaBridge	172:65be27845400	1897	__STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address)
AnnaBridge	172:65be27845400	1898	{
AnnaBridge	172:65be27845400	1899	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	1900
AnnaBridge	172:65be27845400	1901	MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M1AR, DMA_SxM1AR_M1A, Address);
AnnaBridge	172:65be27845400	1902	}
AnnaBridge	172:65be27845400	1903
AnnaBridge	172:65be27845400	1904	/**
AnnaBridge	172:65be27845400	1905	* @brief Get Memory 1 address (used in case of Double buffer mode).
AnnaBridge	172:65be27845400	1906	* @rmtoll M1AR M1A LL_DMA_GetMemory1Address
AnnaBridge	172:65be27845400	1907	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1908	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1909	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	1910	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	1911	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	1912	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	1913	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	1914	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	1915	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	1916	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	1917	* @retval Between 0 to 0xFFFFFFFF
AnnaBridge	172:65be27845400	1918	*/
AnnaBridge	172:65be27845400	1919	__STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	172:65be27845400	1920	{
AnnaBridge	172:65be27845400	1921	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	1922
AnnaBridge	172:65be27845400	1923	return (((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M1AR);
AnnaBridge	172:65be27845400	1924	}
AnnaBridge	172:65be27845400	1925
AnnaBridge	172:65be27845400	1926	/**
AnnaBridge	172:65be27845400	1927	* @}
AnnaBridge	172:65be27845400	1928	*/
AnnaBridge	172:65be27845400	1929
AnnaBridge	172:65be27845400	1930	/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
AnnaBridge	172:65be27845400	1931	* @{
AnnaBridge	172:65be27845400	1932	*/
AnnaBridge	172:65be27845400	1933
AnnaBridge	172:65be27845400	1934	/**
AnnaBridge	172:65be27845400	1935	* @brief Get Stream 0 half transfer flag.
AnnaBridge	172:65be27845400	1936	* @rmtoll LISR HTIF0 LL_DMA_IsActiveFlag_HT0
AnnaBridge	172:65be27845400	1937	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1938	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1939	*/
AnnaBridge	172:65be27845400	1940	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	1941	{
AnnaBridge	172:65be27845400	1942	return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF0) == (DMA_LISR_HTIF0)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1943	}
AnnaBridge	172:65be27845400	1944
AnnaBridge	172:65be27845400	1945	/**
AnnaBridge	172:65be27845400	1946	* @brief Get Stream 1 half transfer flag.
AnnaBridge	172:65be27845400	1947	* @rmtoll LISR HTIF1 LL_DMA_IsActiveFlag_HT1
AnnaBridge	172:65be27845400	1948	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1949	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1950	*/
AnnaBridge	172:65be27845400	1951	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	1952	{
AnnaBridge	172:65be27845400	1953	return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF1) == (DMA_LISR_HTIF1)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1954	}
AnnaBridge	172:65be27845400	1955
AnnaBridge	172:65be27845400	1956	/**
AnnaBridge	172:65be27845400	1957	* @brief Get Stream 2 half transfer flag.
AnnaBridge	172:65be27845400	1958	* @rmtoll LISR HTIF2 LL_DMA_IsActiveFlag_HT2
AnnaBridge	172:65be27845400	1959	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1960	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1961	*/
AnnaBridge	172:65be27845400	1962	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	1963	{
AnnaBridge	172:65be27845400	1964	return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF2) == (DMA_LISR_HTIF2)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1965	}
AnnaBridge	172:65be27845400	1966
AnnaBridge	172:65be27845400	1967	/**
AnnaBridge	172:65be27845400	1968	* @brief Get Stream 3 half transfer flag.
AnnaBridge	172:65be27845400	1969	* @rmtoll LISR HTIF3 LL_DMA_IsActiveFlag_HT3
AnnaBridge	172:65be27845400	1970	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1971	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1972	*/
AnnaBridge	172:65be27845400	1973	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	1974	{
AnnaBridge	172:65be27845400	1975	return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF3) == (DMA_LISR_HTIF3)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1976	}
AnnaBridge	172:65be27845400	1977
AnnaBridge	172:65be27845400	1978	/**
AnnaBridge	172:65be27845400	1979	* @brief Get Stream 4 half transfer flag.
AnnaBridge	172:65be27845400	1980	* @rmtoll HISR HTIF4 LL_DMA_IsActiveFlag_HT4
AnnaBridge	172:65be27845400	1981	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1982	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1983	*/
AnnaBridge	172:65be27845400	1984	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	1985	{
AnnaBridge	172:65be27845400	1986	return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF4) == (DMA_HISR_HTIF4)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1987	}
AnnaBridge	172:65be27845400	1988
AnnaBridge	172:65be27845400	1989	/**
AnnaBridge	172:65be27845400	1990	* @brief Get Stream 5 half transfer flag.
AnnaBridge	172:65be27845400	1991	* @rmtoll HISR HTIF0 LL_DMA_IsActiveFlag_HT5
AnnaBridge	172:65be27845400	1992	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	1993	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1994	*/
AnnaBridge	172:65be27845400	1995	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	1996	{
AnnaBridge	172:65be27845400	1997	return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF5) == (DMA_HISR_HTIF5)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1998	}
AnnaBridge	172:65be27845400	1999
AnnaBridge	172:65be27845400	2000	/**
AnnaBridge	172:65be27845400	2001	* @brief Get Stream 6 half transfer flag.
AnnaBridge	172:65be27845400	2002	* @rmtoll HISR HTIF6 LL_DMA_IsActiveFlag_HT6
AnnaBridge	172:65be27845400	2003	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2004	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	2005	*/
AnnaBridge	172:65be27845400	2006	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2007	{
AnnaBridge	172:65be27845400	2008	return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF6) == (DMA_HISR_HTIF6)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2009	}
AnnaBridge	172:65be27845400	2010
AnnaBridge	172:65be27845400	2011	/**
AnnaBridge	172:65be27845400	2012	* @brief Get Stream 7 half transfer flag.
AnnaBridge	172:65be27845400	2013	* @rmtoll HISR HTIF7 LL_DMA_IsActiveFlag_HT7
AnnaBridge	172:65be27845400	2014	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2015	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	2016	*/
AnnaBridge	172:65be27845400	2017	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2018	{
AnnaBridge	172:65be27845400	2019	return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF7) == (DMA_HISR_HTIF7)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2020	}
AnnaBridge	172:65be27845400	2021
AnnaBridge	172:65be27845400	2022	/**
AnnaBridge	172:65be27845400	2023	* @brief Get Stream 0 transfer complete flag.
AnnaBridge	172:65be27845400	2024	* @rmtoll LISR TCIF0 LL_DMA_IsActiveFlag_TC0
AnnaBridge	172:65be27845400	2025	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2026	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	2027	*/
AnnaBridge	172:65be27845400	2028	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2029	{
AnnaBridge	172:65be27845400	2030	return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF0) == (DMA_LISR_TCIF0)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2031	}
AnnaBridge	172:65be27845400	2032
AnnaBridge	172:65be27845400	2033	/**
AnnaBridge	172:65be27845400	2034	* @brief Get Stream 1 transfer complete flag.
AnnaBridge	172:65be27845400	2035	* @rmtoll LISR TCIF1 LL_DMA_IsActiveFlag_TC1
AnnaBridge	172:65be27845400	2036	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2037	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	2038	*/
AnnaBridge	172:65be27845400	2039	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2040	{
AnnaBridge	172:65be27845400	2041	return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF1) == (DMA_LISR_TCIF1)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2042	}
AnnaBridge	172:65be27845400	2043
AnnaBridge	172:65be27845400	2044	/**
AnnaBridge	172:65be27845400	2045	* @brief Get Stream 2 transfer complete flag.
AnnaBridge	172:65be27845400	2046	* @rmtoll LISR TCIF2 LL_DMA_IsActiveFlag_TC2
AnnaBridge	172:65be27845400	2047	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2048	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	2049	*/
AnnaBridge	172:65be27845400	2050	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2051	{
AnnaBridge	172:65be27845400	2052	return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF2) == (DMA_LISR_TCIF2)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2053	}
AnnaBridge	172:65be27845400	2054
AnnaBridge	172:65be27845400	2055	/**
AnnaBridge	172:65be27845400	2056	* @brief Get Stream 3 transfer complete flag.
AnnaBridge	172:65be27845400	2057	* @rmtoll LISR TCIF3 LL_DMA_IsActiveFlag_TC3
AnnaBridge	172:65be27845400	2058	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2059	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	2060	*/
AnnaBridge	172:65be27845400	2061	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2062	{
AnnaBridge	172:65be27845400	2063	return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF3) == (DMA_LISR_TCIF3)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2064	}
AnnaBridge	172:65be27845400	2065
AnnaBridge	172:65be27845400	2066	/**
AnnaBridge	172:65be27845400	2067	* @brief Get Stream 4 transfer complete flag.
AnnaBridge	172:65be27845400	2068	* @rmtoll HISR TCIF4 LL_DMA_IsActiveFlag_TC4
AnnaBridge	172:65be27845400	2069	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2070	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	2071	*/
AnnaBridge	172:65be27845400	2072	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2073	{
AnnaBridge	172:65be27845400	2074	return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF4) == (DMA_HISR_TCIF4)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2075	}
AnnaBridge	172:65be27845400	2076
AnnaBridge	172:65be27845400	2077	/**
AnnaBridge	172:65be27845400	2078	* @brief Get Stream 5 transfer complete flag.
AnnaBridge	172:65be27845400	2079	* @rmtoll HISR TCIF0 LL_DMA_IsActiveFlag_TC5
AnnaBridge	172:65be27845400	2080	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2081	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	2082	*/
AnnaBridge	172:65be27845400	2083	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2084	{
AnnaBridge	172:65be27845400	2085	return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF5) == (DMA_HISR_TCIF5)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2086	}
AnnaBridge	172:65be27845400	2087
AnnaBridge	172:65be27845400	2088	/**
AnnaBridge	172:65be27845400	2089	* @brief Get Stream 6 transfer complete flag.
AnnaBridge	172:65be27845400	2090	* @rmtoll HISR TCIF6 LL_DMA_IsActiveFlag_TC6
AnnaBridge	172:65be27845400	2091	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2092	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	2093	*/
AnnaBridge	172:65be27845400	2094	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2095	{
AnnaBridge	172:65be27845400	2096	return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF6) == (DMA_HISR_TCIF6)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2097	}
AnnaBridge	172:65be27845400	2098
AnnaBridge	172:65be27845400	2099	/**
AnnaBridge	172:65be27845400	2100	* @brief Get Stream 7 transfer complete flag.
AnnaBridge	172:65be27845400	2101	* @rmtoll HISR TCIF7 LL_DMA_IsActiveFlag_TC7
AnnaBridge	172:65be27845400	2102	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2103	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	2104	*/
AnnaBridge	172:65be27845400	2105	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2106	{
AnnaBridge	172:65be27845400	2107	return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF7) == (DMA_HISR_TCIF7)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2108	}
AnnaBridge	172:65be27845400	2109
AnnaBridge	172:65be27845400	2110	/**
AnnaBridge	172:65be27845400	2111	* @brief Get Stream 0 transfer error flag.
AnnaBridge	172:65be27845400	2112	* @rmtoll LISR TEIF0 LL_DMA_IsActiveFlag_TE0
AnnaBridge	172:65be27845400	2113	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2114	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	2115	*/
AnnaBridge	172:65be27845400	2116	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2117	{
AnnaBridge	172:65be27845400	2118	return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF0) == (DMA_LISR_TEIF0)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2119	}
AnnaBridge	172:65be27845400	2120
AnnaBridge	172:65be27845400	2121	/**
AnnaBridge	172:65be27845400	2122	* @brief Get Stream 1 transfer error flag.
AnnaBridge	172:65be27845400	2123	* @rmtoll LISR TEIF1 LL_DMA_IsActiveFlag_TE1
AnnaBridge	172:65be27845400	2124	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2125	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	2126	*/
AnnaBridge	172:65be27845400	2127	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2128	{
AnnaBridge	172:65be27845400	2129	return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF1) == (DMA_LISR_TEIF1)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2130	}
AnnaBridge	172:65be27845400	2131
AnnaBridge	172:65be27845400	2132	/**
AnnaBridge	172:65be27845400	2133	* @brief Get Stream 2 transfer error flag.
AnnaBridge	172:65be27845400	2134	* @rmtoll LISR TEIF2 LL_DMA_IsActiveFlag_TE2
AnnaBridge	172:65be27845400	2135	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2136	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	2137	*/
AnnaBridge	172:65be27845400	2138	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2139	{
AnnaBridge	172:65be27845400	2140	return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF2) == (DMA_LISR_TEIF2)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2141	}
AnnaBridge	172:65be27845400	2142
AnnaBridge	172:65be27845400	2143	/**
AnnaBridge	172:65be27845400	2144	* @brief Get Stream 3 transfer error flag.
AnnaBridge	172:65be27845400	2145	* @rmtoll LISR TEIF3 LL_DMA_IsActiveFlag_TE3
AnnaBridge	172:65be27845400	2146	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2147	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	2148	*/
AnnaBridge	172:65be27845400	2149	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2150	{
AnnaBridge	172:65be27845400	2151	return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF3) == (DMA_LISR_TEIF3)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2152	}
AnnaBridge	172:65be27845400	2153
AnnaBridge	172:65be27845400	2154	/**
AnnaBridge	172:65be27845400	2155	* @brief Get Stream 4 transfer error flag.
AnnaBridge	172:65be27845400	2156	* @rmtoll HISR TEIF4 LL_DMA_IsActiveFlag_TE4
AnnaBridge	172:65be27845400	2157	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2158	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	2159	*/
AnnaBridge	172:65be27845400	2160	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2161	{
AnnaBridge	172:65be27845400	2162	return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF4) == (DMA_HISR_TEIF4)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2163	}
AnnaBridge	172:65be27845400	2164
AnnaBridge	172:65be27845400	2165	/**
AnnaBridge	172:65be27845400	2166	* @brief Get Stream 5 transfer error flag.
AnnaBridge	172:65be27845400	2167	* @rmtoll HISR TEIF0 LL_DMA_IsActiveFlag_TE5
AnnaBridge	172:65be27845400	2168	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2169	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	2170	*/
AnnaBridge	172:65be27845400	2171	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2172	{
AnnaBridge	172:65be27845400	2173	return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF5) == (DMA_HISR_TEIF5)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2174	}
AnnaBridge	172:65be27845400	2175
AnnaBridge	172:65be27845400	2176	/**
AnnaBridge	172:65be27845400	2177	* @brief Get Stream 6 transfer error flag.
AnnaBridge	172:65be27845400	2178	* @rmtoll HISR TEIF6 LL_DMA_IsActiveFlag_TE6
AnnaBridge	172:65be27845400	2179	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2180	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	2181	*/
AnnaBridge	172:65be27845400	2182	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2183	{
AnnaBridge	172:65be27845400	2184	return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF6) == (DMA_HISR_TEIF6)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2185	}
AnnaBridge	172:65be27845400	2186
AnnaBridge	172:65be27845400	2187	/**
AnnaBridge	172:65be27845400	2188	* @brief Get Stream 7 transfer error flag.
AnnaBridge	172:65be27845400	2189	* @rmtoll HISR TEIF7 LL_DMA_IsActiveFlag_TE7
AnnaBridge	172:65be27845400	2190	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2191	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	2192	*/
AnnaBridge	172:65be27845400	2193	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2194	{
AnnaBridge	172:65be27845400	2195	return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF7) == (DMA_HISR_TEIF7)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2196	}
AnnaBridge	172:65be27845400	2197
AnnaBridge	172:65be27845400	2198	/**
AnnaBridge	172:65be27845400	2199	* @brief Get Stream 0 direct mode error flag.
AnnaBridge	172:65be27845400	2200	* @rmtoll LISR DMEIF0 LL_DMA_IsActiveFlag_DME0
AnnaBridge	172:65be27845400	2201	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2202	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	2203	*/
AnnaBridge	172:65be27845400	2204	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2205	{
AnnaBridge	172:65be27845400	2206	return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF0) == (DMA_LISR_DMEIF0)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2207	}
AnnaBridge	172:65be27845400	2208
AnnaBridge	172:65be27845400	2209	/**
AnnaBridge	172:65be27845400	2210	* @brief Get Stream 1 direct mode error flag.
AnnaBridge	172:65be27845400	2211	* @rmtoll LISR DMEIF1 LL_DMA_IsActiveFlag_DME1
AnnaBridge	172:65be27845400	2212	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2213	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	2214	*/
AnnaBridge	172:65be27845400	2215	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2216	{
AnnaBridge	172:65be27845400	2217	return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF1) == (DMA_LISR_DMEIF1)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2218	}
AnnaBridge	172:65be27845400	2219
AnnaBridge	172:65be27845400	2220	/**
AnnaBridge	172:65be27845400	2221	* @brief Get Stream 2 direct mode error flag.
AnnaBridge	172:65be27845400	2222	* @rmtoll LISR DMEIF2 LL_DMA_IsActiveFlag_DME2
AnnaBridge	172:65be27845400	2223	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2224	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	2225	*/
AnnaBridge	172:65be27845400	2226	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2227	{
AnnaBridge	172:65be27845400	2228	return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF2) == (DMA_LISR_DMEIF2)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2229	}
AnnaBridge	172:65be27845400	2230
AnnaBridge	172:65be27845400	2231	/**
AnnaBridge	172:65be27845400	2232	* @brief Get Stream 3 direct mode error flag.
AnnaBridge	172:65be27845400	2233	* @rmtoll LISR DMEIF3 LL_DMA_IsActiveFlag_DME3
AnnaBridge	172:65be27845400	2234	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2235	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	2236	*/
AnnaBridge	172:65be27845400	2237	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2238	{
AnnaBridge	172:65be27845400	2239	return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF3) == (DMA_LISR_DMEIF3)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2240	}
AnnaBridge	172:65be27845400	2241
AnnaBridge	172:65be27845400	2242	/**
AnnaBridge	172:65be27845400	2243	* @brief Get Stream 4 direct mode error flag.
AnnaBridge	172:65be27845400	2244	* @rmtoll HISR DMEIF4 LL_DMA_IsActiveFlag_DME4
AnnaBridge	172:65be27845400	2245	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2246	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	2247	*/
AnnaBridge	172:65be27845400	2248	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2249	{
AnnaBridge	172:65be27845400	2250	return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF4) == (DMA_HISR_DMEIF4)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2251	}
AnnaBridge	172:65be27845400	2252
AnnaBridge	172:65be27845400	2253	/**
AnnaBridge	172:65be27845400	2254	* @brief Get Stream 5 direct mode error flag.
AnnaBridge	172:65be27845400	2255	* @rmtoll HISR DMEIF0 LL_DMA_IsActiveFlag_DME5
AnnaBridge	172:65be27845400	2256	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2257	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	2258	*/
AnnaBridge	172:65be27845400	2259	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2260	{
AnnaBridge	172:65be27845400	2261	return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF5) == (DMA_HISR_DMEIF5)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2262	}
AnnaBridge	172:65be27845400	2263
AnnaBridge	172:65be27845400	2264	/**
AnnaBridge	172:65be27845400	2265	* @brief Get Stream 6 direct mode error flag.
AnnaBridge	172:65be27845400	2266	* @rmtoll HISR DMEIF6 LL_DMA_IsActiveFlag_DME6
AnnaBridge	172:65be27845400	2267	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2268	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	2269	*/
AnnaBridge	172:65be27845400	2270	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2271	{
AnnaBridge	172:65be27845400	2272	return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF6) == (DMA_HISR_DMEIF6)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2273	}
AnnaBridge	172:65be27845400	2274
AnnaBridge	172:65be27845400	2275	/**
AnnaBridge	172:65be27845400	2276	* @brief Get Stream 7 direct mode error flag.
AnnaBridge	172:65be27845400	2277	* @rmtoll HISR DMEIF7 LL_DMA_IsActiveFlag_DME7
AnnaBridge	172:65be27845400	2278	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2279	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	2280	*/
AnnaBridge	172:65be27845400	2281	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2282	{
AnnaBridge	172:65be27845400	2283	return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF7) == (DMA_HISR_DMEIF7)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2284	}
AnnaBridge	172:65be27845400	2285
AnnaBridge	172:65be27845400	2286	/**
AnnaBridge	172:65be27845400	2287	* @brief Get Stream 0 FIFO error flag.
AnnaBridge	172:65be27845400	2288	* @rmtoll LISR FEIF0 LL_DMA_IsActiveFlag_FE0
AnnaBridge	172:65be27845400	2289	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2290	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	2291	*/
AnnaBridge	172:65be27845400	2292	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2293	{
AnnaBridge	172:65be27845400	2294	return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF0) == (DMA_LISR_FEIF0)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2295	}
AnnaBridge	172:65be27845400	2296
AnnaBridge	172:65be27845400	2297	/**
AnnaBridge	172:65be27845400	2298	* @brief Get Stream 1 FIFO error flag.
AnnaBridge	172:65be27845400	2299	* @rmtoll LISR FEIF1 LL_DMA_IsActiveFlag_FE1
AnnaBridge	172:65be27845400	2300	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2301	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	2302	*/
AnnaBridge	172:65be27845400	2303	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2304	{
AnnaBridge	172:65be27845400	2305	return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF1) == (DMA_LISR_FEIF1)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2306	}
AnnaBridge	172:65be27845400	2307
AnnaBridge	172:65be27845400	2308	/**
AnnaBridge	172:65be27845400	2309	* @brief Get Stream 2 FIFO error flag.
AnnaBridge	172:65be27845400	2310	* @rmtoll LISR FEIF2 LL_DMA_IsActiveFlag_FE2
AnnaBridge	172:65be27845400	2311	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2312	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	2313	*/
AnnaBridge	172:65be27845400	2314	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2315	{
AnnaBridge	172:65be27845400	2316	return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF2) == (DMA_LISR_FEIF2)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2317	}
AnnaBridge	172:65be27845400	2318
AnnaBridge	172:65be27845400	2319	/**
AnnaBridge	172:65be27845400	2320	* @brief Get Stream 3 FIFO error flag.
AnnaBridge	172:65be27845400	2321	* @rmtoll LISR FEIF3 LL_DMA_IsActiveFlag_FE3
AnnaBridge	172:65be27845400	2322	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2323	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	2324	*/
AnnaBridge	172:65be27845400	2325	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2326	{
AnnaBridge	172:65be27845400	2327	return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF3) == (DMA_LISR_FEIF3)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2328	}
AnnaBridge	172:65be27845400	2329
AnnaBridge	172:65be27845400	2330	/**
AnnaBridge	172:65be27845400	2331	* @brief Get Stream 4 FIFO error flag.
AnnaBridge	172:65be27845400	2332	* @rmtoll HISR FEIF4 LL_DMA_IsActiveFlag_FE4
AnnaBridge	172:65be27845400	2333	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2334	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	2335	*/
AnnaBridge	172:65be27845400	2336	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2337	{
AnnaBridge	172:65be27845400	2338	return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF4) == (DMA_HISR_FEIF4)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2339	}
AnnaBridge	172:65be27845400	2340
AnnaBridge	172:65be27845400	2341	/**
AnnaBridge	172:65be27845400	2342	* @brief Get Stream 5 FIFO error flag.
AnnaBridge	172:65be27845400	2343	* @rmtoll HISR FEIF0 LL_DMA_IsActiveFlag_FE5
AnnaBridge	172:65be27845400	2344	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2345	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	2346	*/
AnnaBridge	172:65be27845400	2347	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2348	{
AnnaBridge	172:65be27845400	2349	return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF5) == (DMA_HISR_FEIF5)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2350	}
AnnaBridge	172:65be27845400	2351
AnnaBridge	172:65be27845400	2352	/**
AnnaBridge	172:65be27845400	2353	* @brief Get Stream 6 FIFO error flag.
AnnaBridge	172:65be27845400	2354	* @rmtoll HISR FEIF6 LL_DMA_IsActiveFlag_FE6
AnnaBridge	172:65be27845400	2355	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2356	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	2357	*/
AnnaBridge	172:65be27845400	2358	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2359	{
AnnaBridge	172:65be27845400	2360	return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF6) == (DMA_HISR_FEIF6)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2361	}
AnnaBridge	172:65be27845400	2362
AnnaBridge	172:65be27845400	2363	/**
AnnaBridge	172:65be27845400	2364	* @brief Get Stream 7 FIFO error flag.
AnnaBridge	172:65be27845400	2365	* @rmtoll HISR FEIF7 LL_DMA_IsActiveFlag_FE7
AnnaBridge	172:65be27845400	2366	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2367	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	2368	*/
AnnaBridge	172:65be27845400	2369	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2370	{
AnnaBridge	172:65be27845400	2371	return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF7) == (DMA_HISR_FEIF7)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2372	}
AnnaBridge	172:65be27845400	2373
AnnaBridge	172:65be27845400	2374	/**
AnnaBridge	172:65be27845400	2375	* @brief Clear Stream 0 half transfer flag.
AnnaBridge	172:65be27845400	2376	* @rmtoll LIFCR CHTIF0 LL_DMA_ClearFlag_HT0
AnnaBridge	172:65be27845400	2377	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2378	* @retval None
AnnaBridge	172:65be27845400	2379	*/
AnnaBridge	172:65be27845400	2380	__STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2381	{
AnnaBridge	172:65be27845400	2382	WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF0);
AnnaBridge	172:65be27845400	2383	}
AnnaBridge	172:65be27845400	2384
AnnaBridge	172:65be27845400	2385	/**
AnnaBridge	172:65be27845400	2386	* @brief Clear Stream 1 half transfer flag.
AnnaBridge	172:65be27845400	2387	* @rmtoll LIFCR CHTIF1 LL_DMA_ClearFlag_HT1
AnnaBridge	172:65be27845400	2388	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2389	* @retval None
AnnaBridge	172:65be27845400	2390	*/
AnnaBridge	172:65be27845400	2391	__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2392	{
AnnaBridge	172:65be27845400	2393	WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF1);
AnnaBridge	172:65be27845400	2394	}
AnnaBridge	172:65be27845400	2395
AnnaBridge	172:65be27845400	2396	/**
AnnaBridge	172:65be27845400	2397	* @brief Clear Stream 2 half transfer flag.
AnnaBridge	172:65be27845400	2398	* @rmtoll LIFCR CHTIF2 LL_DMA_ClearFlag_HT2
AnnaBridge	172:65be27845400	2399	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2400	* @retval None
AnnaBridge	172:65be27845400	2401	*/
AnnaBridge	172:65be27845400	2402	__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2403	{
AnnaBridge	172:65be27845400	2404	WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF2);
AnnaBridge	172:65be27845400	2405	}
AnnaBridge	172:65be27845400	2406
AnnaBridge	172:65be27845400	2407	/**
AnnaBridge	172:65be27845400	2408	* @brief Clear Stream 3 half transfer flag.
AnnaBridge	172:65be27845400	2409	* @rmtoll LIFCR CHTIF3 LL_DMA_ClearFlag_HT3
AnnaBridge	172:65be27845400	2410	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2411	* @retval None
AnnaBridge	172:65be27845400	2412	*/
AnnaBridge	172:65be27845400	2413	__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2414	{
AnnaBridge	172:65be27845400	2415	WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF3);
AnnaBridge	172:65be27845400	2416	}
AnnaBridge	172:65be27845400	2417
AnnaBridge	172:65be27845400	2418	/**
AnnaBridge	172:65be27845400	2419	* @brief Clear Stream 4 half transfer flag.
AnnaBridge	172:65be27845400	2420	* @rmtoll HIFCR CHTIF4 LL_DMA_ClearFlag_HT4
AnnaBridge	172:65be27845400	2421	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2422	* @retval None
AnnaBridge	172:65be27845400	2423	*/
AnnaBridge	172:65be27845400	2424	__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2425	{
AnnaBridge	172:65be27845400	2426	WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF4);
AnnaBridge	172:65be27845400	2427	}
AnnaBridge	172:65be27845400	2428
AnnaBridge	172:65be27845400	2429	/**
AnnaBridge	172:65be27845400	2430	* @brief Clear Stream 5 half transfer flag.
AnnaBridge	172:65be27845400	2431	* @rmtoll HIFCR CHTIF5 LL_DMA_ClearFlag_HT5
AnnaBridge	172:65be27845400	2432	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2433	* @retval None
AnnaBridge	172:65be27845400	2434	*/
AnnaBridge	172:65be27845400	2435	__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2436	{
AnnaBridge	172:65be27845400	2437	WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF5);
AnnaBridge	172:65be27845400	2438	}
AnnaBridge	172:65be27845400	2439
AnnaBridge	172:65be27845400	2440	/**
AnnaBridge	172:65be27845400	2441	* @brief Clear Stream 6 half transfer flag.
AnnaBridge	172:65be27845400	2442	* @rmtoll HIFCR CHTIF6 LL_DMA_ClearFlag_HT6
AnnaBridge	172:65be27845400	2443	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2444	* @retval None
AnnaBridge	172:65be27845400	2445	*/
AnnaBridge	172:65be27845400	2446	__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2447	{
AnnaBridge	172:65be27845400	2448	WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF6);
AnnaBridge	172:65be27845400	2449	}
AnnaBridge	172:65be27845400	2450
AnnaBridge	172:65be27845400	2451	/**
AnnaBridge	172:65be27845400	2452	* @brief Clear Stream 7 half transfer flag.
AnnaBridge	172:65be27845400	2453	* @rmtoll HIFCR CHTIF7 LL_DMA_ClearFlag_HT7
AnnaBridge	172:65be27845400	2454	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2455	* @retval None
AnnaBridge	172:65be27845400	2456	*/
AnnaBridge	172:65be27845400	2457	__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2458	{
AnnaBridge	172:65be27845400	2459	WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF7);
AnnaBridge	172:65be27845400	2460	}
AnnaBridge	172:65be27845400	2461
AnnaBridge	172:65be27845400	2462	/**
AnnaBridge	172:65be27845400	2463	* @brief Clear Stream 0 transfer complete flag.
AnnaBridge	172:65be27845400	2464	* @rmtoll LIFCR CTCIF0 LL_DMA_ClearFlag_TC0
AnnaBridge	172:65be27845400	2465	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2466	* @retval None
AnnaBridge	172:65be27845400	2467	*/
AnnaBridge	172:65be27845400	2468	__STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2469	{
AnnaBridge	172:65be27845400	2470	WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF0);
AnnaBridge	172:65be27845400	2471	}
AnnaBridge	172:65be27845400	2472
AnnaBridge	172:65be27845400	2473	/**
AnnaBridge	172:65be27845400	2474	* @brief Clear Stream 1 transfer complete flag.
AnnaBridge	172:65be27845400	2475	* @rmtoll LIFCR CTCIF1 LL_DMA_ClearFlag_TC1
AnnaBridge	172:65be27845400	2476	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2477	* @retval None
AnnaBridge	172:65be27845400	2478	*/
AnnaBridge	172:65be27845400	2479	__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2480	{
AnnaBridge	172:65be27845400	2481	WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF1);
AnnaBridge	172:65be27845400	2482	}
AnnaBridge	172:65be27845400	2483
AnnaBridge	172:65be27845400	2484	/**
AnnaBridge	172:65be27845400	2485	* @brief Clear Stream 2 transfer complete flag.
AnnaBridge	172:65be27845400	2486	* @rmtoll LIFCR CTCIF2 LL_DMA_ClearFlag_TC2
AnnaBridge	172:65be27845400	2487	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2488	* @retval None
AnnaBridge	172:65be27845400	2489	*/
AnnaBridge	172:65be27845400	2490	__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2491	{
AnnaBridge	172:65be27845400	2492	WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF2);
AnnaBridge	172:65be27845400	2493	}
AnnaBridge	172:65be27845400	2494
AnnaBridge	172:65be27845400	2495	/**
AnnaBridge	172:65be27845400	2496	* @brief Clear Stream 3 transfer complete flag.
AnnaBridge	172:65be27845400	2497	* @rmtoll LIFCR CTCIF3 LL_DMA_ClearFlag_TC3
AnnaBridge	172:65be27845400	2498	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2499	* @retval None
AnnaBridge	172:65be27845400	2500	*/
AnnaBridge	172:65be27845400	2501	__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2502	{
AnnaBridge	172:65be27845400	2503	WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF3);
AnnaBridge	172:65be27845400	2504	}
AnnaBridge	172:65be27845400	2505
AnnaBridge	172:65be27845400	2506	/**
AnnaBridge	172:65be27845400	2507	* @brief Clear Stream 4 transfer complete flag.
AnnaBridge	172:65be27845400	2508	* @rmtoll HIFCR CTCIF4 LL_DMA_ClearFlag_TC4
AnnaBridge	172:65be27845400	2509	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2510	* @retval None
AnnaBridge	172:65be27845400	2511	*/
AnnaBridge	172:65be27845400	2512	__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2513	{
AnnaBridge	172:65be27845400	2514	WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF4);
AnnaBridge	172:65be27845400	2515	}
AnnaBridge	172:65be27845400	2516
AnnaBridge	172:65be27845400	2517	/**
AnnaBridge	172:65be27845400	2518	* @brief Clear Stream 5 transfer complete flag.
AnnaBridge	172:65be27845400	2519	* @rmtoll HIFCR CTCIF5 LL_DMA_ClearFlag_TC5
AnnaBridge	172:65be27845400	2520	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2521	* @retval None
AnnaBridge	172:65be27845400	2522	*/
AnnaBridge	172:65be27845400	2523	__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2524	{
AnnaBridge	172:65be27845400	2525	WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF5);
AnnaBridge	172:65be27845400	2526	}
AnnaBridge	172:65be27845400	2527
AnnaBridge	172:65be27845400	2528	/**
AnnaBridge	172:65be27845400	2529	* @brief Clear Stream 6 transfer complete flag.
AnnaBridge	172:65be27845400	2530	* @rmtoll HIFCR CTCIF6 LL_DMA_ClearFlag_TC6
AnnaBridge	172:65be27845400	2531	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2532	* @retval None
AnnaBridge	172:65be27845400	2533	*/
AnnaBridge	172:65be27845400	2534	__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2535	{
AnnaBridge	172:65be27845400	2536	WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF6);
AnnaBridge	172:65be27845400	2537	}
AnnaBridge	172:65be27845400	2538
AnnaBridge	172:65be27845400	2539	/**
AnnaBridge	172:65be27845400	2540	* @brief Clear Stream 7 transfer complete flag.
AnnaBridge	172:65be27845400	2541	* @rmtoll HIFCR CTCIF7 LL_DMA_ClearFlag_TC7
AnnaBridge	172:65be27845400	2542	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2543	* @retval None
AnnaBridge	172:65be27845400	2544	*/
AnnaBridge	172:65be27845400	2545	__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2546	{
AnnaBridge	172:65be27845400	2547	WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF7);
AnnaBridge	172:65be27845400	2548	}
AnnaBridge	172:65be27845400	2549
AnnaBridge	172:65be27845400	2550	/**
AnnaBridge	172:65be27845400	2551	* @brief Clear Stream 0 transfer error flag.
AnnaBridge	172:65be27845400	2552	* @rmtoll LIFCR CTEIF0 LL_DMA_ClearFlag_TE0
AnnaBridge	172:65be27845400	2553	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2554	* @retval None
AnnaBridge	172:65be27845400	2555	*/
AnnaBridge	172:65be27845400	2556	__STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2557	{
AnnaBridge	172:65be27845400	2558	WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF0);
AnnaBridge	172:65be27845400	2559	}
AnnaBridge	172:65be27845400	2560
AnnaBridge	172:65be27845400	2561	/**
AnnaBridge	172:65be27845400	2562	* @brief Clear Stream 1 transfer error flag.
AnnaBridge	172:65be27845400	2563	* @rmtoll LIFCR CTEIF1 LL_DMA_ClearFlag_TE1
AnnaBridge	172:65be27845400	2564	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2565	* @retval None
AnnaBridge	172:65be27845400	2566	*/
AnnaBridge	172:65be27845400	2567	__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2568	{
AnnaBridge	172:65be27845400	2569	WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF1);
AnnaBridge	172:65be27845400	2570	}
AnnaBridge	172:65be27845400	2571
AnnaBridge	172:65be27845400	2572	/**
AnnaBridge	172:65be27845400	2573	* @brief Clear Stream 2 transfer error flag.
AnnaBridge	172:65be27845400	2574	* @rmtoll LIFCR CTEIF2 LL_DMA_ClearFlag_TE2
AnnaBridge	172:65be27845400	2575	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2576	* @retval None
AnnaBridge	172:65be27845400	2577	*/
AnnaBridge	172:65be27845400	2578	__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2579	{
AnnaBridge	172:65be27845400	2580	WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF2);
AnnaBridge	172:65be27845400	2581	}
AnnaBridge	172:65be27845400	2582
AnnaBridge	172:65be27845400	2583	/**
AnnaBridge	172:65be27845400	2584	* @brief Clear Stream 3 transfer error flag.
AnnaBridge	172:65be27845400	2585	* @rmtoll LIFCR CTEIF3 LL_DMA_ClearFlag_TE3
AnnaBridge	172:65be27845400	2586	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2587	* @retval None
AnnaBridge	172:65be27845400	2588	*/
AnnaBridge	172:65be27845400	2589	__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2590	{
AnnaBridge	172:65be27845400	2591	WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF3);
AnnaBridge	172:65be27845400	2592	}
AnnaBridge	172:65be27845400	2593
AnnaBridge	172:65be27845400	2594	/**
AnnaBridge	172:65be27845400	2595	* @brief Clear Stream 4 transfer error flag.
AnnaBridge	172:65be27845400	2596	* @rmtoll HIFCR CTEIF4 LL_DMA_ClearFlag_TE4
AnnaBridge	172:65be27845400	2597	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2598	* @retval None
AnnaBridge	172:65be27845400	2599	*/
AnnaBridge	172:65be27845400	2600	__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2601	{
AnnaBridge	172:65be27845400	2602	WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF4);
AnnaBridge	172:65be27845400	2603	}
AnnaBridge	172:65be27845400	2604
AnnaBridge	172:65be27845400	2605	/**
AnnaBridge	172:65be27845400	2606	* @brief Clear Stream 5 transfer error flag.
AnnaBridge	172:65be27845400	2607	* @rmtoll HIFCR CTEIF5 LL_DMA_ClearFlag_TE5
AnnaBridge	172:65be27845400	2608	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2609	* @retval None
AnnaBridge	172:65be27845400	2610	*/
AnnaBridge	172:65be27845400	2611	__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2612	{
AnnaBridge	172:65be27845400	2613	WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF5);
AnnaBridge	172:65be27845400	2614	}
AnnaBridge	172:65be27845400	2615
AnnaBridge	172:65be27845400	2616	/**
AnnaBridge	172:65be27845400	2617	* @brief Clear Stream 6 transfer error flag.
AnnaBridge	172:65be27845400	2618	* @rmtoll HIFCR CTEIF6 LL_DMA_ClearFlag_TE6
AnnaBridge	172:65be27845400	2619	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2620	* @retval None
AnnaBridge	172:65be27845400	2621	*/
AnnaBridge	172:65be27845400	2622	__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2623	{
AnnaBridge	172:65be27845400	2624	WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF6);
AnnaBridge	172:65be27845400	2625	}
AnnaBridge	172:65be27845400	2626
AnnaBridge	172:65be27845400	2627	/**
AnnaBridge	172:65be27845400	2628	* @brief Clear Stream 7 transfer error flag.
AnnaBridge	172:65be27845400	2629	* @rmtoll HIFCR CTEIF7 LL_DMA_ClearFlag_TE7
AnnaBridge	172:65be27845400	2630	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2631	* @retval None
AnnaBridge	172:65be27845400	2632	*/
AnnaBridge	172:65be27845400	2633	__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2634	{
AnnaBridge	172:65be27845400	2635	WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF7);
AnnaBridge	172:65be27845400	2636	}
AnnaBridge	172:65be27845400	2637
AnnaBridge	172:65be27845400	2638	/**
AnnaBridge	172:65be27845400	2639	* @brief Clear Stream 0 direct mode error flag.
AnnaBridge	172:65be27845400	2640	* @rmtoll LIFCR CDMEIF0 LL_DMA_ClearFlag_DME0
AnnaBridge	172:65be27845400	2641	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2642	* @retval None
AnnaBridge	172:65be27845400	2643	*/
AnnaBridge	172:65be27845400	2644	__STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2645	{
AnnaBridge	172:65be27845400	2646	WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF0);
AnnaBridge	172:65be27845400	2647	}
AnnaBridge	172:65be27845400	2648
AnnaBridge	172:65be27845400	2649	/**
AnnaBridge	172:65be27845400	2650	* @brief Clear Stream 1 direct mode error flag.
AnnaBridge	172:65be27845400	2651	* @rmtoll LIFCR CDMEIF1 LL_DMA_ClearFlag_DME1
AnnaBridge	172:65be27845400	2652	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2653	* @retval None
AnnaBridge	172:65be27845400	2654	*/
AnnaBridge	172:65be27845400	2655	__STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2656	{
AnnaBridge	172:65be27845400	2657	WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF1);
AnnaBridge	172:65be27845400	2658	}
AnnaBridge	172:65be27845400	2659
AnnaBridge	172:65be27845400	2660	/**
AnnaBridge	172:65be27845400	2661	* @brief Clear Stream 2 direct mode error flag.
AnnaBridge	172:65be27845400	2662	* @rmtoll LIFCR CDMEIF2 LL_DMA_ClearFlag_DME2
AnnaBridge	172:65be27845400	2663	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2664	* @retval None
AnnaBridge	172:65be27845400	2665	*/
AnnaBridge	172:65be27845400	2666	__STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2667	{
AnnaBridge	172:65be27845400	2668	WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF2);
AnnaBridge	172:65be27845400	2669	}
AnnaBridge	172:65be27845400	2670
AnnaBridge	172:65be27845400	2671	/**
AnnaBridge	172:65be27845400	2672	* @brief Clear Stream 3 direct mode error flag.
AnnaBridge	172:65be27845400	2673	* @rmtoll LIFCR CDMEIF3 LL_DMA_ClearFlag_DME3
AnnaBridge	172:65be27845400	2674	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2675	* @retval None
AnnaBridge	172:65be27845400	2676	*/
AnnaBridge	172:65be27845400	2677	__STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2678	{
AnnaBridge	172:65be27845400	2679	WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF3);
AnnaBridge	172:65be27845400	2680	}
AnnaBridge	172:65be27845400	2681
AnnaBridge	172:65be27845400	2682	/**
AnnaBridge	172:65be27845400	2683	* @brief Clear Stream 4 direct mode error flag.
AnnaBridge	172:65be27845400	2684	* @rmtoll HIFCR CDMEIF4 LL_DMA_ClearFlag_DME4
AnnaBridge	172:65be27845400	2685	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2686	* @retval None
AnnaBridge	172:65be27845400	2687	*/
AnnaBridge	172:65be27845400	2688	__STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2689	{
AnnaBridge	172:65be27845400	2690	WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF4);
AnnaBridge	172:65be27845400	2691	}
AnnaBridge	172:65be27845400	2692
AnnaBridge	172:65be27845400	2693	/**
AnnaBridge	172:65be27845400	2694	* @brief Clear Stream 5 direct mode error flag.
AnnaBridge	172:65be27845400	2695	* @rmtoll HIFCR CDMEIF5 LL_DMA_ClearFlag_DME5
AnnaBridge	172:65be27845400	2696	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2697	* @retval None
AnnaBridge	172:65be27845400	2698	*/
AnnaBridge	172:65be27845400	2699	__STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2700	{
AnnaBridge	172:65be27845400	2701	WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF5);
AnnaBridge	172:65be27845400	2702	}
AnnaBridge	172:65be27845400	2703
AnnaBridge	172:65be27845400	2704	/**
AnnaBridge	172:65be27845400	2705	* @brief Clear Stream 6 direct mode error flag.
AnnaBridge	172:65be27845400	2706	* @rmtoll HIFCR CDMEIF6 LL_DMA_ClearFlag_DME6
AnnaBridge	172:65be27845400	2707	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2708	* @retval None
AnnaBridge	172:65be27845400	2709	*/
AnnaBridge	172:65be27845400	2710	__STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2711	{
AnnaBridge	172:65be27845400	2712	WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF6);
AnnaBridge	172:65be27845400	2713	}
AnnaBridge	172:65be27845400	2714
AnnaBridge	172:65be27845400	2715	/**
AnnaBridge	172:65be27845400	2716	* @brief Clear Stream 7 direct mode error flag.
AnnaBridge	172:65be27845400	2717	* @rmtoll HIFCR CDMEIF7 LL_DMA_ClearFlag_DME7
AnnaBridge	172:65be27845400	2718	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2719	* @retval None
AnnaBridge	172:65be27845400	2720	*/
AnnaBridge	172:65be27845400	2721	__STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2722	{
AnnaBridge	172:65be27845400	2723	WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF7);
AnnaBridge	172:65be27845400	2724	}
AnnaBridge	172:65be27845400	2725
AnnaBridge	172:65be27845400	2726	/**
AnnaBridge	172:65be27845400	2727	* @brief Clear Stream 0 FIFO error flag.
AnnaBridge	172:65be27845400	2728	* @rmtoll LIFCR CFEIF0 LL_DMA_ClearFlag_FE0
AnnaBridge	172:65be27845400	2729	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2730	* @retval None
AnnaBridge	172:65be27845400	2731	*/
AnnaBridge	172:65be27845400	2732	__STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2733	{
AnnaBridge	172:65be27845400	2734	WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF0);
AnnaBridge	172:65be27845400	2735	}
AnnaBridge	172:65be27845400	2736
AnnaBridge	172:65be27845400	2737	/**
AnnaBridge	172:65be27845400	2738	* @brief Clear Stream 1 FIFO error flag.
AnnaBridge	172:65be27845400	2739	* @rmtoll LIFCR CFEIF1 LL_DMA_ClearFlag_FE1
AnnaBridge	172:65be27845400	2740	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2741	* @retval None
AnnaBridge	172:65be27845400	2742	*/
AnnaBridge	172:65be27845400	2743	__STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2744	{
AnnaBridge	172:65be27845400	2745	WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF1);
AnnaBridge	172:65be27845400	2746	}
AnnaBridge	172:65be27845400	2747
AnnaBridge	172:65be27845400	2748	/**
AnnaBridge	172:65be27845400	2749	* @brief Clear Stream 2 FIFO error flag.
AnnaBridge	172:65be27845400	2750	* @rmtoll LIFCR CFEIF2 LL_DMA_ClearFlag_FE2
AnnaBridge	172:65be27845400	2751	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2752	* @retval None
AnnaBridge	172:65be27845400	2753	*/
AnnaBridge	172:65be27845400	2754	__STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2755	{
AnnaBridge	172:65be27845400	2756	WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF2);
AnnaBridge	172:65be27845400	2757	}
AnnaBridge	172:65be27845400	2758
AnnaBridge	172:65be27845400	2759	/**
AnnaBridge	172:65be27845400	2760	* @brief Clear Stream 3 FIFO error flag.
AnnaBridge	172:65be27845400	2761	* @rmtoll LIFCR CFEIF3 LL_DMA_ClearFlag_FE3
AnnaBridge	172:65be27845400	2762	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2763	* @retval None
AnnaBridge	172:65be27845400	2764	*/
AnnaBridge	172:65be27845400	2765	__STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2766	{
AnnaBridge	172:65be27845400	2767	WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF3);
AnnaBridge	172:65be27845400	2768	}
AnnaBridge	172:65be27845400	2769
AnnaBridge	172:65be27845400	2770	/**
AnnaBridge	172:65be27845400	2771	* @brief Clear Stream 4 FIFO error flag.
AnnaBridge	172:65be27845400	2772	* @rmtoll HIFCR CFEIF4 LL_DMA_ClearFlag_FE4
AnnaBridge	172:65be27845400	2773	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2774	* @retval None
AnnaBridge	172:65be27845400	2775	*/
AnnaBridge	172:65be27845400	2776	__STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2777	{
AnnaBridge	172:65be27845400	2778	WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF4);
AnnaBridge	172:65be27845400	2779	}
AnnaBridge	172:65be27845400	2780
AnnaBridge	172:65be27845400	2781	/**
AnnaBridge	172:65be27845400	2782	* @brief Clear Stream 5 FIFO error flag.
AnnaBridge	172:65be27845400	2783	* @rmtoll HIFCR CFEIF5 LL_DMA_ClearFlag_FE5
AnnaBridge	172:65be27845400	2784	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2785	* @retval None
AnnaBridge	172:65be27845400	2786	*/
AnnaBridge	172:65be27845400	2787	__STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2788	{
AnnaBridge	172:65be27845400	2789	WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF5);
AnnaBridge	172:65be27845400	2790	}
AnnaBridge	172:65be27845400	2791
AnnaBridge	172:65be27845400	2792	/**
AnnaBridge	172:65be27845400	2793	* @brief Clear Stream 6 FIFO error flag.
AnnaBridge	172:65be27845400	2794	* @rmtoll HIFCR CFEIF6 LL_DMA_ClearFlag_FE6
AnnaBridge	172:65be27845400	2795	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2796	* @retval None
AnnaBridge	172:65be27845400	2797	*/
AnnaBridge	172:65be27845400	2798	__STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2799	{
AnnaBridge	172:65be27845400	2800	WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF6);
AnnaBridge	172:65be27845400	2801	}
AnnaBridge	172:65be27845400	2802
AnnaBridge	172:65be27845400	2803	/**
AnnaBridge	172:65be27845400	2804	* @brief Clear Stream 7 FIFO error flag.
AnnaBridge	172:65be27845400	2805	* @rmtoll HIFCR CFEIF7 LL_DMA_ClearFlag_FE7
AnnaBridge	172:65be27845400	2806	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2807	* @retval None
AnnaBridge	172:65be27845400	2808	*/
AnnaBridge	172:65be27845400	2809	__STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx)
AnnaBridge	172:65be27845400	2810	{
AnnaBridge	172:65be27845400	2811	WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF7);
AnnaBridge	172:65be27845400	2812	}
AnnaBridge	172:65be27845400	2813
AnnaBridge	172:65be27845400	2814	/**
AnnaBridge	172:65be27845400	2815	* @}
AnnaBridge	172:65be27845400	2816	*/
AnnaBridge	172:65be27845400	2817
AnnaBridge	172:65be27845400	2818	/** @defgroup DMA_LL_EF_IT_Management IT_Management
AnnaBridge	172:65be27845400	2819	* @{
AnnaBridge	172:65be27845400	2820	*/
AnnaBridge	172:65be27845400	2821
AnnaBridge	172:65be27845400	2822	/**
AnnaBridge	172:65be27845400	2823	* @brief Enable Half transfer interrupt.
AnnaBridge	172:65be27845400	2824	* @rmtoll CR HTIE LL_DMA_EnableIT_HT
AnnaBridge	172:65be27845400	2825	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2826	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2827	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	2828	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	2829	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	2830	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	2831	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	2832	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	2833	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	2834	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	2835	* @retval None
AnnaBridge	172:65be27845400	2836	*/
AnnaBridge	172:65be27845400	2837	__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	172:65be27845400	2838	{
AnnaBridge	172:65be27845400	2839	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	2840
AnnaBridge	172:65be27845400	2841	SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE);
AnnaBridge	172:65be27845400	2842	}
AnnaBridge	172:65be27845400	2843
AnnaBridge	172:65be27845400	2844	/**
AnnaBridge	172:65be27845400	2845	* @brief Enable Transfer error interrupt.
AnnaBridge	172:65be27845400	2846	* @rmtoll CR TEIE LL_DMA_EnableIT_TE
AnnaBridge	172:65be27845400	2847	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2848	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2849	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	2850	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	2851	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	2852	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	2853	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	2854	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	2855	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	2856	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	2857	* @retval None
AnnaBridge	172:65be27845400	2858	*/
AnnaBridge	172:65be27845400	2859	__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	172:65be27845400	2860	{
AnnaBridge	172:65be27845400	2861	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	2862
AnnaBridge	172:65be27845400	2863	SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE);
AnnaBridge	172:65be27845400	2864	}
AnnaBridge	172:65be27845400	2865
AnnaBridge	172:65be27845400	2866	/**
AnnaBridge	172:65be27845400	2867	* @brief Enable Transfer complete interrupt.
AnnaBridge	172:65be27845400	2868	* @rmtoll CR TCIE LL_DMA_EnableIT_TC
AnnaBridge	172:65be27845400	2869	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2870	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2871	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	2872	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	2873	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	2874	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	2875	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	2876	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	2877	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	2878	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	2879	* @retval None
AnnaBridge	172:65be27845400	2880	*/
AnnaBridge	172:65be27845400	2881	__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	172:65be27845400	2882	{
AnnaBridge	172:65be27845400	2883	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	2884
AnnaBridge	172:65be27845400	2885	SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE);
AnnaBridge	172:65be27845400	2886	}
AnnaBridge	172:65be27845400	2887
AnnaBridge	172:65be27845400	2888	/**
AnnaBridge	172:65be27845400	2889	* @brief Enable Direct mode error interrupt.
AnnaBridge	172:65be27845400	2890	* @rmtoll CR DMEIE LL_DMA_EnableIT_DME
AnnaBridge	172:65be27845400	2891	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2892	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2893	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	2894	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	2895	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	2896	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	2897	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	2898	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	2899	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	2900	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	2901	* @retval None
AnnaBridge	172:65be27845400	2902	*/
AnnaBridge	172:65be27845400	2903	__STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	172:65be27845400	2904	{
AnnaBridge	172:65be27845400	2905	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	2906
AnnaBridge	172:65be27845400	2907	SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE);
AnnaBridge	172:65be27845400	2908	}
AnnaBridge	172:65be27845400	2909
AnnaBridge	172:65be27845400	2910	/**
AnnaBridge	172:65be27845400	2911	* @brief Enable FIFO error interrupt.
AnnaBridge	172:65be27845400	2912	* @rmtoll FCR FEIE LL_DMA_EnableIT_FE
AnnaBridge	172:65be27845400	2913	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2914	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2915	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	2916	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	2917	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	2918	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	2919	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	2920	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	2921	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	2922	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	2923	* @retval None
AnnaBridge	172:65be27845400	2924	*/
AnnaBridge	172:65be27845400	2925	__STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	172:65be27845400	2926	{
AnnaBridge	172:65be27845400	2927	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	2928
AnnaBridge	172:65be27845400	2929	SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE);
AnnaBridge	172:65be27845400	2930	}
AnnaBridge	172:65be27845400	2931
AnnaBridge	172:65be27845400	2932	/**
AnnaBridge	172:65be27845400	2933	* @brief Disable Half transfer interrupt.
AnnaBridge	172:65be27845400	2934	* @rmtoll CR HTIE LL_DMA_DisableIT_HT
AnnaBridge	172:65be27845400	2935	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2936	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2937	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	2938	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	2939	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	2940	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	2941	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	2942	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	2943	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	2944	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	2945	* @retval None
AnnaBridge	172:65be27845400	2946	*/
AnnaBridge	172:65be27845400	2947	__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	172:65be27845400	2948	{
AnnaBridge	172:65be27845400	2949	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	2950
AnnaBridge	172:65be27845400	2951	CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE);
AnnaBridge	172:65be27845400	2952	}
AnnaBridge	172:65be27845400	2953
AnnaBridge	172:65be27845400	2954	/**
AnnaBridge	172:65be27845400	2955	* @brief Disable Transfer error interrupt.
AnnaBridge	172:65be27845400	2956	* @rmtoll CR TEIE LL_DMA_DisableIT_TE
AnnaBridge	172:65be27845400	2957	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2958	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2959	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	2960	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	2961	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	2962	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	2963	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	2964	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	2965	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	2966	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	2967	* @retval None
AnnaBridge	172:65be27845400	2968	*/
AnnaBridge	172:65be27845400	2969	__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	172:65be27845400	2970	{
AnnaBridge	172:65be27845400	2971	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	2972
AnnaBridge	172:65be27845400	2973	CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE);
AnnaBridge	172:65be27845400	2974	}
AnnaBridge	172:65be27845400	2975
AnnaBridge	172:65be27845400	2976	/**
AnnaBridge	172:65be27845400	2977	* @brief Disable Transfer complete interrupt.
AnnaBridge	172:65be27845400	2978	* @rmtoll CR TCIE LL_DMA_DisableIT_TC
AnnaBridge	172:65be27845400	2979	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	2980	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2981	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	2982	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	2983	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	2984	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	2985	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	2986	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	2987	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	2988	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	2989	* @retval None
AnnaBridge	172:65be27845400	2990	*/
AnnaBridge	172:65be27845400	2991	__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	172:65be27845400	2992	{
AnnaBridge	172:65be27845400	2993	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	2994
AnnaBridge	172:65be27845400	2995	CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE);
AnnaBridge	172:65be27845400	2996	}
AnnaBridge	172:65be27845400	2997
AnnaBridge	172:65be27845400	2998	/**
AnnaBridge	172:65be27845400	2999	* @brief Disable Direct mode error interrupt.
AnnaBridge	172:65be27845400	3000	* @rmtoll CR DMEIE LL_DMA_DisableIT_DME
AnnaBridge	172:65be27845400	3001	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	3002	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3003	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	3004	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	3005	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	3006	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	3007	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	3008	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	3009	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	3010	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	3011	* @retval None
AnnaBridge	172:65be27845400	3012	*/
AnnaBridge	172:65be27845400	3013	__STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	172:65be27845400	3014	{
AnnaBridge	172:65be27845400	3015	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	3016
AnnaBridge	172:65be27845400	3017	CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE);
AnnaBridge	172:65be27845400	3018	}
AnnaBridge	172:65be27845400	3019
AnnaBridge	172:65be27845400	3020	/**
AnnaBridge	172:65be27845400	3021	* @brief Disable FIFO error interrupt.
AnnaBridge	172:65be27845400	3022	* @rmtoll FCR FEIE LL_DMA_DisableIT_FE
AnnaBridge	172:65be27845400	3023	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	3024	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3025	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	3026	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	3027	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	3028	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	3029	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	3030	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	3031	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	3032	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	3033	* @retval None
AnnaBridge	172:65be27845400	3034	*/
AnnaBridge	172:65be27845400	3035	__STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	172:65be27845400	3036	{
AnnaBridge	172:65be27845400	3037	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	3038
AnnaBridge	172:65be27845400	3039	CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE);
AnnaBridge	172:65be27845400	3040	}
AnnaBridge	172:65be27845400	3041
AnnaBridge	172:65be27845400	3042	/**
AnnaBridge	172:65be27845400	3043	* @brief Check if Half transfer interrup is enabled.
AnnaBridge	172:65be27845400	3044	* @rmtoll CR HTIE LL_DMA_IsEnabledIT_HT
AnnaBridge	172:65be27845400	3045	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	3046	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3047	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	3048	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	3049	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	3050	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	3051	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	3052	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	3053	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	3054	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	3055	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	3056	*/
AnnaBridge	172:65be27845400	3057	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	172:65be27845400	3058	{
AnnaBridge	172:65be27845400	3059	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	3060
AnnaBridge	172:65be27845400	3061	return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	3062	}
AnnaBridge	172:65be27845400	3063
AnnaBridge	172:65be27845400	3064	/**
AnnaBridge	172:65be27845400	3065	* @brief Check if Transfer error nterrup is enabled.
AnnaBridge	172:65be27845400	3066	* @rmtoll CR TEIE LL_DMA_IsEnabledIT_TE
AnnaBridge	172:65be27845400	3067	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	3068	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3069	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	3070	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	3071	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	3072	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	3073	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	3074	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	3075	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	3076	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	3077	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	3078	*/
AnnaBridge	172:65be27845400	3079	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	172:65be27845400	3080	{
AnnaBridge	172:65be27845400	3081	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	3082
AnnaBridge	172:65be27845400	3083	return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	3084	}
AnnaBridge	172:65be27845400	3085
AnnaBridge	172:65be27845400	3086	/**
AnnaBridge	172:65be27845400	3087	* @brief Check if Transfer complete interrup is enabled.
AnnaBridge	172:65be27845400	3088	* @rmtoll CR TCIE LL_DMA_IsEnabledIT_TC
AnnaBridge	172:65be27845400	3089	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	3090	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3091	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	3092	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	3093	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	3094	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	3095	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	3096	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	3097	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	3098	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	3099	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	3100	*/
AnnaBridge	172:65be27845400	3101	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	172:65be27845400	3102	{
AnnaBridge	172:65be27845400	3103	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	3104
AnnaBridge	172:65be27845400	3105	return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	3106	}
AnnaBridge	172:65be27845400	3107
AnnaBridge	172:65be27845400	3108	/**
AnnaBridge	172:65be27845400	3109	* @brief Check if Direct mode error interrupt is enabled.
AnnaBridge	172:65be27845400	3110	* @rmtoll CR DMEIE LL_DMA_IsEnabledIT_DME
AnnaBridge	172:65be27845400	3111	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	3112	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3113	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	3114	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	3115	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	3116	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	3117	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	3118	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	3119	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	3120	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	3121	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	3122	*/
AnnaBridge	172:65be27845400	3123	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	172:65be27845400	3124	{
AnnaBridge	172:65be27845400	3125	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	3126
AnnaBridge	172:65be27845400	3127	return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	3128	}
AnnaBridge	172:65be27845400	3129
AnnaBridge	172:65be27845400	3130	/**
AnnaBridge	172:65be27845400	3131	* @brief Check if FIFO error interrup is enabled.
AnnaBridge	172:65be27845400	3132	* @rmtoll FCR FEIE LL_DMA_IsEnabledIT_FE
AnnaBridge	172:65be27845400	3133	* @param DMAx DMAx Instance
AnnaBridge	172:65be27845400	3134	* @param Stream This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3135	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	172:65be27845400	3136	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	172:65be27845400	3137	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	172:65be27845400	3138	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	172:65be27845400	3139	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	172:65be27845400	3140	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	172:65be27845400	3141	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	172:65be27845400	3142	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	172:65be27845400	3143	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	3144	*/
AnnaBridge	172:65be27845400	3145	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	172:65be27845400	3146	{
AnnaBridge	172:65be27845400	3147	register uint32_t dma_base_addr = (uint32_t)DMAx;
AnnaBridge	172:65be27845400	3148
AnnaBridge	172:65be27845400	3149	return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	3150	}
AnnaBridge	172:65be27845400	3151
AnnaBridge	172:65be27845400	3152	/**
AnnaBridge	172:65be27845400	3153	* @}
AnnaBridge	172:65be27845400	3154	*/
AnnaBridge	172:65be27845400	3155
AnnaBridge	172:65be27845400	3156	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	172:65be27845400	3157	/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
AnnaBridge	172:65be27845400	3158	* @{
AnnaBridge	172:65be27845400	3159	*/
AnnaBridge	172:65be27845400	3160
AnnaBridge	172:65be27845400	3161	uint32_t LL_DMA_Init(DMA_TypeDef DMAx, uint32_t Stream, LL_DMA_InitTypeDef DMA_InitStruct);
AnnaBridge	172:65be27845400	3162	uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream);
AnnaBridge	172:65be27845400	3163	void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
AnnaBridge	172:65be27845400	3164
AnnaBridge	172:65be27845400	3165	/**
AnnaBridge	172:65be27845400	3166	* @}
AnnaBridge	172:65be27845400	3167	*/
AnnaBridge	172:65be27845400	3168	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	172:65be27845400	3169
AnnaBridge	172:65be27845400	3170	/**
AnnaBridge	172:65be27845400	3171	* @}
AnnaBridge	172:65be27845400	3172	*/
AnnaBridge	172:65be27845400	3173
AnnaBridge	172:65be27845400	3174	/**
AnnaBridge	172:65be27845400	3175	* @}
AnnaBridge	172:65be27845400	3176	*/
AnnaBridge	172:65be27845400	3177
AnnaBridge	172:65be27845400	3178	#endif /* DMA1 \|\| DMA2 */
AnnaBridge	172:65be27845400	3179
AnnaBridge	172:65be27845400	3180	/**
AnnaBridge	172:65be27845400	3181	* @}
AnnaBridge	172:65be27845400	3182	*/
AnnaBridge	172:65be27845400	3183
AnnaBridge	172:65be27845400	3184	#ifdef __cplusplus
AnnaBridge	172:65be27845400	3185	}
AnnaBridge	172:65be27845400	3186	#endif
AnnaBridge	172:65be27845400	3187
AnnaBridge	172:65be27845400	3188	#endif /* __STM32H7xx_LL_DMA_H */
AnnaBridge	172:65be27845400	3189
AnnaBridge	172:65be27845400	3190	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/