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TARGET_NUCLEO_F103RB/TOOLCHAIN_IAR/stm32f1xx_hal_adc.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 171:3a7713b1edbc | 1 | /** |
| AnnaBridge | 171:3a7713b1edbc | 2 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 3 | * @file stm32f1xx_hal_adc.h |
| AnnaBridge | 171:3a7713b1edbc | 4 | * @author MCD Application Team |
| AnnaBridge | 171:3a7713b1edbc | 5 | * @brief Header file containing functions prototypes of ADC HAL library. |
| AnnaBridge | 171:3a7713b1edbc | 6 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 7 | * @attention |
| AnnaBridge | 171:3a7713b1edbc | 8 | * |
| AnnaBridge | 171:3a7713b1edbc | 9 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| AnnaBridge | 171:3a7713b1edbc | 10 | * |
| AnnaBridge | 171:3a7713b1edbc | 11 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 171:3a7713b1edbc | 12 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 171:3a7713b1edbc | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 14 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 171:3a7713b1edbc | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 16 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 171:3a7713b1edbc | 17 | * and/or other materials provided with the distribution. |
| AnnaBridge | 171:3a7713b1edbc | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 171:3a7713b1edbc | 19 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 171:3a7713b1edbc | 20 | * without specific prior written permission. |
| AnnaBridge | 171:3a7713b1edbc | 21 | * |
| AnnaBridge | 171:3a7713b1edbc | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 171:3a7713b1edbc | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 171:3a7713b1edbc | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 171:3a7713b1edbc | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 171:3a7713b1edbc | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 171:3a7713b1edbc | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 171:3a7713b1edbc | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 171:3a7713b1edbc | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 171:3a7713b1edbc | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 171:3a7713b1edbc | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 171:3a7713b1edbc | 32 | * |
| AnnaBridge | 171:3a7713b1edbc | 33 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 34 | */ |
| AnnaBridge | 171:3a7713b1edbc | 35 | |
| AnnaBridge | 171:3a7713b1edbc | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 37 | #ifndef __STM32F1xx_HAL_ADC_H |
| AnnaBridge | 171:3a7713b1edbc | 38 | #define __STM32F1xx_HAL_ADC_H |
| AnnaBridge | 171:3a7713b1edbc | 39 | |
| AnnaBridge | 171:3a7713b1edbc | 40 | #ifdef __cplusplus |
| AnnaBridge | 171:3a7713b1edbc | 41 | extern "C" { |
| AnnaBridge | 171:3a7713b1edbc | 42 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 43 | |
| AnnaBridge | 171:3a7713b1edbc | 44 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 45 | #include "stm32f1xx_hal_def.h" |
| AnnaBridge | 171:3a7713b1edbc | 46 | /** @addtogroup STM32F1xx_HAL_Driver |
| AnnaBridge | 171:3a7713b1edbc | 47 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 48 | */ |
| AnnaBridge | 171:3a7713b1edbc | 49 | |
| AnnaBridge | 171:3a7713b1edbc | 50 | /** @addtogroup ADC |
| AnnaBridge | 171:3a7713b1edbc | 51 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 52 | */ |
| AnnaBridge | 171:3a7713b1edbc | 53 | |
| AnnaBridge | 171:3a7713b1edbc | 54 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 55 | /** @defgroup ADC_Exported_Types ADC Exported Types |
| AnnaBridge | 171:3a7713b1edbc | 56 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 57 | */ |
| AnnaBridge | 171:3a7713b1edbc | 58 | |
| AnnaBridge | 171:3a7713b1edbc | 59 | /** |
| AnnaBridge | 171:3a7713b1edbc | 60 | * @brief Structure definition of ADC and regular group initialization |
| AnnaBridge | 171:3a7713b1edbc | 61 | * @note Parameters of this structure are shared within 2 scopes: |
| AnnaBridge | 171:3a7713b1edbc | 62 | * - Scope entire ADC (affects regular and injected groups): DataAlign, ScanConvMode. |
| AnnaBridge | 171:3a7713b1edbc | 63 | * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv. |
| AnnaBridge | 171:3a7713b1edbc | 64 | * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state. |
| AnnaBridge | 171:3a7713b1edbc | 65 | * ADC can be either disabled or enabled without conversion on going on regular group. |
| AnnaBridge | 171:3a7713b1edbc | 66 | */ |
| AnnaBridge | 171:3a7713b1edbc | 67 | typedef struct |
| AnnaBridge | 171:3a7713b1edbc | 68 | { |
| AnnaBridge | 171:3a7713b1edbc | 69 | uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting) |
| AnnaBridge | 171:3a7713b1edbc | 70 | or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3). |
| AnnaBridge | 171:3a7713b1edbc | 71 | This parameter can be a value of @ref ADC_Data_align */ |
| AnnaBridge | 171:3a7713b1edbc | 72 | uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups. |
| AnnaBridge | 171:3a7713b1edbc | 73 | This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. |
| AnnaBridge | 171:3a7713b1edbc | 74 | If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). |
| AnnaBridge | 171:3a7713b1edbc | 75 | Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). |
| AnnaBridge | 171:3a7713b1edbc | 76 | If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank). |
| AnnaBridge | 171:3a7713b1edbc | 77 | Scan direction is upward: from rank1 to rank 'n'. |
| AnnaBridge | 171:3a7713b1edbc | 78 | This parameter can be a value of @ref ADC_Scan_mode |
| AnnaBridge | 171:3a7713b1edbc | 79 | Note: For regular group, this parameter should be enabled in conversion either by polling (HAL_ADC_Start with Discontinuous mode and NbrOfDiscConversion=1) |
| AnnaBridge | 171:3a7713b1edbc | 80 | or by DMA (HAL_ADC_Start_DMA), but not by interruption (HAL_ADC_Start_IT): in scan mode, interruption is triggered only on the |
| AnnaBridge | 171:3a7713b1edbc | 81 | the last conversion of the sequence. All previous conversions would be overwritten by the last one. |
| AnnaBridge | 171:3a7713b1edbc | 82 | Injected group used with scan mode has not this constraint: each rank has its own result register, no data is overwritten. */ |
| AnnaBridge | 171:3a7713b1edbc | 83 | uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group, |
| AnnaBridge | 171:3a7713b1edbc | 84 | after the selected trigger occurred (software start or external trigger). |
| AnnaBridge | 171:3a7713b1edbc | 85 | This parameter can be set to ENABLE or DISABLE. */ |
| AnnaBridge | 171:3a7713b1edbc | 86 | uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer. |
| AnnaBridge | 171:3a7713b1edbc | 87 | To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. |
| AnnaBridge | 171:3a7713b1edbc | 88 | This parameter must be a number between Min_Data = 1 and Max_Data = 16. */ |
| AnnaBridge | 171:3a7713b1edbc | 89 | uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). |
| AnnaBridge | 171:3a7713b1edbc | 90 | Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. |
| AnnaBridge | 171:3a7713b1edbc | 91 | Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. |
| AnnaBridge | 171:3a7713b1edbc | 92 | This parameter can be set to ENABLE or DISABLE. */ |
| AnnaBridge | 171:3a7713b1edbc | 93 | uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided. |
| AnnaBridge | 171:3a7713b1edbc | 94 | If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. |
| AnnaBridge | 171:3a7713b1edbc | 95 | This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ |
| AnnaBridge | 171:3a7713b1edbc | 96 | uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group. |
| AnnaBridge | 171:3a7713b1edbc | 97 | If set to ADC_SOFTWARE_START, external triggers are disabled. |
| AnnaBridge | 171:3a7713b1edbc | 98 | If set to external trigger source, triggering is on event rising edge. |
| AnnaBridge | 171:3a7713b1edbc | 99 | This parameter can be a value of @ref ADC_External_trigger_source_Regular */ |
| AnnaBridge | 171:3a7713b1edbc | 100 | }ADC_InitTypeDef; |
| AnnaBridge | 171:3a7713b1edbc | 101 | |
| AnnaBridge | 171:3a7713b1edbc | 102 | /** |
| AnnaBridge | 171:3a7713b1edbc | 103 | * @brief Structure definition of ADC channel for regular group |
| AnnaBridge | 171:3a7713b1edbc | 104 | * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state. |
| AnnaBridge | 171:3a7713b1edbc | 105 | * ADC can be either disabled or enabled without conversion on going on regular group. |
| AnnaBridge | 171:3a7713b1edbc | 106 | */ |
| AnnaBridge | 171:3a7713b1edbc | 107 | typedef struct |
| AnnaBridge | 171:3a7713b1edbc | 108 | { |
| AnnaBridge | 171:3a7713b1edbc | 109 | uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group. |
| AnnaBridge | 171:3a7713b1edbc | 110 | This parameter can be a value of @ref ADC_channels |
| AnnaBridge | 171:3a7713b1edbc | 111 | Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. |
| AnnaBridge | 171:3a7713b1edbc | 112 | Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor) |
| AnnaBridge | 171:3a7713b1edbc | 113 | Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection trigger. |
| AnnaBridge | 171:3a7713b1edbc | 114 | It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel. |
| AnnaBridge | 171:3a7713b1edbc | 115 | Refer to errata sheet of these devices for more details. */ |
| AnnaBridge | 171:3a7713b1edbc | 116 | uint32_t Rank; /*!< Specifies the rank in the regular group sequencer |
| AnnaBridge | 171:3a7713b1edbc | 117 | This parameter can be a value of @ref ADC_regular_rank |
| AnnaBridge | 171:3a7713b1edbc | 118 | Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */ |
| AnnaBridge | 171:3a7713b1edbc | 119 | uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. |
| AnnaBridge | 171:3a7713b1edbc | 120 | Unit: ADC clock cycles |
| AnnaBridge | 171:3a7713b1edbc | 121 | Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits). |
| AnnaBridge | 171:3a7713b1edbc | 122 | This parameter can be a value of @ref ADC_sampling_times |
| AnnaBridge | 171:3a7713b1edbc | 123 | Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. |
| AnnaBridge | 171:3a7713b1edbc | 124 | If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. |
| AnnaBridge | 171:3a7713b1edbc | 125 | Note: In case of usage of internal measurement channels (VrefInt/TempSensor), |
| AnnaBridge | 171:3a7713b1edbc | 126 | sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) |
| AnnaBridge | 171:3a7713b1edbc | 127 | Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 5us to 17.1us min). */ |
| AnnaBridge | 171:3a7713b1edbc | 128 | }ADC_ChannelConfTypeDef; |
| AnnaBridge | 171:3a7713b1edbc | 129 | |
| AnnaBridge | 171:3a7713b1edbc | 130 | /** |
| AnnaBridge | 171:3a7713b1edbc | 131 | * @brief ADC Configuration analog watchdog definition |
| AnnaBridge | 171:3a7713b1edbc | 132 | * @note The setting of these parameters with function is conditioned to ADC state. |
| AnnaBridge | 171:3a7713b1edbc | 133 | * ADC state can be either disabled or enabled without conversion on going on regular and injected groups. |
| AnnaBridge | 171:3a7713b1edbc | 134 | */ |
| AnnaBridge | 171:3a7713b1edbc | 135 | typedef struct |
| AnnaBridge | 171:3a7713b1edbc | 136 | { |
| AnnaBridge | 171:3a7713b1edbc | 137 | uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group. |
| AnnaBridge | 171:3a7713b1edbc | 138 | This parameter can be a value of @ref ADC_analog_watchdog_mode. */ |
| AnnaBridge | 171:3a7713b1edbc | 139 | uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog. |
| AnnaBridge | 171:3a7713b1edbc | 140 | This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode) |
| AnnaBridge | 171:3a7713b1edbc | 141 | This parameter can be a value of @ref ADC_channels. */ |
| AnnaBridge | 171:3a7713b1edbc | 142 | uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode. |
| AnnaBridge | 171:3a7713b1edbc | 143 | This parameter can be set to ENABLE or DISABLE */ |
| AnnaBridge | 171:3a7713b1edbc | 144 | uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value. |
| AnnaBridge | 171:3a7713b1edbc | 145 | This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ |
| AnnaBridge | 171:3a7713b1edbc | 146 | uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value. |
| AnnaBridge | 171:3a7713b1edbc | 147 | This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ |
| AnnaBridge | 171:3a7713b1edbc | 148 | uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */ |
| AnnaBridge | 171:3a7713b1edbc | 149 | }ADC_AnalogWDGConfTypeDef; |
| AnnaBridge | 171:3a7713b1edbc | 150 | |
| AnnaBridge | 171:3a7713b1edbc | 151 | /** |
| AnnaBridge | 171:3a7713b1edbc | 152 | * @brief HAL ADC state machine: ADC states definition (bitfields) |
| AnnaBridge | 171:3a7713b1edbc | 153 | */ |
| AnnaBridge | 171:3a7713b1edbc | 154 | /* States of ADC global scope */ |
| AnnaBridge | 171:3a7713b1edbc | 155 | #define HAL_ADC_STATE_RESET 0x00000000U /*!< ADC not yet initialized or disabled */ |
| AnnaBridge | 171:3a7713b1edbc | 156 | #define HAL_ADC_STATE_READY 0x00000001U /*!< ADC peripheral ready for use */ |
| AnnaBridge | 171:3a7713b1edbc | 157 | #define HAL_ADC_STATE_BUSY_INTERNAL 0x00000002U /*!< ADC is busy to internal process (initialization, calibration) */ |
| AnnaBridge | 171:3a7713b1edbc | 158 | #define HAL_ADC_STATE_TIMEOUT 0x00000004U /*!< TimeOut occurrence */ |
| AnnaBridge | 171:3a7713b1edbc | 159 | |
| AnnaBridge | 171:3a7713b1edbc | 160 | /* States of ADC errors */ |
| AnnaBridge | 171:3a7713b1edbc | 161 | #define HAL_ADC_STATE_ERROR_INTERNAL 0x00000010U /*!< Internal error occurrence */ |
| AnnaBridge | 171:3a7713b1edbc | 162 | #define HAL_ADC_STATE_ERROR_CONFIG 0x00000020U /*!< Configuration error occurrence */ |
| AnnaBridge | 171:3a7713b1edbc | 163 | #define HAL_ADC_STATE_ERROR_DMA 0x00000040U /*!< DMA error occurrence */ |
| AnnaBridge | 171:3a7713b1edbc | 164 | |
| AnnaBridge | 171:3a7713b1edbc | 165 | /* States of ADC group regular */ |
| AnnaBridge | 171:3a7713b1edbc | 166 | #define HAL_ADC_STATE_REG_BUSY 0x00000100U /*!< A conversion on group regular is ongoing or can occur (either by continuous mode, |
| AnnaBridge | 171:3a7713b1edbc | 167 | external trigger, low power auto power-on, multimode ADC master control) */ |
| AnnaBridge | 171:3a7713b1edbc | 168 | #define HAL_ADC_STATE_REG_EOC 0x00000200U /*!< Conversion data available on group regular */ |
| AnnaBridge | 171:3a7713b1edbc | 169 | #define HAL_ADC_STATE_REG_OVR 0x00000400U /*!< Not available on STM32F1 device: Overrun occurrence */ |
| AnnaBridge | 171:3a7713b1edbc | 170 | #define HAL_ADC_STATE_REG_EOSMP 0x00000800U /*!< Not available on STM32F1 device: End Of Sampling flag raised */ |
| AnnaBridge | 171:3a7713b1edbc | 171 | |
| AnnaBridge | 171:3a7713b1edbc | 172 | /* States of ADC group injected */ |
| AnnaBridge | 171:3a7713b1edbc | 173 | #define HAL_ADC_STATE_INJ_BUSY 0x00001000U /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode, |
| AnnaBridge | 171:3a7713b1edbc | 174 | external trigger, low power auto power-on, multimode ADC master control) */ |
| AnnaBridge | 171:3a7713b1edbc | 175 | #define HAL_ADC_STATE_INJ_EOC 0x00002000U /*!< Conversion data available on group injected */ |
| AnnaBridge | 171:3a7713b1edbc | 176 | #define HAL_ADC_STATE_INJ_JQOVF 0x00004000U /*!< Not available on STM32F1 device: Injected queue overflow occurrence */ |
| AnnaBridge | 171:3a7713b1edbc | 177 | |
| AnnaBridge | 171:3a7713b1edbc | 178 | /* States of ADC analog watchdogs */ |
| AnnaBridge | 171:3a7713b1edbc | 179 | #define HAL_ADC_STATE_AWD1 0x00010000U /*!< Out-of-window occurrence of analog watchdog 1 */ |
| AnnaBridge | 171:3a7713b1edbc | 180 | #define HAL_ADC_STATE_AWD2 0x00020000U /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 2 */ |
| AnnaBridge | 171:3a7713b1edbc | 181 | #define HAL_ADC_STATE_AWD3 0x00040000U /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 3 */ |
| AnnaBridge | 171:3a7713b1edbc | 182 | |
| AnnaBridge | 171:3a7713b1edbc | 183 | /* States of ADC multi-mode */ |
| AnnaBridge | 171:3a7713b1edbc | 184 | #define HAL_ADC_STATE_MULTIMODE_SLAVE 0x00100000U /*!< ADC in multimode slave state, controlled by another ADC master ( */ |
| AnnaBridge | 171:3a7713b1edbc | 185 | |
| AnnaBridge | 171:3a7713b1edbc | 186 | |
| AnnaBridge | 171:3a7713b1edbc | 187 | /** |
| AnnaBridge | 171:3a7713b1edbc | 188 | * @brief ADC handle Structure definition |
| AnnaBridge | 171:3a7713b1edbc | 189 | */ |
| AnnaBridge | 171:3a7713b1edbc | 190 | typedef struct |
| AnnaBridge | 171:3a7713b1edbc | 191 | { |
| AnnaBridge | 171:3a7713b1edbc | 192 | ADC_TypeDef *Instance; /*!< Register base address */ |
| AnnaBridge | 171:3a7713b1edbc | 193 | |
| AnnaBridge | 171:3a7713b1edbc | 194 | ADC_InitTypeDef Init; /*!< ADC required parameters */ |
| AnnaBridge | 171:3a7713b1edbc | 195 | |
| AnnaBridge | 171:3a7713b1edbc | 196 | DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ |
| AnnaBridge | 171:3a7713b1edbc | 197 | |
| AnnaBridge | 171:3a7713b1edbc | 198 | HAL_LockTypeDef Lock; /*!< ADC locking object */ |
| AnnaBridge | 171:3a7713b1edbc | 199 | |
| AnnaBridge | 171:3a7713b1edbc | 200 | __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ |
| AnnaBridge | 171:3a7713b1edbc | 201 | |
| AnnaBridge | 171:3a7713b1edbc | 202 | __IO uint32_t ErrorCode; /*!< ADC Error code */ |
| AnnaBridge | 171:3a7713b1edbc | 203 | }ADC_HandleTypeDef; |
| AnnaBridge | 171:3a7713b1edbc | 204 | /** |
| AnnaBridge | 171:3a7713b1edbc | 205 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 206 | */ |
| AnnaBridge | 171:3a7713b1edbc | 207 | |
| AnnaBridge | 171:3a7713b1edbc | 208 | |
| AnnaBridge | 171:3a7713b1edbc | 209 | |
| AnnaBridge | 171:3a7713b1edbc | 210 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 211 | |
| AnnaBridge | 171:3a7713b1edbc | 212 | /** @defgroup ADC_Exported_Constants ADC Exported Constants |
| AnnaBridge | 171:3a7713b1edbc | 213 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 214 | */ |
| AnnaBridge | 171:3a7713b1edbc | 215 | |
| AnnaBridge | 171:3a7713b1edbc | 216 | /** @defgroup ADC_Error_Code ADC Error Code |
| AnnaBridge | 171:3a7713b1edbc | 217 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 218 | */ |
| AnnaBridge | 171:3a7713b1edbc | 219 | #define HAL_ADC_ERROR_NONE 0x00U /*!< No error */ |
| AnnaBridge | 171:3a7713b1edbc | 220 | #define HAL_ADC_ERROR_INTERNAL 0x01U /*!< ADC IP internal error: if problem of clocking, |
| AnnaBridge | 171:3a7713b1edbc | 221 | enable/disable, erroneous state */ |
| AnnaBridge | 171:3a7713b1edbc | 222 | #define HAL_ADC_ERROR_OVR 0x02U /*!< Overrun error */ |
| AnnaBridge | 171:3a7713b1edbc | 223 | #define HAL_ADC_ERROR_DMA 0x04U /*!< DMA transfer error */ |
| AnnaBridge | 171:3a7713b1edbc | 224 | |
| AnnaBridge | 171:3a7713b1edbc | 225 | /** |
| AnnaBridge | 171:3a7713b1edbc | 226 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 227 | */ |
| AnnaBridge | 171:3a7713b1edbc | 228 | |
| AnnaBridge | 171:3a7713b1edbc | 229 | |
| AnnaBridge | 171:3a7713b1edbc | 230 | /** @defgroup ADC_Data_align ADC data alignment |
| AnnaBridge | 171:3a7713b1edbc | 231 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 232 | */ |
| AnnaBridge | 171:3a7713b1edbc | 233 | #define ADC_DATAALIGN_RIGHT 0x00000000U |
| AnnaBridge | 171:3a7713b1edbc | 234 | #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN) |
| AnnaBridge | 171:3a7713b1edbc | 235 | /** |
| AnnaBridge | 171:3a7713b1edbc | 236 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 237 | */ |
| AnnaBridge | 171:3a7713b1edbc | 238 | |
| AnnaBridge | 171:3a7713b1edbc | 239 | /** @defgroup ADC_Scan_mode ADC scan mode |
| AnnaBridge | 171:3a7713b1edbc | 240 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 241 | */ |
| AnnaBridge | 171:3a7713b1edbc | 242 | /* Note: Scan mode values are not among binary choices ENABLE/DISABLE for */ |
| AnnaBridge | 171:3a7713b1edbc | 243 | /* compatibility with other STM32 devices having a sequencer with */ |
| AnnaBridge | 171:3a7713b1edbc | 244 | /* additional options. */ |
| AnnaBridge | 171:3a7713b1edbc | 245 | #define ADC_SCAN_DISABLE 0x00000000U |
| AnnaBridge | 171:3a7713b1edbc | 246 | #define ADC_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN) |
| AnnaBridge | 171:3a7713b1edbc | 247 | /** |
| AnnaBridge | 171:3a7713b1edbc | 248 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 249 | */ |
| AnnaBridge | 171:3a7713b1edbc | 250 | |
| AnnaBridge | 171:3a7713b1edbc | 251 | /** @defgroup ADC_External_trigger_edge_Regular ADC external trigger enable for regular group |
| AnnaBridge | 171:3a7713b1edbc | 252 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 253 | */ |
| AnnaBridge | 171:3a7713b1edbc | 254 | #define ADC_EXTERNALTRIGCONVEDGE_NONE 0x00000000U |
| AnnaBridge | 171:3a7713b1edbc | 255 | #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTTRIG) |
| AnnaBridge | 171:3a7713b1edbc | 256 | /** |
| AnnaBridge | 171:3a7713b1edbc | 257 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 258 | */ |
| AnnaBridge | 171:3a7713b1edbc | 259 | |
| AnnaBridge | 171:3a7713b1edbc | 260 | /** @defgroup ADC_channels ADC channels |
| AnnaBridge | 171:3a7713b1edbc | 261 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 262 | */ |
| AnnaBridge | 171:3a7713b1edbc | 263 | /* Note: Depending on devices, some channels may not be available on package */ |
| AnnaBridge | 171:3a7713b1edbc | 264 | /* pins. Refer to device datasheet for channels availability. */ |
| AnnaBridge | 171:3a7713b1edbc | 265 | #define ADC_CHANNEL_0 0x00000000U |
| AnnaBridge | 171:3a7713b1edbc | 266 | #define ADC_CHANNEL_1 ((uint32_t)( ADC_SQR3_SQ1_0)) |
| AnnaBridge | 171:3a7713b1edbc | 267 | #define ADC_CHANNEL_2 ((uint32_t)( ADC_SQR3_SQ1_1 )) |
| AnnaBridge | 171:3a7713b1edbc | 268 | #define ADC_CHANNEL_3 ((uint32_t)( ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) |
| AnnaBridge | 171:3a7713b1edbc | 269 | #define ADC_CHANNEL_4 ((uint32_t)( ADC_SQR3_SQ1_2 )) |
| AnnaBridge | 171:3a7713b1edbc | 270 | #define ADC_CHANNEL_5 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0)) |
| AnnaBridge | 171:3a7713b1edbc | 271 | #define ADC_CHANNEL_6 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 )) |
| AnnaBridge | 171:3a7713b1edbc | 272 | #define ADC_CHANNEL_7 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) |
| AnnaBridge | 171:3a7713b1edbc | 273 | #define ADC_CHANNEL_8 ((uint32_t)( ADC_SQR3_SQ1_3 )) |
| AnnaBridge | 171:3a7713b1edbc | 274 | #define ADC_CHANNEL_9 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_0)) |
| AnnaBridge | 171:3a7713b1edbc | 275 | #define ADC_CHANNEL_10 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 )) |
| AnnaBridge | 171:3a7713b1edbc | 276 | #define ADC_CHANNEL_11 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) |
| AnnaBridge | 171:3a7713b1edbc | 277 | #define ADC_CHANNEL_12 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 )) |
| AnnaBridge | 171:3a7713b1edbc | 278 | #define ADC_CHANNEL_13 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0)) |
| AnnaBridge | 171:3a7713b1edbc | 279 | #define ADC_CHANNEL_14 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 )) |
| AnnaBridge | 171:3a7713b1edbc | 280 | #define ADC_CHANNEL_15 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) |
| AnnaBridge | 171:3a7713b1edbc | 281 | #define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ1_4 )) |
| AnnaBridge | 171:3a7713b1edbc | 282 | #define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ1_4 | ADC_SQR3_SQ1_0)) |
| AnnaBridge | 171:3a7713b1edbc | 283 | |
| AnnaBridge | 171:3a7713b1edbc | 284 | #define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 /* ADC internal channel (no connection on device pin) */ |
| AnnaBridge | 171:3a7713b1edbc | 285 | #define ADC_CHANNEL_VREFINT ADC_CHANNEL_17 /* ADC internal channel (no connection on device pin) */ |
| AnnaBridge | 171:3a7713b1edbc | 286 | /** |
| AnnaBridge | 171:3a7713b1edbc | 287 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 288 | */ |
| AnnaBridge | 171:3a7713b1edbc | 289 | |
| AnnaBridge | 171:3a7713b1edbc | 290 | /** @defgroup ADC_sampling_times ADC sampling times |
| AnnaBridge | 171:3a7713b1edbc | 291 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 292 | */ |
| AnnaBridge | 171:3a7713b1edbc | 293 | #define ADC_SAMPLETIME_1CYCLE_5 0x00000000U /*!< Sampling time 1.5 ADC clock cycle */ |
| AnnaBridge | 171:3a7713b1edbc | 294 | #define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_0)) /*!< Sampling time 7.5 ADC clock cycles */ |
| AnnaBridge | 171:3a7713b1edbc | 295 | #define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_1 )) /*!< Sampling time 13.5 ADC clock cycles */ |
| AnnaBridge | 171:3a7713b1edbc | 296 | #define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 28.5 ADC clock cycles */ |
| AnnaBridge | 171:3a7713b1edbc | 297 | #define ADC_SAMPLETIME_41CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 )) /*!< Sampling time 41.5 ADC clock cycles */ |
| AnnaBridge | 171:3a7713b1edbc | 298 | #define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 55.5 ADC clock cycles */ |
| AnnaBridge | 171:3a7713b1edbc | 299 | #define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 )) /*!< Sampling time 71.5 ADC clock cycles */ |
| AnnaBridge | 171:3a7713b1edbc | 300 | #define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 239.5 ADC clock cycles */ |
| AnnaBridge | 171:3a7713b1edbc | 301 | /** |
| AnnaBridge | 171:3a7713b1edbc | 302 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 303 | */ |
| AnnaBridge | 171:3a7713b1edbc | 304 | |
| AnnaBridge | 171:3a7713b1edbc | 305 | /** @defgroup ADC_regular_rank ADC rank into regular group |
| AnnaBridge | 171:3a7713b1edbc | 306 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 307 | */ |
| AnnaBridge | 171:3a7713b1edbc | 308 | #define ADC_REGULAR_RANK_1 0x00000001U |
| AnnaBridge | 171:3a7713b1edbc | 309 | #define ADC_REGULAR_RANK_2 0x00000002U |
| AnnaBridge | 171:3a7713b1edbc | 310 | #define ADC_REGULAR_RANK_3 0x00000003U |
| AnnaBridge | 171:3a7713b1edbc | 311 | #define ADC_REGULAR_RANK_4 0x00000004U |
| AnnaBridge | 171:3a7713b1edbc | 312 | #define ADC_REGULAR_RANK_5 0x00000005U |
| AnnaBridge | 171:3a7713b1edbc | 313 | #define ADC_REGULAR_RANK_6 0x00000006U |
| AnnaBridge | 171:3a7713b1edbc | 314 | #define ADC_REGULAR_RANK_7 0x00000007U |
| AnnaBridge | 171:3a7713b1edbc | 315 | #define ADC_REGULAR_RANK_8 0x00000008U |
| AnnaBridge | 171:3a7713b1edbc | 316 | #define ADC_REGULAR_RANK_9 0x00000009U |
| AnnaBridge | 171:3a7713b1edbc | 317 | #define ADC_REGULAR_RANK_10 0x0000000AU |
| AnnaBridge | 171:3a7713b1edbc | 318 | #define ADC_REGULAR_RANK_11 0x0000000BU |
| AnnaBridge | 171:3a7713b1edbc | 319 | #define ADC_REGULAR_RANK_12 0x0000000CU |
| AnnaBridge | 171:3a7713b1edbc | 320 | #define ADC_REGULAR_RANK_13 0x0000000DU |
| AnnaBridge | 171:3a7713b1edbc | 321 | #define ADC_REGULAR_RANK_14 0x0000000EU |
| AnnaBridge | 171:3a7713b1edbc | 322 | #define ADC_REGULAR_RANK_15 0x0000000FU |
| AnnaBridge | 171:3a7713b1edbc | 323 | #define ADC_REGULAR_RANK_16 0x00000010U |
| AnnaBridge | 171:3a7713b1edbc | 324 | /** |
| AnnaBridge | 171:3a7713b1edbc | 325 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 326 | */ |
| AnnaBridge | 171:3a7713b1edbc | 327 | |
| AnnaBridge | 171:3a7713b1edbc | 328 | /** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode |
| AnnaBridge | 171:3a7713b1edbc | 329 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 330 | */ |
| AnnaBridge | 171:3a7713b1edbc | 331 | #define ADC_ANALOGWATCHDOG_NONE 0x00000000U |
| AnnaBridge | 171:3a7713b1edbc | 332 | #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN)) |
| AnnaBridge | 171:3a7713b1edbc | 333 | #define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN)) |
| AnnaBridge | 171:3a7713b1edbc | 334 | #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) |
| AnnaBridge | 171:3a7713b1edbc | 335 | #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN) |
| AnnaBridge | 171:3a7713b1edbc | 336 | #define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN) |
| AnnaBridge | 171:3a7713b1edbc | 337 | #define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) |
| AnnaBridge | 171:3a7713b1edbc | 338 | /** |
| AnnaBridge | 171:3a7713b1edbc | 339 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 340 | */ |
| AnnaBridge | 171:3a7713b1edbc | 341 | |
| AnnaBridge | 171:3a7713b1edbc | 342 | /** @defgroup ADC_conversion_group ADC conversion group |
| AnnaBridge | 171:3a7713b1edbc | 343 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 344 | */ |
| AnnaBridge | 171:3a7713b1edbc | 345 | #define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC)) |
| AnnaBridge | 171:3a7713b1edbc | 346 | #define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC)) |
| AnnaBridge | 171:3a7713b1edbc | 347 | #define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_JEOC)) |
| AnnaBridge | 171:3a7713b1edbc | 348 | /** |
| AnnaBridge | 171:3a7713b1edbc | 349 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 350 | */ |
| AnnaBridge | 171:3a7713b1edbc | 351 | |
| AnnaBridge | 171:3a7713b1edbc | 352 | /** @defgroup ADC_Event_type ADC Event type |
| AnnaBridge | 171:3a7713b1edbc | 353 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 354 | */ |
| AnnaBridge | 171:3a7713b1edbc | 355 | #define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /*!< ADC Analog watchdog event */ |
| AnnaBridge | 171:3a7713b1edbc | 356 | |
| AnnaBridge | 171:3a7713b1edbc | 357 | #define ADC_AWD1_EVENT ADC_AWD_EVENT /*!< ADC Analog watchdog 1 event: Alternate naming for compatibility with other STM32 devices having several analog watchdogs */ |
| AnnaBridge | 171:3a7713b1edbc | 358 | /** |
| AnnaBridge | 171:3a7713b1edbc | 359 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 360 | */ |
| AnnaBridge | 171:3a7713b1edbc | 361 | |
| AnnaBridge | 171:3a7713b1edbc | 362 | /** @defgroup ADC_interrupts_definition ADC interrupts definition |
| AnnaBridge | 171:3a7713b1edbc | 363 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 364 | */ |
| AnnaBridge | 171:3a7713b1edbc | 365 | #define ADC_IT_EOC ADC_CR1_EOCIE /*!< ADC End of Regular Conversion interrupt source */ |
| AnnaBridge | 171:3a7713b1edbc | 366 | #define ADC_IT_JEOC ADC_CR1_JEOCIE /*!< ADC End of Injected Conversion interrupt source */ |
| AnnaBridge | 171:3a7713b1edbc | 367 | #define ADC_IT_AWD ADC_CR1_AWDIE /*!< ADC Analog watchdog interrupt source */ |
| AnnaBridge | 171:3a7713b1edbc | 368 | /** |
| AnnaBridge | 171:3a7713b1edbc | 369 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 370 | */ |
| AnnaBridge | 171:3a7713b1edbc | 371 | |
| AnnaBridge | 171:3a7713b1edbc | 372 | /** @defgroup ADC_flags_definition ADC flags definition |
| AnnaBridge | 171:3a7713b1edbc | 373 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 374 | */ |
| AnnaBridge | 171:3a7713b1edbc | 375 | #define ADC_FLAG_STRT ADC_SR_STRT /*!< ADC Regular group start flag */ |
| AnnaBridge | 171:3a7713b1edbc | 376 | #define ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC Injected group start flag */ |
| AnnaBridge | 171:3a7713b1edbc | 377 | #define ADC_FLAG_EOC ADC_SR_EOC /*!< ADC End of Regular conversion flag */ |
| AnnaBridge | 171:3a7713b1edbc | 378 | #define ADC_FLAG_JEOC ADC_SR_JEOC /*!< ADC End of Injected conversion flag */ |
| AnnaBridge | 171:3a7713b1edbc | 379 | #define ADC_FLAG_AWD ADC_SR_AWD /*!< ADC Analog watchdog flag */ |
| AnnaBridge | 171:3a7713b1edbc | 380 | /** |
| AnnaBridge | 171:3a7713b1edbc | 381 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 382 | */ |
| AnnaBridge | 171:3a7713b1edbc | 383 | |
| AnnaBridge | 171:3a7713b1edbc | 384 | |
| AnnaBridge | 171:3a7713b1edbc | 385 | /** |
| AnnaBridge | 171:3a7713b1edbc | 386 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 387 | */ |
| AnnaBridge | 171:3a7713b1edbc | 388 | |
| AnnaBridge | 171:3a7713b1edbc | 389 | /* Private constants ---------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 390 | |
| AnnaBridge | 171:3a7713b1edbc | 391 | /** @addtogroup ADC_Private_Constants ADC Private Constants |
| AnnaBridge | 171:3a7713b1edbc | 392 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 393 | */ |
| AnnaBridge | 171:3a7713b1edbc | 394 | |
| AnnaBridge | 171:3a7713b1edbc | 395 | /** @defgroup ADC_conversion_cycles ADC conversion cycles |
| AnnaBridge | 171:3a7713b1edbc | 396 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 397 | */ |
| AnnaBridge | 171:3a7713b1edbc | 398 | /* ADC conversion cycles (unit: ADC clock cycles) */ |
| AnnaBridge | 171:3a7713b1edbc | 399 | /* (selected sampling time + conversion time of 12.5 ADC clock cycles, with */ |
| AnnaBridge | 171:3a7713b1edbc | 400 | /* resolution 12 bits) */ |
| AnnaBridge | 171:3a7713b1edbc | 401 | #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5 14U |
| AnnaBridge | 171:3a7713b1edbc | 402 | #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 20U |
| AnnaBridge | 171:3a7713b1edbc | 403 | #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5 26U |
| AnnaBridge | 171:3a7713b1edbc | 404 | #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5 41U |
| AnnaBridge | 171:3a7713b1edbc | 405 | #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5 54U |
| AnnaBridge | 171:3a7713b1edbc | 406 | #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5 68U |
| AnnaBridge | 171:3a7713b1edbc | 407 | #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 84U |
| AnnaBridge | 171:3a7713b1edbc | 408 | #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 252U |
| AnnaBridge | 171:3a7713b1edbc | 409 | /** |
| AnnaBridge | 171:3a7713b1edbc | 410 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 411 | */ |
| AnnaBridge | 171:3a7713b1edbc | 412 | |
| AnnaBridge | 171:3a7713b1edbc | 413 | /** @defgroup ADC_sampling_times_all_channels ADC sampling times all channels |
| AnnaBridge | 171:3a7713b1edbc | 414 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 415 | */ |
| AnnaBridge | 171:3a7713b1edbc | 416 | #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \ |
| AnnaBridge | 171:3a7713b1edbc | 417 | (ADC_SMPR2_SMP9_2 | ADC_SMPR2_SMP8_2 | ADC_SMPR2_SMP7_2 | ADC_SMPR2_SMP6_2 | \ |
| AnnaBridge | 171:3a7713b1edbc | 418 | ADC_SMPR2_SMP5_2 | ADC_SMPR2_SMP4_2 | ADC_SMPR2_SMP3_2 | ADC_SMPR2_SMP2_2 | \ |
| AnnaBridge | 171:3a7713b1edbc | 419 | ADC_SMPR2_SMP1_2 | ADC_SMPR2_SMP0_2) |
| AnnaBridge | 171:3a7713b1edbc | 420 | #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \ |
| AnnaBridge | 171:3a7713b1edbc | 421 | (ADC_SMPR1_SMP17_2 | ADC_SMPR1_SMP16_2 | ADC_SMPR1_SMP15_2 | ADC_SMPR1_SMP14_2 | \ |
| AnnaBridge | 171:3a7713b1edbc | 422 | ADC_SMPR1_SMP13_2 | ADC_SMPR1_SMP12_2 | ADC_SMPR1_SMP11_2 | ADC_SMPR1_SMP10_2 ) |
| AnnaBridge | 171:3a7713b1edbc | 423 | |
| AnnaBridge | 171:3a7713b1edbc | 424 | #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \ |
| AnnaBridge | 171:3a7713b1edbc | 425 | (ADC_SMPR2_SMP9_1 | ADC_SMPR2_SMP8_1 | ADC_SMPR2_SMP7_1 | ADC_SMPR2_SMP6_1 | \ |
| AnnaBridge | 171:3a7713b1edbc | 426 | ADC_SMPR2_SMP5_1 | ADC_SMPR2_SMP4_1 | ADC_SMPR2_SMP3_1 | ADC_SMPR2_SMP2_1 | \ |
| AnnaBridge | 171:3a7713b1edbc | 427 | ADC_SMPR2_SMP1_1 | ADC_SMPR2_SMP0_1) |
| AnnaBridge | 171:3a7713b1edbc | 428 | #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \ |
| AnnaBridge | 171:3a7713b1edbc | 429 | (ADC_SMPR1_SMP17_1 | ADC_SMPR1_SMP16_1 | ADC_SMPR1_SMP15_1 | ADC_SMPR1_SMP14_1 | \ |
| AnnaBridge | 171:3a7713b1edbc | 430 | ADC_SMPR1_SMP13_1 | ADC_SMPR1_SMP12_1 | ADC_SMPR1_SMP11_1 | ADC_SMPR1_SMP10_1 ) |
| AnnaBridge | 171:3a7713b1edbc | 431 | |
| AnnaBridge | 171:3a7713b1edbc | 432 | #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 \ |
| AnnaBridge | 171:3a7713b1edbc | 433 | (ADC_SMPR2_SMP9_0 | ADC_SMPR2_SMP8_0 | ADC_SMPR2_SMP7_0 | ADC_SMPR2_SMP6_0 | \ |
| AnnaBridge | 171:3a7713b1edbc | 434 | ADC_SMPR2_SMP5_0 | ADC_SMPR2_SMP4_0 | ADC_SMPR2_SMP3_0 | ADC_SMPR2_SMP2_0 | \ |
| AnnaBridge | 171:3a7713b1edbc | 435 | ADC_SMPR2_SMP1_0 | ADC_SMPR2_SMP0_0) |
| AnnaBridge | 171:3a7713b1edbc | 436 | #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \ |
| AnnaBridge | 171:3a7713b1edbc | 437 | (ADC_SMPR1_SMP17_0 | ADC_SMPR1_SMP16_0 | ADC_SMPR1_SMP15_0 | ADC_SMPR1_SMP14_0 | \ |
| AnnaBridge | 171:3a7713b1edbc | 438 | ADC_SMPR1_SMP13_0 | ADC_SMPR1_SMP12_0 | ADC_SMPR1_SMP11_0 | ADC_SMPR1_SMP10_0 ) |
| AnnaBridge | 171:3a7713b1edbc | 439 | |
| AnnaBridge | 171:3a7713b1edbc | 440 | #define ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS 0x00000000U |
| AnnaBridge | 171:3a7713b1edbc | 441 | #define ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) |
| AnnaBridge | 171:3a7713b1edbc | 442 | #define ADC_SAMPLETIME_13CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) |
| AnnaBridge | 171:3a7713b1edbc | 443 | #define ADC_SAMPLETIME_28CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) |
| AnnaBridge | 171:3a7713b1edbc | 444 | #define ADC_SAMPLETIME_41CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) |
| AnnaBridge | 171:3a7713b1edbc | 445 | #define ADC_SAMPLETIME_55CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) |
| AnnaBridge | 171:3a7713b1edbc | 446 | #define ADC_SAMPLETIME_71CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) |
| AnnaBridge | 171:3a7713b1edbc | 447 | #define ADC_SAMPLETIME_239CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) |
| AnnaBridge | 171:3a7713b1edbc | 448 | |
| AnnaBridge | 171:3a7713b1edbc | 449 | #define ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS 0x00000000U |
| AnnaBridge | 171:3a7713b1edbc | 450 | #define ADC_SAMPLETIME_7CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) |
| AnnaBridge | 171:3a7713b1edbc | 451 | #define ADC_SAMPLETIME_13CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) |
| AnnaBridge | 171:3a7713b1edbc | 452 | #define ADC_SAMPLETIME_28CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) |
| AnnaBridge | 171:3a7713b1edbc | 453 | #define ADC_SAMPLETIME_41CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) |
| AnnaBridge | 171:3a7713b1edbc | 454 | #define ADC_SAMPLETIME_55CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) |
| AnnaBridge | 171:3a7713b1edbc | 455 | #define ADC_SAMPLETIME_71CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) |
| AnnaBridge | 171:3a7713b1edbc | 456 | #define ADC_SAMPLETIME_239CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) |
| AnnaBridge | 171:3a7713b1edbc | 457 | /** |
| AnnaBridge | 171:3a7713b1edbc | 458 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 459 | */ |
| AnnaBridge | 171:3a7713b1edbc | 460 | |
| AnnaBridge | 171:3a7713b1edbc | 461 | /* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */ |
| AnnaBridge | 171:3a7713b1edbc | 462 | #define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_JEOC | ADC_FLAG_AWD ) |
| AnnaBridge | 171:3a7713b1edbc | 463 | |
| AnnaBridge | 171:3a7713b1edbc | 464 | /** |
| AnnaBridge | 171:3a7713b1edbc | 465 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 466 | */ |
| AnnaBridge | 171:3a7713b1edbc | 467 | |
| AnnaBridge | 171:3a7713b1edbc | 468 | |
| AnnaBridge | 171:3a7713b1edbc | 469 | /* Exported macro ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 470 | |
| AnnaBridge | 171:3a7713b1edbc | 471 | /** @defgroup ADC_Exported_Macros ADC Exported Macros |
| AnnaBridge | 171:3a7713b1edbc | 472 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 473 | */ |
| AnnaBridge | 171:3a7713b1edbc | 474 | /* Macro for internal HAL driver usage, and possibly can be used into code of */ |
| AnnaBridge | 171:3a7713b1edbc | 475 | /* final user. */ |
| AnnaBridge | 171:3a7713b1edbc | 476 | |
| AnnaBridge | 171:3a7713b1edbc | 477 | /** |
| AnnaBridge | 171:3a7713b1edbc | 478 | * @brief Enable the ADC peripheral |
| AnnaBridge | 171:3a7713b1edbc | 479 | * @note ADC enable requires a delay for ADC stabilization time |
| AnnaBridge | 171:3a7713b1edbc | 480 | * (refer to device datasheet, parameter tSTAB) |
| AnnaBridge | 171:3a7713b1edbc | 481 | * @note On STM32F1, if ADC is already enabled this macro trigs a conversion |
| AnnaBridge | 171:3a7713b1edbc | 482 | * SW start on regular group. |
| AnnaBridge | 171:3a7713b1edbc | 483 | * @param __HANDLE__: ADC handle |
| AnnaBridge | 171:3a7713b1edbc | 484 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 485 | */ |
| AnnaBridge | 171:3a7713b1edbc | 486 | #define __HAL_ADC_ENABLE(__HANDLE__) \ |
| AnnaBridge | 171:3a7713b1edbc | 487 | (SET_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON))) |
| AnnaBridge | 171:3a7713b1edbc | 488 | |
| AnnaBridge | 171:3a7713b1edbc | 489 | /** |
| AnnaBridge | 171:3a7713b1edbc | 490 | * @brief Disable the ADC peripheral |
| AnnaBridge | 171:3a7713b1edbc | 491 | * @param __HANDLE__: ADC handle |
| AnnaBridge | 171:3a7713b1edbc | 492 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 493 | */ |
| AnnaBridge | 171:3a7713b1edbc | 494 | #define __HAL_ADC_DISABLE(__HANDLE__) \ |
| AnnaBridge | 171:3a7713b1edbc | 495 | (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON))) |
| AnnaBridge | 171:3a7713b1edbc | 496 | |
| AnnaBridge | 171:3a7713b1edbc | 497 | /** @brief Enable the ADC end of conversion interrupt. |
| AnnaBridge | 171:3a7713b1edbc | 498 | * @param __HANDLE__: ADC handle |
| AnnaBridge | 171:3a7713b1edbc | 499 | * @param __INTERRUPT__: ADC Interrupt |
| AnnaBridge | 171:3a7713b1edbc | 500 | * This parameter can be any combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 501 | * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source |
| AnnaBridge | 171:3a7713b1edbc | 502 | * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source |
| AnnaBridge | 171:3a7713b1edbc | 503 | * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source |
| AnnaBridge | 171:3a7713b1edbc | 504 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 505 | */ |
| AnnaBridge | 171:3a7713b1edbc | 506 | #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ |
| AnnaBridge | 171:3a7713b1edbc | 507 | (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__))) |
| AnnaBridge | 171:3a7713b1edbc | 508 | |
| AnnaBridge | 171:3a7713b1edbc | 509 | /** @brief Disable the ADC end of conversion interrupt. |
| AnnaBridge | 171:3a7713b1edbc | 510 | * @param __HANDLE__: ADC handle |
| AnnaBridge | 171:3a7713b1edbc | 511 | * @param __INTERRUPT__: ADC Interrupt |
| AnnaBridge | 171:3a7713b1edbc | 512 | * This parameter can be any combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 513 | * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source |
| AnnaBridge | 171:3a7713b1edbc | 514 | * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source |
| AnnaBridge | 171:3a7713b1edbc | 515 | * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source |
| AnnaBridge | 171:3a7713b1edbc | 516 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 517 | */ |
| AnnaBridge | 171:3a7713b1edbc | 518 | #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ |
| AnnaBridge | 171:3a7713b1edbc | 519 | (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__))) |
| AnnaBridge | 171:3a7713b1edbc | 520 | |
| AnnaBridge | 171:3a7713b1edbc | 521 | /** @brief Checks if the specified ADC interrupt source is enabled or disabled. |
| AnnaBridge | 171:3a7713b1edbc | 522 | * @param __HANDLE__: ADC handle |
| AnnaBridge | 171:3a7713b1edbc | 523 | * @param __INTERRUPT__: ADC interrupt source to check |
| AnnaBridge | 171:3a7713b1edbc | 524 | * This parameter can be any combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 525 | * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source |
| AnnaBridge | 171:3a7713b1edbc | 526 | * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source |
| AnnaBridge | 171:3a7713b1edbc | 527 | * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source |
| AnnaBridge | 171:3a7713b1edbc | 528 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 529 | */ |
| AnnaBridge | 171:3a7713b1edbc | 530 | #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ |
| AnnaBridge | 171:3a7713b1edbc | 531 | (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) |
| AnnaBridge | 171:3a7713b1edbc | 532 | |
| AnnaBridge | 171:3a7713b1edbc | 533 | /** @brief Get the selected ADC's flag status. |
| AnnaBridge | 171:3a7713b1edbc | 534 | * @param __HANDLE__: ADC handle |
| AnnaBridge | 171:3a7713b1edbc | 535 | * @param __FLAG__: ADC flag |
| AnnaBridge | 171:3a7713b1edbc | 536 | * This parameter can be any combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 537 | * @arg ADC_FLAG_STRT: ADC Regular group start flag |
| AnnaBridge | 171:3a7713b1edbc | 538 | * @arg ADC_FLAG_JSTRT: ADC Injected group start flag |
| AnnaBridge | 171:3a7713b1edbc | 539 | * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag |
| AnnaBridge | 171:3a7713b1edbc | 540 | * @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag |
| AnnaBridge | 171:3a7713b1edbc | 541 | * @arg ADC_FLAG_AWD: ADC Analog watchdog flag |
| AnnaBridge | 171:3a7713b1edbc | 542 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 543 | */ |
| AnnaBridge | 171:3a7713b1edbc | 544 | #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ |
| AnnaBridge | 171:3a7713b1edbc | 545 | ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) |
| AnnaBridge | 171:3a7713b1edbc | 546 | |
| AnnaBridge | 171:3a7713b1edbc | 547 | /** @brief Clear the ADC's pending flags |
| AnnaBridge | 171:3a7713b1edbc | 548 | * @param __HANDLE__: ADC handle |
| AnnaBridge | 171:3a7713b1edbc | 549 | * @param __FLAG__: ADC flag |
| AnnaBridge | 171:3a7713b1edbc | 550 | * This parameter can be any combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 551 | * @arg ADC_FLAG_STRT: ADC Regular group start flag |
| AnnaBridge | 171:3a7713b1edbc | 552 | * @arg ADC_FLAG_JSTRT: ADC Injected group start flag |
| AnnaBridge | 171:3a7713b1edbc | 553 | * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag |
| AnnaBridge | 171:3a7713b1edbc | 554 | * @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag |
| AnnaBridge | 171:3a7713b1edbc | 555 | * @arg ADC_FLAG_AWD: ADC Analog watchdog flag |
| AnnaBridge | 171:3a7713b1edbc | 556 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 557 | */ |
| AnnaBridge | 171:3a7713b1edbc | 558 | #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ |
| AnnaBridge | 171:3a7713b1edbc | 559 | (WRITE_REG((__HANDLE__)->Instance->SR, ~(__FLAG__))) |
| AnnaBridge | 171:3a7713b1edbc | 560 | |
| AnnaBridge | 171:3a7713b1edbc | 561 | /** @brief Reset ADC handle state |
| AnnaBridge | 171:3a7713b1edbc | 562 | * @param __HANDLE__: ADC handle |
| AnnaBridge | 171:3a7713b1edbc | 563 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 564 | */ |
| AnnaBridge | 171:3a7713b1edbc | 565 | #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ |
| AnnaBridge | 171:3a7713b1edbc | 566 | ((__HANDLE__)->State = HAL_ADC_STATE_RESET) |
| AnnaBridge | 171:3a7713b1edbc | 567 | |
| AnnaBridge | 171:3a7713b1edbc | 568 | /** |
| AnnaBridge | 171:3a7713b1edbc | 569 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 570 | */ |
| AnnaBridge | 171:3a7713b1edbc | 571 | |
| AnnaBridge | 171:3a7713b1edbc | 572 | /* Private macro ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 573 | |
| AnnaBridge | 171:3a7713b1edbc | 574 | /** @defgroup ADC_Private_Macros ADC Private Macros |
| AnnaBridge | 171:3a7713b1edbc | 575 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 576 | */ |
| AnnaBridge | 171:3a7713b1edbc | 577 | /* Macro reserved for internal HAL driver usage, not intended to be used in */ |
| AnnaBridge | 171:3a7713b1edbc | 578 | /* code of final user. */ |
| AnnaBridge | 171:3a7713b1edbc | 579 | |
| AnnaBridge | 171:3a7713b1edbc | 580 | /** |
| AnnaBridge | 171:3a7713b1edbc | 581 | * @brief Verification of ADC state: enabled or disabled |
| AnnaBridge | 171:3a7713b1edbc | 582 | * @param __HANDLE__: ADC handle |
| AnnaBridge | 171:3a7713b1edbc | 583 | * @retval SET (ADC enabled) or RESET (ADC disabled) |
| AnnaBridge | 171:3a7713b1edbc | 584 | */ |
| AnnaBridge | 171:3a7713b1edbc | 585 | #define ADC_IS_ENABLE(__HANDLE__) \ |
| AnnaBridge | 171:3a7713b1edbc | 586 | ((( ((__HANDLE__)->Instance->CR2 & ADC_CR2_ADON) == ADC_CR2_ADON ) \ |
| AnnaBridge | 171:3a7713b1edbc | 587 | ) ? SET : RESET) |
| AnnaBridge | 171:3a7713b1edbc | 588 | |
| AnnaBridge | 171:3a7713b1edbc | 589 | /** |
| AnnaBridge | 171:3a7713b1edbc | 590 | * @brief Test if conversion trigger of regular group is software start |
| AnnaBridge | 171:3a7713b1edbc | 591 | * or external trigger. |
| AnnaBridge | 171:3a7713b1edbc | 592 | * @param __HANDLE__: ADC handle |
| AnnaBridge | 171:3a7713b1edbc | 593 | * @retval SET (software start) or RESET (external trigger) |
| AnnaBridge | 171:3a7713b1edbc | 594 | */ |
| AnnaBridge | 171:3a7713b1edbc | 595 | #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ |
| AnnaBridge | 171:3a7713b1edbc | 596 | (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_EXTSEL) == ADC_SOFTWARE_START) |
| AnnaBridge | 171:3a7713b1edbc | 597 | |
| AnnaBridge | 171:3a7713b1edbc | 598 | /** |
| AnnaBridge | 171:3a7713b1edbc | 599 | * @brief Test if conversion trigger of injected group is software start |
| AnnaBridge | 171:3a7713b1edbc | 600 | * or external trigger. |
| AnnaBridge | 171:3a7713b1edbc | 601 | * @param __HANDLE__: ADC handle |
| AnnaBridge | 171:3a7713b1edbc | 602 | * @retval SET (software start) or RESET (external trigger) |
| AnnaBridge | 171:3a7713b1edbc | 603 | */ |
| AnnaBridge | 171:3a7713b1edbc | 604 | #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ |
| AnnaBridge | 171:3a7713b1edbc | 605 | (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_JEXTSEL) == ADC_INJECTED_SOFTWARE_START) |
| AnnaBridge | 171:3a7713b1edbc | 606 | |
| AnnaBridge | 171:3a7713b1edbc | 607 | /** |
| AnnaBridge | 171:3a7713b1edbc | 608 | * @brief Simultaneously clears and sets specific bits of the handle State |
| AnnaBridge | 171:3a7713b1edbc | 609 | * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), |
| AnnaBridge | 171:3a7713b1edbc | 610 | * the first parameter is the ADC handle State, the second parameter is the |
| AnnaBridge | 171:3a7713b1edbc | 611 | * bit field to clear, the third and last parameter is the bit field to set. |
| AnnaBridge | 171:3a7713b1edbc | 612 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 613 | */ |
| AnnaBridge | 171:3a7713b1edbc | 614 | #define ADC_STATE_CLR_SET MODIFY_REG |
| AnnaBridge | 171:3a7713b1edbc | 615 | |
| AnnaBridge | 171:3a7713b1edbc | 616 | /** |
| AnnaBridge | 171:3a7713b1edbc | 617 | * @brief Clear ADC error code (set it to error code: "no error") |
| AnnaBridge | 171:3a7713b1edbc | 618 | * @param __HANDLE__: ADC handle |
| AnnaBridge | 171:3a7713b1edbc | 619 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 620 | */ |
| AnnaBridge | 171:3a7713b1edbc | 621 | #define ADC_CLEAR_ERRORCODE(__HANDLE__) \ |
| AnnaBridge | 171:3a7713b1edbc | 622 | ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) |
| AnnaBridge | 171:3a7713b1edbc | 623 | |
| AnnaBridge | 171:3a7713b1edbc | 624 | /** |
| AnnaBridge | 171:3a7713b1edbc | 625 | * @brief Set ADC number of conversions into regular channel sequence length. |
| AnnaBridge | 171:3a7713b1edbc | 626 | * @param _NbrOfConversion_: Regular channel sequence length |
| AnnaBridge | 171:3a7713b1edbc | 627 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 628 | */ |
| AnnaBridge | 171:3a7713b1edbc | 629 | #define ADC_SQR1_L_SHIFT(_NbrOfConversion_) \ |
| AnnaBridge | 171:3a7713b1edbc | 630 | (((_NbrOfConversion_) - (uint8_t)1) << ADC_SQR1_L_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 631 | |
| AnnaBridge | 171:3a7713b1edbc | 632 | /** |
| AnnaBridge | 171:3a7713b1edbc | 633 | * @brief Set the ADC's sample time for channel numbers between 10 and 18. |
| AnnaBridge | 171:3a7713b1edbc | 634 | * @param _SAMPLETIME_: Sample time parameter. |
| AnnaBridge | 171:3a7713b1edbc | 635 | * @param _CHANNELNB_: Channel number. |
| AnnaBridge | 171:3a7713b1edbc | 636 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 637 | */ |
| AnnaBridge | 171:3a7713b1edbc | 638 | #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) \ |
| AnnaBridge | 171:3a7713b1edbc | 639 | ((_SAMPLETIME_) << (ADC_SMPR1_SMP11_Pos * ((_CHANNELNB_) - 10))) |
| AnnaBridge | 171:3a7713b1edbc | 640 | |
| AnnaBridge | 171:3a7713b1edbc | 641 | /** |
| AnnaBridge | 171:3a7713b1edbc | 642 | * @brief Set the ADC's sample time for channel numbers between 0 and 9. |
| AnnaBridge | 171:3a7713b1edbc | 643 | * @param _SAMPLETIME_: Sample time parameter. |
| AnnaBridge | 171:3a7713b1edbc | 644 | * @param _CHANNELNB_: Channel number. |
| AnnaBridge | 171:3a7713b1edbc | 645 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 646 | */ |
| AnnaBridge | 171:3a7713b1edbc | 647 | #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) \ |
| AnnaBridge | 171:3a7713b1edbc | 648 | ((_SAMPLETIME_) << (ADC_SMPR2_SMP1_Pos * (_CHANNELNB_))) |
| AnnaBridge | 171:3a7713b1edbc | 649 | |
| AnnaBridge | 171:3a7713b1edbc | 650 | /** |
| AnnaBridge | 171:3a7713b1edbc | 651 | * @brief Set the selected regular channel rank for rank between 1 and 6. |
| AnnaBridge | 171:3a7713b1edbc | 652 | * @param _CHANNELNB_: Channel number. |
| AnnaBridge | 171:3a7713b1edbc | 653 | * @param _RANKNB_: Rank number. |
| AnnaBridge | 171:3a7713b1edbc | 654 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 655 | */ |
| AnnaBridge | 171:3a7713b1edbc | 656 | #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) \ |
| AnnaBridge | 171:3a7713b1edbc | 657 | ((_CHANNELNB_) << (ADC_SQR3_SQ2_Pos * ((_RANKNB_) - 1))) |
| AnnaBridge | 171:3a7713b1edbc | 658 | |
| AnnaBridge | 171:3a7713b1edbc | 659 | /** |
| AnnaBridge | 171:3a7713b1edbc | 660 | * @brief Set the selected regular channel rank for rank between 7 and 12. |
| AnnaBridge | 171:3a7713b1edbc | 661 | * @param _CHANNELNB_: Channel number. |
| AnnaBridge | 171:3a7713b1edbc | 662 | * @param _RANKNB_: Rank number. |
| AnnaBridge | 171:3a7713b1edbc | 663 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 664 | */ |
| AnnaBridge | 171:3a7713b1edbc | 665 | #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) \ |
| AnnaBridge | 171:3a7713b1edbc | 666 | ((_CHANNELNB_) << (ADC_SQR2_SQ8_Pos * ((_RANKNB_) - 7))) |
| AnnaBridge | 171:3a7713b1edbc | 667 | |
| AnnaBridge | 171:3a7713b1edbc | 668 | /** |
| AnnaBridge | 171:3a7713b1edbc | 669 | * @brief Set the selected regular channel rank for rank between 13 and 16. |
| AnnaBridge | 171:3a7713b1edbc | 670 | * @param _CHANNELNB_: Channel number. |
| AnnaBridge | 171:3a7713b1edbc | 671 | * @param _RANKNB_: Rank number. |
| AnnaBridge | 171:3a7713b1edbc | 672 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 673 | */ |
| AnnaBridge | 171:3a7713b1edbc | 674 | #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) \ |
| AnnaBridge | 171:3a7713b1edbc | 675 | ((_CHANNELNB_) << (ADC_SQR1_SQ14_Pos * ((_RANKNB_) - 13))) |
| AnnaBridge | 171:3a7713b1edbc | 676 | |
| AnnaBridge | 171:3a7713b1edbc | 677 | /** |
| AnnaBridge | 171:3a7713b1edbc | 678 | * @brief Set the injected sequence length. |
| AnnaBridge | 171:3a7713b1edbc | 679 | * @param _JSQR_JL_: Sequence length. |
| AnnaBridge | 171:3a7713b1edbc | 680 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 681 | */ |
| AnnaBridge | 171:3a7713b1edbc | 682 | #define ADC_JSQR_JL_SHIFT(_JSQR_JL_) \ |
| AnnaBridge | 171:3a7713b1edbc | 683 | (((_JSQR_JL_) -1) << ADC_JSQR_JL_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 684 | |
| AnnaBridge | 171:3a7713b1edbc | 685 | /** |
| AnnaBridge | 171:3a7713b1edbc | 686 | * @brief Set the selected injected channel rank |
| AnnaBridge | 171:3a7713b1edbc | 687 | * Note: on STM32F1 devices, channel rank position in JSQR register |
| AnnaBridge | 171:3a7713b1edbc | 688 | * is depending on total number of ranks selected into |
| AnnaBridge | 171:3a7713b1edbc | 689 | * injected sequencer (ranks sequence starting from 4-JL) |
| AnnaBridge | 171:3a7713b1edbc | 690 | * @param _CHANNELNB_: Channel number. |
| AnnaBridge | 171:3a7713b1edbc | 691 | * @param _RANKNB_: Rank number. |
| AnnaBridge | 171:3a7713b1edbc | 692 | * @param _JSQR_JL_: Sequence length. |
| AnnaBridge | 171:3a7713b1edbc | 693 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 694 | */ |
| AnnaBridge | 171:3a7713b1edbc | 695 | #define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) \ |
| AnnaBridge | 171:3a7713b1edbc | 696 | ((_CHANNELNB_) << (ADC_JSQR_JSQ2_Pos * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1))) |
| AnnaBridge | 171:3a7713b1edbc | 697 | |
| AnnaBridge | 171:3a7713b1edbc | 698 | /** |
| AnnaBridge | 171:3a7713b1edbc | 699 | * @brief Enable ADC continuous conversion mode. |
| AnnaBridge | 171:3a7713b1edbc | 700 | * @param _CONTINUOUS_MODE_: Continuous mode. |
| AnnaBridge | 171:3a7713b1edbc | 701 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 702 | */ |
| AnnaBridge | 171:3a7713b1edbc | 703 | #define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) \ |
| AnnaBridge | 171:3a7713b1edbc | 704 | ((_CONTINUOUS_MODE_) << ADC_CR2_CONT_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 705 | |
| AnnaBridge | 171:3a7713b1edbc | 706 | /** |
| AnnaBridge | 171:3a7713b1edbc | 707 | * @brief Configures the number of discontinuous conversions for the regular group channels. |
| AnnaBridge | 171:3a7713b1edbc | 708 | * @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions. |
| AnnaBridge | 171:3a7713b1edbc | 709 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 710 | */ |
| AnnaBridge | 171:3a7713b1edbc | 711 | #define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) \ |
| AnnaBridge | 171:3a7713b1edbc | 712 | (((_NBR_DISCONTINUOUS_CONV_) - 1) << ADC_CR1_DISCNUM_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 713 | |
| AnnaBridge | 171:3a7713b1edbc | 714 | /** |
| AnnaBridge | 171:3a7713b1edbc | 715 | * @brief Enable ADC scan mode to convert multiple ranks with sequencer. |
| AnnaBridge | 171:3a7713b1edbc | 716 | * @param _SCAN_MODE_: Scan conversion mode. |
| AnnaBridge | 171:3a7713b1edbc | 717 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 718 | */ |
| AnnaBridge | 171:3a7713b1edbc | 719 | /* Note: Scan mode is compared to ENABLE for legacy purpose, this parameter */ |
| AnnaBridge | 171:3a7713b1edbc | 720 | /* is equivalent to ADC_SCAN_ENABLE. */ |
| AnnaBridge | 171:3a7713b1edbc | 721 | #define ADC_CR1_SCAN_SET(_SCAN_MODE_) \ |
| AnnaBridge | 171:3a7713b1edbc | 722 | (( ((_SCAN_MODE_) == ADC_SCAN_ENABLE) || ((_SCAN_MODE_) == ENABLE) \ |
| AnnaBridge | 171:3a7713b1edbc | 723 | )? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE) \ |
| AnnaBridge | 171:3a7713b1edbc | 724 | ) |
| AnnaBridge | 171:3a7713b1edbc | 725 | |
| AnnaBridge | 171:3a7713b1edbc | 726 | /** |
| AnnaBridge | 171:3a7713b1edbc | 727 | * @brief Get the maximum ADC conversion cycles on all channels. |
| AnnaBridge | 171:3a7713b1edbc | 728 | * Returns the selected sampling time + conversion time (12.5 ADC clock cycles) |
| AnnaBridge | 171:3a7713b1edbc | 729 | * Approximation of sampling time within 4 ranges, returns the highest value: |
| AnnaBridge | 171:3a7713b1edbc | 730 | * below 7.5 cycles {1.5 cycle; 7.5 cycles}, |
| AnnaBridge | 171:3a7713b1edbc | 731 | * between 13.5 cycles and 28.5 cycles {13.5 cycles; 28.5 cycles} |
| AnnaBridge | 171:3a7713b1edbc | 732 | * between 41.5 cycles and 71.5 cycles {41.5 cycles; 55.5 cycles; 71.5cycles} |
| AnnaBridge | 171:3a7713b1edbc | 733 | * equal to 239.5 cycles |
| AnnaBridge | 171:3a7713b1edbc | 734 | * Unit: ADC clock cycles |
| AnnaBridge | 171:3a7713b1edbc | 735 | * @param __HANDLE__: ADC handle |
| AnnaBridge | 171:3a7713b1edbc | 736 | * @retval ADC conversion cycles on all channels |
| AnnaBridge | 171:3a7713b1edbc | 737 | */ |
| AnnaBridge | 171:3a7713b1edbc | 738 | #define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \ |
| AnnaBridge | 171:3a7713b1edbc | 739 | (( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && \ |
| AnnaBridge | 171:3a7713b1edbc | 740 | (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) ) ? \ |
| AnnaBridge | 171:3a7713b1edbc | 741 | \ |
| AnnaBridge | 171:3a7713b1edbc | 742 | (( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \ |
| AnnaBridge | 171:3a7713b1edbc | 743 | (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET) ) ? \ |
| AnnaBridge | 171:3a7713b1edbc | 744 | ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5) \ |
| AnnaBridge | 171:3a7713b1edbc | 745 | : \ |
| AnnaBridge | 171:3a7713b1edbc | 746 | ((((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \ |
| AnnaBridge | 171:3a7713b1edbc | 747 | (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET)) || \ |
| AnnaBridge | 171:3a7713b1edbc | 748 | ((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET) && \ |
| AnnaBridge | 171:3a7713b1edbc | 749 | (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET))) ? \ |
| AnnaBridge | 171:3a7713b1edbc | 750 | ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5) \ |
| AnnaBridge | 171:3a7713b1edbc | 751 | ) |
| AnnaBridge | 171:3a7713b1edbc | 752 | |
| AnnaBridge | 171:3a7713b1edbc | 753 | #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ |
| AnnaBridge | 171:3a7713b1edbc | 754 | ((ALIGN) == ADC_DATAALIGN_LEFT) ) |
| AnnaBridge | 171:3a7713b1edbc | 755 | |
| AnnaBridge | 171:3a7713b1edbc | 756 | #define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \ |
| AnnaBridge | 171:3a7713b1edbc | 757 | ((SCAN_MODE) == ADC_SCAN_ENABLE) ) |
| AnnaBridge | 171:3a7713b1edbc | 758 | |
| AnnaBridge | 171:3a7713b1edbc | 759 | #define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ |
| AnnaBridge | 171:3a7713b1edbc | 760 | ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) ) |
| AnnaBridge | 171:3a7713b1edbc | 761 | |
| AnnaBridge | 171:3a7713b1edbc | 762 | #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ |
| AnnaBridge | 171:3a7713b1edbc | 763 | ((CHANNEL) == ADC_CHANNEL_1) || \ |
| AnnaBridge | 171:3a7713b1edbc | 764 | ((CHANNEL) == ADC_CHANNEL_2) || \ |
| AnnaBridge | 171:3a7713b1edbc | 765 | ((CHANNEL) == ADC_CHANNEL_3) || \ |
| AnnaBridge | 171:3a7713b1edbc | 766 | ((CHANNEL) == ADC_CHANNEL_4) || \ |
| AnnaBridge | 171:3a7713b1edbc | 767 | ((CHANNEL) == ADC_CHANNEL_5) || \ |
| AnnaBridge | 171:3a7713b1edbc | 768 | ((CHANNEL) == ADC_CHANNEL_6) || \ |
| AnnaBridge | 171:3a7713b1edbc | 769 | ((CHANNEL) == ADC_CHANNEL_7) || \ |
| AnnaBridge | 171:3a7713b1edbc | 770 | ((CHANNEL) == ADC_CHANNEL_8) || \ |
| AnnaBridge | 171:3a7713b1edbc | 771 | ((CHANNEL) == ADC_CHANNEL_9) || \ |
| AnnaBridge | 171:3a7713b1edbc | 772 | ((CHANNEL) == ADC_CHANNEL_10) || \ |
| AnnaBridge | 171:3a7713b1edbc | 773 | ((CHANNEL) == ADC_CHANNEL_11) || \ |
| AnnaBridge | 171:3a7713b1edbc | 774 | ((CHANNEL) == ADC_CHANNEL_12) || \ |
| AnnaBridge | 171:3a7713b1edbc | 775 | ((CHANNEL) == ADC_CHANNEL_13) || \ |
| AnnaBridge | 171:3a7713b1edbc | 776 | ((CHANNEL) == ADC_CHANNEL_14) || \ |
| AnnaBridge | 171:3a7713b1edbc | 777 | ((CHANNEL) == ADC_CHANNEL_15) || \ |
| AnnaBridge | 171:3a7713b1edbc | 778 | ((CHANNEL) == ADC_CHANNEL_16) || \ |
| AnnaBridge | 171:3a7713b1edbc | 779 | ((CHANNEL) == ADC_CHANNEL_17) ) |
| AnnaBridge | 171:3a7713b1edbc | 780 | |
| AnnaBridge | 171:3a7713b1edbc | 781 | #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \ |
| AnnaBridge | 171:3a7713b1edbc | 782 | ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \ |
| AnnaBridge | 171:3a7713b1edbc | 783 | ((TIME) == ADC_SAMPLETIME_13CYCLES_5) || \ |
| AnnaBridge | 171:3a7713b1edbc | 784 | ((TIME) == ADC_SAMPLETIME_28CYCLES_5) || \ |
| AnnaBridge | 171:3a7713b1edbc | 785 | ((TIME) == ADC_SAMPLETIME_41CYCLES_5) || \ |
| AnnaBridge | 171:3a7713b1edbc | 786 | ((TIME) == ADC_SAMPLETIME_55CYCLES_5) || \ |
| AnnaBridge | 171:3a7713b1edbc | 787 | ((TIME) == ADC_SAMPLETIME_71CYCLES_5) || \ |
| AnnaBridge | 171:3a7713b1edbc | 788 | ((TIME) == ADC_SAMPLETIME_239CYCLES_5) ) |
| AnnaBridge | 171:3a7713b1edbc | 789 | |
| AnnaBridge | 171:3a7713b1edbc | 790 | #define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \ |
| AnnaBridge | 171:3a7713b1edbc | 791 | ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \ |
| AnnaBridge | 171:3a7713b1edbc | 792 | ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \ |
| AnnaBridge | 171:3a7713b1edbc | 793 | ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \ |
| AnnaBridge | 171:3a7713b1edbc | 794 | ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \ |
| AnnaBridge | 171:3a7713b1edbc | 795 | ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \ |
| AnnaBridge | 171:3a7713b1edbc | 796 | ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \ |
| AnnaBridge | 171:3a7713b1edbc | 797 | ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \ |
| AnnaBridge | 171:3a7713b1edbc | 798 | ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \ |
| AnnaBridge | 171:3a7713b1edbc | 799 | ((CHANNEL) == ADC_REGULAR_RANK_10) || \ |
| AnnaBridge | 171:3a7713b1edbc | 800 | ((CHANNEL) == ADC_REGULAR_RANK_11) || \ |
| AnnaBridge | 171:3a7713b1edbc | 801 | ((CHANNEL) == ADC_REGULAR_RANK_12) || \ |
| AnnaBridge | 171:3a7713b1edbc | 802 | ((CHANNEL) == ADC_REGULAR_RANK_13) || \ |
| AnnaBridge | 171:3a7713b1edbc | 803 | ((CHANNEL) == ADC_REGULAR_RANK_14) || \ |
| AnnaBridge | 171:3a7713b1edbc | 804 | ((CHANNEL) == ADC_REGULAR_RANK_15) || \ |
| AnnaBridge | 171:3a7713b1edbc | 805 | ((CHANNEL) == ADC_REGULAR_RANK_16) ) |
| AnnaBridge | 171:3a7713b1edbc | 806 | |
| AnnaBridge | 171:3a7713b1edbc | 807 | #define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \ |
| AnnaBridge | 171:3a7713b1edbc | 808 | ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ |
| AnnaBridge | 171:3a7713b1edbc | 809 | ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ |
| AnnaBridge | 171:3a7713b1edbc | 810 | ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ |
| AnnaBridge | 171:3a7713b1edbc | 811 | ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \ |
| AnnaBridge | 171:3a7713b1edbc | 812 | ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ |
| AnnaBridge | 171:3a7713b1edbc | 813 | ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) |
| AnnaBridge | 171:3a7713b1edbc | 814 | |
| AnnaBridge | 171:3a7713b1edbc | 815 | #define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP) || \ |
| AnnaBridge | 171:3a7713b1edbc | 816 | ((CONVERSION) == ADC_INJECTED_GROUP) || \ |
| AnnaBridge | 171:3a7713b1edbc | 817 | ((CONVERSION) == ADC_REGULAR_INJECTED_GROUP) ) |
| AnnaBridge | 171:3a7713b1edbc | 818 | |
| AnnaBridge | 171:3a7713b1edbc | 819 | #define IS_ADC_EVENT_TYPE(EVENT) ((EVENT) == ADC_AWD_EVENT) |
| AnnaBridge | 171:3a7713b1edbc | 820 | |
| AnnaBridge | 171:3a7713b1edbc | 821 | |
| AnnaBridge | 171:3a7713b1edbc | 822 | /** @defgroup ADC_range_verification ADC range verification |
| AnnaBridge | 171:3a7713b1edbc | 823 | * For a unique ADC resolution: 12 bits |
| AnnaBridge | 171:3a7713b1edbc | 824 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 825 | */ |
| AnnaBridge | 171:3a7713b1edbc | 826 | #define IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= 0x0FFFU) |
| AnnaBridge | 171:3a7713b1edbc | 827 | /** |
| AnnaBridge | 171:3a7713b1edbc | 828 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 829 | */ |
| AnnaBridge | 171:3a7713b1edbc | 830 | |
| AnnaBridge | 171:3a7713b1edbc | 831 | /** @defgroup ADC_regular_nb_conv_verification ADC regular nb conv verification |
| AnnaBridge | 171:3a7713b1edbc | 832 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 833 | */ |
| AnnaBridge | 171:3a7713b1edbc | 834 | #define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 16U)) |
| AnnaBridge | 171:3a7713b1edbc | 835 | /** |
| AnnaBridge | 171:3a7713b1edbc | 836 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 837 | */ |
| AnnaBridge | 171:3a7713b1edbc | 838 | |
| AnnaBridge | 171:3a7713b1edbc | 839 | /** @defgroup ADC_regular_discontinuous_mode_number_verification ADC regular discontinuous mode number verification |
| AnnaBridge | 171:3a7713b1edbc | 840 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 841 | */ |
| AnnaBridge | 171:3a7713b1edbc | 842 | #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U)) |
| AnnaBridge | 171:3a7713b1edbc | 843 | /** |
| AnnaBridge | 171:3a7713b1edbc | 844 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 845 | */ |
| AnnaBridge | 171:3a7713b1edbc | 846 | |
| AnnaBridge | 171:3a7713b1edbc | 847 | /** |
| AnnaBridge | 171:3a7713b1edbc | 848 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 849 | */ |
| AnnaBridge | 171:3a7713b1edbc | 850 | |
| AnnaBridge | 171:3a7713b1edbc | 851 | /* Include ADC HAL Extension module */ |
| AnnaBridge | 171:3a7713b1edbc | 852 | #include "stm32f1xx_hal_adc_ex.h" |
| AnnaBridge | 171:3a7713b1edbc | 853 | |
| AnnaBridge | 171:3a7713b1edbc | 854 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 855 | /** @addtogroup ADC_Exported_Functions |
| AnnaBridge | 171:3a7713b1edbc | 856 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 857 | */ |
| AnnaBridge | 171:3a7713b1edbc | 858 | |
| AnnaBridge | 171:3a7713b1edbc | 859 | /** @addtogroup ADC_Exported_Functions_Group1 |
| AnnaBridge | 171:3a7713b1edbc | 860 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 861 | */ |
| AnnaBridge | 171:3a7713b1edbc | 862 | |
| AnnaBridge | 171:3a7713b1edbc | 863 | |
| AnnaBridge | 171:3a7713b1edbc | 864 | /* Initialization and de-initialization functions **********************************/ |
| AnnaBridge | 171:3a7713b1edbc | 865 | HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); |
| AnnaBridge | 171:3a7713b1edbc | 866 | HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); |
| AnnaBridge | 171:3a7713b1edbc | 867 | void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); |
| AnnaBridge | 171:3a7713b1edbc | 868 | void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); |
| AnnaBridge | 171:3a7713b1edbc | 869 | /** |
| AnnaBridge | 171:3a7713b1edbc | 870 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 871 | */ |
| AnnaBridge | 171:3a7713b1edbc | 872 | |
| AnnaBridge | 171:3a7713b1edbc | 873 | /* IO operation functions *****************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 874 | |
| AnnaBridge | 171:3a7713b1edbc | 875 | /** @addtogroup ADC_Exported_Functions_Group2 |
| AnnaBridge | 171:3a7713b1edbc | 876 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 877 | */ |
| AnnaBridge | 171:3a7713b1edbc | 878 | |
| AnnaBridge | 171:3a7713b1edbc | 879 | |
| AnnaBridge | 171:3a7713b1edbc | 880 | /* Blocking mode: Polling */ |
| AnnaBridge | 171:3a7713b1edbc | 881 | HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); |
| AnnaBridge | 171:3a7713b1edbc | 882 | HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); |
| AnnaBridge | 171:3a7713b1edbc | 883 | HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); |
| AnnaBridge | 171:3a7713b1edbc | 884 | HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout); |
| AnnaBridge | 171:3a7713b1edbc | 885 | |
| AnnaBridge | 171:3a7713b1edbc | 886 | /* Non-blocking mode: Interruption */ |
| AnnaBridge | 171:3a7713b1edbc | 887 | HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); |
| AnnaBridge | 171:3a7713b1edbc | 888 | HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); |
| AnnaBridge | 171:3a7713b1edbc | 889 | |
| AnnaBridge | 171:3a7713b1edbc | 890 | /* Non-blocking mode: DMA */ |
| AnnaBridge | 171:3a7713b1edbc | 891 | HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); |
| AnnaBridge | 171:3a7713b1edbc | 892 | HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); |
| AnnaBridge | 171:3a7713b1edbc | 893 | |
| AnnaBridge | 171:3a7713b1edbc | 894 | /* ADC retrieve conversion value intended to be used with polling or interruption */ |
| AnnaBridge | 171:3a7713b1edbc | 895 | uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc); |
| AnnaBridge | 171:3a7713b1edbc | 896 | |
| AnnaBridge | 171:3a7713b1edbc | 897 | /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ |
| AnnaBridge | 171:3a7713b1edbc | 898 | void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc); |
| AnnaBridge | 171:3a7713b1edbc | 899 | void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc); |
| AnnaBridge | 171:3a7713b1edbc | 900 | void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc); |
| AnnaBridge | 171:3a7713b1edbc | 901 | void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc); |
| AnnaBridge | 171:3a7713b1edbc | 902 | void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); |
| AnnaBridge | 171:3a7713b1edbc | 903 | /** |
| AnnaBridge | 171:3a7713b1edbc | 904 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 905 | */ |
| AnnaBridge | 171:3a7713b1edbc | 906 | |
| AnnaBridge | 171:3a7713b1edbc | 907 | |
| AnnaBridge | 171:3a7713b1edbc | 908 | /* Peripheral Control functions ***********************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 909 | /** @addtogroup ADC_Exported_Functions_Group3 |
| AnnaBridge | 171:3a7713b1edbc | 910 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 911 | */ |
| AnnaBridge | 171:3a7713b1edbc | 912 | HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); |
| AnnaBridge | 171:3a7713b1edbc | 913 | HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); |
| AnnaBridge | 171:3a7713b1edbc | 914 | /** |
| AnnaBridge | 171:3a7713b1edbc | 915 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 916 | */ |
| AnnaBridge | 171:3a7713b1edbc | 917 | |
| AnnaBridge | 171:3a7713b1edbc | 918 | |
| AnnaBridge | 171:3a7713b1edbc | 919 | /* Peripheral State functions *************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 920 | /** @addtogroup ADC_Exported_Functions_Group4 |
| AnnaBridge | 171:3a7713b1edbc | 921 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 922 | */ |
| AnnaBridge | 171:3a7713b1edbc | 923 | uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc); |
| AnnaBridge | 171:3a7713b1edbc | 924 | uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); |
| AnnaBridge | 171:3a7713b1edbc | 925 | /** |
| AnnaBridge | 171:3a7713b1edbc | 926 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 927 | */ |
| AnnaBridge | 171:3a7713b1edbc | 928 | |
| AnnaBridge | 171:3a7713b1edbc | 929 | |
| AnnaBridge | 171:3a7713b1edbc | 930 | /** |
| AnnaBridge | 171:3a7713b1edbc | 931 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 932 | */ |
| AnnaBridge | 171:3a7713b1edbc | 933 | |
| AnnaBridge | 171:3a7713b1edbc | 934 | |
| AnnaBridge | 171:3a7713b1edbc | 935 | /* Internal HAL driver functions **********************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 936 | /** @addtogroup ADC_Private_Functions |
| AnnaBridge | 171:3a7713b1edbc | 937 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 938 | */ |
| AnnaBridge | 171:3a7713b1edbc | 939 | HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc); |
| AnnaBridge | 171:3a7713b1edbc | 940 | HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc); |
| AnnaBridge | 171:3a7713b1edbc | 941 | void ADC_StabilizationTime(uint32_t DelayUs); |
| AnnaBridge | 171:3a7713b1edbc | 942 | void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); |
| AnnaBridge | 171:3a7713b1edbc | 943 | void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); |
| AnnaBridge | 171:3a7713b1edbc | 944 | void ADC_DMAError(DMA_HandleTypeDef *hdma); |
| AnnaBridge | 171:3a7713b1edbc | 945 | /** |
| AnnaBridge | 171:3a7713b1edbc | 946 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 947 | */ |
| AnnaBridge | 171:3a7713b1edbc | 948 | |
| AnnaBridge | 171:3a7713b1edbc | 949 | |
| AnnaBridge | 171:3a7713b1edbc | 950 | /** |
| AnnaBridge | 171:3a7713b1edbc | 951 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 952 | */ |
| AnnaBridge | 171:3a7713b1edbc | 953 | |
| AnnaBridge | 171:3a7713b1edbc | 954 | /** |
| AnnaBridge | 171:3a7713b1edbc | 955 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 956 | */ |
| AnnaBridge | 171:3a7713b1edbc | 957 | |
| AnnaBridge | 171:3a7713b1edbc | 958 | #ifdef __cplusplus |
| AnnaBridge | 171:3a7713b1edbc | 959 | } |
| AnnaBridge | 171:3a7713b1edbc | 960 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 961 | |
| AnnaBridge | 171:3a7713b1edbc | 962 | |
| AnnaBridge | 171:3a7713b1edbc | 963 | #endif /* __STM32F1xx_HAL_ADC_H */ |
| AnnaBridge | 171:3a7713b1edbc | 964 | |
| AnnaBridge | 171:3a7713b1edbc | 965 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
