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TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/stm32f1xx_ll_system.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 171:3a7713b1edbc | 1 | /** |
| AnnaBridge | 171:3a7713b1edbc | 2 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 3 | * @file stm32f1xx_ll_system.h |
| AnnaBridge | 171:3a7713b1edbc | 4 | * @author MCD Application Team |
| AnnaBridge | 171:3a7713b1edbc | 5 | * @brief Header file of SYSTEM LL module. |
| AnnaBridge | 171:3a7713b1edbc | 6 | @verbatim |
| AnnaBridge | 171:3a7713b1edbc | 7 | ============================================================================== |
| AnnaBridge | 171:3a7713b1edbc | 8 | ##### How to use this driver ##### |
| AnnaBridge | 171:3a7713b1edbc | 9 | ============================================================================== |
| AnnaBridge | 171:3a7713b1edbc | 10 | [..] |
| AnnaBridge | 171:3a7713b1edbc | 11 | The LL SYSTEM driver contains a set of generic APIs that can be |
| AnnaBridge | 171:3a7713b1edbc | 12 | used by user: |
| AnnaBridge | 171:3a7713b1edbc | 13 | (+) Some of the FLASH features need to be handled in the SYSTEM file. |
| AnnaBridge | 171:3a7713b1edbc | 14 | (+) Access to DBGCMU registers |
| AnnaBridge | 171:3a7713b1edbc | 15 | (+) Access to SYSCFG registers |
| AnnaBridge | 171:3a7713b1edbc | 16 | |
| AnnaBridge | 171:3a7713b1edbc | 17 | @endverbatim |
| AnnaBridge | 171:3a7713b1edbc | 18 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 19 | * @attention |
| AnnaBridge | 171:3a7713b1edbc | 20 | * |
| AnnaBridge | 171:3a7713b1edbc | 21 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| AnnaBridge | 171:3a7713b1edbc | 22 | * |
| AnnaBridge | 171:3a7713b1edbc | 23 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 171:3a7713b1edbc | 24 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 171:3a7713b1edbc | 25 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 26 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 171:3a7713b1edbc | 27 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 28 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 171:3a7713b1edbc | 29 | * and/or other materials provided with the distribution. |
| AnnaBridge | 171:3a7713b1edbc | 30 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 171:3a7713b1edbc | 31 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 171:3a7713b1edbc | 32 | * without specific prior written permission. |
| AnnaBridge | 171:3a7713b1edbc | 33 | * |
| AnnaBridge | 171:3a7713b1edbc | 34 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 171:3a7713b1edbc | 35 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 171:3a7713b1edbc | 36 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 171:3a7713b1edbc | 37 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 171:3a7713b1edbc | 38 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 171:3a7713b1edbc | 39 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 171:3a7713b1edbc | 40 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 171:3a7713b1edbc | 41 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 171:3a7713b1edbc | 42 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 171:3a7713b1edbc | 43 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 171:3a7713b1edbc | 44 | * |
| AnnaBridge | 171:3a7713b1edbc | 45 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 46 | */ |
| AnnaBridge | 171:3a7713b1edbc | 47 | |
| AnnaBridge | 171:3a7713b1edbc | 48 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 49 | #ifndef __STM32F1xx_LL_SYSTEM_H |
| AnnaBridge | 171:3a7713b1edbc | 50 | #define __STM32F1xx_LL_SYSTEM_H |
| AnnaBridge | 171:3a7713b1edbc | 51 | |
| AnnaBridge | 171:3a7713b1edbc | 52 | #ifdef __cplusplus |
| AnnaBridge | 171:3a7713b1edbc | 53 | extern "C" { |
| AnnaBridge | 171:3a7713b1edbc | 54 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 55 | |
| AnnaBridge | 171:3a7713b1edbc | 56 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 57 | #include "stm32f1xx.h" |
| AnnaBridge | 171:3a7713b1edbc | 58 | |
| AnnaBridge | 171:3a7713b1edbc | 59 | /** @addtogroup STM32F1xx_LL_Driver |
| AnnaBridge | 171:3a7713b1edbc | 60 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 61 | */ |
| AnnaBridge | 171:3a7713b1edbc | 62 | |
| AnnaBridge | 171:3a7713b1edbc | 63 | #if defined (FLASH) || defined (DBGMCU) |
| AnnaBridge | 171:3a7713b1edbc | 64 | |
| AnnaBridge | 171:3a7713b1edbc | 65 | /** @defgroup SYSTEM_LL SYSTEM |
| AnnaBridge | 171:3a7713b1edbc | 66 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 67 | */ |
| AnnaBridge | 171:3a7713b1edbc | 68 | |
| AnnaBridge | 171:3a7713b1edbc | 69 | /* Private types -------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 70 | /* Private variables ---------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 71 | |
| AnnaBridge | 171:3a7713b1edbc | 72 | /* Private constants ---------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 73 | /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants |
| AnnaBridge | 171:3a7713b1edbc | 74 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 75 | */ |
| AnnaBridge | 171:3a7713b1edbc | 76 | |
| AnnaBridge | 171:3a7713b1edbc | 77 | /** |
| AnnaBridge | 171:3a7713b1edbc | 78 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 79 | */ |
| AnnaBridge | 171:3a7713b1edbc | 80 | |
| AnnaBridge | 171:3a7713b1edbc | 81 | /* Private macros ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 82 | |
| AnnaBridge | 171:3a7713b1edbc | 83 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 84 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 85 | /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants |
| AnnaBridge | 171:3a7713b1edbc | 86 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 87 | */ |
| AnnaBridge | 171:3a7713b1edbc | 88 | |
| AnnaBridge | 171:3a7713b1edbc | 89 | |
| AnnaBridge | 171:3a7713b1edbc | 90 | |
| AnnaBridge | 171:3a7713b1edbc | 91 | /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment |
| AnnaBridge | 171:3a7713b1edbc | 92 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 93 | */ |
| AnnaBridge | 171:3a7713b1edbc | 94 | #define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */ |
| AnnaBridge | 171:3a7713b1edbc | 95 | #define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */ |
| AnnaBridge | 171:3a7713b1edbc | 96 | #define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */ |
| AnnaBridge | 171:3a7713b1edbc | 97 | #define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */ |
| AnnaBridge | 171:3a7713b1edbc | 98 | #define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */ |
| AnnaBridge | 171:3a7713b1edbc | 99 | /** |
| AnnaBridge | 171:3a7713b1edbc | 100 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 101 | */ |
| AnnaBridge | 171:3a7713b1edbc | 102 | |
| AnnaBridge | 171:3a7713b1edbc | 103 | /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP |
| AnnaBridge | 171:3a7713b1edbc | 104 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 105 | */ |
| AnnaBridge | 171:3a7713b1edbc | 106 | #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */ |
| AnnaBridge | 171:3a7713b1edbc | 107 | #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */ |
| AnnaBridge | 171:3a7713b1edbc | 108 | #define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP /*!< TIM4 counter stopped when core is halted */ |
| AnnaBridge | 171:3a7713b1edbc | 109 | #if defined(DBGMCU_CR_DBG_TIM5_STOP) |
| AnnaBridge | 171:3a7713b1edbc | 110 | #define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_CR_DBG_TIM5_STOP /*!< TIM5 counter stopped when core is halted */ |
| AnnaBridge | 171:3a7713b1edbc | 111 | #endif /* DBGMCU_CR_DBG_TIM5_STOP */ |
| AnnaBridge | 171:3a7713b1edbc | 112 | #if defined(DBGMCU_CR_DBG_TIM6_STOP) |
| AnnaBridge | 171:3a7713b1edbc | 113 | #define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_CR_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */ |
| AnnaBridge | 171:3a7713b1edbc | 114 | #endif /* DBGMCU_CR_DBG_TIM6_STOP */ |
| AnnaBridge | 171:3a7713b1edbc | 115 | #if defined(DBGMCU_CR_DBG_TIM7_STOP) |
| AnnaBridge | 171:3a7713b1edbc | 116 | #define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_CR_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */ |
| AnnaBridge | 171:3a7713b1edbc | 117 | #endif /* DBGMCU_CR_DBG_TIM7_STOP */ |
| AnnaBridge | 171:3a7713b1edbc | 118 | #if defined(DBGMCU_CR_DBG_TIM12_STOP) |
| AnnaBridge | 171:3a7713b1edbc | 119 | #define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_CR_DBG_TIM12_STOP /*!< TIM12 counter stopped when core is halted */ |
| AnnaBridge | 171:3a7713b1edbc | 120 | #endif /* DBGMCU_CR_DBG_TIM12_STOP */ |
| AnnaBridge | 171:3a7713b1edbc | 121 | #if defined(DBGMCU_CR_DBG_TIM13_STOP) |
| AnnaBridge | 171:3a7713b1edbc | 122 | #define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_CR_DBG_TIM13_STOP /*!< TIM13 counter stopped when core is halted */ |
| AnnaBridge | 171:3a7713b1edbc | 123 | #endif /* DBGMCU_CR_DBG_TIM13_STOP */ |
| AnnaBridge | 171:3a7713b1edbc | 124 | #if defined(DBGMCU_CR_DBG_TIM14_STOP) |
| AnnaBridge | 171:3a7713b1edbc | 125 | #define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_CR_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */ |
| AnnaBridge | 171:3a7713b1edbc | 126 | #endif /* DBGMCU_CR_DBG_TIM14_STOP */ |
| AnnaBridge | 171:3a7713b1edbc | 127 | #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */ |
| AnnaBridge | 171:3a7713b1edbc | 128 | #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */ |
| AnnaBridge | 171:3a7713b1edbc | 129 | #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ |
| AnnaBridge | 171:3a7713b1edbc | 130 | #if defined(DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) |
| AnnaBridge | 171:3a7713b1edbc | 131 | #define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */ |
| AnnaBridge | 171:3a7713b1edbc | 132 | #endif /* DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT */ |
| AnnaBridge | 171:3a7713b1edbc | 133 | #if defined(DBGMCU_CR_DBG_CAN1_STOP) |
| AnnaBridge | 171:3a7713b1edbc | 134 | #define LL_DBGMCU_APB1_GRP1_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP /*!< CAN1 debug stopped when Core is halted */ |
| AnnaBridge | 171:3a7713b1edbc | 135 | #endif /* DBGMCU_CR_DBG_CAN1_STOP */ |
| AnnaBridge | 171:3a7713b1edbc | 136 | #if defined(DBGMCU_CR_DBG_CAN2_STOP) |
| AnnaBridge | 171:3a7713b1edbc | 137 | #define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_CR_DBG_CAN2_STOP /*!< CAN2 debug stopped when Core is halted */ |
| AnnaBridge | 171:3a7713b1edbc | 138 | #endif /* DBGMCU_CR_DBG_CAN2_STOP */ |
| AnnaBridge | 171:3a7713b1edbc | 139 | /** |
| AnnaBridge | 171:3a7713b1edbc | 140 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 141 | */ |
| AnnaBridge | 171:3a7713b1edbc | 142 | |
| AnnaBridge | 171:3a7713b1edbc | 143 | /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP |
| AnnaBridge | 171:3a7713b1edbc | 144 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 145 | */ |
| AnnaBridge | 171:3a7713b1edbc | 146 | #define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */ |
| AnnaBridge | 171:3a7713b1edbc | 147 | #if defined(DBGMCU_CR_DBG_TIM8_STOP) |
| AnnaBridge | 171:3a7713b1edbc | 148 | #define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_CR_DBG_TIM8_STOP /*!< TIM8 counter stopped when core is halted */ |
| AnnaBridge | 171:3a7713b1edbc | 149 | #endif /* DBGMCU_CR_DBG_CAN1_STOP */ |
| AnnaBridge | 171:3a7713b1edbc | 150 | #if defined(DBGMCU_CR_DBG_TIM9_STOP) |
| AnnaBridge | 171:3a7713b1edbc | 151 | #define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_CR_DBG_TIM9_STOP /*!< TIM9 counter stopped when core is halted */ |
| AnnaBridge | 171:3a7713b1edbc | 152 | #endif /* DBGMCU_CR_DBG_TIM9_STOP */ |
| AnnaBridge | 171:3a7713b1edbc | 153 | #if defined(DBGMCU_CR_DBG_TIM10_STOP) |
| AnnaBridge | 171:3a7713b1edbc | 154 | #define LL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_CR_DBG_TIM10_STOP /*!< TIM10 counter stopped when core is halted */ |
| AnnaBridge | 171:3a7713b1edbc | 155 | #endif /* DBGMCU_CR_DBG_TIM10_STOP */ |
| AnnaBridge | 171:3a7713b1edbc | 156 | #if defined(DBGMCU_CR_DBG_TIM11_STOP) |
| AnnaBridge | 171:3a7713b1edbc | 157 | #define LL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_CR_DBG_TIM11_STOP /*!< TIM11 counter stopped when core is halted */ |
| AnnaBridge | 171:3a7713b1edbc | 158 | #endif /* DBGMCU_CR_DBG_TIM11_STOP */ |
| AnnaBridge | 171:3a7713b1edbc | 159 | #if defined(DBGMCU_CR_DBG_TIM15_STOP) |
| AnnaBridge | 171:3a7713b1edbc | 160 | #define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_CR_DBG_TIM15_STOP /*!< TIM15 counter stopped when core is halted */ |
| AnnaBridge | 171:3a7713b1edbc | 161 | #endif /* DBGMCU_CR_DBG_TIM15_STOP */ |
| AnnaBridge | 171:3a7713b1edbc | 162 | #if defined(DBGMCU_CR_DBG_TIM16_STOP) |
| AnnaBridge | 171:3a7713b1edbc | 163 | #define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_CR_DBG_TIM16_STOP /*!< TIM16 counter stopped when core is halted */ |
| AnnaBridge | 171:3a7713b1edbc | 164 | #endif /* DBGMCU_CR_DBG_TIM16_STOP */ |
| AnnaBridge | 171:3a7713b1edbc | 165 | #if defined(DBGMCU_CR_DBG_TIM17_STOP) |
| AnnaBridge | 171:3a7713b1edbc | 166 | #define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_CR_DBG_TIM17_STOP /*!< TIM17 counter stopped when core is halted */ |
| AnnaBridge | 171:3a7713b1edbc | 167 | #endif /* DBGMCU_CR_DBG_TIM17_STOP */ |
| AnnaBridge | 171:3a7713b1edbc | 168 | /** |
| AnnaBridge | 171:3a7713b1edbc | 169 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 170 | */ |
| AnnaBridge | 171:3a7713b1edbc | 171 | |
| AnnaBridge | 171:3a7713b1edbc | 172 | /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY |
| AnnaBridge | 171:3a7713b1edbc | 173 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 174 | */ |
| AnnaBridge | 171:3a7713b1edbc | 175 | #if defined(FLASH_ACR_LATENCY) |
| AnnaBridge | 171:3a7713b1edbc | 176 | #define LL_FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */ |
| AnnaBridge | 171:3a7713b1edbc | 177 | #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */ |
| AnnaBridge | 171:3a7713b1edbc | 178 | #define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two wait states */ |
| AnnaBridge | 171:3a7713b1edbc | 179 | #else |
| AnnaBridge | 171:3a7713b1edbc | 180 | #endif /* FLASH_ACR_LATENCY */ |
| AnnaBridge | 171:3a7713b1edbc | 181 | /** |
| AnnaBridge | 171:3a7713b1edbc | 182 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 183 | */ |
| AnnaBridge | 171:3a7713b1edbc | 184 | |
| AnnaBridge | 171:3a7713b1edbc | 185 | /** |
| AnnaBridge | 171:3a7713b1edbc | 186 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 187 | */ |
| AnnaBridge | 171:3a7713b1edbc | 188 | |
| AnnaBridge | 171:3a7713b1edbc | 189 | /* Exported macro ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 190 | |
| AnnaBridge | 171:3a7713b1edbc | 191 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 192 | /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions |
| AnnaBridge | 171:3a7713b1edbc | 193 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 194 | */ |
| AnnaBridge | 171:3a7713b1edbc | 195 | |
| AnnaBridge | 171:3a7713b1edbc | 196 | |
| AnnaBridge | 171:3a7713b1edbc | 197 | |
| AnnaBridge | 171:3a7713b1edbc | 198 | /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU |
| AnnaBridge | 171:3a7713b1edbc | 199 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 200 | */ |
| AnnaBridge | 171:3a7713b1edbc | 201 | |
| AnnaBridge | 171:3a7713b1edbc | 202 | /** |
| AnnaBridge | 171:3a7713b1edbc | 203 | * @brief Return the device identifier |
| AnnaBridge | 171:3a7713b1edbc | 204 | * @note For Low Density devices, the device ID is 0x412 |
| AnnaBridge | 171:3a7713b1edbc | 205 | * @note For Medium Density devices, the device ID is 0x410 |
| AnnaBridge | 171:3a7713b1edbc | 206 | * @note For High Density devices, the device ID is 0x414 |
| AnnaBridge | 171:3a7713b1edbc | 207 | * @note For XL Density devices, the device ID is 0x430 |
| AnnaBridge | 171:3a7713b1edbc | 208 | * @note For Connectivity Line devices, the device ID is 0x418 |
| AnnaBridge | 171:3a7713b1edbc | 209 | * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID |
| AnnaBridge | 171:3a7713b1edbc | 210 | * @retval Values between Min_Data=0x00 and Max_Data=0xFFF |
| AnnaBridge | 171:3a7713b1edbc | 211 | */ |
| AnnaBridge | 171:3a7713b1edbc | 212 | __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) |
| AnnaBridge | 171:3a7713b1edbc | 213 | { |
| AnnaBridge | 171:3a7713b1edbc | 214 | return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); |
| AnnaBridge | 171:3a7713b1edbc | 215 | } |
| AnnaBridge | 171:3a7713b1edbc | 216 | |
| AnnaBridge | 171:3a7713b1edbc | 217 | /** |
| AnnaBridge | 171:3a7713b1edbc | 218 | * @brief Return the device revision identifier |
| AnnaBridge | 171:3a7713b1edbc | 219 | * @note This field indicates the revision of the device. |
| AnnaBridge | 171:3a7713b1edbc | 220 | For example, it is read as revA -> 0x1000,for Low Density devices |
| AnnaBridge | 171:3a7713b1edbc | 221 | For example, it is read as revA -> 0x0000, revB -> 0x2000, revZ -> 0x2001, rev1,2,3,X or Y -> 0x2003,for Medium Density devices |
| AnnaBridge | 171:3a7713b1edbc | 222 | For example, it is read as revA or 1 -> 0x1000, revZ -> 0x1001,rev1,2,3,X or Y -> 0x1003,for Medium Density devices |
| AnnaBridge | 171:3a7713b1edbc | 223 | For example, it is read as revA or 1 -> 0x1003,for XL Density devices |
| AnnaBridge | 171:3a7713b1edbc | 224 | For example, it is read as revA -> 0x1000, revZ -> 0x1001 for Connectivity line devices |
| AnnaBridge | 171:3a7713b1edbc | 225 | * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID |
| AnnaBridge | 171:3a7713b1edbc | 226 | * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF |
| AnnaBridge | 171:3a7713b1edbc | 227 | */ |
| AnnaBridge | 171:3a7713b1edbc | 228 | __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) |
| AnnaBridge | 171:3a7713b1edbc | 229 | { |
| AnnaBridge | 171:3a7713b1edbc | 230 | return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); |
| AnnaBridge | 171:3a7713b1edbc | 231 | } |
| AnnaBridge | 171:3a7713b1edbc | 232 | |
| AnnaBridge | 171:3a7713b1edbc | 233 | /** |
| AnnaBridge | 171:3a7713b1edbc | 234 | * @brief Enable the Debug Module during SLEEP mode |
| AnnaBridge | 171:3a7713b1edbc | 235 | * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode |
| AnnaBridge | 171:3a7713b1edbc | 236 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 237 | */ |
| AnnaBridge | 171:3a7713b1edbc | 238 | __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void) |
| AnnaBridge | 171:3a7713b1edbc | 239 | { |
| AnnaBridge | 171:3a7713b1edbc | 240 | SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); |
| AnnaBridge | 171:3a7713b1edbc | 241 | } |
| AnnaBridge | 171:3a7713b1edbc | 242 | |
| AnnaBridge | 171:3a7713b1edbc | 243 | /** |
| AnnaBridge | 171:3a7713b1edbc | 244 | * @brief Disable the Debug Module during SLEEP mode |
| AnnaBridge | 171:3a7713b1edbc | 245 | * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode |
| AnnaBridge | 171:3a7713b1edbc | 246 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 247 | */ |
| AnnaBridge | 171:3a7713b1edbc | 248 | __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void) |
| AnnaBridge | 171:3a7713b1edbc | 249 | { |
| AnnaBridge | 171:3a7713b1edbc | 250 | CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); |
| AnnaBridge | 171:3a7713b1edbc | 251 | } |
| AnnaBridge | 171:3a7713b1edbc | 252 | |
| AnnaBridge | 171:3a7713b1edbc | 253 | /** |
| AnnaBridge | 171:3a7713b1edbc | 254 | * @brief Enable the Debug Module during STOP mode |
| AnnaBridge | 171:3a7713b1edbc | 255 | * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode |
| AnnaBridge | 171:3a7713b1edbc | 256 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 257 | */ |
| AnnaBridge | 171:3a7713b1edbc | 258 | __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) |
| AnnaBridge | 171:3a7713b1edbc | 259 | { |
| AnnaBridge | 171:3a7713b1edbc | 260 | SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); |
| AnnaBridge | 171:3a7713b1edbc | 261 | } |
| AnnaBridge | 171:3a7713b1edbc | 262 | |
| AnnaBridge | 171:3a7713b1edbc | 263 | /** |
| AnnaBridge | 171:3a7713b1edbc | 264 | * @brief Disable the Debug Module during STOP mode |
| AnnaBridge | 171:3a7713b1edbc | 265 | * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode |
| AnnaBridge | 171:3a7713b1edbc | 266 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 267 | */ |
| AnnaBridge | 171:3a7713b1edbc | 268 | __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void) |
| AnnaBridge | 171:3a7713b1edbc | 269 | { |
| AnnaBridge | 171:3a7713b1edbc | 270 | CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); |
| AnnaBridge | 171:3a7713b1edbc | 271 | } |
| AnnaBridge | 171:3a7713b1edbc | 272 | |
| AnnaBridge | 171:3a7713b1edbc | 273 | /** |
| AnnaBridge | 171:3a7713b1edbc | 274 | * @brief Enable the Debug Module during STANDBY mode |
| AnnaBridge | 171:3a7713b1edbc | 275 | * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode |
| AnnaBridge | 171:3a7713b1edbc | 276 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 277 | */ |
| AnnaBridge | 171:3a7713b1edbc | 278 | __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) |
| AnnaBridge | 171:3a7713b1edbc | 279 | { |
| AnnaBridge | 171:3a7713b1edbc | 280 | SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); |
| AnnaBridge | 171:3a7713b1edbc | 281 | } |
| AnnaBridge | 171:3a7713b1edbc | 282 | |
| AnnaBridge | 171:3a7713b1edbc | 283 | /** |
| AnnaBridge | 171:3a7713b1edbc | 284 | * @brief Disable the Debug Module during STANDBY mode |
| AnnaBridge | 171:3a7713b1edbc | 285 | * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode |
| AnnaBridge | 171:3a7713b1edbc | 286 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 287 | */ |
| AnnaBridge | 171:3a7713b1edbc | 288 | __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) |
| AnnaBridge | 171:3a7713b1edbc | 289 | { |
| AnnaBridge | 171:3a7713b1edbc | 290 | CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); |
| AnnaBridge | 171:3a7713b1edbc | 291 | } |
| AnnaBridge | 171:3a7713b1edbc | 292 | |
| AnnaBridge | 171:3a7713b1edbc | 293 | /** |
| AnnaBridge | 171:3a7713b1edbc | 294 | * @brief Set Trace pin assignment control |
| AnnaBridge | 171:3a7713b1edbc | 295 | * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n |
| AnnaBridge | 171:3a7713b1edbc | 296 | * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment |
| AnnaBridge | 171:3a7713b1edbc | 297 | * @param PinAssignment This parameter can be one of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 298 | * @arg @ref LL_DBGMCU_TRACE_NONE |
| AnnaBridge | 171:3a7713b1edbc | 299 | * @arg @ref LL_DBGMCU_TRACE_ASYNCH |
| AnnaBridge | 171:3a7713b1edbc | 300 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 |
| AnnaBridge | 171:3a7713b1edbc | 301 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 |
| AnnaBridge | 171:3a7713b1edbc | 302 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 |
| AnnaBridge | 171:3a7713b1edbc | 303 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 304 | */ |
| AnnaBridge | 171:3a7713b1edbc | 305 | __STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment) |
| AnnaBridge | 171:3a7713b1edbc | 306 | { |
| AnnaBridge | 171:3a7713b1edbc | 307 | MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment); |
| AnnaBridge | 171:3a7713b1edbc | 308 | } |
| AnnaBridge | 171:3a7713b1edbc | 309 | |
| AnnaBridge | 171:3a7713b1edbc | 310 | /** |
| AnnaBridge | 171:3a7713b1edbc | 311 | * @brief Get Trace pin assignment control |
| AnnaBridge | 171:3a7713b1edbc | 312 | * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n |
| AnnaBridge | 171:3a7713b1edbc | 313 | * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment |
| AnnaBridge | 171:3a7713b1edbc | 314 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 315 | * @arg @ref LL_DBGMCU_TRACE_NONE |
| AnnaBridge | 171:3a7713b1edbc | 316 | * @arg @ref LL_DBGMCU_TRACE_ASYNCH |
| AnnaBridge | 171:3a7713b1edbc | 317 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 |
| AnnaBridge | 171:3a7713b1edbc | 318 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 |
| AnnaBridge | 171:3a7713b1edbc | 319 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 |
| AnnaBridge | 171:3a7713b1edbc | 320 | */ |
| AnnaBridge | 171:3a7713b1edbc | 321 | __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void) |
| AnnaBridge | 171:3a7713b1edbc | 322 | { |
| AnnaBridge | 171:3a7713b1edbc | 323 | return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)); |
| AnnaBridge | 171:3a7713b1edbc | 324 | } |
| AnnaBridge | 171:3a7713b1edbc | 325 | |
| AnnaBridge | 171:3a7713b1edbc | 326 | /** |
| AnnaBridge | 171:3a7713b1edbc | 327 | * @brief Freeze APB1 peripherals (group1 peripherals) |
| AnnaBridge | 171:3a7713b1edbc | 328 | * @rmtoll DBGMCU_CR_APB1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 329 | * DBGMCU_CR_APB1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 330 | * DBGMCU_CR_APB1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 331 | * DBGMCU_CR_APB1 DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 332 | * DBGMCU_CR_APB1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 333 | * DBGMCU_CR_APB1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 334 | * DBGMCU_CR_APB1 DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 335 | * DBGMCU_CR_APB1 DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 336 | * DBGMCU_CR_APB1 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 337 | * DBGMCU_CR_APB1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 338 | * DBGMCU_CR_APB1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 339 | * DBGMCU_CR_APB1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 340 | * DBGMCU_CR_APB1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 341 | * DBGMCU_CR_APB1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 342 | * DBGMCU_CR_APB1 DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 343 | * DBGMCU_CR_APB1 DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph |
| AnnaBridge | 171:3a7713b1edbc | 344 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 345 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP |
| AnnaBridge | 171:3a7713b1edbc | 346 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP |
| AnnaBridge | 171:3a7713b1edbc | 347 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP |
| AnnaBridge | 171:3a7713b1edbc | 348 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP |
| AnnaBridge | 171:3a7713b1edbc | 349 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP |
| AnnaBridge | 171:3a7713b1edbc | 350 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP |
| AnnaBridge | 171:3a7713b1edbc | 351 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP |
| AnnaBridge | 171:3a7713b1edbc | 352 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP |
| AnnaBridge | 171:3a7713b1edbc | 353 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP |
| AnnaBridge | 171:3a7713b1edbc | 354 | * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP |
| AnnaBridge | 171:3a7713b1edbc | 355 | * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP |
| AnnaBridge | 171:3a7713b1edbc | 356 | * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP |
| AnnaBridge | 171:3a7713b1edbc | 357 | * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*) |
| AnnaBridge | 171:3a7713b1edbc | 358 | * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*) |
| AnnaBridge | 171:3a7713b1edbc | 359 | * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*) |
| AnnaBridge | 171:3a7713b1edbc | 360 | * |
| AnnaBridge | 171:3a7713b1edbc | 361 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 362 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 363 | */ |
| AnnaBridge | 171:3a7713b1edbc | 364 | __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 365 | { |
| AnnaBridge | 171:3a7713b1edbc | 366 | SET_BIT(DBGMCU->CR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 367 | } |
| AnnaBridge | 171:3a7713b1edbc | 368 | |
| AnnaBridge | 171:3a7713b1edbc | 369 | /** |
| AnnaBridge | 171:3a7713b1edbc | 370 | * @brief Unfreeze APB1 peripherals (group1 peripherals) |
| AnnaBridge | 171:3a7713b1edbc | 371 | * @rmtoll DBGMCU_CR_APB1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 372 | * DBGMCU_CR_APB1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 373 | * DBGMCU_CR_APB1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 374 | * DBGMCU_CR_APB1 DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 375 | * DBGMCU_CR_APB1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 376 | * DBGMCU_CR_APB1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 377 | * DBGMCU_CR_APB1 DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 378 | * DBGMCU_CR_APB1 DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 379 | * DBGMCU_CR_APB1 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 380 | * DBGMCU_CR_APB1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 381 | * DBGMCU_CR_APB1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 382 | * DBGMCU_CR_APB1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 383 | * DBGMCU_CR_APB1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 384 | * DBGMCU_CR_APB1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 385 | * DBGMCU_CR_APB1 DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 386 | * DBGMCU_CR_APB1 DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph |
| AnnaBridge | 171:3a7713b1edbc | 387 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 388 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP |
| AnnaBridge | 171:3a7713b1edbc | 389 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP |
| AnnaBridge | 171:3a7713b1edbc | 390 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP |
| AnnaBridge | 171:3a7713b1edbc | 391 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP |
| AnnaBridge | 171:3a7713b1edbc | 392 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP |
| AnnaBridge | 171:3a7713b1edbc | 393 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP |
| AnnaBridge | 171:3a7713b1edbc | 394 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP |
| AnnaBridge | 171:3a7713b1edbc | 395 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP |
| AnnaBridge | 171:3a7713b1edbc | 396 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP |
| AnnaBridge | 171:3a7713b1edbc | 397 | * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP |
| AnnaBridge | 171:3a7713b1edbc | 398 | * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP |
| AnnaBridge | 171:3a7713b1edbc | 399 | * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP |
| AnnaBridge | 171:3a7713b1edbc | 400 | * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP |
| AnnaBridge | 171:3a7713b1edbc | 401 | * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*) |
| AnnaBridge | 171:3a7713b1edbc | 402 | * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*) |
| AnnaBridge | 171:3a7713b1edbc | 403 | * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*) |
| AnnaBridge | 171:3a7713b1edbc | 404 | * |
| AnnaBridge | 171:3a7713b1edbc | 405 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 406 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 407 | */ |
| AnnaBridge | 171:3a7713b1edbc | 408 | __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 409 | { |
| AnnaBridge | 171:3a7713b1edbc | 410 | CLEAR_BIT(DBGMCU->CR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 411 | } |
| AnnaBridge | 171:3a7713b1edbc | 412 | |
| AnnaBridge | 171:3a7713b1edbc | 413 | /** |
| AnnaBridge | 171:3a7713b1edbc | 414 | * @brief Freeze APB2 peripherals |
| AnnaBridge | 171:3a7713b1edbc | 415 | * @rmtoll DBGMCU_CR_APB2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 416 | * DBGMCU_CR_APB2 DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 417 | * DBGMCU_CR_APB2 DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 418 | * DBGMCU_CR_APB2 DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 419 | * DBGMCU_CR_APB2 DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 420 | * DBGMCU_CR_APB2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 421 | * DBGMCU_CR_APB2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 422 | * DBGMCU_CR_APB2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph |
| AnnaBridge | 171:3a7713b1edbc | 423 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 424 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP |
| AnnaBridge | 171:3a7713b1edbc | 425 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*) |
| AnnaBridge | 171:3a7713b1edbc | 426 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*) |
| AnnaBridge | 171:3a7713b1edbc | 427 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*) |
| AnnaBridge | 171:3a7713b1edbc | 428 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*) |
| AnnaBridge | 171:3a7713b1edbc | 429 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*) |
| AnnaBridge | 171:3a7713b1edbc | 430 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*) |
| AnnaBridge | 171:3a7713b1edbc | 431 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*) |
| AnnaBridge | 171:3a7713b1edbc | 432 | * |
| AnnaBridge | 171:3a7713b1edbc | 433 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 434 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 435 | */ |
| AnnaBridge | 171:3a7713b1edbc | 436 | __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 437 | { |
| AnnaBridge | 171:3a7713b1edbc | 438 | SET_BIT(DBGMCU->CR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 439 | } |
| AnnaBridge | 171:3a7713b1edbc | 440 | |
| AnnaBridge | 171:3a7713b1edbc | 441 | /** |
| AnnaBridge | 171:3a7713b1edbc | 442 | * @brief Unfreeze APB2 peripherals |
| AnnaBridge | 171:3a7713b1edbc | 443 | * @rmtoll DBGMCU_CR_APB2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 444 | * DBGMCU_CR_APB2 DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 445 | * DBGMCU_CR_APB2 DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 446 | * DBGMCU_CR_APB2 DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 447 | * DBGMCU_CR_APB2 DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 448 | * DBGMCU_CR_APB2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 449 | * DBGMCU_CR_APB2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 450 | * DBGMCU_CR_APB2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph |
| AnnaBridge | 171:3a7713b1edbc | 451 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 452 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP |
| AnnaBridge | 171:3a7713b1edbc | 453 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*) |
| AnnaBridge | 171:3a7713b1edbc | 454 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*) |
| AnnaBridge | 171:3a7713b1edbc | 455 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*) |
| AnnaBridge | 171:3a7713b1edbc | 456 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*) |
| AnnaBridge | 171:3a7713b1edbc | 457 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*) |
| AnnaBridge | 171:3a7713b1edbc | 458 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*) |
| AnnaBridge | 171:3a7713b1edbc | 459 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*) |
| AnnaBridge | 171:3a7713b1edbc | 460 | * |
| AnnaBridge | 171:3a7713b1edbc | 461 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 462 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 463 | */ |
| AnnaBridge | 171:3a7713b1edbc | 464 | __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 465 | { |
| AnnaBridge | 171:3a7713b1edbc | 466 | CLEAR_BIT(DBGMCU->CR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 467 | } |
| AnnaBridge | 171:3a7713b1edbc | 468 | /** |
| AnnaBridge | 171:3a7713b1edbc | 469 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 470 | */ |
| AnnaBridge | 171:3a7713b1edbc | 471 | |
| AnnaBridge | 171:3a7713b1edbc | 472 | #if defined(FLASH_ACR_LATENCY) |
| AnnaBridge | 171:3a7713b1edbc | 473 | /** @defgroup SYSTEM_LL_EF_FLASH FLASH |
| AnnaBridge | 171:3a7713b1edbc | 474 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 475 | */ |
| AnnaBridge | 171:3a7713b1edbc | 476 | |
| AnnaBridge | 171:3a7713b1edbc | 477 | /** |
| AnnaBridge | 171:3a7713b1edbc | 478 | * @brief Set FLASH Latency |
| AnnaBridge | 171:3a7713b1edbc | 479 | * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency |
| AnnaBridge | 171:3a7713b1edbc | 480 | * @param Latency This parameter can be one of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 481 | * @arg @ref LL_FLASH_LATENCY_0 |
| AnnaBridge | 171:3a7713b1edbc | 482 | * @arg @ref LL_FLASH_LATENCY_1 |
| AnnaBridge | 171:3a7713b1edbc | 483 | * @arg @ref LL_FLASH_LATENCY_2 |
| AnnaBridge | 171:3a7713b1edbc | 484 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 485 | */ |
| AnnaBridge | 171:3a7713b1edbc | 486 | __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) |
| AnnaBridge | 171:3a7713b1edbc | 487 | { |
| AnnaBridge | 171:3a7713b1edbc | 488 | MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); |
| AnnaBridge | 171:3a7713b1edbc | 489 | } |
| AnnaBridge | 171:3a7713b1edbc | 490 | |
| AnnaBridge | 171:3a7713b1edbc | 491 | /** |
| AnnaBridge | 171:3a7713b1edbc | 492 | * @brief Get FLASH Latency |
| AnnaBridge | 171:3a7713b1edbc | 493 | * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency |
| AnnaBridge | 171:3a7713b1edbc | 494 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 495 | * @arg @ref LL_FLASH_LATENCY_0 |
| AnnaBridge | 171:3a7713b1edbc | 496 | * @arg @ref LL_FLASH_LATENCY_1 |
| AnnaBridge | 171:3a7713b1edbc | 497 | * @arg @ref LL_FLASH_LATENCY_2 |
| AnnaBridge | 171:3a7713b1edbc | 498 | */ |
| AnnaBridge | 171:3a7713b1edbc | 499 | __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) |
| AnnaBridge | 171:3a7713b1edbc | 500 | { |
| AnnaBridge | 171:3a7713b1edbc | 501 | return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); |
| AnnaBridge | 171:3a7713b1edbc | 502 | } |
| AnnaBridge | 171:3a7713b1edbc | 503 | |
| AnnaBridge | 171:3a7713b1edbc | 504 | /** |
| AnnaBridge | 171:3a7713b1edbc | 505 | * @brief Enable Prefetch |
| AnnaBridge | 171:3a7713b1edbc | 506 | * @rmtoll FLASH_ACR PRFTBE LL_FLASH_EnablePrefetch |
| AnnaBridge | 171:3a7713b1edbc | 507 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 508 | */ |
| AnnaBridge | 171:3a7713b1edbc | 509 | __STATIC_INLINE void LL_FLASH_EnablePrefetch(void) |
| AnnaBridge | 171:3a7713b1edbc | 510 | { |
| AnnaBridge | 171:3a7713b1edbc | 511 | SET_BIT(FLASH->ACR, FLASH_ACR_PRFTBE); |
| AnnaBridge | 171:3a7713b1edbc | 512 | } |
| AnnaBridge | 171:3a7713b1edbc | 513 | |
| AnnaBridge | 171:3a7713b1edbc | 514 | /** |
| AnnaBridge | 171:3a7713b1edbc | 515 | * @brief Disable Prefetch |
| AnnaBridge | 171:3a7713b1edbc | 516 | * @rmtoll FLASH_ACR PRFTBE LL_FLASH_DisablePrefetch |
| AnnaBridge | 171:3a7713b1edbc | 517 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 518 | */ |
| AnnaBridge | 171:3a7713b1edbc | 519 | __STATIC_INLINE void LL_FLASH_DisablePrefetch(void) |
| AnnaBridge | 171:3a7713b1edbc | 520 | { |
| AnnaBridge | 171:3a7713b1edbc | 521 | CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTBE); |
| AnnaBridge | 171:3a7713b1edbc | 522 | } |
| AnnaBridge | 171:3a7713b1edbc | 523 | |
| AnnaBridge | 171:3a7713b1edbc | 524 | /** |
| AnnaBridge | 171:3a7713b1edbc | 525 | * @brief Check if Prefetch buffer is enabled |
| AnnaBridge | 171:3a7713b1edbc | 526 | * @rmtoll FLASH_ACR PRFTBS LL_FLASH_IsPrefetchEnabled |
| AnnaBridge | 171:3a7713b1edbc | 527 | * @retval State of bit (1 or 0). |
| AnnaBridge | 171:3a7713b1edbc | 528 | */ |
| AnnaBridge | 171:3a7713b1edbc | 529 | __STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void) |
| AnnaBridge | 171:3a7713b1edbc | 530 | { |
| AnnaBridge | 171:3a7713b1edbc | 531 | return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTBS) == (FLASH_ACR_PRFTBS)); |
| AnnaBridge | 171:3a7713b1edbc | 532 | } |
| AnnaBridge | 171:3a7713b1edbc | 533 | |
| AnnaBridge | 171:3a7713b1edbc | 534 | #endif /* FLASH_ACR_LATENCY */ |
| AnnaBridge | 171:3a7713b1edbc | 535 | /** |
| AnnaBridge | 171:3a7713b1edbc | 536 | * @brief Enable Flash Half Cycle Access |
| AnnaBridge | 171:3a7713b1edbc | 537 | * @rmtoll FLASH_ACR HLFCYA LL_FLASH_EnableHalfCycleAccess |
| AnnaBridge | 171:3a7713b1edbc | 538 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 539 | */ |
| AnnaBridge | 171:3a7713b1edbc | 540 | __STATIC_INLINE void LL_FLASH_EnableHalfCycleAccess(void) |
| AnnaBridge | 171:3a7713b1edbc | 541 | { |
| AnnaBridge | 171:3a7713b1edbc | 542 | SET_BIT(FLASH->ACR, FLASH_ACR_HLFCYA); |
| AnnaBridge | 171:3a7713b1edbc | 543 | } |
| AnnaBridge | 171:3a7713b1edbc | 544 | |
| AnnaBridge | 171:3a7713b1edbc | 545 | /** |
| AnnaBridge | 171:3a7713b1edbc | 546 | * @brief Disable Flash Half Cycle Access |
| AnnaBridge | 171:3a7713b1edbc | 547 | * @rmtoll FLASH_ACR HLFCYA LL_FLASH_DisableHalfCycleAccess |
| AnnaBridge | 171:3a7713b1edbc | 548 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 549 | */ |
| AnnaBridge | 171:3a7713b1edbc | 550 | __STATIC_INLINE void LL_FLASH_DisableHalfCycleAccess(void) |
| AnnaBridge | 171:3a7713b1edbc | 551 | { |
| AnnaBridge | 171:3a7713b1edbc | 552 | CLEAR_BIT(FLASH->ACR, FLASH_ACR_HLFCYA); |
| AnnaBridge | 171:3a7713b1edbc | 553 | } |
| AnnaBridge | 171:3a7713b1edbc | 554 | |
| AnnaBridge | 171:3a7713b1edbc | 555 | /** |
| AnnaBridge | 171:3a7713b1edbc | 556 | * @brief Check if Flash Half Cycle Access is enabled or not |
| AnnaBridge | 171:3a7713b1edbc | 557 | * @rmtoll FLASH_ACR HLFCYA LL_FLASH_IsHalfCycleAccessEnabled |
| AnnaBridge | 171:3a7713b1edbc | 558 | * @retval State of bit (1 or 0). |
| AnnaBridge | 171:3a7713b1edbc | 559 | */ |
| AnnaBridge | 171:3a7713b1edbc | 560 | __STATIC_INLINE uint32_t LL_FLASH_IsHalfCycleAccessEnabled(void) |
| AnnaBridge | 171:3a7713b1edbc | 561 | { |
| AnnaBridge | 171:3a7713b1edbc | 562 | return (READ_BIT(FLASH->ACR, FLASH_ACR_HLFCYA) == (FLASH_ACR_HLFCYA)); |
| AnnaBridge | 171:3a7713b1edbc | 563 | } |
| AnnaBridge | 171:3a7713b1edbc | 564 | |
| AnnaBridge | 171:3a7713b1edbc | 565 | |
| AnnaBridge | 171:3a7713b1edbc | 566 | /** |
| AnnaBridge | 171:3a7713b1edbc | 567 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 568 | */ |
| AnnaBridge | 171:3a7713b1edbc | 569 | |
| AnnaBridge | 171:3a7713b1edbc | 570 | /** |
| AnnaBridge | 171:3a7713b1edbc | 571 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 572 | */ |
| AnnaBridge | 171:3a7713b1edbc | 573 | |
| AnnaBridge | 171:3a7713b1edbc | 574 | /** |
| AnnaBridge | 171:3a7713b1edbc | 575 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 576 | */ |
| AnnaBridge | 171:3a7713b1edbc | 577 | |
| AnnaBridge | 171:3a7713b1edbc | 578 | #endif /* defined (FLASH) || defined (DBGMCU) */ |
| AnnaBridge | 171:3a7713b1edbc | 579 | |
| AnnaBridge | 171:3a7713b1edbc | 580 | /** |
| AnnaBridge | 171:3a7713b1edbc | 581 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 582 | */ |
| AnnaBridge | 171:3a7713b1edbc | 583 | |
| AnnaBridge | 171:3a7713b1edbc | 584 | #ifdef __cplusplus |
| AnnaBridge | 171:3a7713b1edbc | 585 | } |
| AnnaBridge | 171:3a7713b1edbc | 586 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 587 | |
| AnnaBridge | 171:3a7713b1edbc | 588 | #endif /* __STM32F1xx_LL_SYSTEM_H */ |
| AnnaBridge | 171:3a7713b1edbc | 589 | |
| AnnaBridge | 171:3a7713b1edbc | 590 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
