Maxim Integrated / MAX77659

SIMO PMIC with 300mA Switching Charger

MAX77659_regs.h@0:047a7089311e, 21 months ago (annotated)

Committer:
Okan Sahin
Date:
Mon Aug 22 19:05:12 2022 +0300
Revision:
0:047a7089311e
Initial Commit

Who changed what in which revision?

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Okan Sahin 0:047a7089311e 1 /*******************************************************************************
Okan Sahin 0:047a7089311e 2 * Copyright (C) 2022 Analog Devices, Inc., All rights Reserved.
Okan Sahin 0:047a7089311e 3 *
Okan Sahin 0:047a7089311e 4 * This software is protected by copyright laws of the United States and
Okan Sahin 0:047a7089311e 5 * of foreign countries. This material may also be protected by patent laws
Okan Sahin 0:047a7089311e 6 * and technology transfer regulations of the United States and of foreign
Okan Sahin 0:047a7089311e 7 * countries. This software is furnished under a license agreement and/or a
Okan Sahin 0:047a7089311e 8 * nondisclosure agreement and may only be used or reproduced in accordance
Okan Sahin 0:047a7089311e 9 * with the terms of those agreements. Dissemination of this information to
Okan Sahin 0:047a7089311e 10 * any party or parties not specified in the license agreement and/or
Okan Sahin 0:047a7089311e 11 * nondisclosure agreement is expressly prohibited.
Okan Sahin 0:047a7089311e 12 *
Okan Sahin 0:047a7089311e 13 * The above copyright notice and this permission notice shall be included
Okan Sahin 0:047a7089311e 14 * in all copies or substantial portions of the Software.
Okan Sahin 0:047a7089311e 15 *
Okan Sahin 0:047a7089311e 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
Okan Sahin 0:047a7089311e 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
Okan Sahin 0:047a7089311e 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
Okan Sahin 0:047a7089311e 19 * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY CLAIM, DAMAGES
Okan Sahin 0:047a7089311e 20 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
Okan Sahin 0:047a7089311e 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
Okan Sahin 0:047a7089311e 22 * OTHER DEALINGS IN THE SOFTWARE.
Okan Sahin 0:047a7089311e 23 *
Okan Sahin 0:047a7089311e 24 * Except as contained in this notice, the name of Maxim Integrated
Okan Sahin 0:047a7089311e 25 * Products, Inc. shall not be used except as stated in the Maxim Integrated
Okan Sahin 0:047a7089311e 26 * Products, Inc. Branding Policy.
Okan Sahin 0:047a7089311e 27 *
Okan Sahin 0:047a7089311e 28 * The mere transfer of this software does not imply any licenses
Okan Sahin 0:047a7089311e 29 * of trade secrets, proprietary technology, copyrights, patents,
Okan Sahin 0:047a7089311e 30 * trademarks, maskwork rights, or any other form of intellectual
Okan Sahin 0:047a7089311e 31 * property whatsoever. Analog Devices, Inc. retains all
Okan Sahin 0:047a7089311e 32 * ownership rights.
Okan Sahin 0:047a7089311e 33 *******************************************************************************
Okan Sahin 0:047a7089311e 34 */
Okan Sahin 0:047a7089311e 35
Okan Sahin 0:047a7089311e 36 #ifndef MAX77659_REGS_H_
Okan Sahin 0:047a7089311e 37 #define MAX77659_REGS_H_
Okan Sahin 0:047a7089311e 38
Okan Sahin 0:047a7089311e 39 /**
Okan Sahin 0:047a7089311e 40 * @brief INT_GLBL0 Register
Okan Sahin 0:047a7089311e 41 *
Okan Sahin 0:047a7089311e 42 * Address : 0x00
Okan Sahin 0:047a7089311e 43 */
Okan Sahin 0:047a7089311e 44 typedef union {
Okan Sahin 0:047a7089311e 45 unsigned char raw;
Okan Sahin 0:047a7089311e 46 struct {
Okan Sahin 0:047a7089311e 47 unsigned char gpi0_f : 1; /**< GPI Falling Interrupt. Bit 0.
Okan Sahin 0:047a7089311e 48 Note that "GPI" refers to the GPIO programmed to be an input.
Okan Sahin 0:047a7089311e 49 0 = No GPI falling edges have occurred since the last time this bit was read.
Okan Sahin 0:047a7089311e 50 1 = A GPI falling edge has occurred since the last time this bit was read. */
Okan Sahin 0:047a7089311e 51 unsigned char gpi0_r : 1; /**< GPI Rising Interrupt. Bit 1.
Okan Sahin 0:047a7089311e 52 Note that "GPI" refers to the GPIO programmed to be an input.
Okan Sahin 0:047a7089311e 53 0 = No GPI rising edges have occurred since the last time this bit was read.
Okan Sahin 0:047a7089311e 54 1 = A GPI rising edge has occurred since the last time this bit was read. */
Okan Sahin 0:047a7089311e 55 unsigned char nen_f : 1; /**< nEN Falling Interrupt.Bit 2.
Okan Sahin 0:047a7089311e 56 0 = No nEN falling edges have occurred since the last time this bit was read.
Okan Sahin 0:047a7089311e 57 1 = A nEN falling edge as occurred since the last time this bit was read. */
Okan Sahin 0:047a7089311e 58 unsigned char nen_r : 1; /**< nEN Rising Interrupt. Bit 3.
Okan Sahin 0:047a7089311e 59 0 = No nEN rising edges have occurred since the last time this bit was read.
Okan Sahin 0:047a7089311e 60 1 = A nEN rising edge as occurred since the last time this bit was read. */
Okan Sahin 0:047a7089311e 61 unsigned char tjal1_r : 1; /**< Thermal Alarm 1 Rising Interrupt. Bit 4.
Okan Sahin 0:047a7089311e 62 0 = The junction temperature has not risen above TJAL1 since the last time this bit was read.
Okan Sahin 0:047a7089311e 63 1 = The junction temperature has risen above TJAL1 since the last time this bit was read. */
Okan Sahin 0:047a7089311e 64 unsigned char tjal2_r : 1; /**< Thermal Alarm 2 Rising Interrupt. Bit 5.
Okan Sahin 0:047a7089311e 65 0 = The junction temperature has not risen above TJAL2 since the last time this bit was read.
Okan Sahin 0:047a7089311e 66 1 = The junction temperature has risen above TJAL2 since the last time this bit was read. */
Okan Sahin 0:047a7089311e 67 unsigned char rsvd : 1; /**< Reserved. Unutilized bit. Write to 0. Reads are don't care. Bit 6. */
Okan Sahin 0:047a7089311e 68 unsigned char dod_r : 1; /**< LDO Dropout Detector Rising Interrupt. Bit 7.
Okan Sahin 0:047a7089311e 69 0 = The LDO has not detected dropout since the last time this bit was read.
Okan Sahin 0:047a7089311e 70 1 = The LDO has detected dropout since the last time this bit was read. */
Okan Sahin 0:047a7089311e 71 } bits;
Okan Sahin 0:047a7089311e 72 } reg_int_glbl0_t;
Okan Sahin 0:047a7089311e 73
Okan Sahin 0:047a7089311e 74 /**
Okan Sahin 0:047a7089311e 75 * @brief INT_GLBL1 Register
Okan Sahin 0:047a7089311e 76 *
Okan Sahin 0:047a7089311e 77 * Address : 0x04
Okan Sahin 0:047a7089311e 78 */
Okan Sahin 0:047a7089311e 79 typedef union {
Okan Sahin 0:047a7089311e 80 unsigned char raw;
Okan Sahin 0:047a7089311e 81 struct {
Okan Sahin 0:047a7089311e 82 unsigned char gpi1_f : 1; /**< GPI Falling Interrupt. Bit 0.
Okan Sahin 0:047a7089311e 83 Note that "GPI" refers to the GPIO programmed to be an input.
Okan Sahin 0:047a7089311e 84 0 = No GPI falling edges have occurred since the last time this bit was read.
Okan Sahin 0:047a7089311e 85 1 = A GPI falling edge has occurred since the last time this bit was read. */
Okan Sahin 0:047a7089311e 86 unsigned char gpi1_r : 1; /**< GPI Rising Interrupt. Bit 1.
Okan Sahin 0:047a7089311e 87 Note that "GPI" refers to the GPIO programmed to be an input.
Okan Sahin 0:047a7089311e 88 0 = No GPI rising edges have occurred since the last time this bit was read.
Okan Sahin 0:047a7089311e 89 1 = A GPI rising edge has occurred since the last time this bit was read. */
Okan Sahin 0:047a7089311e 90 unsigned char rsvd1 : 2; /**< Reserved. Unutilized bit. Write to 0. Reads are don't care. Bit 3:2. */
Okan Sahin 0:047a7089311e 91 unsigned char sbb_to : 1; /**< SBB Timeout. Bit 4.
Okan Sahin 0:047a7089311e 92 0 = NO SBB timeout occurred since the last time this bit was read
Okan Sahin 0:047a7089311e 93 1 = SBB timeout occurred since the last time this bit was read */
Okan Sahin 0:047a7089311e 94 unsigned char ldo_f : 1; /**< LDO Fault Interrupt. Bit 5.
Okan Sahin 0:047a7089311e 95 0 = No fault has occurred on LDO since the last time this bit was read.
Okan Sahin 0:047a7089311e 96 1 = LDO has fallen out of regulation since the last time this bit was read. */
Okan Sahin 0:047a7089311e 97 unsigned char ldo1_f : 1; /**< LDO1 Fault Interrupt. Bit 6.
Okan Sahin 0:047a7089311e 98 0 = No fault has occurred on LDO1 since the last time this bit was read.
Okan Sahin 0:047a7089311e 99 1 = LDO1 has fallen out of regulation since the last time this bit was read. */
Okan Sahin 0:047a7089311e 100 unsigned char rsvd2 : 2; /**< Reserved. Unutilized bit. Write to 0. Reads are don't care. Bit 7:6. */
Okan Sahin 0:047a7089311e 101 } bits;
Okan Sahin 0:047a7089311e 102 } reg_int_glbl1_t;
Okan Sahin 0:047a7089311e 103
Okan Sahin 0:047a7089311e 104 /**
Okan Sahin 0:047a7089311e 105 * @brief ERCFLAG Register
Okan Sahin 0:047a7089311e 106 *
Okan Sahin 0:047a7089311e 107 * Address : 0x05
Okan Sahin 0:047a7089311e 108 */
Okan Sahin 0:047a7089311e 109 typedef union {
Okan Sahin 0:047a7089311e 110 unsigned char raw;
Okan Sahin 0:047a7089311e 111 struct {
Okan Sahin 0:047a7089311e 112 unsigned char tovld : 1; /**< Thermal Overload. Bit 0.
Okan Sahin 0:047a7089311e 113 0 = Thermal overload has not occurred since the last read of this register.
Okan Sahin 0:047a7089311e 114 1 = Thermal overload has occurred since the list read of this register.
Okan Sahin 0:047a7089311e 115 This indicates that the junction temperature has exceeded 165ºC. */
Okan Sahin 0:047a7089311e 116 unsigned char sysovlo : 1; /**< SYS Domain Overvoltage Lockout. Bit 1.
Okan Sahin 0:047a7089311e 117 0 = The SYS domain overvoltage lockout has not occurred since this last read of this register.
Okan Sahin 0:047a7089311e 118 1 = The SYS domain overvoltage lockout has occurred since the last read of this register. */
Okan Sahin 0:047a7089311e 119 unsigned char avluvlo : 1; /**< AVL Domain Undervoltage Lockout. Bit 2.
Okan Sahin 0:047a7089311e 120 0 = The AVL domain undervoltage lockout has not occurred since this last read of this register.
Okan Sahin 0:047a7089311e 121 1 = The AVL domain undervoltage lockout has occurred since the last read of this register. */
Okan Sahin 0:047a7089311e 122 unsigned char mrst : 1; /**< Manual Reset Timer. Bit 3.
Okan Sahin 0:047a7089311e 123 0 = A Manual Reset has not occurred since this last read of this register.
Okan Sahin 0:047a7089311e 124 1 = A Manual Reset has occurred since this last read of this register. */
Okan Sahin 0:047a7089311e 125 unsigned char sft_off_f : 1; /**< Software Off Flag. Bit 4.
Okan Sahin 0:047a7089311e 126 0 = The SFT_OFF function has not occurred since the last read of this register.
Okan Sahin 0:047a7089311e 127 1 = The SFT_OFF function has occurred since the last read of this register. */
Okan Sahin 0:047a7089311e 128 unsigned char sft_crst_f: 1; /**< Software Cold Reset Flag. Bit 5.
Okan Sahin 0:047a7089311e 129 0 = The software cold reset has not occurred since the last read of this register.
Okan Sahin 0:047a7089311e 130 1 = The software cold reset has occurred since the last read of this register. */
Okan Sahin 0:047a7089311e 131 unsigned char wdt_off : 1; /**< Watchdog Timer OFF Flag. Bit 6.
Okan Sahin 0:047a7089311e 132 This bit sets when the watchdog timer expires and causes a power-off.
Okan Sahin 0:047a7089311e 133 0 = Watchdog timer has not caused a power-off since the last time this bit was read.
Okan Sahin 0:047a7089311e 134 1 = Watchdog timer has expired and caused a power-off since the last time this bit was read. */
Okan Sahin 0:047a7089311e 135 unsigned char wdt_rst : 1; /**< Watchdog Timer Reset Flag. Bit 7.
Okan Sahin 0:047a7089311e 136 This bit sets when the watchdog timer expires and causes a power-reset.
Okan Sahin 0:047a7089311e 137 0 = Watchdog timer has not caused a power-reset since the last time this bit was read.
Okan Sahin 0:047a7089311e 138 1 = Watchdog timer has expired and caused a power-reset since the last time this bit was read.*/
Okan Sahin 0:047a7089311e 139 } bits;
Okan Sahin 0:047a7089311e 140 } reg_ercflag_t;
Okan Sahin 0:047a7089311e 141
Okan Sahin 0:047a7089311e 142 /**
Okan Sahin 0:047a7089311e 143 * @brief STAT_GLBL Register
Okan Sahin 0:047a7089311e 144 *
Okan Sahin 0:047a7089311e 145 * Address : 0x06
Okan Sahin 0:047a7089311e 146 */
Okan Sahin 0:047a7089311e 147 typedef union {
Okan Sahin 0:047a7089311e 148 unsigned char raw;
Okan Sahin 0:047a7089311e 149 struct {
Okan Sahin 0:047a7089311e 150 unsigned char stat_irq : 1; /**< Software Version of the nIRQ MOSFET gate drive. Bit 0.
Okan Sahin 0:047a7089311e 151 0 = unmasked gate drive is logic low
Okan Sahin 0:047a7089311e 152 1 = unmasked gate drive is logic high */
Okan Sahin 0:047a7089311e 153 unsigned char stat_en : 1; /**< Debounced Status for the nEN input. Bit 1.
Okan Sahin 0:047a7089311e 154 0 = nEN is not active (logic high)
Okan Sahin 0:047a7089311e 155 1 = nEN is active (logic low) */
Okan Sahin 0:047a7089311e 156 unsigned char tjal1_s : 1; /**< Thermal Alarm 1 Status. Bit 2.
Okan Sahin 0:047a7089311e 157 0 = The junction temperature is less than TJAL1
Okan Sahin 0:047a7089311e 158 1 = The junction temperature is greater than TJAL1 */
Okan Sahin 0:047a7089311e 159 unsigned char tjal2_s : 1; /**< Thermal Alarm 2 Status. Bit 3.
Okan Sahin 0:047a7089311e 160 0 = The junction temperature is less than TJAL2
Okan Sahin 0:047a7089311e 161 1 = The junction temperature is greater than TJAL2 */
Okan Sahin 0:047a7089311e 162 unsigned char rsvd : 1; /**< Reserved. Unutilized bit. Write to 0. Reads are don't care. */
Okan Sahin 0:047a7089311e 163 unsigned char dod_s : 1; /**< LDO0 Dropout Detector Rising Status. Bit 5.
Okan Sahin 0:047a7089311e 164 0 = LDO0 is not in dropout
Okan Sahin 0:047a7089311e 165 1 = LDO0 is in dropout */
Okan Sahin 0:047a7089311e 166 unsigned char bok : 1; /**< BOK Interrupt Status. Bit 6.
Okan Sahin 0:047a7089311e 167 0 = Main Bias is not ready.
Okan Sahin 0:047a7089311e 168 1 = Main Bias enabled and ready. */
Okan Sahin 0:047a7089311e 169 unsigned char didm : 1; /**< Device Identification Bits for Metal Options. Bit 7.
Okan Sahin 0:047a7089311e 170 0 = MAX77659
Okan Sahin 0:047a7089311e 171 1 = Reserved */
Okan Sahin 0:047a7089311e 172 } bits;
Okan Sahin 0:047a7089311e 173 } reg_stat_glbl_t;
Okan Sahin 0:047a7089311e 174
Okan Sahin 0:047a7089311e 175 /**
Okan Sahin 0:047a7089311e 176 * @brief INTM_GLBL1 Register
Okan Sahin 0:047a7089311e 177 *
Okan Sahin 0:047a7089311e 178 * Address : 0x08
Okan Sahin 0:047a7089311e 179 */
Okan Sahin 0:047a7089311e 180 typedef union {
Okan Sahin 0:047a7089311e 181 unsigned char raw;
Okan Sahin 0:047a7089311e 182 struct {
Okan Sahin 0:047a7089311e 183 unsigned char gpi1_fm : 1; /**< GPI Falling Interrupt Mask. Bit 0.
Okan Sahin 0:047a7089311e 184 0 = Unmasked. If GPI_F goes from 0 to 1, then nIRQ goes low.
Okan Sahin 0:047a7089311e 185 nIRQ goes high when all interrupt bits are cleared.
Okan Sahin 0:047a7089311e 186 1 = Masked. nIRQ does not go low due to GPI_F. */
Okan Sahin 0:047a7089311e 187 unsigned char gpi1_rm : 1; /**< GPI Rising Interrupt Mask. Bit 1.
Okan Sahin 0:047a7089311e 188 0 = Unmasked. If GPI_R goes from 0 to 1, then nIRQ goes low.
Okan Sahin 0:047a7089311e 189 nIRQ goes high when all interrupt bits are cleared.
Okan Sahin 0:047a7089311e 190 1 = Masked. nIRQ does not go low due to GPI_R. */
Okan Sahin 0:047a7089311e 191 unsigned char rsvd1 : 2; /**< Reserved. Unutilized bit. Write to 0. Reads are don't care. Bit 3:2. */
Okan Sahin 0:047a7089311e 192 unsigned char sbb_to_m : 1; /**< SBB Timeout Mask. Bit 4.
Okan Sahin 0:047a7089311e 193 0 = Unmasked. If SBB_TO goes from 0 to 1, then nIRQ goes low.
Okan Sahin 0:047a7089311e 194 nIRQ goes high when all interrupt bits are cleared.
Okan Sahin 0:047a7089311e 195 1 = Masked. nIRQ does not go low due to SBB_TO */
Okan Sahin 0:047a7089311e 196 unsigned char ldo_m : 1; /**< LDO0 Fault Interrupt. Bit 5.
Okan Sahin 0:047a7089311e 197 0 = Unmasked. If LDO0_F goes from 0 to 1, then nIRQ goes low.
Okan Sahin 0:047a7089311e 198 nIRQ goes high when all interrupt bits are cleared.
Okan Sahin 0:047a7089311e 199 1 = Masked. nIRQ does not go low due to LDO0_F. */
Okan Sahin 0:047a7089311e 200 unsigned char rsvd2 : 2; /**< Reserved. Unutilized bit. Write to 0. Reads are don't care. Bit 7:6. */
Okan Sahin 0:047a7089311e 201 } bits;
Okan Sahin 0:047a7089311e 202 } reg_intm_glbl1_t;
Okan Sahin 0:047a7089311e 203
Okan Sahin 0:047a7089311e 204 /**
Okan Sahin 0:047a7089311e 205 * @brief INTM_GLBL0 Register
Okan Sahin 0:047a7089311e 206 *
Okan Sahin 0:047a7089311e 207 * Address : 0x09
Okan Sahin 0:047a7089311e 208 */
Okan Sahin 0:047a7089311e 209 typedef union {
Okan Sahin 0:047a7089311e 210 unsigned char raw;
Okan Sahin 0:047a7089311e 211 struct {
Okan Sahin 0:047a7089311e 212 unsigned char gpi0_fm : 1; /**< GPI Falling Interrupt Mask. Bit 0.
Okan Sahin 0:047a7089311e 213 0 = Unmasked. If GPI_F goes from 0 to 1, then nIRQ goes low.
Okan Sahin 0:047a7089311e 214 nIRQ goes high when all interrupt bits are cleared.
Okan Sahin 0:047a7089311e 215 1 = Masked. nIRQ does not go low due to GPI_F. */
Okan Sahin 0:047a7089311e 216 unsigned char gpi0_rm : 1; /**< GPI Rising Interrupt Mask. Bit 1.
Okan Sahin 0:047a7089311e 217 0 = Unmasked. If GPI_R goes from 0 to 1, then nIRQ goes low.
Okan Sahin 0:047a7089311e 218 nIRQ goes high when all interrupt bits are cleared.
Okan Sahin 0:047a7089311e 219 1 = Masked. nIRQ does not go low due to GPI_R. */
Okan Sahin 0:047a7089311e 220 unsigned char nen_fm : 1; /**< nEN Falling Interrupt Mask. Bit 2.
Okan Sahin 0:047a7089311e 221 0 = Unmasked. If nEN_F goes from 0 to 1, then nIRQ goes low.
Okan Sahin 0:047a7089311e 222 nIRQ goes high when all interrupt bits are cleared.
Okan Sahin 0:047a7089311e 223 1 = Masked. nIRQ does not go low due to nEN_F. */
Okan Sahin 0:047a7089311e 224 unsigned char nen_rm : 1; /**< nEN Rising Interrupt Mask. Bit 3.
Okan Sahin 0:047a7089311e 225 0 = Unmasked. If nEN_R goes from 0 to 1, then nIRQ goes low.
Okan Sahin 0:047a7089311e 226 nIRQ goes high when all interrupt bits are cleared.
Okan Sahin 0:047a7089311e 227 1 = Masked. nIRQ does not go low due to nEN_R. */
Okan Sahin 0:047a7089311e 228 unsigned char tjal1_rm : 1; /**< Thermal Alarm 1 Rising Interrupt Mask. Bit 4.
Okan Sahin 0:047a7089311e 229 0 = Unmasked. If TJAL1_R goes from 0 to 1, then nIRQ goes low.
Okan Sahin 0:047a7089311e 230 nIRQ goes high when all interrupt bits are cleared.
Okan Sahin 0:047a7089311e 231 1 = Masked. nIRQ does not go low due to TJAL1_R. */
Okan Sahin 0:047a7089311e 232 unsigned char tjal2_rm : 1; /**< Thermal Alarm 2 Rising Interrupt Mask. Bit 5.
Okan Sahin 0:047a7089311e 233 0 = Unmasked. If TJAL2_R goes from 0 to 1, then nIRQ goes low.
Okan Sahin 0:047a7089311e 234 nIRQ goes high when all interrupt bits are cleared.
Okan Sahin 0:047a7089311e 235 1 = Masked. nIRQ does not go low due to TJAL2_R. */
Okan Sahin 0:047a7089311e 236 unsigned char rsvd : 1; /**< Reserved. Unutilized bit. Write to 0. Reads are don't care. Bit 6. */
Okan Sahin 0:047a7089311e 237 unsigned char dod_rm : 1; /**< LDO Dropout Detector Rising Interrupt Mask. Bit 7.
Okan Sahin 0:047a7089311e 238 0 = Unmasked. If DOD0_R goes from 0 to 1, then nIRQ goes low.
Okan Sahin 0:047a7089311e 239 nIRQ goes high when all interrupt bits are cleared.
Okan Sahin 0:047a7089311e 240 1 = Masked. nIRQ does not go low due to DOD0_R. */
Okan Sahin 0:047a7089311e 241 } bits;
Okan Sahin 0:047a7089311e 242 } reg_intm_glbl0_t;
Okan Sahin 0:047a7089311e 243
Okan Sahin 0:047a7089311e 244 /**
Okan Sahin 0:047a7089311e 245 * @brief CNFG_GLBL Register
Okan Sahin 0:047a7089311e 246 *
Okan Sahin 0:047a7089311e 247 * Address : 0x10
Okan Sahin 0:047a7089311e 248 */
Okan Sahin 0:047a7089311e 249 typedef union {
Okan Sahin 0:047a7089311e 250 unsigned char raw;
Okan Sahin 0:047a7089311e 251 struct {
Okan Sahin 0:047a7089311e 252 unsigned char sft_ctrl : 2; /**< Software Reset Functions. Bit 1:0.
Okan Sahin 0:047a7089311e 253 0b00 = No Action
Okan Sahin 0:047a7089311e 254 0b01 = Software Cold Reset (SFT_CRST). The device powers down, resets, and the powers up again.
Okan Sahin 0:047a7089311e 255 0b10 = Software Off (SFT_OFF). The device powers down, resets, and then remains off and waiting for a wake-up event.
Okan Sahin 0:047a7089311e 256 0b11 = Factory-Ship Mode Enter (FSM). */
Okan Sahin 0:047a7089311e 257 unsigned char dben_nen : 1; /**< Debounce Timer Enable for the nEN Pin. Bit 2.
Okan Sahin 0:047a7089311e 258 0 = 500μs Debounce
Okan Sahin 0:047a7089311e 259 1 = 30ms Debounce */
Okan Sahin 0:047a7089311e 260 unsigned char nen_mode : 1; /**< nEN Input (ON-KEY) Default Configuration Mode. Bit 3.
Okan Sahin 0:047a7089311e 261 0 = Push-Button Mode
Okan Sahin 0:047a7089311e 262 1 = Slide-Switch Mode */
Okan Sahin 0:047a7089311e 263 unsigned char sbia_en : 1; /**< Main Bias Enable Software Request. Bit 4.
Okan Sahin 0:047a7089311e 264 0 = Main Bias not enabled by software.
Okan Sahin 0:047a7089311e 265 Note that the main bias may be on via the on/off controller.
Okan Sahin 0:047a7089311e 266 1 = Main Bias force enabled by software. */
Okan Sahin 0:047a7089311e 267 unsigned char sbia_lpm : 1; /**< Main Bias Low-Power Mode Software Request. Bit 5.
Okan Sahin 0:047a7089311e 268 0 = Main Bias requested to be in Normal-Power Mode by software.
Okan Sahin 0:047a7089311e 269 1 = Main Bias request to be in Low-Power Mode by software. */
Okan Sahin 0:047a7089311e 270 unsigned char t_mrst : 1; /**< Sets the Manual Reset Time (tMRST). Bit 6.
Okan Sahin 0:047a7089311e 271 0 = 8s
Okan Sahin 0:047a7089311e 272 1 = 3.3s */
Okan Sahin 0:047a7089311e 273 unsigned char pu_dis : 1; /**< nEN Internal Pullup Resistor. Bit 7.
Okan Sahin 0:047a7089311e 274 0 = Strong internal nEN pullup (200kΩ)
Okan Sahin 0:047a7089311e 275 1 = Weak internal nEN pullup (10MΩ) */
Okan Sahin 0:047a7089311e 276 } bits;
Okan Sahin 0:047a7089311e 277 } reg_cnfg_glbl_t;
Okan Sahin 0:047a7089311e 278
Okan Sahin 0:047a7089311e 279 /**
Okan Sahin 0:047a7089311e 280 * @brief CNFG_GPIO0 Register
Okan Sahin 0:047a7089311e 281 *
Okan Sahin 0:047a7089311e 282 * Address : 0x11
Okan Sahin 0:047a7089311e 283 */
Okan Sahin 0:047a7089311e 284 typedef union {
Okan Sahin 0:047a7089311e 285 unsigned char raw;
Okan Sahin 0:047a7089311e 286 struct {
Okan Sahin 0:047a7089311e 287 unsigned char gpo_dir : 1; /**< GPIO Direction. Bit 0.
Okan Sahin 0:047a7089311e 288 0 = General purpose output (GPO)
Okan Sahin 0:047a7089311e 289 1 = General purpose input (GPI) */
Okan Sahin 0:047a7089311e 290 unsigned char gpo_di : 1; /**< GPIO Digital Input Value. Bit 1.
Okan Sahin 0:047a7089311e 291 0 = Input logic low
Okan Sahin 0:047a7089311e 292 1 = Input logic high */
Okan Sahin 0:047a7089311e 293 unsigned char gpo_drv : 1; /**< General Purpose Output Driver Type. Bit 2.
Okan Sahin 0:047a7089311e 294 This bit is a don't care when DIR = 1 (configured as input) When set for GPO (DIR = 0):
Okan Sahin 0:047a7089311e 295 0 = Open-Drain
Okan Sahin 0:047a7089311e 296 1 = Push-Pull */
Okan Sahin 0:047a7089311e 297 unsigned char gpo_do : 1; /**< General Purpose Output Data Output. Bit 3.
Okan Sahin 0:047a7089311e 298 This bit is a don't care when DIR = 1 (configured as input). When set for GPO (DIR = 0):
Okan Sahin 0:047a7089311e 299 0 = GPIO is output is logic low
Okan Sahin 0:047a7089311e 300 1 = GPIO is output logic high when set as push-pull output (DRV = 1). */
Okan Sahin 0:047a7089311e 301 unsigned char dben_gpi : 1; /**< General Purpose Input Debounce Timer Enable. Bit 4.
Okan Sahin 0:047a7089311e 302 0 = no debounce
Okan Sahin 0:047a7089311e 303 1 = 30ms debounce */
Okan Sahin 0:047a7089311e 304 unsigned char alt_gpio : 1; /**< Alternate Mode Enable for GPIO0. Bit 5.
Okan Sahin 0:047a7089311e 305 0 = Standard GPIO.
Okan Sahin 0:047a7089311e 306 1 = Active-high input, enable control for low-power mode. */
Okan Sahin 0:047a7089311e 307 unsigned char : 1; /**< Bit 6. */
Okan Sahin 0:047a7089311e 308 unsigned char rsvd : 1; /**< Reserved. Bit 7. Unutilized bit. Write to 0. Reads are don't care. */
Okan Sahin 0:047a7089311e 309 } bits;
Okan Sahin 0:047a7089311e 310 } reg_cnfg_gpio0_t;
Okan Sahin 0:047a7089311e 311
Okan Sahin 0:047a7089311e 312 /**
Okan Sahin 0:047a7089311e 313 * @brief CNFG_GPIO1 Register
Okan Sahin 0:047a7089311e 314 *
Okan Sahin 0:047a7089311e 315 * Address : 0x12
Okan Sahin 0:047a7089311e 316 */
Okan Sahin 0:047a7089311e 317 typedef union {
Okan Sahin 0:047a7089311e 318 unsigned char raw;
Okan Sahin 0:047a7089311e 319 struct {
Okan Sahin 0:047a7089311e 320 unsigned char gpo_dir : 1; /**< GPIO Direction. Bit 0.
Okan Sahin 0:047a7089311e 321 0 = General purpose output (GPO)
Okan Sahin 0:047a7089311e 322 1 = General purpose input (GPI) */
Okan Sahin 0:047a7089311e 323 unsigned char gpo_di : 1; /**< GPIO Digital Input Value. Bit 1.
Okan Sahin 0:047a7089311e 324 0 = Input logic low
Okan Sahin 0:047a7089311e 325 1 = Input logic high */
Okan Sahin 0:047a7089311e 326 unsigned char gpo_drv : 1; /**< General Purpose Output Driver Type. Bit 2.
Okan Sahin 0:047a7089311e 327 This bit is a don't care when DIR = 1 (configured as input) When set for GPO (DIR = 0):
Okan Sahin 0:047a7089311e 328 0 = Open-Drain
Okan Sahin 0:047a7089311e 329 1 = Push-Pull */
Okan Sahin 0:047a7089311e 330 unsigned char gpo_do : 1; /**< General Purpose Output Data Output. Bit 3.
Okan Sahin 0:047a7089311e 331 This bit is a don't care when DIR = 1 (configured as input). When set for GPO (DIR = 0):
Okan Sahin 0:047a7089311e 332 0 = GPIO is output is logic low
Okan Sahin 0:047a7089311e 333 1 = GPIO is output logic high when set as push-pull output (DRV = 1). */
Okan Sahin 0:047a7089311e 334 unsigned char dben_gpi : 1; /**< General Purpose Input Debounce Timer Enable. Bit 4.
Okan Sahin 0:047a7089311e 335 0 = no debounce
Okan Sahin 0:047a7089311e 336 1 = 30ms debounce */
Okan Sahin 0:047a7089311e 337 unsigned char alt_gpio : 1; /**< Alternate Mode Enable for GPIO1. Bit 5.
Okan Sahin 0:047a7089311e 338 0 = Standard GPIO.
Okan Sahin 0:047a7089311e 339 1 = Active-high input, enable control for the DVS feature for SBB0. */
Okan Sahin 0:047a7089311e 340 unsigned char rsvd : 2; /**< Reserved. Bit 7:6. Unutilized bit. Write to 0. Reads are don't care. */
Okan Sahin 0:047a7089311e 341 } bits;
Okan Sahin 0:047a7089311e 342 } reg_cnfg_gpio1_t;
Okan Sahin 0:047a7089311e 343
Okan Sahin 0:047a7089311e 344 /**
Okan Sahin 0:047a7089311e 345 * @brief CID Register
Okan Sahin 0:047a7089311e 346 *
Okan Sahin 0:047a7089311e 347 * Address : 0x14
Okan Sahin 0:047a7089311e 348 */
Okan Sahin 0:047a7089311e 349 typedef union {
Okan Sahin 0:047a7089311e 350 unsigned char raw;
Okan Sahin 0:047a7089311e 351 struct {
Okan Sahin 0:047a7089311e 352 unsigned char cid_3_0 : 4; /**< Bits 0 to 3 of the Chip Identification Code. Bit 3:0.
Okan Sahin 0:047a7089311e 353 The Chip Identification Code refers to a set of reset values in the register map, or the "OTP configuration.". */
Okan Sahin 0:047a7089311e 354 unsigned char : 3; /**< Bit 6:4. */
Okan Sahin 0:047a7089311e 355 unsigned char cid_7 : 1; /**< Bit 4 of the Chip Identification Code. Bit 7.
Okan Sahin 0:047a7089311e 356 The Chip Identification Code refers to a set of reset values in the register map, or the "OTP configuration.". */
Okan Sahin 0:047a7089311e 357 } bits;
Okan Sahin 0:047a7089311e 358 } reg_cid_t;
Okan Sahin 0:047a7089311e 359
Okan Sahin 0:047a7089311e 360 /**
Okan Sahin 0:047a7089311e 361 * @brief CNFG_WDT Register
Okan Sahin 0:047a7089311e 362 *
Okan Sahin 0:047a7089311e 363 * Address : 0x17
Okan Sahin 0:047a7089311e 364 */
Okan Sahin 0:047a7089311e 365 typedef union {
Okan Sahin 0:047a7089311e 366 unsigned char raw;
Okan Sahin 0:047a7089311e 367 struct {
Okan Sahin 0:047a7089311e 368 unsigned char wdt_lock : 1; /**< Factory-Set Safety Bit for the Watchdog Timer. Bit 0.
Okan Sahin 0:047a7089311e 369 0 = Watchdog timer can be enabled and disabled with WDT_EN.
Okan Sahin 0:047a7089311e 370 1 = Watchdog timer can not be disabled with WDT_EN.
Okan Sahin 0:047a7089311e 371 However, WDT_EN can still be used to enable the watchdog timer. */
Okan Sahin 0:047a7089311e 372 unsigned char wdt_en : 1; /**< Watchdog Timer Enable. Bit 1.
Okan Sahin 0:047a7089311e 373 0 = Watchdog timer is not enabled.
Okan Sahin 0:047a7089311e 374 1 = Watchdog timer is enabled. The timer will expire if not reset by setting WDT_CLR. */
Okan Sahin 0:047a7089311e 375 unsigned char wdt_clr : 1; /**< Watchdog Timer Clear Control. Bit 2.
Okan Sahin 0:047a7089311e 376 0 = Watchdog timer period is not reset.
Okan Sahin 0:047a7089311e 377 1 = Watchdog timer is reset back to tWD. */
Okan Sahin 0:047a7089311e 378 unsigned char wdt_mode : 1; /**< Watchdog Timer Expired Action. Bit 3.
Okan Sahin 0:047a7089311e 379 0 = Watchdog timer expire causes power-off.
Okan Sahin 0:047a7089311e 380 1 = Watchdog timer expire causes power-reset. */
Okan Sahin 0:047a7089311e 381 unsigned char wdt_per : 2; /**< Watchdog Timer Period. Bit 5:4.
Okan Sahin 0:047a7089311e 382 0b00 = 16 seconds 0b01 = 32 seconds
Okan Sahin 0:047a7089311e 383 0b10 = 64 seconds 0b11 = 128 seconds. */
Okan Sahin 0:047a7089311e 384 unsigned char rsvd : 2; /**< Reserved. Bit 7:6.
Okan Sahin 0:047a7089311e 385 Unutilized bit. Write to 0. Reads are don't care. */
Okan Sahin 0:047a7089311e 386 } bits;
Okan Sahin 0:047a7089311e 387 } reg_cnfg_wdt_t;
Okan Sahin 0:047a7089311e 388
Okan Sahin 0:047a7089311e 389 /**
Okan Sahin 0:047a7089311e 390 * @brief INT_CHG Register
Okan Sahin 0:047a7089311e 391 *
Okan Sahin 0:047a7089311e 392 * Address : 0x01
Okan Sahin 0:047a7089311e 393 */
Okan Sahin 0:047a7089311e 394 typedef union {
Okan Sahin 0:047a7089311e 395 unsigned char raw;
Okan Sahin 0:047a7089311e 396 struct {
Okan Sahin 0:047a7089311e 397 unsigned char thm_i : 1; /**< Thermistor related interrupt. Bit 0.
Okan Sahin 0:047a7089311e 398 0 = The bits in THM_DTLS[2:0] have not changed since the last time this bit was read
Okan Sahin 0:047a7089311e 399 1 = The bits in THM_DTLS[2:0] have changed since the last time this bit was read */
Okan Sahin 0:047a7089311e 400 unsigned char chg_i : 1; /**< Charger related interrupt. Bit 1.
Okan Sahin 0:047a7089311e 401 0 = The bits in CHG_DTLS[3:0] have not changed since the last time this bit was read
Okan Sahin 0:047a7089311e 402 1 = The bits in CHG_DTLS[3:0] have changed since the last time this bit was read */
Okan Sahin 0:047a7089311e 403 unsigned char chgin_i : 1; /**< CHGIN related interrupt. Bit 2.
Okan Sahin 0:047a7089311e 404 0 = The bits in CHGIN_DTLS[1:0] have not changed since the last time this bit was read
Okan Sahin 0:047a7089311e 405 1 = The bits in CHGIN_DTLS[1:0] have changed since the last time this bit was read */
Okan Sahin 0:047a7089311e 406 unsigned char tj_reg_i : 1; /**< Die junction temperature regulation interrupt. Bit 3.
Okan Sahin 0:047a7089311e 407 0 = The die temperature has not exceeded TJ-REG since the last time this bit was read
Okan Sahin 0:047a7089311e 408 1 = The die temperature has exceeded TJ-REG since the last time this bit was read */
Okan Sahin 0:047a7089311e 409 unsigned char sys_ctrl_i : 1; /**< Minimum System Voltage Regulation-loop related interrupt. Bit 4.
Okan Sahin 0:047a7089311e 410 0 = The minimum system voltage regulation loop has not engaged since the last time this bit was read
Okan Sahin 0:047a7089311e 411 1 = The minimum system voltage regulation loop has engaged since the last time this bit was read */
Okan Sahin 0:047a7089311e 412 unsigned char rsvd : 1; /**< Reserved. Bit 7:5. Unutilized bit. Write to 0. Reads are don't care. */
Okan Sahin 0:047a7089311e 413 } bits;
Okan Sahin 0:047a7089311e 414 } reg_int_chg_t;
Okan Sahin 0:047a7089311e 415
Okan Sahin 0:047a7089311e 416 /**
Okan Sahin 0:047a7089311e 417 * @brief STAT_CHG_A
Okan Sahin 0:047a7089311e 418 *
Okan Sahin 0:047a7089311e 419 * Address : 0x02
Okan Sahin 0:047a7089311e 420 */
Okan Sahin 0:047a7089311e 421 typedef union {
Okan Sahin 0:047a7089311e 422 unsigned char raw;
Okan Sahin 0:047a7089311e 423 struct
Okan Sahin 0:047a7089311e 424 {
Okan Sahin 0:047a7089311e 425 unsigned char thm_dtls : 3; /**< Battery Temperature Details. Bit 2:0.
Okan Sahin 0:047a7089311e 426 0b000 = Thermistor is disabled (THM_EN = 0)
Okan Sahin 0:047a7089311e 427 0b001 = Battery is cold as programmed by THM_COLD[1:0] If thermistor and charger are enabled while the battery is cold, a battery temperature fault will occur.
Okan Sahin 0:047a7089311e 428 0b010 = Battery is cool as programmed by THM_COOL[1:0]
Okan Sahin 0:047a7089311e 429 0b011 = Battery is warm as programmed by THM_WARM[1:0]
Okan Sahin 0:047a7089311e 430 0b100 = Battery is hot as programmed by THM_HOT[1:0]. If thermistor and charger are enabled while the battery is hot, a battery temperature fault will occur.
Okan Sahin 0:047a7089311e 431 0b101 = Battery is in the normal temperature region
Okan Sahin 0:047a7089311e 432 0b110 - 0b111 = reserved */
Okan Sahin 0:047a7089311e 433 unsigned char tj_reg_stat : 1; /**< Maximum Junction Temperature Regulation Loop Status. Bit 3.
Okan Sahin 0:047a7089311e 434 0 = The maximum junction temperature regulation loop is not engaged
Okan Sahin 0:047a7089311e 435 1 = The maximum junction temperature regulation loop has engaged to regulate the junction temperature to less than TJ-REG */
Okan Sahin 0:047a7089311e 436 unsigned char vsys_min_stat : 1; /**< Minimum System Voltage Regulation Loop Status. Bit 4.
Okan Sahin 0:047a7089311e 437 0 = The minimum system voltage regulation loop is not enganged
Okan Sahin 0:047a7089311e 438 1 = The minimum system voltage regulation loop is engaged to regulate VSYS ≥ VSYS-MIN */
Okan Sahin 0:047a7089311e 439 unsigned char rsvd : 3; /**< Reserved. Bit 7:5. Unutilized bit. Write to 0. Reads are don't care. */
Okan Sahin 0:047a7089311e 440 } bits;
Okan Sahin 0:047a7089311e 441 } reg_stat_chg_a_t;
Okan Sahin 0:047a7089311e 442
Okan Sahin 0:047a7089311e 443 /**
Okan Sahin 0:047a7089311e 444 * @brief STAT_CHG_B
Okan Sahin 0:047a7089311e 445 *
Okan Sahin 0:047a7089311e 446 * Address : 0x03
Okan Sahin 0:047a7089311e 447 */
Okan Sahin 0:047a7089311e 448 typedef union {
Okan Sahin 0:047a7089311e 449 unsigned char raw;
Okan Sahin 0:047a7089311e 450 struct
Okan Sahin 0:047a7089311e 451 {
Okan Sahin 0:047a7089311e 452 unsigned char time_sus : 1; /**< Time Suspend Indicator. Bit 0.
Okan Sahin 0:047a7089311e 453 0 = The charger's timers are either not active, or not suspended
Okan Sahin 0:047a7089311e 454 1 = The charger's active timer is suspended due to one of three reasons:
Okan Sahin 0:047a7089311e 455 charge current dropped below 20% of IFAST-CHG while the charger state machine is in FAST CHARGE CC mode,
Okan Sahin 0:047a7089311e 456 the charger is in SUPPLEMENT mode, or the charger state machine is in BATTERY TEMPERATURE FAULT mode. */
Okan Sahin 0:047a7089311e 457 unsigned char chg : 1; /**< Quick Charger Status. Bit 1.
Okan Sahin 0:047a7089311e 458 0 = Charging is not happening
Okan Sahin 0:047a7089311e 459 1 = Charging is happening */
Okan Sahin 0:047a7089311e 460 unsigned char chgin_dtls : 2; /**< CHGIN Status Detail. Bit 3:2.
Okan Sahin 0:047a7089311e 461 0b00 = The CHGIN input voltage is below the UVLO threshold (VCHGIN < VUVLO)
Okan Sahin 0:047a7089311e 462 0b01 = The CHGIN input voltage is above the OVP threshold (VCHGIN > VOVP)
Okan Sahin 0:047a7089311e 463 0b10 = The CHGIN input is being debounced (no power accepted from CHGIN during debounce)
Okan Sahin 0:047a7089311e 464 0b11 = The CHGIN input is okay and debounced */
Okan Sahin 0:047a7089311e 465 unsigned char chg_dtls : 4; /**< Charger Details. Bit 7:4.
Okan Sahin 0:047a7089311e 466 0b0000 = Off
Okan Sahin 0:047a7089311e 467 0b0001 = Prequalification mode
Okan Sahin 0:047a7089311e 468 0b0010 = Fast-charge constant-current (CC) mode
Okan Sahin 0:047a7089311e 469 0b0011 = JEITA modified fast-charge constant-current mode
Okan Sahin 0:047a7089311e 470 0b0100 = Fast-charge constant-voltage (CV) mode
Okan Sahin 0:047a7089311e 471 0b0101 = JEITA modified fast-charge constant-voltage mode
Okan Sahin 0:047a7089311e 472 0b0110 = Top-off mode
Okan Sahin 0:047a7089311e 473 0b0111 = JEITA modified top-off mode
Okan Sahin 0:047a7089311e 474 0b1000 = Done
Okan Sahin 0:047a7089311e 475 0b1001 = JEITA modified done (done was entered through the JEITA-modified fast-charge states)
Okan Sahin 0:047a7089311e 476 0b1010 = Prequalification timer fault
Okan Sahin 0:047a7089311e 477 0b1011 = Fast-charge timer fault
Okan Sahin 0:047a7089311e 478 0b1100 = Battery temperature fault
Okan Sahin 0:047a7089311e 479 0b1101 - 0b1111 = reserved */
Okan Sahin 0:047a7089311e 480 } bits;
Okan Sahin 0:047a7089311e 481 } reg_stat_chg_b_t;
Okan Sahin 0:047a7089311e 482
Okan Sahin 0:047a7089311e 483 /**
Okan Sahin 0:047a7089311e 484 * @brief INT_M_CHG Register
Okan Sahin 0:047a7089311e 485 *
Okan Sahin 0:047a7089311e 486 * Address : 0x07
Okan Sahin 0:047a7089311e 487 */
Okan Sahin 0:047a7089311e 488 typedef union {
Okan Sahin 0:047a7089311e 489 unsigned char raw;
Okan Sahin 0:047a7089311e 490 struct {
Okan Sahin 0:047a7089311e 491 unsigned char thm_m : 1; /**< Setting this bit prevents the THM_I bit from causing hardware IRQs. Bit 0.
Okan Sahin 0:047a7089311e 492 0 = THM_I is not masked
Okan Sahin 0:047a7089311e 493 1 = THM_I is masked */
Okan Sahin 0:047a7089311e 494 unsigned char chg_m : 1; /**< Setting this bit prevents the CHG_I bit from causing hardware IRQs. Bit 1.
Okan Sahin 0:047a7089311e 495 0 = CHG_I is not masked
Okan Sahin 0:047a7089311e 496 1 = CHG_I is masked */
Okan Sahin 0:047a7089311e 497 unsigned char chgin_m : 1; /**< Setting this bit prevents the CHGIN_I bit from causing hardware IRQs. Bit 2.
Okan Sahin 0:047a7089311e 498 0 = CHGIN_I is not masked
Okan Sahin 0:047a7089311e 499 1 = CHGIN_I is masked */
Okan Sahin 0:047a7089311e 500 unsigned char tj_reg_m : 1; /**< Setting this bit prevents the TJREG_I bit from causing hardware IRQs. Bit 3.
Okan Sahin 0:047a7089311e 501 0 = TJREG_I is not masked
Okan Sahin 0:047a7089311e 502 1 = TJREG_I is masked */
Okan Sahin 0:047a7089311e 503 unsigned char sys_ctrl_m : 1; /**< Setting this bit prevents the SYS_CTRL_I bit from causing hardware IRQs. Bit 4.
Okan Sahin 0:047a7089311e 504 0 = SYS_CTRL_I is not masked
Okan Sahin 0:047a7089311e 505 1 = SYS_CTRL_I is masked */
Okan Sahin 0:047a7089311e 506 unsigned char rsvd : 3; /**< Reserved. Bit 7:5. Unutilized bit. Write to 0. Reads are don't care. */
Okan Sahin 0:047a7089311e 507 } bits;
Okan Sahin 0:047a7089311e 508 } reg_int_m_chg_t;
Okan Sahin 0:047a7089311e 509
Okan Sahin 0:047a7089311e 510 /**
Okan Sahin 0:047a7089311e 511 * @brief CNFG_CHG_A
Okan Sahin 0:047a7089311e 512 *
Okan Sahin 0:047a7089311e 513 * Address : 0x20
Okan Sahin 0:047a7089311e 514 */
Okan Sahin 0:047a7089311e 515 typedef union {
Okan Sahin 0:047a7089311e 516 unsigned char raw;
Okan Sahin 0:047a7089311e 517 struct
Okan Sahin 0:047a7089311e 518 {
Okan Sahin 0:047a7089311e 519 unsigned char thm_cold : 2; /**< Sets the VCOLD JEITA Temperature Threshold. Bit 1:0.
Okan Sahin 0:047a7089311e 520 0b00 = VCOLD = 1.024V (-10ºC for β = 3380K)
Okan Sahin 0:047a7089311e 521 0b01 = VCOLD = 0.976V (-5ºC for β = 3380K)
Okan Sahin 0:047a7089311e 522 0b10 = VCOLD = 0.923V (0ºC for β = 3380K)
Okan Sahin 0:047a7089311e 523 0b11 = VCOLD = 0.867V (5ºC for β = 3380K) */
Okan Sahin 0:047a7089311e 524 unsigned char thm_cool : 2; /**< Sets the VCOOL JEITA Temperature Threshold. Bit 3:2.
Okan Sahin 0:047a7089311e 525 0b00 = VCOOL = 0.923V (0ºC for β = 3380K)
Okan Sahin 0:047a7089311e 526 0b01 = VCOOL = 0.867V (5ºC for β = 3380K)
Okan Sahin 0:047a7089311e 527 0b10 = VCOOL = 0.807V (10ºC for β = 3380K)
Okan Sahin 0:047a7089311e 528 0b11 = VCOOL = 0.747V (15ºC for β = 3380K) */
Okan Sahin 0:047a7089311e 529 unsigned char thm_warm : 2; /**< Sets the VWARM JEITA Temperature Threshold. Bit 5:4.
Okan Sahin 0:047a7089311e 530 0b00 = VWARM = 0.511V (35ºC for β = 3380K)
Okan Sahin 0:047a7089311e 531 0b01 = VWARM = 0.459V (40ºC for β = 3380K)
Okan Sahin 0:047a7089311e 532 0b10 = VWARM = 0.411V (45ºC for β = 3380K)
Okan Sahin 0:047a7089311e 533 0b11 = VWARM = 0.367V (50ºC for β = 3380K) */
Okan Sahin 0:047a7089311e 534 unsigned char thm_hot : 2; /**< Sets the VHOT JEITA Temperature Threshold. Bit 7:6.
Okan Sahin 0:047a7089311e 535 0b00 = VHOT = 0.411V (45ºC for β = 3380K)
Okan Sahin 0:047a7089311e 536 0b01 = VHOT = 0.367V (50ºC for β = 3380K)
Okan Sahin 0:047a7089311e 537 0b10 = VHOT = 0.327V (55ºC for β = 3380K)
Okan Sahin 0:047a7089311e 538 0b11 = VHOT = 0.291V (60ºC for β = 3380K) */
Okan Sahin 0:047a7089311e 539 } bits;
Okan Sahin 0:047a7089311e 540 } reg_cnfg_chg_a_t;
Okan Sahin 0:047a7089311e 541
Okan Sahin 0:047a7089311e 542 /**
Okan Sahin 0:047a7089311e 543 * @brief CNFG_CHG_B
Okan Sahin 0:047a7089311e 544 *
Okan Sahin 0:047a7089311e 545 * Address : 0x21
Okan Sahin 0:047a7089311e 546 */
Okan Sahin 0:047a7089311e 547 typedef union {
Okan Sahin 0:047a7089311e 548 unsigned char raw;
Okan Sahin 0:047a7089311e 549 struct
Okan Sahin 0:047a7089311e 550 {
Okan Sahin 0:047a7089311e 551 unsigned char chg_en : 1; /**< Charger Enable. Bit 0.
Okan Sahin 0:047a7089311e 552 0 = the battery charger is disabled
Okan Sahin 0:047a7089311e 553 1 = the battery charger is enabled */
Okan Sahin 0:047a7089311e 554 unsigned char i_pq : 1; /**< Sets the prequalification charge current (IPQ) as a percentage of IFAST-CHG. Bit 1.
Okan Sahin 0:047a7089311e 555 0 = 10% 1 = 20% */
Okan Sahin 0:047a7089311e 556 unsigned char rsvd : 6; /**< Reserved. Bit 7:2. Unutilized bit. Write to 0. Reads are don't care. */
Okan Sahin 0:047a7089311e 557 } bits;
Okan Sahin 0:047a7089311e 558 } reg_cnfg_chg_b_t;
Okan Sahin 0:047a7089311e 559
Okan Sahin 0:047a7089311e 560 /**
Okan Sahin 0:047a7089311e 561 * @brief CNFG_CHG_C
Okan Sahin 0:047a7089311e 562 *
Okan Sahin 0:047a7089311e 563 * Address : 0x22
Okan Sahin 0:047a7089311e 564 */
Okan Sahin 0:047a7089311e 565 typedef union {
Okan Sahin 0:047a7089311e 566 unsigned char raw;
Okan Sahin 0:047a7089311e 567 struct
Okan Sahin 0:047a7089311e 568 {
Okan Sahin 0:047a7089311e 569 unsigned char t_topoff : 3; /**< Top-off timer value (tTO). Bit 2:0.
Okan Sahin 0:047a7089311e 570 0b000 = 0 minutes 0b001 = 5 minutes
Okan Sahin 0:047a7089311e 571 0b010 = 10 minutes 0b011 = 15 minutes
Okan Sahin 0:047a7089311e 572 0b100 = 20 minutes 0b101 = 25 minutes
Okan Sahin 0:047a7089311e 573 0b110 = 30 minutes 0b111 = 35 minutes */
Okan Sahin 0:047a7089311e 574 unsigned char i_term : 2; /**< Charger Termination Current (ITERM). Bit 4:3.
Okan Sahin 0:047a7089311e 575 00 = 5% 01 = 7.5%
Okan Sahin 0:047a7089311e 576 10 = 10% 11 = 15% */
Okan Sahin 0:047a7089311e 577 unsigned char chg_pq : 3; /**< Battery prequalification voltage threshold (VPQ). Bit 7:5.
Okan Sahin 0:047a7089311e 578 0b000 = 2.3V 0b001 = 2.4V
Okan Sahin 0:047a7089311e 579 0b010 = 2.5V 0b011 = 2.6V
Okan Sahin 0:047a7089311e 580 0b100 = 2.7V 0b101 = 2.8V
Okan Sahin 0:047a7089311e 581 0b110 = 2.9V 0b111 = 3.0V */
Okan Sahin 0:047a7089311e 582 } bits;
Okan Sahin 0:047a7089311e 583 } reg_cnfg_chg_c_t;
Okan Sahin 0:047a7089311e 584
Okan Sahin 0:047a7089311e 585 /**
Okan Sahin 0:047a7089311e 586 * @brief CNFG_CHG_D
Okan Sahin 0:047a7089311e 587 *
Okan Sahin 0:047a7089311e 588 * Address : 0x23
Okan Sahin 0:047a7089311e 589 */
Okan Sahin 0:047a7089311e 590 typedef union {
Okan Sahin 0:047a7089311e 591 unsigned char raw;
Okan Sahin 0:047a7089311e 592 struct
Okan Sahin 0:047a7089311e 593 {
Okan Sahin 0:047a7089311e 594 unsigned char vsys_min : 2; /**< Minimum SYS Voltage . Bit 1:0.
Okan Sahin 0:047a7089311e 595 0x0 = 3.2V 0x1 = 3.3V
Okan Sahin 0:047a7089311e 596 0x2 = 3.4V 0x3 = 3.5V */
Okan Sahin 0:047a7089311e 597 unsigned char rsvd : 2; /**< Reserved. Bit 3:2. Unutilized bit. Write to 0. Reads are don't care. */
Okan Sahin 0:047a7089311e 598 unsigned char vsys_hdrm : 1; /**< SYS Headroom Voltage Regulation. Bit 4.
Okan Sahin 0:047a7089311e 599 0b0 = 0.15V 0b1 = 0.20V */
Okan Sahin 0:047a7089311e 600 unsigned char tj_reg : 3; /**< Sets the die junction temperature regulation point, TJ-REG. Bit 7:5.
Okan Sahin 0:047a7089311e 601 0b000 = 60ºC 0b001 = 70ºC
Okan Sahin 0:047a7089311e 602 0b010 = 80ºC 0b011 = 90ºC
Okan Sahin 0:047a7089311e 603 0b100 - 0b111 = 100ºC */
Okan Sahin 0:047a7089311e 604 } bits;
Okan Sahin 0:047a7089311e 605 } reg_cnfg_chg_d_t;
Okan Sahin 0:047a7089311e 606
Okan Sahin 0:047a7089311e 607 /**
Okan Sahin 0:047a7089311e 608 * @brief CNFG_CHG_E
Okan Sahin 0:047a7089311e 609 *
Okan Sahin 0:047a7089311e 610 * Address : 0x25
Okan Sahin 0:047a7089311e 611 */
Okan Sahin 0:047a7089311e 612 typedef union {
Okan Sahin 0:047a7089311e 613 unsigned char raw;
Okan Sahin 0:047a7089311e 614 struct
Okan Sahin 0:047a7089311e 615 {
Okan Sahin 0:047a7089311e 616 unsigned char t_fast_chg : 2; /**< System voltage regulation (VSYS-REG). Bit 1:0.
Okan Sahin 0:047a7089311e 617 0b00 = timer disabled 0b01 = 3 hours
Okan Sahin 0:047a7089311e 618 0b10 = 5 hours 0b11 = 7 hours */
Okan Sahin 0:047a7089311e 619 unsigned char chg_cc : 6; /**< Sets the fast-charge constant current value, IFAST-CHG. Bit 7:2.
Okan Sahin 0:047a7089311e 620 0x0 = 7.5mA 0x1 = 15.0mA
Okan Sahin 0:047a7089311e 621 0x2 = 22.5mA ...
Okan Sahin 0:047a7089311e 622 0x26 = 292.5mA 0x27 - 0x3F = 300.0mA */
Okan Sahin 0:047a7089311e 623 } bits;
Okan Sahin 0:047a7089311e 624 } reg_cnfg_chg_e_t;
Okan Sahin 0:047a7089311e 625
Okan Sahin 0:047a7089311e 626 /**
Okan Sahin 0:047a7089311e 627 * @brief CNFG_CHG_F
Okan Sahin 0:047a7089311e 628 *
Okan Sahin 0:047a7089311e 629 * Address : 0x25
Okan Sahin 0:047a7089311e 630 */
Okan Sahin 0:047a7089311e 631 typedef union {
Okan Sahin 0:047a7089311e 632 unsigned char raw;
Okan Sahin 0:047a7089311e 633 struct
Okan Sahin 0:047a7089311e 634 {
Okan Sahin 0:047a7089311e 635 unsigned char : 1; /**< Bit 0*/
Okan Sahin 0:047a7089311e 636 unsigned char thm_en : 1; /**< Thermistor enable bit. Bit 1.
Okan Sahin 0:047a7089311e 637 0 = Thermistor is disabled
Okan Sahin 0:047a7089311e 638 1 = Thermistor is enabled */
Okan Sahin 0:047a7089311e 639 unsigned char chg_cc_jeita : 6; /**< Sets IFAST-CHG-JEITA for when the battery is either cool or warm as defined
Okan Sahin 0:047a7089311e 640 by the VCOOL and VWARM temperature thresholds. Bit 7:2.
Okan Sahin 0:047a7089311e 641 0x0 = 7.5mA 0x1 = 15.0mA
Okan Sahin 0:047a7089311e 642 0x2 = 22.5mA ...
Okan Sahin 0:047a7089311e 643 0x26 = 292.5mA 0x27 - 0x3F = 300.0mA */
Okan Sahin 0:047a7089311e 644 } bits;
Okan Sahin 0:047a7089311e 645 } reg_cnfg_chg_f_t;
Okan Sahin 0:047a7089311e 646
Okan Sahin 0:047a7089311e 647 /**
Okan Sahin 0:047a7089311e 648 * @brief CNFG_CHG_G
Okan Sahin 0:047a7089311e 649 *
Okan Sahin 0:047a7089311e 650 * Address : 0x26
Okan Sahin 0:047a7089311e 651 */
Okan Sahin 0:047a7089311e 652 typedef union {
Okan Sahin 0:047a7089311e 653 unsigned char raw;
Okan Sahin 0:047a7089311e 654 struct
Okan Sahin 0:047a7089311e 655 {
Okan Sahin 0:047a7089311e 656 unsigned char rsvd : 1; /**< Reserved. Bit 0. Unutilized bit. Write to 0. Reads are don't care.*/
Okan Sahin 0:047a7089311e 657 unsigned char usbs : 1; /**< Setting this bit places CHGIN in USB suspend mode. Bit 1.
Okan Sahin 0:047a7089311e 658 0 = CHGIN is not suspended and may draw current from an adapter source
Okan Sahin 0:047a7089311e 659 1 = CHGIN is suspended and may draw no current from an adapter source */
Okan Sahin 0:047a7089311e 660 unsigned char chg_cv : 6; /**< Sets fast-charge battery regulation voltage, VFAST-CHG. Bit 7:2.
Okan Sahin 0:047a7089311e 661 0x0 = 3.600V 0x1 = 3.625V
Okan Sahin 0:047a7089311e 662 0x2 = 3.650V ...
Okan Sahin 0:047a7089311e 663 0x27 = 4.575V 0x28 - 0x3F = 4.600V */
Okan Sahin 0:047a7089311e 664 } bits;
Okan Sahin 0:047a7089311e 665 } reg_cnfg_chg_g_t;
Okan Sahin 0:047a7089311e 666
Okan Sahin 0:047a7089311e 667 /**
Okan Sahin 0:047a7089311e 668 * @brief CNFG_CHG_H
Okan Sahin 0:047a7089311e 669 *
Okan Sahin 0:047a7089311e 670 * Address : 0x27
Okan Sahin 0:047a7089311e 671 */
Okan Sahin 0:047a7089311e 672 typedef union {
Okan Sahin 0:047a7089311e 673 unsigned char raw;
Okan Sahin 0:047a7089311e 674 struct
Okan Sahin 0:047a7089311e 675 {
Okan Sahin 0:047a7089311e 676 unsigned char rsvd : 2; /**< Reserved. Bit 1:0. Unutilized bit. Write to 0. Reads are don't care.*/
Okan Sahin 0:047a7089311e 677 unsigned char chg_cv_jeita : 6; /**< Sets fast-charge battery regulation voltage, VFAST-CHG. Bit 7:2.
Okan Sahin 0:047a7089311e 678 0x0 = 3.600V 0x1 = 3.625V
Okan Sahin 0:047a7089311e 679 0x2 = 3.650V ...
Okan Sahin 0:047a7089311e 680 0x27 = 4.575V 0x28 - 0x3F = 4.600V */
Okan Sahin 0:047a7089311e 681 } bits;
Okan Sahin 0:047a7089311e 682 } reg_cnfg_chg_h_t;
Okan Sahin 0:047a7089311e 683
Okan Sahin 0:047a7089311e 684 /**
Okan Sahin 0:047a7089311e 685 * @brief CNFG_CHG_I
Okan Sahin 0:047a7089311e 686 *
Okan Sahin 0:047a7089311e 687 * Address : 0x28
Okan Sahin 0:047a7089311e 688 */
Okan Sahin 0:047a7089311e 689 typedef union {
Okan Sahin 0:047a7089311e 690 unsigned char raw;
Okan Sahin 0:047a7089311e 691 struct
Okan Sahin 0:047a7089311e 692 {
Okan Sahin 0:047a7089311e 693 unsigned char mux_sel : 4; /**< Selects the analog channel to connect to AMUX. Bit 3:0.
Okan Sahin 0:047a7089311e 694 0b0000 = Multiplexer is disabled and AMUX is high-impedance.
Okan Sahin 0:047a7089311e 695 0b0001 = CHGIN voltage monitor.
Okan Sahin 0:047a7089311e 696 0b0010 = CHGIN current monitor.
Okan Sahin 0:047a7089311e 697 0b0011 = BATT voltage monitor.
Okan Sahin 0:047a7089311e 698 0b0100 = BATT charge current monitor. Valid only while battery charging is happening (CHG = 1).
Okan Sahin 0:047a7089311e 699 0b0101 = BATT discharge current monitor normal measurement.
Okan Sahin 0:047a7089311e 700 0b0110 = BATT discharge current monitor nulling measurement.
Okan Sahin 0:047a7089311e 701 0b0111 = THM voltage monitor 0b1000 = TBIAS voltage monitor
Okan Sahin 0:047a7089311e 702 0b1001 = AGND voltage monitor (through 100Ω pull-down resistor)
Okan Sahin 0:047a7089311e 703 0b1010 - 0b1111 = SYS voltage monitor */
Okan Sahin 0:047a7089311e 704 unsigned char imon_dischg_scale : 4; /**< Selects the battery discharge current full-scale current value. Bit 7:4.
Okan Sahin 0:047a7089311e 705 0x0 = 8.2mA 0x1 = 40.5mA 0x2 = 72.3mA
Okan Sahin 0:047a7089311e 706 0x3 = 103.4mA 0x4 = 134.1mA
Okan Sahin 0:047a7089311e 707 0x5 = 164.1mA 0x6 = 193.7mA
Okan Sahin 0:047a7089311e 708 0x7 = 222.7mA 0x8 = 251.2mA
Okan Sahin 0:047a7089311e 709 0x9 = 279.3mA 0xA - 0xF = 300.0mA */
Okan Sahin 0:047a7089311e 710 } bits;
Okan Sahin 0:047a7089311e 711 } reg_cnfg_chg_i_t;
Okan Sahin 0:047a7089311e 712
Okan Sahin 0:047a7089311e 713 /**
Okan Sahin 0:047a7089311e 714 * @brief CNFG_SBB0_A
Okan Sahin 0:047a7089311e 715 *
Okan Sahin 0:047a7089311e 716 * Address : 0x29
Okan Sahin 0:047a7089311e 717 */
Okan Sahin 0:047a7089311e 718 typedef union {
Okan Sahin 0:047a7089311e 719 unsigned char raw;
Okan Sahin 0:047a7089311e 720 struct
Okan Sahin 0:047a7089311e 721 {
Okan Sahin 0:047a7089311e 722 unsigned char tv_sbb0 : 7; /**< SIMO Buck-Boost Channel 0 Target Output Voltage. Bit 6:0.
Okan Sahin 0:047a7089311e 723 0x00 = 0.500V 0x01 = 0.525V 0x02 = 0.550V
Okan Sahin 0:047a7089311e 724 0x03 = 0.575V 0x04 = 0.600V
Okan Sahin 0:047a7089311e 725 ...
Okan Sahin 0:047a7089311e 726 0x30 = 1.700V 0x31 = 1.750V 0x32 = 1.800V
Okan Sahin 0:047a7089311e 727 ...
Okan Sahin 0:047a7089311e 728 0x7B = 5.450V 0x7C = 5.500V
Okan Sahin 0:047a7089311e 729 0x7D to 0x7F = Reserved */
Okan Sahin 0:047a7089311e 730 unsigned char : 1; /**< Bit 7. */
Okan Sahin 0:047a7089311e 731 } bits;
Okan Sahin 0:047a7089311e 732 } reg_cnfg_sbb0_a_t;
Okan Sahin 0:047a7089311e 733
Okan Sahin 0:047a7089311e 734 /**
Okan Sahin 0:047a7089311e 735 * @brief CNFG_SBB0_B
Okan Sahin 0:047a7089311e 736 *
Okan Sahin 0:047a7089311e 737 * Address : 0x2A
Okan Sahin 0:047a7089311e 738 */
Okan Sahin 0:047a7089311e 739 typedef union {
Okan Sahin 0:047a7089311e 740 unsigned char raw;
Okan Sahin 0:047a7089311e 741 struct
Okan Sahin 0:047a7089311e 742 {
Okan Sahin 0:047a7089311e 743 unsigned char en_sbb0 : 3; /**< Enable Control for SIMO Buck-Boost Channel 0,
Okan Sahin 0:047a7089311e 744 selecting either an FPS slot the channel powers-up and powers-down in
Okan Sahin 0:047a7089311e 745 or whether the channel is forced on or off. Bit 2:0.
Okan Sahin 0:047a7089311e 746 0b000 = FPS slot 0 0b001 = FPS slot 1
Okan Sahin 0:047a7089311e 747 0b010 = FPS slot 2 0b011 = FPS slot 3
Okan Sahin 0:047a7089311e 748 0b100 = Off irrespective of FPS
Okan Sahin 0:047a7089311e 749 0b101 = same as 0b100 0b110 = On irrespective of FPS
Okan Sahin 0:047a7089311e 750 0b111 = same as 0b110 */
Okan Sahin 0:047a7089311e 751 unsigned char ade_sbb0 : 1; /**< SIMO Buck-Boost Channel 0 Active-Discharge Enable. Bit 3.
Okan Sahin 0:047a7089311e 752 0 = The active discharge function is disabled.
Okan Sahin 0:047a7089311e 753 When SBB0 is disabled, its discharge rate is a function of the output capacitance and the external load.
Okan Sahin 0:047a7089311e 754 1 = The active discharge function is enabled.
Okan Sahin 0:047a7089311e 755 When SBB0 is disabled, an internal resistor (RAD_SBB0) is activated from SBB0 to PGND to help the output voltage discharge. */
Okan Sahin 0:047a7089311e 756 unsigned char : 2; /**< Bit 5:4*/
Okan Sahin 0:047a7089311e 757 unsigned char op_mode : 1; /**< Operation mode of SBB0. Bit 6.
Okan Sahin 0:047a7089311e 758 0 = Buck-Boost Mode
Okan Sahin 0:047a7089311e 759 1 = Buck Mode*/
Okan Sahin 0:047a7089311e 760 unsigned char rsvd : 1; /**< Reserved. Bit 7. Unutilized bit. Write to 0. Reads are don't care.*/
Okan Sahin 0:047a7089311e 761 } bits;
Okan Sahin 0:047a7089311e 762 } reg_cnfg_sbb0_b_t;
Okan Sahin 0:047a7089311e 763
Okan Sahin 0:047a7089311e 764 /**
Okan Sahin 0:047a7089311e 765 * @brief CNFG_SBB1_A
Okan Sahin 0:047a7089311e 766 *
Okan Sahin 0:047a7089311e 767 * Address : 0x2B
Okan Sahin 0:047a7089311e 768 */
Okan Sahin 0:047a7089311e 769 typedef union {
Okan Sahin 0:047a7089311e 770 unsigned char raw;
Okan Sahin 0:047a7089311e 771 struct
Okan Sahin 0:047a7089311e 772 {
Okan Sahin 0:047a7089311e 773 unsigned char tv_sbb1 : 7; /**< SIMO Buck-Boost Channel 1 Target Output Voltage. Bit 6:0.
Okan Sahin 0:047a7089311e 774 0x00 = 0.500V 0x01 = 0.525V 0x02 = 0.550V
Okan Sahin 0:047a7089311e 775 0x03 = 0.575V 0x04 = 0.600V
Okan Sahin 0:047a7089311e 776 ...
Okan Sahin 0:047a7089311e 777 0x30 = 1.700V 0x31 = 1.750V 0x32 = 1.800V
Okan Sahin 0:047a7089311e 778 ...
Okan Sahin 0:047a7089311e 779 0x7B = 5.450V 0x7C = 5.500V
Okan Sahin 0:047a7089311e 780 0x7D to 0x7F = Reserved */
Okan Sahin 0:047a7089311e 781 unsigned char : 1; /**< Bit 7. */
Okan Sahin 0:047a7089311e 782 } bits;
Okan Sahin 0:047a7089311e 783 } reg_cnfg_sbb1_a_t;
Okan Sahin 0:047a7089311e 784
Okan Sahin 0:047a7089311e 785 /**
Okan Sahin 0:047a7089311e 786 * @brief CNFG_SBB1_B
Okan Sahin 0:047a7089311e 787 *
Okan Sahin 0:047a7089311e 788 * Address : 0x2C
Okan Sahin 0:047a7089311e 789 */
Okan Sahin 0:047a7089311e 790 typedef union {
Okan Sahin 0:047a7089311e 791 unsigned char raw;
Okan Sahin 0:047a7089311e 792 struct
Okan Sahin 0:047a7089311e 793 {
Okan Sahin 0:047a7089311e 794 unsigned char en_sbb1 : 3; /**< Enable Control for SIMO Buck-Boost Channel 1,
Okan Sahin 0:047a7089311e 795 selecting either an FPS slot the channel powers-up and powers-down in
Okan Sahin 0:047a7089311e 796 or whether the channel is forced on or off. Bit 2:0.
Okan Sahin 0:047a7089311e 797 0b000 = FPS slot 0 0b001 = FPS slot 1
Okan Sahin 0:047a7089311e 798 0b010 = FPS slot 2 0b011 = FPS slot 3
Okan Sahin 0:047a7089311e 799 0b100 = Off irrespective of FPS
Okan Sahin 0:047a7089311e 800 0b101 = same as 0b100 0b110 = On irrespective of FPS
Okan Sahin 0:047a7089311e 801 0b111 = same as 0b110 */
Okan Sahin 0:047a7089311e 802 unsigned char ade_sbb1 : 1; /**< SIMO Buck-Boost Channel 1 Active-Discharge Enable. Bit 3.
Okan Sahin 0:047a7089311e 803 0 = The active discharge function is disabled.
Okan Sahin 0:047a7089311e 804 When SBB0 is disabled, its discharge rate is a function of the output capacitance and the external load.
Okan Sahin 0:047a7089311e 805 1 = The active discharge function is enabled.
Okan Sahin 0:047a7089311e 806 When SBB0 is disabled, an internal resistor (RAD_SBB0) is activated from SBB0 to PGND to help the output voltage discharge. */
Okan Sahin 0:047a7089311e 807 unsigned char : 2; /**< Bit 5:4.*/
Okan Sahin 0:047a7089311e 808 unsigned char op_mode : 1; /**< Operation mode of SBB1. Bit 6.
Okan Sahin 0:047a7089311e 809 0 = Buck-Boost Mode
Okan Sahin 0:047a7089311e 810 1 = Buck Mode*/
Okan Sahin 0:047a7089311e 811 unsigned char rsvd : 1; /**< Reserved. Bit 7. Unutilized bit. Write to 0. Reads are don't care.*/
Okan Sahin 0:047a7089311e 812 } bits;
Okan Sahin 0:047a7089311e 813 } reg_cnfg_sbb1_b_t;
Okan Sahin 0:047a7089311e 814
Okan Sahin 0:047a7089311e 815 /**
Okan Sahin 0:047a7089311e 816 * @brief CNFG_SBB2_A
Okan Sahin 0:047a7089311e 817 *
Okan Sahin 0:047a7089311e 818 * Address : 0x2D
Okan Sahin 0:047a7089311e 819 */
Okan Sahin 0:047a7089311e 820 typedef union {
Okan Sahin 0:047a7089311e 821 unsigned char raw;
Okan Sahin 0:047a7089311e 822 struct
Okan Sahin 0:047a7089311e 823 {
Okan Sahin 0:047a7089311e 824 unsigned char tv_sbb2 : 7; /**< SIMO Buck-Boost Channel 2 Target Output Voltage. Bit 6:0.
Okan Sahin 0:047a7089311e 825 0x00 = 0.500V 0x01 = 0.525V 0x02 = 0.550V
Okan Sahin 0:047a7089311e 826 0x03 = 0.575V 0x04 = 0.600V
Okan Sahin 0:047a7089311e 827 ...
Okan Sahin 0:047a7089311e 828 0x30 = 1.700V 0x31 = 1.750V 0x32 = 1.800V
Okan Sahin 0:047a7089311e 829 ...
Okan Sahin 0:047a7089311e 830 0x7B = 5.450V 0x7C = 5.500V
Okan Sahin 0:047a7089311e 831 0x7D to 0x7F = Reserved */
Okan Sahin 0:047a7089311e 832 unsigned char : 1; /**< Bit 7. */
Okan Sahin 0:047a7089311e 833 } bits;
Okan Sahin 0:047a7089311e 834 } reg_cnfg_sbb2_a_t;
Okan Sahin 0:047a7089311e 835
Okan Sahin 0:047a7089311e 836 /**
Okan Sahin 0:047a7089311e 837 * @brief CNFG_SBB2_B
Okan Sahin 0:047a7089311e 838 *
Okan Sahin 0:047a7089311e 839 * Address : 0x2E
Okan Sahin 0:047a7089311e 840 */
Okan Sahin 0:047a7089311e 841 typedef union {
Okan Sahin 0:047a7089311e 842 unsigned char raw;
Okan Sahin 0:047a7089311e 843 struct
Okan Sahin 0:047a7089311e 844 {
Okan Sahin 0:047a7089311e 845 unsigned char en_sbb2 : 3; /**< Enable Control for SIMO Buck-Boost Channel 2,
Okan Sahin 0:047a7089311e 846 selecting either an FPS slot the channel powers-up and powers-down in
Okan Sahin 0:047a7089311e 847 or whether the channel is forced on or off. Bit 2:0.
Okan Sahin 0:047a7089311e 848 0b000 = FPS slot 0 0b001 = FPS slot 1
Okan Sahin 0:047a7089311e 849 0b010 = FPS slot 2 0b011 = FPS slot 3
Okan Sahin 0:047a7089311e 850 0b100 = Off irrespective of FPS
Okan Sahin 0:047a7089311e 851 0b101 = same as 0b100 0b110 = On irrespective of FPS
Okan Sahin 0:047a7089311e 852 0b111 = same as 0b110 */
Okan Sahin 0:047a7089311e 853 unsigned char ade_sbb2 : 1; /**< SIMO Buck-Boost Channel 2 Active-Discharge Enable Bit 3.
Okan Sahin 0:047a7089311e 854 0 = The active discharge function is disabled.
Okan Sahin 0:047a7089311e 855 When SBB0 is disabled, its discharge rate is a function of the output capacitance and the external load.
Okan Sahin 0:047a7089311e 856 1 = The active discharge function is enabled.
Okan Sahin 0:047a7089311e 857 When SBB0 is disabled, an internal resistor (RAD_SBB0) is activated from SBB0 to PGND to help the output voltage discharge. */
Okan Sahin 0:047a7089311e 858 unsigned char : 2; /**< Bit 5:4. */
Okan Sahin 0:047a7089311e 859 unsigned char op_mode : 1; /**< Operation mode of SBB2. Bit 6.
Okan Sahin 0:047a7089311e 860 0 = Buck-Boost Mode
Okan Sahin 0:047a7089311e 861 1 = Buck Mode*/
Okan Sahin 0:047a7089311e 862 unsigned char rsvd : 1; /**< Reserved. Bit 7. Unutilized bit. Write to 0. Reads are don't care.*/
Okan Sahin 0:047a7089311e 863 } bits;
Okan Sahin 0:047a7089311e 864 } reg_cnfg_sbb2_b_t;
Okan Sahin 0:047a7089311e 865
Okan Sahin 0:047a7089311e 866 /**
Okan Sahin 0:047a7089311e 867 * @brief CNFG_SBB_TOP
Okan Sahin 0:047a7089311e 868 *
Okan Sahin 0:047a7089311e 869 * Address : 0x2F
Okan Sahin 0:047a7089311e 870 */
Okan Sahin 0:047a7089311e 871 typedef union {
Okan Sahin 0:047a7089311e 872 unsigned char raw;
Okan Sahin 0:047a7089311e 873 struct
Okan Sahin 0:047a7089311e 874 {
Okan Sahin 0:047a7089311e 875 unsigned char drv_sbb : 2; /**< SIMO Buck-Boost (all channels) Drive Strength Trim. Bit 1:0.
Okan Sahin 0:047a7089311e 876 0b00 = fastest transition time
Okan Sahin 0:047a7089311e 877 0b01 = a little slower than 0b00
Okan Sahin 0:047a7089311e 878 0b10 = a little slower than 0b01
Okan Sahin 0:047a7089311e 879 0b11 = a little slower than 0b10 */
Okan Sahin 0:047a7089311e 880 unsigned char : 5; /**< Bit 6:2. */
Okan Sahin 0:047a7089311e 881 unsigned char op_mode_chg : 1; /**< Operation mode of the charging channel of SIMO. Bit 7.
Okan Sahin 0:047a7089311e 882 0 = Buck-boost mode
Okan Sahin 0:047a7089311e 883 1 = Buck mode */
Okan Sahin 0:047a7089311e 884 } bits;
Okan Sahin 0:047a7089311e 885 } reg_cnfg_sbb_top_t;
Okan Sahin 0:047a7089311e 886
Okan Sahin 0:047a7089311e 887 /**
Okan Sahin 0:047a7089311e 888 * @brief CNFG_SBB_TOP_B
Okan Sahin 0:047a7089311e 889 *
Okan Sahin 0:047a7089311e 890 * Address : 0x30
Okan Sahin 0:047a7089311e 891 */
Okan Sahin 0:047a7089311e 892 typedef union {
Okan Sahin 0:047a7089311e 893 unsigned char raw;
Okan Sahin 0:047a7089311e 894 struct
Okan Sahin 0:047a7089311e 895 {
Okan Sahin 0:047a7089311e 896 unsigned char ip_sbb0 : 2; /**< SIMO Buck-Boost Channel 0 Peak Current Limit. Bit 1:0.
Okan Sahin 0:047a7089311e 897 0b00 = 1.000A
Okan Sahin 0:047a7089311e 898 0b01 = 0.750A
Okan Sahin 0:047a7089311e 899 0b10 = 0.500A
Okan Sahin 0:047a7089311e 900 0b11 = 0.333A */
Okan Sahin 0:047a7089311e 901 unsigned char ip_sbb1 : 2; /**< SIMO Buck-Boost Channel 1 Peak Current Limit. Bit 3:2.
Okan Sahin 0:047a7089311e 902 0b00 = 1.000A
Okan Sahin 0:047a7089311e 903 0b01 = 0.750A
Okan Sahin 0:047a7089311e 904 0b10 = 0.500A
Okan Sahin 0:047a7089311e 905 0b11 = 0.333A */
Okan Sahin 0:047a7089311e 906 unsigned char ip_sbb2 : 2; /**< SIMO Buck-Boost Channel 2 Peak Current Limit. Bit 5:4.
Okan Sahin 0:047a7089311e 907 0b00 = 1.000A
Okan Sahin 0:047a7089311e 908 0b01 = 0.750A
Okan Sahin 0:047a7089311e 909 0b10 = 0.500A
Okan Sahin 0:047a7089311e 910 0b11 = 0.333A */
Okan Sahin 0:047a7089311e 911 unsigned char ip_chg : 2; /**< SIMO Buck-Boost Charging Channel Peak Current Limit. Bit 7:6.
Okan Sahin 0:047a7089311e 912 0b00 = 2.000A
Okan Sahin 0:047a7089311e 913 0b01 = 1.500A
Okan Sahin 0:047a7089311e 914 0b10 = 1.000A
Okan Sahin 0:047a7089311e 915 0b11 = 0.500A */
Okan Sahin 0:047a7089311e 916 } bits;
Okan Sahin 0:047a7089311e 917 } reg_cnfg_sbb_top_b_t;
Okan Sahin 0:047a7089311e 918
Okan Sahin 0:047a7089311e 919 /**
Okan Sahin 0:047a7089311e 920 * @brief CNFG_LDO0_A
Okan Sahin 0:047a7089311e 921 *
Okan Sahin 0:047a7089311e 922 * Address : 0x38
Okan Sahin 0:047a7089311e 923 */
Okan Sahin 0:047a7089311e 924 typedef union {
Okan Sahin 0:047a7089311e 925 unsigned char raw;
Okan Sahin 0:047a7089311e 926 struct
Okan Sahin 0:047a7089311e 927 {
Okan Sahin 0:047a7089311e 928 unsigned char tv_ldo_volt : 7; /**< LDO Target Output Voltage This 7-bit configuration is a linear transfer function
Okan Sahin 0:047a7089311e 929 that starts at 0.5V and ends at 3.675V, with 25mV increments. Bit 6:0.
Okan Sahin 0:047a7089311e 930 0x00 = 0.500V 0x01 = 0.525V
Okan Sahin 0:047a7089311e 931 0x02 = 0.550V 0x03 = 0.575V
Okan Sahin 0:047a7089311e 932 0x04 = 0.600V 0x05 = 0.625V
Okan Sahin 0:047a7089311e 933 0x06 = 0.650V ...
Okan Sahin 0:047a7089311e 934 0x7D = 3.625V 0x7E = 3.650V
Okan Sahin 0:047a7089311e 935 0x7F = 3.675V */
Okan Sahin 0:047a7089311e 936 unsigned char tv_ldo_offset : 1; /**< LDO Output Voltage. This bit applies a 1.325V offset to the output voltage of the LDO. Bit 7.
Okan Sahin 0:047a7089311e 937 0b0 = No offset 0b1 = 1.325V offset*/
Okan Sahin 0:047a7089311e 938 } bits;
Okan Sahin 0:047a7089311e 939 } reg_cnfg_ldo0_a_t;
Okan Sahin 0:047a7089311e 940
Okan Sahin 0:047a7089311e 941 /**
Okan Sahin 0:047a7089311e 942 * @brief CNFG_LDO0_B
Okan Sahin 0:047a7089311e 943 *
Okan Sahin 0:047a7089311e 944 * Address : 0x39
Okan Sahin 0:047a7089311e 945 */
Okan Sahin 0:047a7089311e 946 typedef union {
Okan Sahin 0:047a7089311e 947 unsigned char raw;
Okan Sahin 0:047a7089311e 948 struct
Okan Sahin 0:047a7089311e 949 {
Okan Sahin 0:047a7089311e 950 unsigned char en_ldo : 3; /**< Enable Control for LDO0, selecting either an FPS slot the channel powers-up and
Okan Sahin 0:047a7089311e 951 powers-down in or whether the channel is forced on or off. Bit 2:0.
Okan Sahin 0:047a7089311e 952 0b000 = FPS slot 0 0b001 = FPS slot 1
Okan Sahin 0:047a7089311e 953 0b010 = FPS slot 2 0b011 = FPS slot 3
Okan Sahin 0:047a7089311e 954 0b100 = Off irrespective of FPS
Okan Sahin 0:047a7089311e 955 0b101 = same as 0b100
Okan Sahin 0:047a7089311e 956 0b110 = On irrespective of FPS
Okan Sahin 0:047a7089311e 957 0b111 = same as 0b110 */
Okan Sahin 0:047a7089311e 958 unsigned char ade_ldo : 1; /**< LDO0 Active-Discharge Enable. Bit 3.
Okan Sahin 0:047a7089311e 959 0 = The active discharge function is disabled.
Okan Sahin 0:047a7089311e 960 1 = The active discharge function is enabled. */
Okan Sahin 0:047a7089311e 961 unsigned char ldo_md : 1; /**< Operation mode of LDO0. Bit 4.
Okan Sahin 0:047a7089311e 962 0 = Low Dropout Linear Regulator (LDO) Mode
Okan Sahin 0:047a7089311e 963 1 = Load Switch (LSW) Mode */
Okan Sahin 0:047a7089311e 964 unsigned char rsvd : 3; /**< Bit 7:5. Reserved. Unutilized bit. Write to 0. Reads are don't care. */
Okan Sahin 0:047a7089311e 965 } bits;
Okan Sahin 0:047a7089311e 966 } reg_cnfg_ldo0_b_t;
Okan Sahin 0:047a7089311e 967
Okan Sahin 0:047a7089311e 968 #endif /* MAX77659_REGS_H_ */