Maxim Integrated
MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output BuckBoost, 1-LDO for Long Battery Life Mbed Driver
MAX77643_2.h@0:55f664e8c56c, 21 months ago (annotated)
- Committer:
- Okan Sahin
- Date:
- Fri Aug 26 14:20:53 2022 +0300
- Revision:
- 0:55f664e8c56c
Initial Commit
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Okan Sahin |
0:55f664e8c56c | 1 | /******************************************************************************* |
| Okan Sahin |
0:55f664e8c56c | 2 | * Copyright(C) Analog Devices Inc., All Rights Reserved. |
| Okan Sahin |
0:55f664e8c56c | 3 | * |
| Okan Sahin |
0:55f664e8c56c | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| Okan Sahin |
0:55f664e8c56c | 5 | * copy of this software and associated documentation files(the "Software"), |
| Okan Sahin |
0:55f664e8c56c | 6 | * to deal in the Software without restriction, including without limitation |
| Okan Sahin |
0:55f664e8c56c | 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| Okan Sahin |
0:55f664e8c56c | 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| Okan Sahin |
0:55f664e8c56c | 9 | * Software is furnished to do so, subject to the following conditions: |
| Okan Sahin |
0:55f664e8c56c | 10 | * |
| Okan Sahin |
0:55f664e8c56c | 11 | * The above copyright notice and this permission notice shall be included |
| Okan Sahin |
0:55f664e8c56c | 12 | * in all copies or substantial portions of the Software. |
| Okan Sahin |
0:55f664e8c56c | 13 | * |
| Okan Sahin |
0:55f664e8c56c | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| Okan Sahin |
0:55f664e8c56c | 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| Okan Sahin |
0:55f664e8c56c | 16 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| Okan Sahin |
0:55f664e8c56c | 17 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
| Okan Sahin |
0:55f664e8c56c | 18 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| Okan Sahin |
0:55f664e8c56c | 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| Okan Sahin |
0:55f664e8c56c | 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| Okan Sahin |
0:55f664e8c56c | 21 | * |
| Okan Sahin |
0:55f664e8c56c | 22 | * Except as contained in this notice, the name of Analog Devices Inc. |
| Okan Sahin |
0:55f664e8c56c | 23 | * shall not be used except as stated in the Analog Devices Inc. |
| Okan Sahin |
0:55f664e8c56c | 24 | * Branding Policy. |
| Okan Sahin |
0:55f664e8c56c | 25 | * |
| Okan Sahin |
0:55f664e8c56c | 26 | * The mere transfer of this software does not imply any licenses |
| Okan Sahin |
0:55f664e8c56c | 27 | * of trade secrets, proprietary technology, copyrights, patents, |
| Okan Sahin |
0:55f664e8c56c | 28 | * trademarks, maskwork rights, or any other form of intellectual |
| Okan Sahin |
0:55f664e8c56c | 29 | * property whatsoever. Analog Devices Inc.retains all ownership rights. |
| Okan Sahin |
0:55f664e8c56c | 30 | ******************************************************************************* |
| Okan Sahin |
0:55f664e8c56c | 31 | */ |
| Okan Sahin |
0:55f664e8c56c | 32 | |
| Okan Sahin |
0:55f664e8c56c | 33 | #ifndef _MAX77643_2_H_ |
| Okan Sahin |
0:55f664e8c56c | 34 | #define _MAX77643_2_H_ |
| Okan Sahin |
0:55f664e8c56c | 35 | |
| Okan Sahin |
0:55f664e8c56c | 36 | #include "mbed.h" |
| Okan Sahin |
0:55f664e8c56c | 37 | #include "MAX77643_2_regs.h" |
| Okan Sahin |
0:55f664e8c56c | 38 | |
| Okan Sahin |
0:55f664e8c56c | 39 | #define MAX77643_2_NO_ERROR 0 |
| Okan Sahin |
0:55f664e8c56c | 40 | #define MAX77643_2_VALUE_NULL -1 |
| Okan Sahin |
0:55f664e8c56c | 41 | #define MAX77643_2_WRITE_DATA_FAILED -2 |
| Okan Sahin |
0:55f664e8c56c | 42 | #define MAX77643_2_READ_DATA_FAILED -3 |
| Okan Sahin |
0:55f664e8c56c | 43 | #define MAX77643_2_INVALID_DATA -4 |
| Okan Sahin |
0:55f664e8c56c | 44 | |
| Okan Sahin |
0:55f664e8c56c | 45 | #define MAX77643_2_I2C_ADDRESS 0x90 |
| Okan Sahin |
0:55f664e8c56c | 46 | |
| Okan Sahin |
0:55f664e8c56c | 47 | /** |
| Okan Sahin |
0:55f664e8c56c | 48 | * @brief MAX77643_2 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, |
| Okan Sahin |
0:55f664e8c56c | 49 | * 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications |
| Okan Sahin |
0:55f664e8c56c | 50 | * |
| Okan Sahin |
0:55f664e8c56c | 51 | * @details The MAX77643_2/MAX77643_2 provide power supply solutions for low-power applications where size and efficiency |
| Okan Sahin |
0:55f664e8c56c | 52 | * are critical. The MAX77643_2's SIMO and LDO output voltages are individually programmable through resistors. |
| Okan Sahin |
0:55f664e8c56c | 53 | * |
| Okan Sahin |
0:55f664e8c56c | 54 | * @code |
| Okan Sahin |
0:55f664e8c56c | 55 | * @endcode |
| Okan Sahin |
0:55f664e8c56c | 56 | */ |
| Okan Sahin |
0:55f664e8c56c | 57 | |
| Okan Sahin |
0:55f664e8c56c | 58 | class MAX77643_2 |
| Okan Sahin |
0:55f664e8c56c | 59 | { |
| Okan Sahin |
0:55f664e8c56c | 60 | private: |
| Okan Sahin |
0:55f664e8c56c | 61 | I2C *i2c_handler; |
| Okan Sahin |
0:55f664e8c56c | 62 | InterruptIn *irq_pin; // interrupt pin |
| Okan Sahin |
0:55f664e8c56c | 63 | |
| Okan Sahin |
0:55f664e8c56c | 64 | /** |
| Okan Sahin |
0:55f664e8c56c | 65 | * @brief Register Addresses |
| Okan Sahin |
0:55f664e8c56c | 66 | * @details Enumerated MAX77643_2 register addresses |
| Okan Sahin |
0:55f664e8c56c | 67 | */ |
| Okan Sahin |
0:55f664e8c56c | 68 | typedef enum { |
| Okan Sahin |
0:55f664e8c56c | 69 | /*Global*/ |
| Okan Sahin |
0:55f664e8c56c | 70 | INT_GLBL0 = 0x00, // Interrupt Status 0 |
| Okan Sahin |
0:55f664e8c56c | 71 | INT_GLBL1 = 0x01, // Interrupt Status 1 |
| Okan Sahin |
0:55f664e8c56c | 72 | ERCFLAG = 0x02, // Flags |
| Okan Sahin |
0:55f664e8c56c | 73 | STAT_GLBL = 0x03, // Global Status |
| Okan Sahin |
0:55f664e8c56c | 74 | INTM_GLBL0 = 0x04, // Interrupt Mask 0 |
| Okan Sahin |
0:55f664e8c56c | 75 | INTM_GLBL1 = 0x05, // Interrupt Mask 1 |
| Okan Sahin |
0:55f664e8c56c | 76 | CNFG_GLBL0 = 0x06, // Configuration Global 0 |
| Okan Sahin |
0:55f664e8c56c | 77 | CNFG_GLBL1 = 0x07, // Configuration Global 1 |
| Okan Sahin |
0:55f664e8c56c | 78 | CNFG_GPIO0 = 0x08, // GPIO0 Configuration |
| Okan Sahin |
0:55f664e8c56c | 79 | CNFG_GPIO1 = 0x09, // GPIO1 Configuration |
| Okan Sahin |
0:55f664e8c56c | 80 | CID = 0x10, // Chip Identification Code |
| Okan Sahin |
0:55f664e8c56c | 81 | CNFG_WDT = 0x17, // Configuration WatchDog Timer |
| Okan Sahin |
0:55f664e8c56c | 82 | /*SBB*/ |
| Okan Sahin |
0:55f664e8c56c | 83 | CNFG_SBB_TOP = 0x28, // SIMO Buck-Boost Configuration |
| Okan Sahin |
0:55f664e8c56c | 84 | CNFG_SBB0_A = 0x29, // SIMO Buck-Boost 0 Configuration A |
| Okan Sahin |
0:55f664e8c56c | 85 | CNFG_SBB0_B = 0x2A, // SIMO Buck-Boost 0 Configuration B |
| Okan Sahin |
0:55f664e8c56c | 86 | CNFG_SBB1_A = 0x2B, // SIMO Buck-Boost 1 Configuration A |
| Okan Sahin |
0:55f664e8c56c | 87 | CNFG_SBB1_B = 0x2C, // SIMO Buck-Boost 1 Configuration B |
| Okan Sahin |
0:55f664e8c56c | 88 | CNFG_SBB2_A = 0x2D, // SIMO Buck-Boost 2 Configuration A |
| Okan Sahin |
0:55f664e8c56c | 89 | CNFG_SBB2_B = 0x2E, // SIMO Buck-Boost 2 Configuration B |
| Okan Sahin |
0:55f664e8c56c | 90 | CNFG_DVS_SBB0_A = 0x2F, // SIMO Buck-Boost 0 DVS Configuration A |
| Okan Sahin |
0:55f664e8c56c | 91 | /*LDO*/ |
| Okan Sahin |
0:55f664e8c56c | 92 | CNFG_LDO0_A = 0x38, // LDO0 Output Voltage |
| Okan Sahin |
0:55f664e8c56c | 93 | CNFG_LDO0_B = 0x39 // LDO0 Output Voltage Configuration |
| Okan Sahin |
0:55f664e8c56c | 94 | } reg_t; |
| Okan Sahin |
0:55f664e8c56c | 95 | |
| Okan Sahin |
0:55f664e8c56c | 96 | void interrupt_handler(); |
| Okan Sahin |
0:55f664e8c56c | 97 | |
| Okan Sahin |
0:55f664e8c56c | 98 | void (MAX77643_2::*funcptr)(void); |
| Okan Sahin |
0:55f664e8c56c | 99 | |
| Okan Sahin |
0:55f664e8c56c | 100 | void post_interrupt_work(); |
| Okan Sahin |
0:55f664e8c56c | 101 | |
| Okan Sahin |
0:55f664e8c56c | 102 | Thread *post_intr_work_thread; |
| Okan Sahin |
0:55f664e8c56c | 103 | |
| Okan Sahin |
0:55f664e8c56c | 104 | struct handler { |
| Okan Sahin |
0:55f664e8c56c | 105 | void (*func)(void *); |
| Okan Sahin |
0:55f664e8c56c | 106 | void *cb; |
| Okan Sahin |
0:55f664e8c56c | 107 | }; |
| Okan Sahin |
0:55f664e8c56c | 108 | |
| Okan Sahin |
0:55f664e8c56c | 109 | handler *interrupt_handler_list; |
| Okan Sahin |
0:55f664e8c56c | 110 | |
| Okan Sahin |
0:55f664e8c56c | 111 | public: |
| Okan Sahin |
0:55f664e8c56c | 112 | /** |
| Okan Sahin |
0:55f664e8c56c | 113 | * @brief MAX77643_2 constructor. |
| Okan Sahin |
0:55f664e8c56c | 114 | */ |
| Okan Sahin |
0:55f664e8c56c | 115 | MAX77643_2(I2C *i2c, PinName IRQPin = NC); |
| Okan Sahin |
0:55f664e8c56c | 116 | |
| Okan Sahin |
0:55f664e8c56c | 117 | /** |
| Okan Sahin |
0:55f664e8c56c | 118 | * @brief MAX77643_2 destructor. |
| Okan Sahin |
0:55f664e8c56c | 119 | */ |
| Okan Sahin |
0:55f664e8c56c | 120 | ~MAX77643_2(); |
| Okan Sahin |
0:55f664e8c56c | 121 | |
| Okan Sahin |
0:55f664e8c56c | 122 | /** |
| Okan Sahin |
0:55f664e8c56c | 123 | * @brief Function pointer type to interrupt handler function |
| Okan Sahin |
0:55f664e8c56c | 124 | */ |
| Okan Sahin |
0:55f664e8c56c | 125 | typedef void (*interrupt_handler_function)(void *); |
| Okan Sahin |
0:55f664e8c56c | 126 | |
| Okan Sahin |
0:55f664e8c56c | 127 | /** |
| Okan Sahin |
0:55f664e8c56c | 128 | * @brief Read from a register. |
| Okan Sahin |
0:55f664e8c56c | 129 | * |
| Okan Sahin |
0:55f664e8c56c | 130 | * @param[in] reg Address of a register to be written. |
| Okan Sahin |
0:55f664e8c56c | 131 | * @param[out] value Pointer to save result value. |
| Okan Sahin |
0:55f664e8c56c | 132 | * |
| Okan Sahin |
0:55f664e8c56c | 133 | * @returns 0 on success, negative error code on failure. |
| Okan Sahin |
0:55f664e8c56c | 134 | */ |
| Okan Sahin |
0:55f664e8c56c | 135 | int read_register(uint8_t reg, uint8_t *value); |
| Okan Sahin |
0:55f664e8c56c | 136 | |
| Okan Sahin |
0:55f664e8c56c | 137 | /** |
| Okan Sahin |
0:55f664e8c56c | 138 | * @brief Write to a register. |
| Okan Sahin |
0:55f664e8c56c | 139 | * |
| Okan Sahin |
0:55f664e8c56c | 140 | * @param[in] reg Address of a register to be written. |
| Okan Sahin |
0:55f664e8c56c | 141 | * @param[out] value Pointer of value to be written to register. |
| Okan Sahin |
0:55f664e8c56c | 142 | * |
| Okan Sahin |
0:55f664e8c56c | 143 | * @returns 0 on success, negative error code on failure. |
| Okan Sahin |
0:55f664e8c56c | 144 | */ |
| Okan Sahin |
0:55f664e8c56c | 145 | int write_register(uint8_t reg, const uint8_t *value); |
| Okan Sahin |
0:55f664e8c56c | 146 | |
| Okan Sahin |
0:55f664e8c56c | 147 | /** |
| Okan Sahin |
0:55f664e8c56c | 148 | * @brief Register Configuration. |
| Okan Sahin |
0:55f664e8c56c | 149 | * All Interrupt Flags combined from INT_GLBL0 (0x00) and INT_GLBL1(0x01) |
| Okan Sahin |
0:55f664e8c56c | 150 | * |
| Okan Sahin |
0:55f664e8c56c | 151 | * @details |
| Okan Sahin |
0:55f664e8c56c | 152 | * - Register : INT_GLBL0 (0x00) and INT_GLBL1(0x01) |
| Okan Sahin |
0:55f664e8c56c | 153 | * - Bit Fields : |
| Okan Sahin |
0:55f664e8c56c | 154 | * - Default : 0x0 |
| Okan Sahin |
0:55f664e8c56c | 155 | * - Description : Enumerated interrupts. |
| Okan Sahin |
0:55f664e8c56c | 156 | */ |
| Okan Sahin |
0:55f664e8c56c | 157 | typedef enum { |
| Okan Sahin |
0:55f664e8c56c | 158 | INT_GLBL0_GPI0_F, |
| Okan Sahin |
0:55f664e8c56c | 159 | INT_GLBL0_GPI0_R, |
| Okan Sahin |
0:55f664e8c56c | 160 | INT_GLBL0_NEN_F, |
| Okan Sahin |
0:55f664e8c56c | 161 | INT_GLBL0_NEN_R, |
| Okan Sahin |
0:55f664e8c56c | 162 | INT_GLBL0_TJAL1_R, |
| Okan Sahin |
0:55f664e8c56c | 163 | INT_GLBL0_TJAL2_R, |
| Okan Sahin |
0:55f664e8c56c | 164 | INT_GLBL0_DOD_R, |
| Okan Sahin |
0:55f664e8c56c | 165 | INT_GLBL0_RSVD, |
| Okan Sahin |
0:55f664e8c56c | 166 | INT_GLBL1_GPI1_F, |
| Okan Sahin |
0:55f664e8c56c | 167 | INT_GLBL1_GPI1_R, |
| Okan Sahin |
0:55f664e8c56c | 168 | INT_GLBL1_SBB0_F, |
| Okan Sahin |
0:55f664e8c56c | 169 | INT_GLBL1_SBB1_F, |
| Okan Sahin |
0:55f664e8c56c | 170 | INT_GLBL1_SBB2_F, |
| Okan Sahin |
0:55f664e8c56c | 171 | INT_GLBL1_LDO_F, |
| Okan Sahin |
0:55f664e8c56c | 172 | INT_GLBL1_RSVD, |
| Okan Sahin |
0:55f664e8c56c | 173 | INT_CHG_END |
| Okan Sahin |
0:55f664e8c56c | 174 | } reg_bit_int_glbl_t; |
| Okan Sahin |
0:55f664e8c56c | 175 | |
| Okan Sahin |
0:55f664e8c56c | 176 | /** |
| Okan Sahin |
0:55f664e8c56c | 177 | * @brief Register Configuration |
| Okan Sahin |
0:55f664e8c56c | 178 | * |
| Okan Sahin |
0:55f664e8c56c | 179 | * @details |
| Okan Sahin |
0:55f664e8c56c | 180 | * - Register : ERCFLAG (0x02) |
| Okan Sahin |
0:55f664e8c56c | 181 | * - Bit Fields : [7:0] |
| Okan Sahin |
0:55f664e8c56c | 182 | * - Default : 0x0 |
| Okan Sahin |
0:55f664e8c56c | 183 | * - Description : Event Recorder Flags. |
| Okan Sahin |
0:55f664e8c56c | 184 | */ |
| Okan Sahin |
0:55f664e8c56c | 185 | typedef enum { |
| Okan Sahin |
0:55f664e8c56c | 186 | ERCFLAG_TOVLD, |
| Okan Sahin |
0:55f664e8c56c | 187 | ERCFLAG_INOVLO, |
| Okan Sahin |
0:55f664e8c56c | 188 | ERCFLAG_INUVLO, |
| Okan Sahin |
0:55f664e8c56c | 189 | ERCFLAG_MRST_F, |
| Okan Sahin |
0:55f664e8c56c | 190 | ERCFLAG_SFT_OFF_F, |
| Okan Sahin |
0:55f664e8c56c | 191 | ERCFLAG_SFT_CRST_F, |
| Okan Sahin |
0:55f664e8c56c | 192 | ERCFLAG_WDT_EXP_F, |
| Okan Sahin |
0:55f664e8c56c | 193 | ERCFLAG_SBB_FAULT_F |
| Okan Sahin |
0:55f664e8c56c | 194 | }reg_bit_ercflag_t; |
| Okan Sahin |
0:55f664e8c56c | 195 | |
| Okan Sahin |
0:55f664e8c56c | 196 | /** |
| Okan Sahin |
0:55f664e8c56c | 197 | * @brief Get bit field of ERCFLAG (0x02) register. |
| Okan Sahin |
0:55f664e8c56c | 198 | * |
| Okan Sahin |
0:55f664e8c56c | 199 | * @param[in] bit_field ERCFLAG register bit field to be written. |
| Okan Sahin |
0:55f664e8c56c | 200 | * @param[out] flag Pointer to save result of ercglag bit states. |
| Okan Sahin |
0:55f664e8c56c | 201 | * For individual bit |
| Okan Sahin |
0:55f664e8c56c | 202 | * 0x0: ERCFLAG has not occurred, |
| Okan Sahin |
0:55f664e8c56c | 203 | * 0x1: ERCFLAG has occurred. |
| Okan Sahin |
0:55f664e8c56c | 204 | * |
| Okan Sahin |
0:55f664e8c56c | 205 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:55f664e8c56c | 206 | */ |
| Okan Sahin |
0:55f664e8c56c | 207 | int get_ercflag(reg_bit_ercflag_t bit_field, uint8_t *flag); |
| Okan Sahin |
0:55f664e8c56c | 208 | |
| Okan Sahin |
0:55f664e8c56c | 209 | /** |
| Okan Sahin |
0:55f664e8c56c | 210 | * @brief Register Configuration |
| Okan Sahin |
0:55f664e8c56c | 211 | * |
| Okan Sahin |
0:55f664e8c56c | 212 | * @details |
| Okan Sahin |
0:55f664e8c56c | 213 | * - Register : STAT_GLBL (0x03) |
| Okan Sahin |
0:55f664e8c56c | 214 | * - Bit Fields : [7:0] |
| Okan Sahin |
0:55f664e8c56c | 215 | * - Default : 0x0 |
| Okan Sahin |
0:55f664e8c56c | 216 | * - Description : Global Status. |
| Okan Sahin |
0:55f664e8c56c | 217 | */ |
| Okan Sahin |
0:55f664e8c56c | 218 | typedef enum { |
| Okan Sahin |
0:55f664e8c56c | 219 | STAT_GLBL_STAT_IRQ, |
| Okan Sahin |
0:55f664e8c56c | 220 | STAT_GLBL_STAT_EN, |
| Okan Sahin |
0:55f664e8c56c | 221 | STAT_GLBL_TJAL1_S, |
| Okan Sahin |
0:55f664e8c56c | 222 | STAT_GLBL_TJAL2_S, |
| Okan Sahin |
0:55f664e8c56c | 223 | STAT_GLBL_DOD_S, |
| Okan Sahin |
0:55f664e8c56c | 224 | STAT_GLBL_RSVD, |
| Okan Sahin |
0:55f664e8c56c | 225 | STAT_GLBL_BOK, |
| Okan Sahin |
0:55f664e8c56c | 226 | STAT_GLBL_DIDM |
| Okan Sahin |
0:55f664e8c56c | 227 | }reg_bit_stat_glbl_t; |
| Okan Sahin |
0:55f664e8c56c | 228 | |
| Okan Sahin |
0:55f664e8c56c | 229 | /** |
| Okan Sahin |
0:55f664e8c56c | 230 | * @brief Get bit field of STAT_GLBL (0x03) register. |
| Okan Sahin |
0:55f664e8c56c | 231 | * |
| Okan Sahin |
0:55f664e8c56c | 232 | * @param[in] bit_field STAT_GLBL register bit field to be written. |
| Okan Sahin |
0:55f664e8c56c | 233 | * @param[out] status Pointer to save result of Status Global bit state. |
| Okan Sahin |
0:55f664e8c56c | 234 | * |
| Okan Sahin |
0:55f664e8c56c | 235 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:55f664e8c56c | 236 | */ |
| Okan Sahin |
0:55f664e8c56c | 237 | int get_stat_glbl(reg_bit_stat_glbl_t bit_field, uint8_t *status); |
| Okan Sahin |
0:55f664e8c56c | 238 | |
| Okan Sahin |
0:55f664e8c56c | 239 | /** |
| Okan Sahin |
0:55f664e8c56c | 240 | * @brief Register Configuration |
| Okan Sahin |
0:55f664e8c56c | 241 | * |
| Okan Sahin |
0:55f664e8c56c | 242 | * @details |
| Okan Sahin |
0:55f664e8c56c | 243 | * - Register : INTM_GLBL0 (0x04) and INTM_GLBL1 (0x05) |
| Okan Sahin |
0:55f664e8c56c | 244 | * - Bit Fields : [7:0] |
| Okan Sahin |
0:55f664e8c56c | 245 | * - Default : 0x0 |
| Okan Sahin |
0:55f664e8c56c | 246 | * - Description : All interrupt mask bits. |
| Okan Sahin |
0:55f664e8c56c | 247 | */ |
| Okan Sahin |
0:55f664e8c56c | 248 | typedef enum { |
| Okan Sahin |
0:55f664e8c56c | 249 | INTM_GLBL0_GPI0_FM, |
| Okan Sahin |
0:55f664e8c56c | 250 | INTM_GLBL0_GPI0_RM, |
| Okan Sahin |
0:55f664e8c56c | 251 | INTM_GLBL0_nEN_FM, |
| Okan Sahin |
0:55f664e8c56c | 252 | INTM_GLBL0_nEN_RM, |
| Okan Sahin |
0:55f664e8c56c | 253 | INTM_GLBL0_TJAL1_RM, |
| Okan Sahin |
0:55f664e8c56c | 254 | INTM_GLBL0_TJAL2_RM, |
| Okan Sahin |
0:55f664e8c56c | 255 | INTM_GLBL0_DOD_RM, |
| Okan Sahin |
0:55f664e8c56c | 256 | INTM_GLBL0_RSVD, |
| Okan Sahin |
0:55f664e8c56c | 257 | INTM_GLBL1_GPI1_FM, |
| Okan Sahin |
0:55f664e8c56c | 258 | INTM_GLBL1_GPI1_RM, |
| Okan Sahin |
0:55f664e8c56c | 259 | INTM_GLBL1_SBB0_FM, |
| Okan Sahin |
0:55f664e8c56c | 260 | INTM_GLBL1_SBB1_FM, |
| Okan Sahin |
0:55f664e8c56c | 261 | INTM_GLBL1_SBB2_FM, |
| Okan Sahin |
0:55f664e8c56c | 262 | INTM_GLBL1_LDO_M, |
| Okan Sahin |
0:55f664e8c56c | 263 | INTM_GLBL1_RSVD, |
| Okan Sahin |
0:55f664e8c56c | 264 | INTM_NUM_OF_BIT |
| Okan Sahin |
0:55f664e8c56c | 265 | }reg_bit_int_mask_t; |
| Okan Sahin |
0:55f664e8c56c | 266 | |
| Okan Sahin |
0:55f664e8c56c | 267 | /** |
| Okan Sahin |
0:55f664e8c56c | 268 | * @brief Set bit field of INTM_GLBL0 (0x04) or INTM_GLBL1 (0x05) register. |
| Okan Sahin |
0:55f664e8c56c | 269 | * |
| Okan Sahin |
0:55f664e8c56c | 270 | * @param[in] bit_field Register bit field to be set. |
| Okan Sahin |
0:55f664e8c56c | 271 | * @param[out] maskBit 0x0: Interrupt is unmasked, |
| Okan Sahin |
0:55f664e8c56c | 272 | * 0x1: Interrupt is masked. |
| Okan Sahin |
0:55f664e8c56c | 273 | * |
| Okan Sahin |
0:55f664e8c56c | 274 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:55f664e8c56c | 275 | */ |
| Okan Sahin |
0:55f664e8c56c | 276 | int set_interrupt_mask(reg_bit_int_mask_t bit_field, uint8_t maskBit); |
| Okan Sahin |
0:55f664e8c56c | 277 | |
| Okan Sahin |
0:55f664e8c56c | 278 | /** |
| Okan Sahin |
0:55f664e8c56c | 279 | * @brief Get bit field of INTM_GLBL0 (0x04) or INTM_GLBL1 (0x05) register. |
| Okan Sahin |
0:55f664e8c56c | 280 | * |
| Okan Sahin |
0:55f664e8c56c | 281 | * @param[in] bit_field Register bit field to be written. |
| Okan Sahin |
0:55f664e8c56c | 282 | * @param[out] maskBit 0x0: Interrupt is unmasked, |
| Okan Sahin |
0:55f664e8c56c | 283 | * 0x1: Interrupt is masked. |
| Okan Sahin |
0:55f664e8c56c | 284 | * |
| Okan Sahin |
0:55f664e8c56c | 285 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:55f664e8c56c | 286 | */ |
| Okan Sahin |
0:55f664e8c56c | 287 | int get_interrupt_mask(reg_bit_int_mask_t bit_field, uint8_t *maskBit); |
| Okan Sahin |
0:55f664e8c56c | 288 | |
| Okan Sahin |
0:55f664e8c56c | 289 | /** |
| Okan Sahin |
0:55f664e8c56c | 290 | * @brief Register Configuration |
| Okan Sahin |
0:55f664e8c56c | 291 | * |
| Okan Sahin |
0:55f664e8c56c | 292 | * @details |
| Okan Sahin |
0:55f664e8c56c | 293 | * - Register : CNFG_GLBL0 (0x06) |
| Okan Sahin |
0:55f664e8c56c | 294 | * - Bit Fields : [7:0] |
| Okan Sahin |
0:55f664e8c56c | 295 | * - Default : 0x0 |
| Okan Sahin |
0:55f664e8c56c | 296 | * - Description : Event Recorder Flags. |
| Okan Sahin |
0:55f664e8c56c | 297 | */ |
| Okan Sahin |
0:55f664e8c56c | 298 | typedef enum { |
| Okan Sahin |
0:55f664e8c56c | 299 | CNFG_GLBL0_SFT_CTRL, |
| Okan Sahin |
0:55f664e8c56c | 300 | CNFG_GLBL0_DBEN_nEN, |
| Okan Sahin |
0:55f664e8c56c | 301 | CNFG_GLBL0_nEN_MODE, |
| Okan Sahin |
0:55f664e8c56c | 302 | CNFG_GLBL0_SBIA_LPM, |
| Okan Sahin |
0:55f664e8c56c | 303 | CNFG_GLBL0_T_MRST, |
| Okan Sahin |
0:55f664e8c56c | 304 | CNFG_GLBL0_PU_DIS |
| Okan Sahin |
0:55f664e8c56c | 305 | }reg_bit_cnfg_glbl0_t; |
| Okan Sahin |
0:55f664e8c56c | 306 | |
| Okan Sahin |
0:55f664e8c56c | 307 | /** |
| Okan Sahin |
0:55f664e8c56c | 308 | * @brief Set CNFG_GLBL0 (0x06) register. |
| Okan Sahin |
0:55f664e8c56c | 309 | * |
| Okan Sahin |
0:55f664e8c56c | 310 | * @param[in] bit_field Register bit field to be written. |
| Okan Sahin |
0:55f664e8c56c | 311 | * @param[in] config Register bit field to be written. |
| Okan Sahin |
0:55f664e8c56c | 312 | * |
| Okan Sahin |
0:55f664e8c56c | 313 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:55f664e8c56c | 314 | */ |
| Okan Sahin |
0:55f664e8c56c | 315 | int set_cnfg_glbl0(reg_bit_cnfg_glbl0_t bit_field, uint8_t config); |
| Okan Sahin |
0:55f664e8c56c | 316 | |
| Okan Sahin |
0:55f664e8c56c | 317 | /** |
| Okan Sahin |
0:55f664e8c56c | 318 | * @brief Get CNFG_GLBL0 (0x06) register. |
| Okan Sahin |
0:55f664e8c56c | 319 | * |
| Okan Sahin |
0:55f664e8c56c | 320 | * @param[in] bit_field Register bit field to be written. |
| Okan Sahin |
0:55f664e8c56c | 321 | * @param[out] config Pointer of value to be read. |
| Okan Sahin |
0:55f664e8c56c | 322 | * |
| Okan Sahin |
0:55f664e8c56c | 323 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:55f664e8c56c | 324 | */ |
| Okan Sahin |
0:55f664e8c56c | 325 | int get_cnfg_glbl0(reg_bit_cnfg_glbl0_t bit_field, uint8_t *config); |
| Okan Sahin |
0:55f664e8c56c | 326 | |
| Okan Sahin |
0:55f664e8c56c | 327 | /** |
| Okan Sahin |
0:55f664e8c56c | 328 | * @brief Register Configuration |
| Okan Sahin |
0:55f664e8c56c | 329 | * |
| Okan Sahin |
0:55f664e8c56c | 330 | * @details |
| Okan Sahin |
0:55f664e8c56c | 331 | * - Register : CNFG_GLBL1 (0x07) |
| Okan Sahin |
0:55f664e8c56c | 332 | * - Bit Fields : [7:0] |
| Okan Sahin |
0:55f664e8c56c | 333 | * - Default : 0x0 |
| Okan Sahin |
0:55f664e8c56c | 334 | * - Description : Event Recorder Flags. |
| Okan Sahin |
0:55f664e8c56c | 335 | */ |
| Okan Sahin |
0:55f664e8c56c | 336 | typedef enum { |
| Okan Sahin |
0:55f664e8c56c | 337 | CNFG_GLBL1_AUTO_WKT, |
| Okan Sahin |
0:55f664e8c56c | 338 | CNFG_GLBL1_SBB_F_SHUTDN, |
| Okan Sahin |
0:55f664e8c56c | 339 | CNFG_GLBL1_RSVD |
| Okan Sahin |
0:55f664e8c56c | 340 | }reg_bit_cnfg_glbl1_t; |
| Okan Sahin |
0:55f664e8c56c | 341 | |
| Okan Sahin |
0:55f664e8c56c | 342 | /** |
| Okan Sahin |
0:55f664e8c56c | 343 | * @brief Set CNFG_GLBL1 (0x07) register. |
| Okan Sahin |
0:55f664e8c56c | 344 | * |
| Okan Sahin |
0:55f664e8c56c | 345 | * @param[in] bit_field Register bit field to be written. |
| Okan Sahin |
0:55f664e8c56c | 346 | * @param[in] config Register bit field to be written. |
| Okan Sahin |
0:55f664e8c56c | 347 | * |
| Okan Sahin |
0:55f664e8c56c | 348 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:55f664e8c56c | 349 | */ |
| Okan Sahin |
0:55f664e8c56c | 350 | int set_cnfg_glbl1(reg_bit_cnfg_glbl1_t bit_field, uint8_t config); |
| Okan Sahin |
0:55f664e8c56c | 351 | |
| Okan Sahin |
0:55f664e8c56c | 352 | /** |
| Okan Sahin |
0:55f664e8c56c | 353 | * @brief Get CNFG_GLBL1 (0x07) register. |
| Okan Sahin |
0:55f664e8c56c | 354 | * |
| Okan Sahin |
0:55f664e8c56c | 355 | * @param[in] bit_field Register bit field to be written. |
| Okan Sahin |
0:55f664e8c56c | 356 | * @param[out] config Pointer of value to be read. |
| Okan Sahin |
0:55f664e8c56c | 357 | * |
| Okan Sahin |
0:55f664e8c56c | 358 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:55f664e8c56c | 359 | */ |
| Okan Sahin |
0:55f664e8c56c | 360 | int get_cnfg_glbl1(reg_bit_cnfg_glbl1_t bit_field, uint8_t *config); |
| Okan Sahin |
0:55f664e8c56c | 361 | |
| Okan Sahin |
0:55f664e8c56c | 362 | /** |
| Okan Sahin |
0:55f664e8c56c | 363 | * @brief Register Configuration |
| Okan Sahin |
0:55f664e8c56c | 364 | * |
| Okan Sahin |
0:55f664e8c56c | 365 | * @details |
| Okan Sahin |
0:55f664e8c56c | 366 | * - Register : CNFG_GPIO0 (0x08) or CNFG_GPIO1 (0x09) |
| Okan Sahin |
0:55f664e8c56c | 367 | * - Bit Fields : [7:0] |
| Okan Sahin |
0:55f664e8c56c | 368 | * - Default : 0x0 |
| Okan Sahin |
0:55f664e8c56c | 369 | * - Description : Event Recorder Flags. |
| Okan Sahin |
0:55f664e8c56c | 370 | */ |
| Okan Sahin |
0:55f664e8c56c | 371 | typedef enum { |
| Okan Sahin |
0:55f664e8c56c | 372 | CNFG_GPIO_DIR, |
| Okan Sahin |
0:55f664e8c56c | 373 | CNFG_GPIO_DI, |
| Okan Sahin |
0:55f664e8c56c | 374 | CNFG_GPIO_DRV, |
| Okan Sahin |
0:55f664e8c56c | 375 | CNFG_GPIO_DO, |
| Okan Sahin |
0:55f664e8c56c | 376 | CNFG_GPIO_DBEN_GPI, |
| Okan Sahin |
0:55f664e8c56c | 377 | CNFG_GPIO_ALT_GPIO, |
| Okan Sahin |
0:55f664e8c56c | 378 | CNFG_GPIO_RSVD |
| Okan Sahin |
0:55f664e8c56c | 379 | }reg_bit_cnfg_gpio_t; |
| Okan Sahin |
0:55f664e8c56c | 380 | |
| Okan Sahin |
0:55f664e8c56c | 381 | /** |
| Okan Sahin |
0:55f664e8c56c | 382 | * @brief Set either CNFG_GPIO0 (0x08) or CNFG_GPIO1 (0x09). |
| Okan Sahin |
0:55f664e8c56c | 383 | * |
| Okan Sahin |
0:55f664e8c56c | 384 | * @param[in] bit_field Register bit field to be written. |
| Okan Sahin |
0:55f664e8c56c | 385 | * @param[in] channel Channel number: 0 or 1 |
| Okan Sahin |
0:55f664e8c56c | 386 | * @param[in] config Register bit field to be written. |
| Okan Sahin |
0:55f664e8c56c | 387 | * |
| Okan Sahin |
0:55f664e8c56c | 388 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:55f664e8c56c | 389 | */ |
| Okan Sahin |
0:55f664e8c56c | 390 | int set_cnfg_gpio(reg_bit_cnfg_gpio_t bit_field, uint8_t channel, uint8_t config); |
| Okan Sahin |
0:55f664e8c56c | 391 | |
| Okan Sahin |
0:55f664e8c56c | 392 | /** |
| Okan Sahin |
0:55f664e8c56c | 393 | * @brief Get either CNFG_GPIO0 (0x08) or CNFG_GPIO1 (0x09). |
| Okan Sahin |
0:55f664e8c56c | 394 | * |
| Okan Sahin |
0:55f664e8c56c | 395 | * @param[in] bit_field Register bit field to be written. |
| Okan Sahin |
0:55f664e8c56c | 396 | * @param[in] channel Channel number: 0 or 1 |
| Okan Sahin |
0:55f664e8c56c | 397 | * @param[out] config Pointer of value to be read. |
| Okan Sahin |
0:55f664e8c56c | 398 | * |
| Okan Sahin |
0:55f664e8c56c | 399 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:55f664e8c56c | 400 | */ |
| Okan Sahin |
0:55f664e8c56c | 401 | int get_cnfg_gpio(reg_bit_cnfg_gpio_t bit_field, uint8_t channel, uint8_t *config); |
| Okan Sahin |
0:55f664e8c56c | 402 | |
| Okan Sahin |
0:55f664e8c56c | 403 | /** |
| Okan Sahin |
0:55f664e8c56c | 404 | * @brief Get bit field of CID (0x10) register. |
| Okan Sahin |
0:55f664e8c56c | 405 | * |
| Okan Sahin |
0:55f664e8c56c | 406 | * @param[in] config Register bit field to be written |
| Okan Sahin |
0:55f664e8c56c | 407 | * |
| Okan Sahin |
0:55f664e8c56c | 408 | * @return CID on success, error code on failure. |
| Okan Sahin |
0:55f664e8c56c | 409 | */ |
| Okan Sahin |
0:55f664e8c56c | 410 | int get_cid(void); |
| Okan Sahin |
0:55f664e8c56c | 411 | |
| Okan Sahin |
0:55f664e8c56c | 412 | /** |
| Okan Sahin |
0:55f664e8c56c | 413 | * @brief Register Configuration |
| Okan Sahin |
0:55f664e8c56c | 414 | * |
| Okan Sahin |
0:55f664e8c56c | 415 | * @details |
| Okan Sahin |
0:55f664e8c56c | 416 | * - Register : CNFG_WDT (0x17) |
| Okan Sahin |
0:55f664e8c56c | 417 | * - Bit Fields : [7:0] |
| Okan Sahin |
0:55f664e8c56c | 418 | * - Default : 0x0 |
| Okan Sahin |
0:55f664e8c56c | 419 | * - Description : Watchdog Timer Configuration. |
| Okan Sahin |
0:55f664e8c56c | 420 | */ |
| Okan Sahin |
0:55f664e8c56c | 421 | typedef enum { |
| Okan Sahin |
0:55f664e8c56c | 422 | CNFG_WDT_WDT_LOCK, |
| Okan Sahin |
0:55f664e8c56c | 423 | CNFG_WDT_WDT_EN, |
| Okan Sahin |
0:55f664e8c56c | 424 | CNFG_WDT_WDT_CLR, |
| Okan Sahin |
0:55f664e8c56c | 425 | CNFG_WDT_WDT_MODE, |
| Okan Sahin |
0:55f664e8c56c | 426 | CNFG_WDT_WDT_PER, |
| Okan Sahin |
0:55f664e8c56c | 427 | CNFG_WDT_RSVD |
| Okan Sahin |
0:55f664e8c56c | 428 | }reg_bit_cnfg_wdt_t; |
| Okan Sahin |
0:55f664e8c56c | 429 | |
| Okan Sahin |
0:55f664e8c56c | 430 | /** |
| Okan Sahin |
0:55f664e8c56c | 431 | * @brief Set CNFG_WDT (0x17) register. |
| Okan Sahin |
0:55f664e8c56c | 432 | * |
| Okan Sahin |
0:55f664e8c56c | 433 | * @param[in] bit_field Register bit field to be written. |
| Okan Sahin |
0:55f664e8c56c | 434 | * @param[in] config Field value to be written. |
| Okan Sahin |
0:55f664e8c56c | 435 | * |
| Okan Sahin |
0:55f664e8c56c | 436 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:55f664e8c56c | 437 | */ |
| Okan Sahin |
0:55f664e8c56c | 438 | int set_cnfg_wdt(reg_bit_cnfg_wdt_t bit_field, uint8_t config); |
| Okan Sahin |
0:55f664e8c56c | 439 | |
| Okan Sahin |
0:55f664e8c56c | 440 | /** |
| Okan Sahin |
0:55f664e8c56c | 441 | * @brief Get CNFG_WDT (0x17) register. |
| Okan Sahin |
0:55f664e8c56c | 442 | * |
| Okan Sahin |
0:55f664e8c56c | 443 | * @param[in] bit_field Register bit field to be written. |
| Okan Sahin |
0:55f664e8c56c | 444 | * @param[out] config Pointer of value to be read. |
| Okan Sahin |
0:55f664e8c56c | 445 | * |
| Okan Sahin |
0:55f664e8c56c | 446 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:55f664e8c56c | 447 | */ |
| Okan Sahin |
0:55f664e8c56c | 448 | int get_cnfg_wdt(reg_bit_cnfg_wdt_t bit_field, uint8_t *config); |
| Okan Sahin |
0:55f664e8c56c | 449 | |
| Okan Sahin |
0:55f664e8c56c | 450 | /*SBB*/ |
| Okan Sahin |
0:55f664e8c56c | 451 | |
| Okan Sahin |
0:55f664e8c56c | 452 | /** |
| Okan Sahin |
0:55f664e8c56c | 453 | * @brief Register Configuration |
| Okan Sahin |
0:55f664e8c56c | 454 | * |
| Okan Sahin |
0:55f664e8c56c | 455 | * @details |
| Okan Sahin |
0:55f664e8c56c | 456 | * - Register : CNFG_SBB_TOP (0x28) |
| Okan Sahin |
0:55f664e8c56c | 457 | * - Bit Fields : [7:0] |
| Okan Sahin |
0:55f664e8c56c | 458 | * - Default : 0x0 |
| Okan Sahin |
0:55f664e8c56c | 459 | * - Description : Watchdog Timer Configuration. |
| Okan Sahin |
0:55f664e8c56c | 460 | */ |
| Okan Sahin |
0:55f664e8c56c | 461 | typedef enum { |
| Okan Sahin |
0:55f664e8c56c | 462 | CNFG_SBB_TOP_DRV_SBB, |
| Okan Sahin |
0:55f664e8c56c | 463 | CNFG_SBB_TOP_DIS_LPM |
| Okan Sahin |
0:55f664e8c56c | 464 | }reg_bit_cnfg_sbb_top_t; |
| Okan Sahin |
0:55f664e8c56c | 465 | |
| Okan Sahin |
0:55f664e8c56c | 466 | /** |
| Okan Sahin |
0:55f664e8c56c | 467 | * @brief Set CNFG_SBB_TOP (0x28) register. |
| Okan Sahin |
0:55f664e8c56c | 468 | * |
| Okan Sahin |
0:55f664e8c56c | 469 | * @param[in] bit_field Register bit field to be written. |
| Okan Sahin |
0:55f664e8c56c | 470 | * @param[in] config Configuration value to be written. |
| Okan Sahin |
0:55f664e8c56c | 471 | * |
| Okan Sahin |
0:55f664e8c56c | 472 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:55f664e8c56c | 473 | */ |
| Okan Sahin |
0:55f664e8c56c | 474 | int set_cnfg_sbb_top(reg_bit_cnfg_sbb_top_t bit_field, uint8_t config); |
| Okan Sahin |
0:55f664e8c56c | 475 | |
| Okan Sahin |
0:55f664e8c56c | 476 | /** |
| Okan Sahin |
0:55f664e8c56c | 477 | * @brief Get CNFG_SBB_TOP (0x28) register. |
| Okan Sahin |
0:55f664e8c56c | 478 | * |
| Okan Sahin |
0:55f664e8c56c | 479 | * @param[in] bit_field Register bit field to be written. |
| Okan Sahin |
0:55f664e8c56c | 480 | * @param[out] config Configuration value to be read. |
| Okan Sahin |
0:55f664e8c56c | 481 | * |
| Okan Sahin |
0:55f664e8c56c | 482 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:55f664e8c56c | 483 | */ |
| Okan Sahin |
0:55f664e8c56c | 484 | int get_cnfg_sbb_top(reg_bit_cnfg_sbb_top_t bit_field, uint8_t *config); |
| Okan Sahin |
0:55f664e8c56c | 485 | |
| Okan Sahin |
0:55f664e8c56c | 486 | /** |
| Okan Sahin |
0:55f664e8c56c | 487 | * @brief Set SIMO Buck-Boost Channel x Target Output Voltage. |
| Okan Sahin |
0:55f664e8c56c | 488 | * CNFG_SBB0_A (0x29), CNFG_SBB1_A (0x2B) and CNFG_SBB2_A (0x2D) |
| Okan Sahin |
0:55f664e8c56c | 489 | * |
| Okan Sahin |
0:55f664e8c56c | 490 | * @param[in] channel Channel number: 0, 1 or 2. |
| Okan Sahin |
0:55f664e8c56c | 491 | * @param[in] voltV SIMO buck-boost channel x target output voltage field to be written. |
| Okan Sahin |
0:55f664e8c56c | 492 | * SBBx = 500mV + 25mV x TV_SBBx[7:0] |
| Okan Sahin |
0:55f664e8c56c | 493 | * 0.500V, 0.525V, 0.550V, 0.575V, 0.600V, 0.625V, |
| Okan Sahin |
0:55f664e8c56c | 494 | * 0.650V, 0.675V, 0.700V, ... |
| Okan Sahin |
0:55f664e8c56c | 495 | * 5.425V, 5.450V, 5.475V, 5.500V. |
| Okan Sahin |
0:55f664e8c56c | 496 | * |
| Okan Sahin |
0:55f664e8c56c | 497 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:55f664e8c56c | 498 | */ |
| Okan Sahin |
0:55f664e8c56c | 499 | int set_tv_sbb(uint8_t channel, float voltV); |
| Okan Sahin |
0:55f664e8c56c | 500 | |
| Okan Sahin |
0:55f664e8c56c | 501 | /** |
| Okan Sahin |
0:55f664e8c56c | 502 | * @brief Get SIMO Buck-Boost Channel x Target Output Voltage. |
| Okan Sahin |
0:55f664e8c56c | 503 | * CNFG_SBB0_A (0x29), CNFG_SBB1_A (0x2B) and CNFG_SBB2_A (0x2D) |
| Okan Sahin |
0:55f664e8c56c | 504 | * |
| Okan Sahin |
0:55f664e8c56c | 505 | * @param[in] channel Channel number: 0, 1 or 2. |
| Okan Sahin |
0:55f664e8c56c | 506 | * @param[out] voltV SIMO buck-boost channel x target output voltage field to be read. |
| Okan Sahin |
0:55f664e8c56c | 507 | * SBBx = 500mV + 25mV x TV_SBBx[7:0] |
| Okan Sahin |
0:55f664e8c56c | 508 | * 0.500V, 0.525V, 0.550V, 0.575V, 0.600V, 0.625V, |
| Okan Sahin |
0:55f664e8c56c | 509 | * 0.650V, 0.675V, 0.700V, ... |
| Okan Sahin |
0:55f664e8c56c | 510 | * 5.425V, 5.450V, 5.475V, 5.500V. |
| Okan Sahin |
0:55f664e8c56c | 511 | * |
| Okan Sahin |
0:55f664e8c56c | 512 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:55f664e8c56c | 513 | */ |
| Okan Sahin |
0:55f664e8c56c | 514 | int get_tv_sbb(uint8_t channel, float *voltV); |
| Okan Sahin |
0:55f664e8c56c | 515 | |
| Okan Sahin |
0:55f664e8c56c | 516 | /** |
| Okan Sahin |
0:55f664e8c56c | 517 | * @brief Register Configuration |
| Okan Sahin |
0:55f664e8c56c | 518 | * |
| Okan Sahin |
0:55f664e8c56c | 519 | * @details |
| Okan Sahin |
0:55f664e8c56c | 520 | * - Register : CNFG_SBB0_B (0x2A), CNFG_SBB1_B (0x2C) and CNFG_SBB2_B (0x2E) |
| Okan Sahin |
0:55f664e8c56c | 521 | * - Bit Fields : [7:6] |
| Okan Sahin |
0:55f664e8c56c | 522 | * - Default : 0x0 |
| Okan Sahin |
0:55f664e8c56c | 523 | * - Description : Operation mode of SBB0, 1 or 2. |
| Okan Sahin |
0:55f664e8c56c | 524 | */ |
| Okan Sahin |
0:55f664e8c56c | 525 | typedef enum { |
| Okan Sahin |
0:55f664e8c56c | 526 | OP_MODE_AUTOMATIC, |
| Okan Sahin |
0:55f664e8c56c | 527 | OP_MODE_BUCK_MODE, |
| Okan Sahin |
0:55f664e8c56c | 528 | OP_MODE_BOOST_MODE, |
| Okan Sahin |
0:55f664e8c56c | 529 | OP_MODE_BUCK_BOOST_MODE |
| Okan Sahin |
0:55f664e8c56c | 530 | }decode_op_mode_t; |
| Okan Sahin |
0:55f664e8c56c | 531 | |
| Okan Sahin |
0:55f664e8c56c | 532 | /** |
| Okan Sahin |
0:55f664e8c56c | 533 | * @brief Set Operation mode of SBBx. |
| Okan Sahin |
0:55f664e8c56c | 534 | * |
| Okan Sahin |
0:55f664e8c56c | 535 | * @param[in] channel Channel number: 0, 1 or 2. |
| Okan Sahin |
0:55f664e8c56c | 536 | * @param[in] mode Operation mode of SBBx bit to be written. |
| Okan Sahin |
0:55f664e8c56c | 537 | * |
| Okan Sahin |
0:55f664e8c56c | 538 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:55f664e8c56c | 539 | */ |
| Okan Sahin |
0:55f664e8c56c | 540 | int set_op_mode(uint8_t channel, decode_op_mode_t mode); |
| Okan Sahin |
0:55f664e8c56c | 541 | |
| Okan Sahin |
0:55f664e8c56c | 542 | /** |
| Okan Sahin |
0:55f664e8c56c | 543 | * @brief Get Operation mode of SBBx. |
| Okan Sahin |
0:55f664e8c56c | 544 | * |
| Okan Sahin |
0:55f664e8c56c | 545 | * @param[in] channel Channel number: 0, 1 or 2. |
| Okan Sahin |
0:55f664e8c56c | 546 | * @param[out] mode Operation mode of SBBx bit to be read. |
| Okan Sahin |
0:55f664e8c56c | 547 | * |
| Okan Sahin |
0:55f664e8c56c | 548 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:55f664e8c56c | 549 | */ |
| Okan Sahin |
0:55f664e8c56c | 550 | int get_op_mode(uint8_t channel, decode_op_mode_t *mode); |
| Okan Sahin |
0:55f664e8c56c | 551 | |
| Okan Sahin |
0:55f664e8c56c | 552 | /** |
| Okan Sahin |
0:55f664e8c56c | 553 | * @brief Register Configuration |
| Okan Sahin |
0:55f664e8c56c | 554 | * |
| Okan Sahin |
0:55f664e8c56c | 555 | * @details |
| Okan Sahin |
0:55f664e8c56c | 556 | * - Register : CNFG_SBB0_B (0x2A), CNFG_SBB1_B (0x2C) and CNFG_SBB2_B (0x2E) |
| Okan Sahin |
0:55f664e8c56c | 557 | * - Bit Fields : [5:4] |
| Okan Sahin |
0:55f664e8c56c | 558 | * - Default : 0x0 |
| Okan Sahin |
0:55f664e8c56c | 559 | * - Description : SIMO Buck-Boost Channel 0, 1 or 2 Peak Current Limit. |
| Okan Sahin |
0:55f664e8c56c | 560 | */ |
| Okan Sahin |
0:55f664e8c56c | 561 | typedef enum { |
| Okan Sahin |
0:55f664e8c56c | 562 | IP_SBB_AMP_1_000A, |
| Okan Sahin |
0:55f664e8c56c | 563 | IP_SBB_AMP_0_750A, |
| Okan Sahin |
0:55f664e8c56c | 564 | IP_SBB_AMP_0_500A, |
| Okan Sahin |
0:55f664e8c56c | 565 | IP_SBB_AMP_0_333A |
| Okan Sahin |
0:55f664e8c56c | 566 | }decode_ip_sbb_t; |
| Okan Sahin |
0:55f664e8c56c | 567 | |
| Okan Sahin |
0:55f664e8c56c | 568 | /** |
| Okan Sahin |
0:55f664e8c56c | 569 | * @brief Set SIMO Buck-Boost Channel x Peak Current Limit. |
| Okan Sahin |
0:55f664e8c56c | 570 | * |
| Okan Sahin |
0:55f664e8c56c | 571 | * @param[in] channel Channel number: 0, 1 or 2. |
| Okan Sahin |
0:55f664e8c56c | 572 | * @param[in] ip_sbb SIMO buck-boost channel 2 peak current limit field to be written. |
| Okan Sahin |
0:55f664e8c56c | 573 | * |
| Okan Sahin |
0:55f664e8c56c | 574 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:55f664e8c56c | 575 | */ |
| Okan Sahin |
0:55f664e8c56c | 576 | int set_ip_sbb(uint8_t channel, decode_ip_sbb_t ip_sbb); |
| Okan Sahin |
0:55f664e8c56c | 577 | |
| Okan Sahin |
0:55f664e8c56c | 578 | /** |
| Okan Sahin |
0:55f664e8c56c | 579 | * @brief Get SIMO Buck-Boost Channel x Peak Current Limit. |
| Okan Sahin |
0:55f664e8c56c | 580 | * |
| Okan Sahin |
0:55f664e8c56c | 581 | * @param[in] channel Channel number: 0, 1 or 2. |
| Okan Sahin |
0:55f664e8c56c | 582 | * @param[out] ip_sbb SIMO buck-boost channel 2 peak current limit field to be read. |
| Okan Sahin |
0:55f664e8c56c | 583 | * |
| Okan Sahin |
0:55f664e8c56c | 584 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:55f664e8c56c | 585 | */ |
| Okan Sahin |
0:55f664e8c56c | 586 | int get_ip_sbb(uint8_t channel, decode_ip_sbb_t *ip_sbb); |
| Okan Sahin |
0:55f664e8c56c | 587 | |
| Okan Sahin |
0:55f664e8c56c | 588 | /** |
| Okan Sahin |
0:55f664e8c56c | 589 | * @brief Register Configuration |
| Okan Sahin |
0:55f664e8c56c | 590 | * |
| Okan Sahin |
0:55f664e8c56c | 591 | * @details |
| Okan Sahin |
0:55f664e8c56c | 592 | * - Register : CNFG_SBB0_B (0x2A), CNFG_SBB1_B (0x2C) and CNFG_SBB2_B (0x2E) |
| Okan Sahin |
0:55f664e8c56c | 593 | * - Bit Fields : [3] |
| Okan Sahin |
0:55f664e8c56c | 594 | * - Default : 0x0 |
| Okan Sahin |
0:55f664e8c56c | 595 | * - Description : SIMO Buck-Boost Channel 0, 1 or 2 Active-Discharge Enable. |
| Okan Sahin |
0:55f664e8c56c | 596 | */ |
| Okan Sahin |
0:55f664e8c56c | 597 | typedef enum { |
| Okan Sahin |
0:55f664e8c56c | 598 | ADE_SBB_DISABLED, |
| Okan Sahin |
0:55f664e8c56c | 599 | ADE_SBB_ENABLED |
| Okan Sahin |
0:55f664e8c56c | 600 | }decode_ade_sbb_t; |
| Okan Sahin |
0:55f664e8c56c | 601 | |
| Okan Sahin |
0:55f664e8c56c | 602 | /** |
| Okan Sahin |
0:55f664e8c56c | 603 | * @brief Set SIMO Buck-Boost Channel x Active-Discharge Enable. |
| Okan Sahin |
0:55f664e8c56c | 604 | * |
| Okan Sahin |
0:55f664e8c56c | 605 | * @param[in] channel Channel number: 0, 1 or 2. |
| Okan Sahin |
0:55f664e8c56c | 606 | * @param[in] ade_sbb SIMO buck-boost channel 2 active-discharge enable bit to be written. |
| Okan Sahin |
0:55f664e8c56c | 607 | * |
| Okan Sahin |
0:55f664e8c56c | 608 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:55f664e8c56c | 609 | */ |
| Okan Sahin |
0:55f664e8c56c | 610 | int set_ade_sbb(uint8_t channel, decode_ade_sbb_t ade_sbb); |
| Okan Sahin |
0:55f664e8c56c | 611 | |
| Okan Sahin |
0:55f664e8c56c | 612 | /** |
| Okan Sahin |
0:55f664e8c56c | 613 | * @brief Get SIMO Buck-Boost Channel x Active-Discharge Enable. |
| Okan Sahin |
0:55f664e8c56c | 614 | * |
| Okan Sahin |
0:55f664e8c56c | 615 | * @param[in] channel Channel number: 0, 1 or 2. |
| Okan Sahin |
0:55f664e8c56c | 616 | * @param[out] ade_sbb SIMO buck-boost channel 2 active-discharge enable bit to be read. |
| Okan Sahin |
0:55f664e8c56c | 617 | * |
| Okan Sahin |
0:55f664e8c56c | 618 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:55f664e8c56c | 619 | */ |
| Okan Sahin |
0:55f664e8c56c | 620 | int get_ade_sbb(uint8_t channel, decode_ade_sbb_t *ade_sbb); |
| Okan Sahin |
0:55f664e8c56c | 621 | |
| Okan Sahin |
0:55f664e8c56c | 622 | /** |
| Okan Sahin |
0:55f664e8c56c | 623 | * @brief Register Configuration |
| Okan Sahin |
0:55f664e8c56c | 624 | * |
| Okan Sahin |
0:55f664e8c56c | 625 | * @details |
| Okan Sahin |
0:55f664e8c56c | 626 | * - Register : CNFG_SBB0_B (0x2A), CNFG_SBB1_B (0x2C) and CNFG_SBB2_B (0x2E) |
| Okan Sahin |
0:55f664e8c56c | 627 | * - Bit Fields : [2:0] |
| Okan Sahin |
0:55f664e8c56c | 628 | * - Default : 0x0 |
| Okan Sahin |
0:55f664e8c56c | 629 | * - Description : Enable Control for SIMO Buck-Boost Channel 0, 1 or 2. |
| Okan Sahin |
0:55f664e8c56c | 630 | */ |
| Okan Sahin |
0:55f664e8c56c | 631 | typedef enum { |
| Okan Sahin |
0:55f664e8c56c | 632 | EN_SBB_FPS_SLOT_0, |
| Okan Sahin |
0:55f664e8c56c | 633 | EN_SBB_FPS_SLOT_1, |
| Okan Sahin |
0:55f664e8c56c | 634 | EN_SBB_FPS_SLOT_2, |
| Okan Sahin |
0:55f664e8c56c | 635 | EN_SBB_FPS_SLOT_3, |
| Okan Sahin |
0:55f664e8c56c | 636 | EN_SBB_OFF, |
| Okan Sahin |
0:55f664e8c56c | 637 | EN_SBB_SAME_AS_0X04, |
| Okan Sahin |
0:55f664e8c56c | 638 | EN_SBB_ON, |
| Okan Sahin |
0:55f664e8c56c | 639 | EN_SBB_SAME_AS_0X06 |
| Okan Sahin |
0:55f664e8c56c | 640 | }decode_en_sbb_t; |
| Okan Sahin |
0:55f664e8c56c | 641 | |
| Okan Sahin |
0:55f664e8c56c | 642 | /** |
| Okan Sahin |
0:55f664e8c56c | 643 | * @brief Set Enable Control for SIMO Buck-Boost Channel x. |
| Okan Sahin |
0:55f664e8c56c | 644 | * |
| Okan Sahin |
0:55f664e8c56c | 645 | * @param[in] channel Channel number: 0, 1 or 2. |
| Okan Sahin |
0:55f664e8c56c | 646 | * @param[in] en_sbb Enable control for SIMO buck-boost channel x field to be written. |
| Okan Sahin |
0:55f664e8c56c | 647 | * |
| Okan Sahin |
0:55f664e8c56c | 648 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:55f664e8c56c | 649 | */ |
| Okan Sahin |
0:55f664e8c56c | 650 | int set_en_sbb(uint8_t channel, decode_en_sbb_t en_sbb); |
| Okan Sahin |
0:55f664e8c56c | 651 | |
| Okan Sahin |
0:55f664e8c56c | 652 | /** |
| Okan Sahin |
0:55f664e8c56c | 653 | * @brief Get Enable Control for SIMO Buck-Boost Channel x. |
| Okan Sahin |
0:55f664e8c56c | 654 | * |
| Okan Sahin |
0:55f664e8c56c | 655 | * @param[in] channel Channel number: 0, 1 or 2. |
| Okan Sahin |
0:55f664e8c56c | 656 | * @param[out] en_sbb Enable control for SIMO buck-boost channel x field to be read. |
| Okan Sahin |
0:55f664e8c56c | 657 | * |
| Okan Sahin |
0:55f664e8c56c | 658 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:55f664e8c56c | 659 | */ |
| Okan Sahin |
0:55f664e8c56c | 660 | int get_en_sbb(uint8_t channel, decode_en_sbb_t *en_sbb); |
| Okan Sahin |
0:55f664e8c56c | 661 | |
| Okan Sahin |
0:55f664e8c56c | 662 | /** |
| Okan Sahin |
0:55f664e8c56c | 663 | * @brief Set SIMO Buck-Boost Channel 0 Target Output Voltage. |
| Okan Sahin |
0:55f664e8c56c | 664 | * Bit 7:0 of CNFG_DVS_SBB0_A (0x2F). |
| Okan Sahin |
0:55f664e8c56c | 665 | * |
| Okan Sahin |
0:55f664e8c56c | 666 | * @param[in] voltV SIMO buck-boost channel 0 target output voltage field to be written. |
| Okan Sahin |
0:55f664e8c56c | 667 | * SBBx = 500mV + 25mV x TV_SBBx[7:0] |
| Okan Sahin |
0:55f664e8c56c | 668 | * 0.500V, 0.525V, 0.550V, 0.575V, 0.600V, 0.625V, |
| Okan Sahin |
0:55f664e8c56c | 669 | * 0.650V, 0.675V, 0.700V, ... |
| Okan Sahin |
0:55f664e8c56c | 670 | * 5.425V, 5.450V, 5.475V, 5.500V. |
| Okan Sahin |
0:55f664e8c56c | 671 | * |
| Okan Sahin |
0:55f664e8c56c | 672 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:55f664e8c56c | 673 | */ |
| Okan Sahin |
0:55f664e8c56c | 674 | int set_tv_sbb_dvs(float voltV); |
| Okan Sahin |
0:55f664e8c56c | 675 | |
| Okan Sahin |
0:55f664e8c56c | 676 | /** |
| Okan Sahin |
0:55f664e8c56c | 677 | * @brief Get SIMO Buck-Boost Channel 0 Target Output Voltage. |
| Okan Sahin |
0:55f664e8c56c | 678 | * Bit 7:0 of CNFG_DVS_SBB0_A (0x2F). |
| Okan Sahin |
0:55f664e8c56c | 679 | * |
| Okan Sahin |
0:55f664e8c56c | 680 | * @param[out] voltV SIMO buck-boost channel 0 target output voltage field to be read. |
| Okan Sahin |
0:55f664e8c56c | 681 | * SBBx = 500mV + 25mV x TV_SBBx[7:0] |
| Okan Sahin |
0:55f664e8c56c | 682 | * 0.500V, 0.525V, 0.550V, 0.575V, 0.600V, 0.625V, |
| Okan Sahin |
0:55f664e8c56c | 683 | * 0.650V, 0.675V, 0.700V, ... |
| Okan Sahin |
0:55f664e8c56c | 684 | * 5.425V, 5.450V, 5.475V, 5.500V. |
| Okan Sahin |
0:55f664e8c56c | 685 | * |
| Okan Sahin |
0:55f664e8c56c | 686 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:55f664e8c56c | 687 | */ |
| Okan Sahin |
0:55f664e8c56c | 688 | int get_tv_sbb_dvs(float *voltV); |
| Okan Sahin |
0:55f664e8c56c | 689 | |
| Okan Sahin |
0:55f664e8c56c | 690 | /*LDO*/ |
| Okan Sahin |
0:55f664e8c56c | 691 | |
| Okan Sahin |
0:55f664e8c56c | 692 | /** |
| Okan Sahin |
0:55f664e8c56c | 693 | * @brief Set LDO Output Channel x Target Output Voltage. Bit 6:0. |
| Okan Sahin |
0:55f664e8c56c | 694 | * CNFG_LDO0_A (0x38) |
| Okan Sahin |
0:55f664e8c56c | 695 | * |
| Okan Sahin |
0:55f664e8c56c | 696 | * @param[in] voltV LDO Output Channel x target output voltage field to be read. |
| Okan Sahin |
0:55f664e8c56c | 697 | * LDOx = 500mV + 25mV x TV_LDOx[6:0] |
| Okan Sahin |
0:55f664e8c56c | 698 | * 0.500V, 0.525V, 0.550V, 0.575V, 0.600V, 0.625V, |
| Okan Sahin |
0:55f664e8c56c | 699 | * 0.650V, 0.675V, 0.700V, ... |
| Okan Sahin |
0:55f664e8c56c | 700 | * 3.650, 3.675. |
| Okan Sahin |
0:55f664e8c56c | 701 | * |
| Okan Sahin |
0:55f664e8c56c | 702 | * When TV_LDO[7] = 0, TV_LDO[6:0] sets the |
| Okan Sahin |
0:55f664e8c56c | 703 | * LDO's output voltage range from 0.5V to 3.675V. |
| Okan Sahin |
0:55f664e8c56c | 704 | * When TV_LDO[7] = 1, TV_LDO[6:0] sets the |
| Okan Sahin |
0:55f664e8c56c | 705 | * LDO's output voltage from 1.825V to 5V. |
| Okan Sahin |
0:55f664e8c56c | 706 | * |
| Okan Sahin |
0:55f664e8c56c | 707 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:55f664e8c56c | 708 | */ |
| Okan Sahin |
0:55f664e8c56c | 709 | int set_tv_ldo(float voltV); |
| Okan Sahin |
0:55f664e8c56c | 710 | |
| Okan Sahin |
0:55f664e8c56c | 711 | /** |
| Okan Sahin |
0:55f664e8c56c | 712 | * @brief Get LDO Output Channel x Target Output Voltage. Bit 6:0. |
| Okan Sahin |
0:55f664e8c56c | 713 | * CNFG_LDO0_A (0x38) |
| Okan Sahin |
0:55f664e8c56c | 714 | * |
| Okan Sahin |
0:55f664e8c56c | 715 | * @param[out] voltV LDO Output Channel x target output voltage field to be read. |
| Okan Sahin |
0:55f664e8c56c | 716 | * LDOx = 500mV + 25mV x TV_LDOx[6:0] |
| Okan Sahin |
0:55f664e8c56c | 717 | * 0.500V, 0.525V, 0.550V, 0.575V, 0.600V, 0.625V, |
| Okan Sahin |
0:55f664e8c56c | 718 | * 0.650V, 0.675V, 0.700V, ... |
| Okan Sahin |
0:55f664e8c56c | 719 | * 3.650, 3.675. |
| Okan Sahin |
0:55f664e8c56c | 720 | * |
| Okan Sahin |
0:55f664e8c56c | 721 | * When TV_LDO[7] = 0, TV_LDO[6:0] sets the |
| Okan Sahin |
0:55f664e8c56c | 722 | * LDO's output voltage range from 0.5V to 3.675V. |
| Okan Sahin |
0:55f664e8c56c | 723 | * When TV_LDO[7] = 1, TV_LDO[6:0] sets the |
| Okan Sahin |
0:55f664e8c56c | 724 | * LDO's output voltage from 1.825V to 5V. |
| Okan Sahin |
0:55f664e8c56c | 725 | * |
| Okan Sahin |
0:55f664e8c56c | 726 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:55f664e8c56c | 727 | */ |
| Okan Sahin |
0:55f664e8c56c | 728 | int get_tv_ldo(float *voltV); |
| Okan Sahin |
0:55f664e8c56c | 729 | |
| Okan Sahin |
0:55f664e8c56c | 730 | /** |
| Okan Sahin |
0:55f664e8c56c | 731 | * @brief Register Configuration |
| Okan Sahin |
0:55f664e8c56c | 732 | * |
| Okan Sahin |
0:55f664e8c56c | 733 | * @details |
| Okan Sahin |
0:55f664e8c56c | 734 | * - Register : CNFG_LDO0_A (0x38) |
| Okan Sahin |
0:55f664e8c56c | 735 | * - Bit Fields : [7] |
| Okan Sahin |
0:55f664e8c56c | 736 | * - Default : 0x0 |
| Okan Sahin |
0:55f664e8c56c | 737 | * - Description : SIMO Buck-Boost Channel 0 Peak Current Limit. |
| Okan Sahin |
0:55f664e8c56c | 738 | */ |
| Okan Sahin |
0:55f664e8c56c | 739 | typedef enum { |
| Okan Sahin |
0:55f664e8c56c | 740 | TV_OFS_LDO_NO_OFFSET, |
| Okan Sahin |
0:55f664e8c56c | 741 | TV_OFS_LDO_NO_1_325V |
| Okan Sahin |
0:55f664e8c56c | 742 | }decode_tv_ofs_ldo_t; |
| Okan Sahin |
0:55f664e8c56c | 743 | |
| Okan Sahin |
0:55f664e8c56c | 744 | /** |
| Okan Sahin |
0:55f664e8c56c | 745 | * @brief Set LDO Output Channel 0 Target Output Voltage. Bit 7. |
| Okan Sahin |
0:55f664e8c56c | 746 | * CNFG_LDO0_A (0x38) |
| Okan Sahin |
0:55f664e8c56c | 747 | * |
| Okan Sahin |
0:55f664e8c56c | 748 | * @param[in] offset LDO Output Channel 0 target output voltage offset field to be read. |
| Okan Sahin |
0:55f664e8c56c | 749 | * 0b0 = No Offset |
| Okan Sahin |
0:55f664e8c56c | 750 | * 0b1 = 1.325V Offset |
| Okan Sahin |
0:55f664e8c56c | 751 | * |
| Okan Sahin |
0:55f664e8c56c | 752 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:55f664e8c56c | 753 | */ |
| Okan Sahin |
0:55f664e8c56c | 754 | int set_tv_ofs_ldo(decode_tv_ofs_ldo_t offset); |
| Okan Sahin |
0:55f664e8c56c | 755 | |
| Okan Sahin |
0:55f664e8c56c | 756 | /** |
| Okan Sahin |
0:55f664e8c56c | 757 | * @brief Get LDO Output Channel 0 Target Output Voltage. Bit 7. |
| Okan Sahin |
0:55f664e8c56c | 758 | * CNFG_LDO0_A (0x38) |
| Okan Sahin |
0:55f664e8c56c | 759 | * |
| Okan Sahin |
0:55f664e8c56c | 760 | * @param[out] offset LDO Output Channel 0 target output voltage offset field to be read. |
| Okan Sahin |
0:55f664e8c56c | 761 | * 0b0 = No Offset |
| Okan Sahin |
0:55f664e8c56c | 762 | * 0b1 = 1.325V Offset |
| Okan Sahin |
0:55f664e8c56c | 763 | * |
| Okan Sahin |
0:55f664e8c56c | 764 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:55f664e8c56c | 765 | */ |
| Okan Sahin |
0:55f664e8c56c | 766 | int get_tv_ofs_ldo(decode_tv_ofs_ldo_t *offset); |
| Okan Sahin |
0:55f664e8c56c | 767 | |
| Okan Sahin |
0:55f664e8c56c | 768 | /** |
| Okan Sahin |
0:55f664e8c56c | 769 | * @brief Register Configuration |
| Okan Sahin |
0:55f664e8c56c | 770 | * |
| Okan Sahin |
0:55f664e8c56c | 771 | * @details |
| Okan Sahin |
0:55f664e8c56c | 772 | * - Register : CNFG_LDO0_B (0x39) |
| Okan Sahin |
0:55f664e8c56c | 773 | * - Bit Fields : [2:0] |
| Okan Sahin |
0:55f664e8c56c | 774 | * - Default : 0x0 |
| Okan Sahin |
0:55f664e8c56c | 775 | * - Description : Enable Control for LDO 0. |
| Okan Sahin |
0:55f664e8c56c | 776 | */ |
| Okan Sahin |
0:55f664e8c56c | 777 | typedef enum { |
| Okan Sahin |
0:55f664e8c56c | 778 | EN_LDO_FPS_SLOT_0, |
| Okan Sahin |
0:55f664e8c56c | 779 | EN_LDO_FPS_SLOT_1, |
| Okan Sahin |
0:55f664e8c56c | 780 | EN_LDO_FPS_SLOT_2, |
| Okan Sahin |
0:55f664e8c56c | 781 | EN_LDO_FPS_SLOT_3, |
| Okan Sahin |
0:55f664e8c56c | 782 | EN_LDO_OFF, |
| Okan Sahin |
0:55f664e8c56c | 783 | EN_LDO_SAME_AS_0X04, |
| Okan Sahin |
0:55f664e8c56c | 784 | EN_LDO_ON, |
| Okan Sahin |
0:55f664e8c56c | 785 | EN_LDO_SAME_AS_0X06 |
| Okan Sahin |
0:55f664e8c56c | 786 | }decode_en_ldo_t; |
| Okan Sahin |
0:55f664e8c56c | 787 | |
| Okan Sahin |
0:55f664e8c56c | 788 | /** |
| Okan Sahin |
0:55f664e8c56c | 789 | * @brief Set Enable Control for LDO Channel 0. |
| Okan Sahin |
0:55f664e8c56c | 790 | * |
| Okan Sahin |
0:55f664e8c56c | 791 | * @param[in] en_ldo Enable control for LDO channel 0 field to be written. |
| Okan Sahin |
0:55f664e8c56c | 792 | * |
| Okan Sahin |
0:55f664e8c56c | 793 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:55f664e8c56c | 794 | */ |
| Okan Sahin |
0:55f664e8c56c | 795 | int set_en_ldo(decode_en_ldo_t en_ldo); |
| Okan Sahin |
0:55f664e8c56c | 796 | |
| Okan Sahin |
0:55f664e8c56c | 797 | /** |
| Okan Sahin |
0:55f664e8c56c | 798 | * @brief Get Enable Control for LDO Channel 0. |
| Okan Sahin |
0:55f664e8c56c | 799 | * |
| Okan Sahin |
0:55f664e8c56c | 800 | * @param[out] en_ldo Enable control for LDO channel x field to be read. |
| Okan Sahin |
0:55f664e8c56c | 801 | * |
| Okan Sahin |
0:55f664e8c56c | 802 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:55f664e8c56c | 803 | */ |
| Okan Sahin |
0:55f664e8c56c | 804 | int get_en_ldo(decode_en_ldo_t *en_ldo); |
| Okan Sahin |
0:55f664e8c56c | 805 | |
| Okan Sahin |
0:55f664e8c56c | 806 | /** |
| Okan Sahin |
0:55f664e8c56c | 807 | * @brief Register Configuration |
| Okan Sahin |
0:55f664e8c56c | 808 | * |
| Okan Sahin |
0:55f664e8c56c | 809 | * @details |
| Okan Sahin |
0:55f664e8c56c | 810 | * - Register : CNFG_LDO0_B (0x39) |
| Okan Sahin |
0:55f664e8c56c | 811 | * - Bit Fields : [3] |
| Okan Sahin |
0:55f664e8c56c | 812 | * - Default : 0x0 |
| Okan Sahin |
0:55f664e8c56c | 813 | * - Description : LDO Channel 0 Active-Discharge Enable. |
| Okan Sahin |
0:55f664e8c56c | 814 | */ |
| Okan Sahin |
0:55f664e8c56c | 815 | typedef enum { |
| Okan Sahin |
0:55f664e8c56c | 816 | ADE_LDO_DISABLED, |
| Okan Sahin |
0:55f664e8c56c | 817 | ADE_LDO_ENABLED |
| Okan Sahin |
0:55f664e8c56c | 818 | }decode_ade_ldo_t; |
| Okan Sahin |
0:55f664e8c56c | 819 | |
| Okan Sahin |
0:55f664e8c56c | 820 | /** |
| Okan Sahin |
0:55f664e8c56c | 821 | * @brief Set LDO Channel 0 Active-Discharge Enable. |
| Okan Sahin |
0:55f664e8c56c | 822 | * |
| Okan Sahin |
0:55f664e8c56c | 823 | * @param[in] ade_ldo LDO channel 0 active-discharge enable bit to be written. |
| Okan Sahin |
0:55f664e8c56c | 824 | * |
| Okan Sahin |
0:55f664e8c56c | 825 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:55f664e8c56c | 826 | */ |
| Okan Sahin |
0:55f664e8c56c | 827 | int set_ade_ldo(decode_ade_ldo_t ade_ldo); |
| Okan Sahin |
0:55f664e8c56c | 828 | |
| Okan Sahin |
0:55f664e8c56c | 829 | /** |
| Okan Sahin |
0:55f664e8c56c | 830 | * @brief Get LDO Channel 0 Active-Discharge Enable. |
| Okan Sahin |
0:55f664e8c56c | 831 | * |
| Okan Sahin |
0:55f664e8c56c | 832 | * @param[out] ade_ldo LDO channel 0 active-discharge enable bit to be read. |
| Okan Sahin |
0:55f664e8c56c | 833 | * |
| Okan Sahin |
0:55f664e8c56c | 834 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:55f664e8c56c | 835 | */ |
| Okan Sahin |
0:55f664e8c56c | 836 | int get_ade_ldo(decode_ade_ldo_t *ade_ldo); |
| Okan Sahin |
0:55f664e8c56c | 837 | |
| Okan Sahin |
0:55f664e8c56c | 838 | /** |
| Okan Sahin |
0:55f664e8c56c | 839 | * @brief Register Configuration |
| Okan Sahin |
0:55f664e8c56c | 840 | * |
| Okan Sahin |
0:55f664e8c56c | 841 | * @details |
| Okan Sahin |
0:55f664e8c56c | 842 | * - Register : CNFG_LDO0_B (0x39) |
| Okan Sahin |
0:55f664e8c56c | 843 | * - Bit Fields : [4] |
| Okan Sahin |
0:55f664e8c56c | 844 | * - Default : 0x0 |
| Okan Sahin |
0:55f664e8c56c | 845 | * - Description : Operation mode of LDO 0. |
| Okan Sahin |
0:55f664e8c56c | 846 | */ |
| Okan Sahin |
0:55f664e8c56c | 847 | typedef enum { |
| Okan Sahin |
0:55f664e8c56c | 848 | LDO_MD_LDO_MODE, |
| Okan Sahin |
0:55f664e8c56c | 849 | LDO_MD_LSW_MODE |
| Okan Sahin |
0:55f664e8c56c | 850 | }decode_ldo_md_t; |
| Okan Sahin |
0:55f664e8c56c | 851 | |
| Okan Sahin |
0:55f664e8c56c | 852 | /** |
| Okan Sahin |
0:55f664e8c56c | 853 | * @brief Set Operation mode of LDO0. |
| Okan Sahin |
0:55f664e8c56c | 854 | * |
| Okan Sahin |
0:55f664e8c56c | 855 | * @param[in] mode Operation mode of LDO0 bit to be written. |
| Okan Sahin |
0:55f664e8c56c | 856 | * |
| Okan Sahin |
0:55f664e8c56c | 857 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:55f664e8c56c | 858 | */ |
| Okan Sahin |
0:55f664e8c56c | 859 | int set_ldo_md(decode_ldo_md_t mode); |
| Okan Sahin |
0:55f664e8c56c | 860 | |
| Okan Sahin |
0:55f664e8c56c | 861 | /** |
| Okan Sahin |
0:55f664e8c56c | 862 | * @brief Get Operation mode of LDO0. |
| Okan Sahin |
0:55f664e8c56c | 863 | * |
| Okan Sahin |
0:55f664e8c56c | 864 | * @param[out] mode Operation mode of LDO0 bit to be read. |
| Okan Sahin |
0:55f664e8c56c | 865 | * |
| Okan Sahin |
0:55f664e8c56c | 866 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:55f664e8c56c | 867 | */ |
| Okan Sahin |
0:55f664e8c56c | 868 | int get_ldo_md(decode_ldo_md_t *mode); |
| Okan Sahin |
0:55f664e8c56c | 869 | |
| Okan Sahin |
0:55f664e8c56c | 870 | /** |
| Okan Sahin |
0:55f664e8c56c | 871 | * @brief Disable all interrupts |
| Okan Sahin |
0:55f664e8c56c | 872 | * |
| Okan Sahin |
0:55f664e8c56c | 873 | * @return 0 on success, error code on failure |
| Okan Sahin |
0:55f664e8c56c | 874 | */ |
| Okan Sahin |
0:55f664e8c56c | 875 | int irq_disable_all(); |
| Okan Sahin |
0:55f664e8c56c | 876 | |
| Okan Sahin |
0:55f664e8c56c | 877 | /** |
| Okan Sahin |
0:55f664e8c56c | 878 | * @brief Set Interrupt Handler for a Specific Interrupt ID. |
| Okan Sahin |
0:55f664e8c56c | 879 | * |
| Okan Sahin |
0:55f664e8c56c | 880 | * @param[in] id reg_bit_reg_bit_int_glbl_t id, one of INTR_ID_*. |
| Okan Sahin |
0:55f664e8c56c | 881 | * @param[in] func Interrupt handler function. |
| Okan Sahin |
0:55f664e8c56c | 882 | * @param[in] cb Interrupt handler data. |
| Okan Sahin |
0:55f664e8c56c | 883 | */ |
| Okan Sahin |
0:55f664e8c56c | 884 | void set_interrupt_handler(reg_bit_int_glbl_t id, interrupt_handler_function func, void *cb); |
| Okan Sahin |
0:55f664e8c56c | 885 | }; |
| Okan Sahin |
0:55f664e8c56c | 886 | #endif |