Yuji Notsu
This program is for OV7670 and TFT-LCD(REL225L01)
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OV7670.h
00001 #include "mbed.h" 00002 00003 #define OV7670_I2C_ADDR 0x42 00004 00005 /* 00006 * Basic window sizes. These probably belong somewhere more globally 00007 * useful. 00008 */ 00009 #define VGA_WIDTH 640 00010 #define VGA_HEIGHT 480 00011 #define QVGA_WIDTH 320 00012 #define QVGA_HEIGHT 240 00013 #define CIF_WIDTH 352 00014 #define CIF_HEIGHT 288 00015 #define QCIF_WIDTH 176 00016 #define QCIF_HEIGHT 144 00017 00018 /* Register */ 00019 #define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */ 00020 #define REG_BLUE 0x01 /* blue gain */ 00021 #define REG_RED 0x02 /* red gain */ 00022 #define REG_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */ 00023 #define REG_COM1 0x04 /* Control 1 */ 00024 #define COM1_CCIR656 0x40 /* CCIR656 enable */ 00025 #define REG_BAVE 0x05 /* U/B Average level */ 00026 #define REG_GbAVE 0x06 /* Y/Gb Average level */ 00027 #define REG_AECHH 0x07 /* AEC MS 5 bits */ 00028 #define REG_RAVE 0x08 /* V/R Average level */ 00029 #define REG_COM2 0x09 /* Control 2 */ 00030 #define COM2_SSLEEP 0x10 /* Soft sleep mode */ 00031 #define REG_PID 0x0a /* Product ID MSB */ 00032 #define REG_VER 0x0b /* Product ID LSB */ 00033 #define REG_COM3 0x0c /* Control 3 */ 00034 #define COM3_SWAP 0x40 /* Byte swap */ 00035 #define COM3_SCALEEN 0x08 /* Enable scaling */ 00036 #define COM3_DCWEN 0x04 /* Enable downsamp/crop/window */ 00037 #define REG_COM4 0x0d /* Control 4 */ 00038 #define REG_COM5 0x0e /* All "reserved" */ 00039 #define REG_COM6 0x0f /* Control 6 */ 00040 #define REG_AECH 0x10 /* More bits of AEC value */ 00041 #define REG_CLKRC 0x11 /* Clocl control */ 00042 #define CLK_EXT 0x40 /* Use external clock directly */ 00043 #define CLK_SCALE 0x3f /* Mask for internal clock scale */ 00044 #define REG_COM7 0x12 /* Control 7 */ 00045 #define COM7_RESET 0x80 /* Register reset */ 00046 #define COM7_FMT_MASK 0x38 00047 #define COM7_FMT_VGA 0x00 00048 #define COM7_FMT_CIF 0x20 /* CIF format */ 00049 #define COM7_FMT_QVGA 0x10 /* QVGA format */ 00050 #define COM7_FMT_QCIF 0x08 /* QCIF format */ 00051 #define COM7_RGB 0x04 /* bits 0 and 2 - RGB format */ 00052 #define COM7_YUV 0x00 /* YUV */ 00053 #define COM7_BAYER 0x01 /* Bayer format */ 00054 #define COM7_PBAYER 0x05 /* "Processed bayer" */ 00055 #define REG_COM8 0x13 /* Control 8 */ 00056 #define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */ 00057 #define COM8_AECSTEP 0x40 /* Unlimited AEC step size */ 00058 #define COM8_BFILT 0x20 /* Band filter enable */ 00059 #define COM8_AGC 0x04 /* Auto gain enable */ 00060 #define COM8_AWB 0x02 /* White balance enable */ 00061 #define COM8_AEC 0x01 /* Auto exposure enable */ 00062 #define REG_COM9 0x14 /* Control 9 - gain ceiling */ 00063 #define REG_COM10 0x15 /* Control 10 */ 00064 #define COM10_HSYNC 0x40 /* HSYNC instead of HREF */ 00065 #define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */ 00066 #define COM10_HREF_REV 0x08 /* Reverse HREF */ 00067 #define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */ 00068 #define COM10_VS_NEG 0x02 /* VSYNC negative */ 00069 #define COM10_HS_NEG 0x01 /* HSYNC negative */ 00070 #define REG_HSTART 0x17 /* Horiz start high bits */ 00071 #define REG_HSTOP 0x18 /* Horiz stop high bits */ 00072 #define REG_VSTART 0x19 /* Vert start high bits */ 00073 #define REG_VSTOP 0x1a /* Vert stop high bits */ 00074 #define REG_PSHFT 0x1b /* Pixel delay after HREF */ 00075 #define REG_MIDH 0x1c /* Manuf. ID high */ 00076 #define REG_MIDL 0x1d /* Manuf. ID low */ 00077 #define REG_MVFP 0x1e /* Mirror / vflip */ 00078 #define MVFP_MIRROR 0x20 /* Mirror image */ 00079 #define MVFP_FLIP 0x10 /* Vertical flip */ 00080 00081 #define REG_AEW 0x24 /* AGC upper limit */ 00082 #define REG_AEB 0x25 /* AGC lower limit */ 00083 #define REG_VPT 0x26 /* AGC/AEC fast mode op region */ 00084 #define REG_HSYST 0x30 /* HSYNC rising edge delay */ 00085 #define REG_HSYEN 0x31 /* HSYNC falling edge delay */ 00086 #define REG_HREF 0x32 /* HREF pieces */ 00087 #define REG_TSLB 0x3a /* lots of stuff */ 00088 #define TSLB_YLAST 0x04 /* UYVY or VYUY - see com13 */ 00089 #define REG_COM11 0x3b /* Control 11 */ 00090 #define COM11_NIGHT 0x80 /* NIght mode enable */ 00091 #define COM11_NMFR 0x60 /* Two bit NM frame rate */ 00092 #define COM11_HZAUTO 0x10 /* Auto detect 50/60 Hz */ 00093 #define COM11_50HZ 0x08 /* Manual 50Hz select */ 00094 #define COM11_EXP 0x02 00095 #define REG_COM12 0x3c /* Control 12 */ 00096 #define COM12_HREF 0x80 /* HREF always */ 00097 #define REG_COM13 0x3d /* Control 13 */ 00098 #define COM13_GAMMA 0x80 /* Gamma enable */ 00099 #define COM13_UVSAT 0x40 /* UV saturation auto adjustment */ 00100 #define COM13_UVSWAP 0x01 /* V before U - w/TSLB */ 00101 #define REG_COM14 0x3e /* Control 14 */ 00102 #define COM14_DCWEN 0x10 /* DCW/PCLK-scale enable */ 00103 #define REG_EDGE 0x3f /* Edge enhancement factor */ 00104 #define REG_COM15 0x40 /* Control 15 */ 00105 #define COM15_R10F0 0x00 /* Data range 10 to F0 */ 00106 #define COM15_R01FE 0x80 /* 01 to FE */ 00107 #define COM15_R00FF 0xc0 /* 00 to FF */ 00108 #define COM15_RGB565 0x10 /* RGB565 output */ 00109 #define COM15_RGB555 0x30 /* RGB555 output */ 00110 #define REG_COM16 0x41 /* Control 16 */ 00111 #define COM16_AWBGAIN 0x08 /* AWB gain enable */ 00112 #define REG_COM17 0x42 /* Control 17 */ 00113 #define COM17_AECWIN 0xc0 /* AEC window - must match COM4 */ 00114 #define COM17_CBAR 0x08 /* DSP Color bar */ 00115 00116 /* 00117 * This matrix defines how the colors are generated, must be 00118 * tweaked to adjust hue and saturation. 00119 * 00120 * Order: v-red, v-green, v-blue, u-red, u-green, u-blue 00121 * 00122 * They are nine-bit signed quantities, with the sign bit 00123 * stored in 0x58. Sign for v-red is bit 0, and up from there. 00124 */ 00125 #define REG_CMATRIX_BASE 0x4f 00126 #define CMATRIX_LEN 6 00127 #define REG_CMATRIX_SIGN 0x58 00128 00129 00130 #define REG_BRIGHT 0x55 /* Brightness */ 00131 #define REG_CONTRAS 0x56 /* Contrast control */ 00132 00133 #define REG_GFIX 0x69 /* Fix gain control */ 00134 00135 #define REG_REG76 0x76 /* OV's name */ 00136 #define R76_BLKPCOR 0x80 /* Black pixel correction enable */ 00137 #define R76_WHTPCOR 0x40 /* White pixel correction enable */ 00138 00139 #define REG_RGB444 0x8c /* RGB 444 control */ 00140 #define R444_ENABLE 0x02 /* Turn on RGB444, overrides 5x5 */ 00141 #define R444_RGBX 0x01 /* Empty nibble at end */ 00142 00143 #define REG_HAECC1 0x9f /* Hist AEC/AGC control 1 */ 00144 #define REG_HAECC2 0xa0 /* Hist AEC/AGC control 2 */ 00145 00146 #define REG_BD50MAX 0xa5 /* 50hz banding step limit */ 00147 #define REG_HAECC3 0xa6 /* Hist AEC/AGC control 3 */ 00148 #define REG_HAECC4 0xa7 /* Hist AEC/AGC control 4 */ 00149 #define REG_HAECC5 0xa8 /* Hist AEC/AGC control 5 */ 00150 #define REG_HAECC6 0xa9 /* Hist AEC/AGC control 6 */ 00151 #define REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */ 00152 #define REG_BD60MAX 0xab /* 60hz banding step limit */ 00153 00154 struct regval_list { 00155 unsigned char reg_num; 00156 unsigned char value; 00157 }; 00158 00159 static struct regval_list ov7670_default_regs[] = { 00160 { REG_COM7, COM7_RESET }, 00161 /* 00162 * Clock scale: 3 = 15fps 00163 * 2 = 20fps 00164 * 1 = 30fps 00165 */ 00166 { REG_CLKRC, 1 }, /* OV: clock scale (30 fps), internal clk= external clk/(1+1) */ 00167 { REG_TSLB, 0x04 }, /* OV */ 00168 { REG_COM7, 0 }, /* VGA,YUV */ 00169 /* 00170 * Set the hardware window. These values from OV don't entirely 00171 * make sense - hstop is less than hstart. But they work... 00172 */ 00173 { REG_HSTART, 0x13 }, { REG_HSTOP, 0x01 }, 00174 { REG_HREF, 0xb6 }, { REG_VSTART, 0x02 }, 00175 { REG_VSTOP, 0x7a }, { REG_VREF, 0x0a }, 00176 00177 { REG_COM3, 0 }, { REG_COM14, 0 }, 00178 /* Mystery scaling numbers */ 00179 { 0x70, 0x3a }, //Bit[7]:Test Pattern 00180 //Bit[6:0]:Horizontal scale factor 00181 { 0x71, 0x35 }, //Bit[7]:Test Pattern (/w 0x70) 00182 //Bit[6:0]:Vertical scale factor 00183 { 0x72, 0x11 }, //DCW control 00184 //Bit[7] Vertical average calculation option 00185 // 0:Vertical truncation 00186 // 1:Vertical rounding 00187 //Bit[6] Vertical down sampling option 00188 // 0:Vertical truncation 00189 // 1:Vertical rounding 00190 //Bit[5:4] Vertical down sampling rate 00191 // 00:No down sampling, 01: by2, 10:by4, 11:by8 00192 //Bit[3] Horizontal averagecalculation option 00193 // 0: Horizontal truncation 00194 // 1: Horizontal rounding 00195 //Bit[2] Horizontal down sampling option 00196 // 0: Horizontal truncation 00197 // 1: Horizontal rounding 00198 //Bit[1:0] Horizontal down sampling rate 00199 // 00: No down sampling, 01: by2, 10:by4, 11:by8 00200 { 0x73, 0xf0 }, //Bit[7:4] Reserved (Original : 0b1111) 00201 //Bit[3] Bypass clock divider for DSP scale control 00202 // 0: Enable clock divider, 1:Bypass clock divider 00203 // Bit[2:0] Clock divider control for DSP scale control 00204 // 000: Divided by 1, 001:Divided by 2, 010:Divided by4 00205 // 100: Divided by 8, 101:Divided by 16, 110-111:Not allowed 00206 { 0xa2, 0x02 }, //Pixel Clock Delay 00207 //Bit[7]: Reserved (original:0) 00208 //Bit[6:0] Scaling output delay (original :0x02) 00209 { REG_COM10, 0x20 },//Common Control 10 (original :0x00) 00210 //Bit[7] Reserved 00211 //Bit[6] HREF changed to HSYNC 00212 //Bit[5] PCLK output option (0: Free running PCLK, 1: PCLK does not toggle during horizontal blank) 00213 //Bit[4] PCLK reverse 00214 //Bit[3] HREF reverse 00215 //Bit[2] VSYNC option (0: VSYNC changes on falling edge of PCLK, 1:rising edge) 00216 //Bit[1] VSYNC negative 00217 //Bit[0] HSYNC negative 00218 00219 /* Gamma curve values */ 00220 { 0x7a, 0x20 }, { 0x7b, 0x10 }, 00221 { 0x7c, 0x1e }, { 0x7d, 0x35 }, 00222 { 0x7e, 0x5a }, { 0x7f, 0x69 }, 00223 { 0x80, 0x76 }, { 0x81, 0x80 }, 00224 { 0x82, 0x88 }, { 0x83, 0x8f }, 00225 { 0x84, 0x96 }, { 0x85, 0xa3 }, 00226 { 0x86, 0xaf }, { 0x87, 0xc4 }, 00227 { 0x88, 0xd7 }, { 0x89, 0xe8 }, 00228 00229 /* AGC and AEC parameters. Note we start by disabling those features, 00230 then turn them only after tweaking the values. */ 00231 { REG_COM8, COM8_FASTAEC | COM8_AECSTEP | COM8_BFILT }, 00232 // Common control 8 (for AGC, AEC Off) 00233 { REG_GAIN, 0 }, 00234 { REG_AECH, 0x04 }, //AEC[9:2] 00235 { 0x07, 0x00 }, //Bit[7:6] Reserved 00236 //Bit[5:0] AEC[15:10] 00237 { 0x04, 0x00 }, //Common control 1 00238 //Bit[7] Reserved 00239 //Bit[6] CCIR format (0:Disable, 1:Enable) 00240 //Bit[5:2] Reserved 00241 //Bit[1:0] AEC[1:0] 00242 { REG_COM4, 0x40 }, /* magic reserved bit */ 00243 //Bit[7:6] Reserved (Original 0b01) 00244 //Bit[5:4] Average option(must be same value as COM17[7:6])(Original 0b00) 00245 //Bit[3:0] Reserved (Original 0b0000) 00246 { REG_COM9, 0x18 }, /* 4x gain + magic rsvd bit */ 00247 { REG_BD50MAX, 0x05 }, { REG_BD60MAX, 0x07 }, 00248 { REG_AEW, 0x95 }, //AGC/AEC - Stable Operating Region(Upper limit) 00249 { REG_AEB, 0x33 }, //AGC/AEC - Stable Operating Region(Lower limit) 00250 { REG_VPT, 0xe3 }, //AGC/AEC Fast mode Operating Region 00251 //Bit[7:4]: High nibble of upper limit of fast mode control zone 00252 //Bit[3:0]: High nibble of lower limit of fast mode control zone 00253 { REG_HAECC1, 0x78 },// Histgram based AEC/AGC Control 1 (Original : 0x78, Spec init:0xC0) 00254 { REG_HAECC2, 0x68 },// Histgram based AEC/AGC Control 2 (Original : 0x68, Spec init:0x90) 00255 { 0xa1, 0x03 }, /* magic */ 00256 { REG_HAECC3, 0xd8 },// Histgram based AEC/AGC Control 3 (Original : 0xd8, Spec init:0xF0) 00257 { REG_HAECC4, 0xd8 },// Histgram based AEC/AGC Control 4 (Original : 0xd8, Spec init:0xC1) 00258 { REG_HAECC5, 0xf0 },// Histgram based AEC/AGC Control 5 (Original : 0xf0, Spec init:0xf0) 00259 { REG_HAECC6, 0x90 },// Histgram based AEC/AGC Control 6 (Original : 0x90, Spec init:0xC1) 00260 { REG_HAECC7, 0x94 },// Histgram based AEC/AGC Control 7 (Original : 0x94, Spec init:0x14) 00261 //Bit[7]: AEC algorithm selection(0:Average-based, 1:Histogram-based) 00262 //Bit[6:0] Reserved 00263 { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC }, 00264 //COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */ 00265 //COM8_AECSTEP 0x40 /* Unlimited AEC step size */ 00266 //COM8_BFILT 0x20 /* Band filter enable */ 00267 //COM8_AGC 0x04 /* Auto gain enable */ 00268 //COM8_AWB 0x02 /* White balance enable */ 00269 //COM8_AEC 0x01 /* Auto exposure enable */ 00270 /* Almost all of these are magic "reserved" values. */ 00271 { REG_COM5, 0x61 }, //Bit[7:0] Reserved 00272 { REG_COM6, 0x4b }, //Bit[7]: Output optical black line output 0:Disable,1:Enable(original:0) 00273 //Bit[6:2] Reserved (0b10010) 00274 //Bit[1] Reset all timing when format changes 0:No reset,1:Reset (original:1) 00275 //Bit[0] Reserved (1) 00276 { 0x16, 0x02 }, //Reserved 00277 { REG_MVFP, 0x03 }, //Bit[7:6] Reserved (original 0b00) 00278 //Bit[5] Mirror 0:Normal, 1:Mirror (original 0) 00279 //Bit[4] VFlip 0:Normal, 1:Vertically flip (origianl 0) 00280 //Bit[3] Reserved (original 0) 00281 //Bit[2] Black sun enable (original 1) 00282 //Bit[1:0] Reserved (original 0b11) 00283 { 0x21, 0x02 }, { 0x22, 0x91 }, 00284 { 0x29, 0x07 }, { 0x33, 0x0b }, 00285 { 0x35, 0x0b }, { 0x37, 0x1d }, 00286 { 0x38, 0x71 }, { 0x39, 0x2a }, 00287 { REG_COM12, 0x68 }, { 0x4d, 0x40 }, 00288 { 0x4e, 0x20 }, { REG_GFIX, 0 }, 00289 { 0x6b, 0xca }, //Bit[7:6] PLL control Original:11(x8) 00290 { 0x74, 0x10 }, //Bit[4]: Digital gain contrl: 1:by VREF[7:6],0:by REG74[1:0] 00291 { 0x8d, 0x4f }, { 0x8e, 0 }, 00292 { 0x8f, 0 }, { 0x90, 0 }, 00293 { 0x91, 0 }, { 0x96, 0 }, 00294 { 0x9a, 0 }, { 0xb0, 0x84 }, 00295 { 0xb1, 0x0c }, { 0xb2, 0x0e }, 00296 { 0xb3, 0x82 }, { 0xb8, 0x0a }, 00297 00298 /* More reserved magic, some of which tweaks white balance */ 00299 { 0x43, 0x0a }, { 0x44, 0xf0 }, 00300 { 0x45, 0x34 }, { 0x46, 0x58 }, 00301 { 0x47, 0x28 }, { 0x48, 0x3a }, 00302 { 0x59, 0x88 }, { 0x5a, 0x88 }, 00303 { 0x5b, 0x44 }, { 0x5c, 0x67 }, 00304 { 0x5d, 0x49 }, { 0x5e, 0x0e }, 00305 { 0x6c, 0x0a }, { 0x6d, 0x55 }, 00306 { 0x6e, 0x11 }, { 0x6f, 0x9f }, /* "9e for advance AWB" */ 00307 { 0x6a, 0x40 }, { REG_BLUE, 0x40 }, 00308 { REG_RED, 0x60 }, 00309 //{ REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC|COM8_AWB }, 00310 { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AWB }, 00311 /* Matrix coefficients */ //default value 00312 { 0x4f, 0x80 }, { 0x50, 0x80 }, 00313 { 0x51, 0 }, { 0x52, 0x22 }, 00314 { 0x53, 0x5e }, { 0x54, 0x80 }, 00315 { 0x58, 0x9e }, 00316 00317 { REG_COM16, COM16_AWBGAIN }, 00318 { REG_EDGE, 0x00 }, //Bit[7:5]: Reserved 00319 //Bit[4:0]: Edge enchandement factor (original: 0x00) 00320 { 0x75, 0x05 }, //Bit[7:5] : reserved, Bit[4:0] : Edge Enhancement lower limit (original:0x05) 00321 { 0x76, 0xff }, //Bit[7]:Black correction enable 0:Disable, 1:Enable(original:1) 00322 //Bit[6]:White pixel correction enable: 0:Disable, 1:Enable(original:1) 00323 //Bit[5]:Reserved (original:0b10) 00324 //Bit[4:0]: Edge Enhancement higher limit(original:0x01) 00325 { 0x4c, 0 }, //De-noise Setength 00326 { 0x77, 0x00 }, //De-noise offset (original 0x01) 00327 { REG_COM13, 0xc3 }, //Common Control 13 00328 //Bit[7] Gamma enable 00329 //Bit[6] UV saturation level 00330 //Bit[5:1] Reserved 00331 //Bit[0] UV swap 00332 { 0x4b, 0x09 }, //Bit[7:1] Reserved 00333 //Bit[0] UV average enable 00334 { 0xc9, 0x60 }, //Saturation Control 00335 //Bit[7:4] UV saturation control min 00336 //Bit[3:0] UV saturation control result 00337 { REG_COM16, 0x38 }, //Common control 16 (Original 0b00111000) 00338 //Bit[7:6] Reserved (Original 0b00) 00339 //Bit[5] Enable edge enhancement threshold auto-adjustment for YUV output (Original 1) 00340 //Bit[4] De-noise threshold auto-adjustment (0:Disable, 1:Enable)(Original 1) 00341 //Bit[3] AWB gain enable (Original 1) 00342 //Bit[2] Reserved 00343 //Bit[1] Color matrix coefficient double option (0: Original, 1:Double) 00344 //Bit[0] Reserved (Original 0) 00345 { 0x56, 0x40 }, //Martix Coefficient Sign for Coefficient 5 to 0 00346 //Bit[7] Auto contrast center enable 00347 //Bit[6] Reserved 00348 //Bit[5:0] Matrix coefficient sign (0:Plus, 1:Minus) 00349 { 0x34, 0x11 }, //Array Reference Control Bit[7:0] Reserved 00350 { REG_COM11, COM11_EXP|COM11_HZAUTO }, //Common control 11 00351 //Bit[7] Night mode (0:disable, 1:Enable) 00352 //Bit[6:5] Minimum frame rate of night mode 00353 //00:same, 01:1/2, 10:1/4, 11:1/8 00354 //Bit[4] D56_Auto (0:Disable, 1:Enable) 00355 //Bit[3] Banding filter value select 00356 // 0: Select BD60ST, 1:Select BD50ST 00357 //Bit[2] Reserved 00358 //Bit[1] Exprosure timing can be less than limit of banding filter 00359 //Bit[0] Reserved 00360 { 0xa4, 0x88 }, { 0x96, 0 }, 00361 { 0x97, 0x30 }, { 0x98, 0x20 }, 00362 { 0x99, 0x30 }, { 0x9a, 0x84 }, 00363 { 0x9b, 0x29 }, { 0x9c, 0x03 }, 00364 { 0x9d, 0x4c }, { 0x9e, 0x3f }, 00365 { 0x78, 0x04 }, 00366 00367 /* Extra-weird stuff. Some sort of multiplexor register */ 00368 { 0x79, 0x01 }, { 0xc8, 0xf0 }, 00369 { 0x79, 0x0f }, { 0xc8, 0x00 }, 00370 { 0x79, 0x10 }, { 0xc8, 0x7e }, 00371 { 0x79, 0x0a }, { 0xc8, 0x80 }, 00372 { 0x79, 0x0b }, { 0xc8, 0x01 }, 00373 { 0x79, 0x0c }, { 0xc8, 0x0f }, 00374 { 0x79, 0x0d }, { 0xc8, 0x20 }, 00375 { 0x79, 0x09 }, { 0xc8, 0x80 }, 00376 { 0x79, 0x02 }, { 0xc8, 0xc0 }, 00377 { 0x79, 0x03 }, { 0xc8, 0x40 }, 00378 { 0x79, 0x05 }, { 0xc8, 0x30 }, 00379 { 0x79, 0x26 }, 00380 00381 /* Added register value */ 00382 //{ 0x30, 0x00 }, //REG_HSYSET (HSYNC Rising Edge Delay : 08 -> 00 00383 //{ 0x2A, 0x00 }, // Dummy Pixel insert MSB 00384 //{ 0x2B, 0x00 }, // Dummy Pixel insert MSB 00385 { 0x15, 0x05 }, // Common Control 10 : Bit[4] 1:PCLK negative 00386 { 0x3A, 0x05 }, //Bit[7:6]: Reserved (origina:0b00) 00387 //Bit[5]: Negative Image 0:Normal, 1:Negative (original:0) 00388 //Bit[4]: UV output value 0:Normal, 1:User define (original:0) 00389 //Bit[3]: Output sequence (original:1) 00390 //Bit[2:1]:reserved 00391 //Bit[0]: Auto output window 00392 00393 { 0xff, 0xff }, /* END MARKER */ 00394 }; 00395 00396 static struct regval_list ov7670_fmt_rgb565[] = { 00397 { REG_COM7, COM7_FMT_QVGA|COM7_RGB }, /* Selects RGB mode */ 00398 { REG_RGB444, 0 }, /* No RGB444 please */ 00399 { REG_COM1, 0x0 }, 00400 { REG_COM15, 0xc0 | COM15_RGB565 }, 00401 { REG_COM9, 0x28 }, /* 16x gain ceiling; 0x8 is reserved bit */ 00402 { 0x4f, 0xb3 }, /* "matrix coefficient 1" */ 00403 { 0x50, 0xb3 }, /* "matrix coefficient 2" */ 00404 { 0x51, 0 }, /* vb */ 00405 { 0x52, 0x3d }, /* "matrix coefficient 4" */ 00406 { 0x53, 0xa7 }, /* "matrix coefficient 5" */ 00407 { 0x54, 0xe4 }, /* "matrix coefficient 6" */ 00408 { REG_COM13, COM13_GAMMA|COM13_UVSAT }, 00409 { 0xff, 0xff }, 00410 }; 00411 00412 // QVGA setting 00413 const int width = QVGA_WIDTH; 00414 const int height= QVGA_HEIGHT; 00415 const int com7_bit= COM7_FMT_QVGA; 00416 const int hstart= 164; /* Empirically determined */ 00417 const int hstop= 20; //Original code: 20 00418 const int vstart= 14; 00419 const int vstop= 494; 00420
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