USBHALHost.h

00001 /* mbed USBHost Library
00002  * Copyright (c) 2006-2013 ARM Limited
00003  *
00004  * Licensed under the Apache License, Version 2.0 (the "License");
00005  * you may not use this file except in compliance with the License.
00006  * You may obtain a copy of the License at
00007  *
00008  *     http://www.apache.org/licenses/LICENSE-2.0
00009  *
00010  * Unless required by applicable law or agreed to in writing, software
00011  * distributed under the License is distributed on an "AS IS" BASIS,
00012  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00013  * See the License for the specific language governing permissions and
00014  * limitations under the License.
00015  */
00016  
00017 #pragma once
00018 #include "mbed.h"
00019 #include "USBHostTypes.h"
00020 #include "USBEndpoint.h"
00021 
00022 #if defined(TARGET_LPC4088)
00023 #define HcRevision      Revision
00024 #define HcControl       Control
00025 #define HcCommandStatus CommandStatus
00026 #define HcInterruptStatus InterruptStatus
00027 #define HcInterruptEnable InterruptEnable
00028 #define HcHCCA          HCCA
00029 #define HcControlHeadED ControlHeadED
00030 #define HcBulkHeadED    BulkHeadED
00031 #define HcFmInterval    FmInterval
00032 #define HcFmNumber      FmNumber
00033 #define HcPeriodicStart PeriodicStart
00034 #define HcRhStatus      RhStatus
00035 #define HcRhPortStatus1 RhPortStatus1
00036 #define OTGStCtrl       StCtrl
00037 #endif
00038 // ------------------ HcControl Register ---------------------
00039 #define  OR_CONTROL_PLE                 0x00000004
00040 #define  OR_CONTROL_IE                  0x00000008
00041 #define  OR_CONTROL_CLE                 0x00000010
00042 #define  OR_CONTROL_BLE                 0x00000020
00043 #define  OR_CONTROL_HCFS                0x000000C0
00044 #define  OR_CONTROL_HC_OPER             0x00000080
00045 // ----------------- HcCommandStatus Register -----------------
00046 #define  OR_CMD_STATUS_HCR              0x00000001
00047 #define  OR_CMD_STATUS_CLF              0x00000002
00048 #define  OR_CMD_STATUS_BLF              0x00000004
00049 // --------------- HcInterruptStatus Register -----------------
00050 #define  OR_INTR_STATUS_WDH             0x00000002
00051 #define  OR_INTR_STATUS_UE              0x00000010
00052 #define  OR_INTR_STATUS_FNO             0x00000020
00053 #define  OR_INTR_STATUS_RHSC            0x00000040
00054 // --------------- HcInterruptEnable Register -----------------
00055 #define  OR_INTR_ENABLE_WDH             0x00000002
00056 #define  OR_INTR_ENABLE_FNO             0x00000020
00057 #define  OR_INTR_ENABLE_RHSC            0x00000040
00058 #define  OR_INTR_ENABLE_MIE             0x80000000
00059 // ---------------- HcRhDescriptorA Register ------------------
00060 #define  OR_RH_STATUS_LPSC              0x00010000
00061 #define  OR_RH_STATUS_DRWE              0x00008000
00062 // -------------- HcRhPortStatus[1:NDP] Register --------------
00063 #define  OR_RH_PORT_CCS                 0x00000001
00064 #define  OR_RH_PORT_PRS                 0x00000010
00065 #define  OR_RH_PORT_LSDA                0x00000200
00066 #define  OR_RH_PORT_CSC                 0x00010000
00067 #define  OR_RH_PORT_PRSC                0x00100000
00068 
00069 // TRANSFER DESCRIPTOR CONTROL FIELDS
00070 #define  TD_ROUNDING     (uint32_t)(0x00040000) /* Buffer Rounding */
00071 #define  TD_SETUP        (uint32_t)(0x00000000) /* Direction of Setup Packet */
00072 #define  TD_IN           (uint32_t)(0x00100000) /* Direction In */
00073 #define  TD_OUT          (uint32_t)(0x00080000) /* Direction Out */
00074 #define  TD_DELAY_INT(x) (uint32_t)((x) << 21)  /* Delay Interrupt */
00075 #define  TD_DI           (uint32_t)(7<<21)      /* desable interrupt */
00076 #define  TD_TOGGLE_0     (uint32_t)(0x02000000) /* Toggle 0 */
00077 #define  TD_TOGGLE_1     (uint32_t)(0x03000000) /* Toggle 1 */
00078 #define  TD_CC           (uint32_t)(0xF0000000) /* Completion Code */
00079 
00080 struct SETUP_PACKET {
00081     uint8_t bmRequestType;
00082     uint8_t bRequest;
00083     uint16_t wValue;
00084     uint16_t wIndex;
00085     uint16_t wLength;
00086     SETUP_PACKET(uint8_t RequestType, uint8_t Request, uint16_t Value, uint16_t Index, uint16_t Length) {
00087         bmRequestType = RequestType;
00088         bRequest = Request;
00089         wValue = Value;
00090         wIndex = Index;
00091         wLength = Length;
00092     }
00093 };
00094 
00095 void* usb_ram_malloc(size_t size, int aligment); // BaseUsbHostLib.cpp
00096 void usb_ram_free(void* p);
00097 
00098 struct TBUF {
00099     uint8_t buf[0];
00100     TBUF(const void* data = NULL, int size = 0);
00101     void* operator new(size_t size, int buf_size) { return usb_ram_malloc(size+buf_size, 4); }
00102     void operator delete(void* p) { usb_ram_free(p); }
00103 };
00104 
00105 struct HCTD {    // HostController Transfer Descriptor
00106     __IO uint32_t Control;    // +0 Transfer descriptor control
00107     __IO uint8_t* CurrBufPtr; // +4 Physical address of current buffer pointer
00108     HCTD* Next;               // +8 Physical pointer to next Transfer Descriptor
00109     uint8_t*  BufEnd;         // +12 Physical address of end of buffer
00110     uint8_t* buf_top;         // +16 Buffer start address
00111     uint16_t buf_size;        // +20 buffer size size
00112     uint8_t _dummy[10];       // +22 dummy
00113     USBEndpoint* ep;          // +32 endpoint object
00114                               // +36
00115     HCTD(USBEndpoint* obj);
00116     void* operator new(size_t size) { return usb_ram_malloc(size, 16); }
00117     void operator delete(void* p) { usb_ram_free(p); }
00118 
00119     void transfer(TBUF* tbuf, int len) {
00120         CurrBufPtr = tbuf->buf;
00121         buf_top = tbuf->buf;
00122         buf_size = len;
00123         BufEnd = const_cast<uint8_t*>(tbuf->buf)+len-1;
00124     }
00125     int getLengthTransferred() {
00126         if (CurrBufPtr) {
00127             return CurrBufPtr - buf_top;
00128         }
00129         return buf_size;
00130     }
00131     int status() {
00132         if (CurrBufPtr) {
00133             return CurrBufPtr - buf_top;
00134         }
00135         return buf_size;
00136     }
00137     
00138     uint8_t ConditionCode() {
00139         return Control>>28;
00140     }    
00141 }; 
00142 
00143 struct HCITD {    // HostController Isochronous Transfer Descriptor
00144     __IO uint32_t Control;      // +0 Transfer descriptor control
00145     uint8_t*  BufferPage0;      // +4 Buffer Page 0
00146     HCITD* Next;                // +8 Physical pointer to next Isochronous Transfer Descriptor
00147     uint8_t*  BufferEnd;        // +12 buffer End
00148     __IO uint16_t OffsetPSW[8]; // +16 Offset/PSW
00149     USBEndpoint* ep;                 // +32 endpoint object
00150     __IO uint8_t buf[0];        // +36 buffer
00151                                 // +36
00152     HCITD(USBEndpoint* obj, uint16_t FrameNumber, int FrameCount, uint16_t PacketSize);
00153     void* operator new(size_t size, int buf_size) { return usb_ram_malloc(size+buf_size, 32); }
00154     void operator delete(void* p) { usb_ram_free(p); }
00155 
00156     uint16_t StartingFrame() {
00157         return Control & 0xffff;
00158     }
00159 
00160     uint8_t FrameCount() {
00161         return ((Control>>24)&7)+1;
00162     }    
00163 
00164     uint8_t ConditionCode() {
00165         return Control>>28;
00166     }
00167 };
00168 
00169 struct HCED {    // HostController EndPoint Descriptor
00170     __IO uint32_t Control; // +0 Endpoint descriptor control
00171     HCTD* TailTd;          // +4 Physical address of tail in Transfer descriptor list
00172     __IO HCTD* HeadTd;     // +8 Physcial address of head in Transfer descriptor list
00173     HCED* Next;            // +12 Physical address of next Endpoint descriptor
00174                            // +16
00175     HCED(USBEndpoint* ep);
00176     void* operator new(size_t size) { return usb_ram_malloc(size, 16); }
00177     void operator delete(void* p) { usb_ram_free(p); }
00178 
00179     uint8_t FunctionAddress() {
00180         return Control & 0x7f;
00181     }
00182 
00183     uint8_t EndpointNumber() {
00184         return (Control>>7) & 0x7f;
00185     }
00186 
00187     int Speed() {
00188         return (Control>>13)&1;
00189     }
00190 
00191     void setFunctionAddress(int addr) {
00192         Control &= ~0x7f;
00193         Control |= addr;
00194     }
00195 
00196     void setMaxPacketSize(uint16_t size) {
00197         Control &= ~0xffff0000;
00198         Control |= size<<16;
00199     }
00200 
00201     void setToggleDATA1() {
00202         uint32_t c = reinterpret_cast<uint32_t>(HeadTd);
00203         c |= 0x02;
00204         HeadTd = reinterpret_cast<HCTD*>(c);
00205     }
00206 
00207     int Skip() {
00208         return (Control>>14) & 1;
00209     }
00210 
00211     void setSkip() {
00212         Control |= (1<<14);
00213     }
00214 
00215     void setFormat() {
00216         Control |= (1<<15);
00217     }
00218 
00219     bool enqueue(HCTD* td);
00220     void init_queue(HCTD* td);
00221 };
00222 
00223 struct HCCA {    // Host Controller Communication Area
00224     HCED* InterruptTable[32]; // +0 Interrupt Table
00225     __IO uint16_t FrameNumber;// +128 Frame Number
00226     __IO uint16_t Pad1;       // +130
00227     __IO HCTD* DoneHead;      // +132 Done Head
00228     uint8_t Reserved[116];    // +136 Reserved for future use
00229     uint8_t Unknown[4];       // +252 Unused
00230                               // +256
00231     void* operator new(size_t size) { return usb_ram_malloc(size, 256); }
00232     void operator delete(void* p) { usb_ram_free(p); }
00233     void enqueue(HCED* ed);
00234 };
00235 
00236 class USBHALHost {
00237 public:
00238     uint8_t LastStatus;
00239     uint8_t prev_LastStatus;
00240     static void enable(ENDPOINT_TYPE type);
00241 
00242 protected:
00243     USBHALHost();
00244     void init();
00245     void init_hw_ohci(HCCA* pHcca);
00246     void ResetRootHub();
00247     virtual bool addDevice(USBDeviceConnected* parent, int port, bool lowSpeed) = 0;
00248     //void setAddr(int addr, bool lowSpeed = false);
00249     //void setEndpoint();
00250     //void token_transfer_init();
00251     void token_init(USBEndpoint* ep);
00252     int token_setup(USBEndpoint* ep, SETUP_PACKET* setup, uint16_t wLength = 0);
00253     int token_in(USBEndpoint* ep, uint8_t* data = NULL, int size = 0, int retryLimit = 0);
00254     int token_out(USBEndpoint* ep, const uint8_t* data = NULL, int size = 0, int retryLimit = 0);
00255     void token_inNB(USBEndpoint* ep, uint8_t* data, int size);
00256     USB_TYPE token_inNB_result(USBEndpoint* ep);
00257     //void token_ready();
00258     // report
00259     uint32_t m_report_irq; 
00260     uint32_t m_report_RHSC;
00261     uint32_t m_report_FNO; 
00262     uint32_t m_report_WDH;  
00263     uint32_t m_report_sp;
00264 
00265 private:
00266     static void _usbisr(void);
00267     void UsbIrqhandler();
00268     HCCA* m_pHcca;
00269     //__IO bool attach_done;
00270     //__IO bool token_done;
00271     bool wait_attach();
00272     bool root_lowSpeed;
00273     static USBHALHost * instHost;
00274 };
00275