schneider françois / FT800okForConnectEvewithLuminosite

Ok for EveConnect

Dependents:   FT800_RGB_demo-for_ConnectEve

FT_Gpu_Hal.cpp@0:352efe1d072f, 2019-03-11 (annotated)

Committer:
schnf30
Date:
Mon Mar 11 19:14:19 2019 +0000
Revision:
0:352efe1d072f
Programme demo FT800 for ConnectEve. It's Ok.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
schnf30 0:352efe1d072f 1 /* mbed Library for FTDI FT800 Enbedded Video Engine "EVE"
schnf30 0:352efe1d072f 2 * based on Original Code Sample from FTDI
schnf30 0:352efe1d072f 3 * ported to mbed by Peter Drescher, DC2PD 2014
schnf30 0:352efe1d072f 4 * Released under the MIT License: http://mbed.org/license/mit
schnf30 0:352efe1d072f 5 * 19.09.14 changed to shorter function names
schnf30 0:352efe1d072f 6 * FTDI was using very long names.
schnf30 0:352efe1d072f 7 * Ft_App_Flush_Co_Buffer -> Flush_Co_Buffer ... */
schnf30 0:352efe1d072f 8
schnf30 0:352efe1d072f 9 #include "FT_Platform.h"
schnf30 0:352efe1d072f 10 #include "mbed.h"
schnf30 0:352efe1d072f 11 #include "FT_LCD_Type.h"
schnf30 0:352efe1d072f 12
schnf30 0:352efe1d072f 13 FT800::FT800(PinName mosi,
schnf30 0:352efe1d072f 14 PinName miso,
schnf30 0:352efe1d072f 15 PinName sck,
schnf30 0:352efe1d072f 16 PinName ss,
schnf30 0:352efe1d072f 17 PinName intr,
schnf30 0:352efe1d072f 18 PinName pd)
schnf30 0:352efe1d072f 19 :_spi(mosi, miso, sck),
schnf30 0:352efe1d072f 20 _ss(ss),
schnf30 0:352efe1d072f 21 _f800_isr(InterruptIn(intr)),
schnf30 0:352efe1d072f 22 _pd(pd)
schnf30 0:352efe1d072f 23 {
schnf30 0:352efe1d072f 24 _spi.format(8,0); // 8 bit spi mode 0
schnf30 0:352efe1d072f 25 _spi.frequency(10000000); // start with 10 Mhz SPI clock
schnf30 0:352efe1d072f 26 _ss = 1; // cs high
schnf30 0:352efe1d072f 27 _pd = 1; // PD high
schnf30 0:352efe1d072f 28 Bootup();
schnf30 0:352efe1d072f 29 }
schnf30 0:352efe1d072f 30
schnf30 0:352efe1d072f 31
schnf30 0:352efe1d072f 32 ft_bool_t FT800::Bootup(void){
schnf30 0:352efe1d072f 33 Open();
schnf30 0:352efe1d072f 34 BootupConfig();
schnf30 0:352efe1d072f 35
schnf30 0:352efe1d072f 36 return(1);
schnf30 0:352efe1d072f 37 }
schnf30 0:352efe1d072f 38
schnf30 0:352efe1d072f 39
schnf30 0:352efe1d072f 40 ft_void_t FT800::BootupConfig(void){
schnf30 0:352efe1d072f 41 ft_uint8_t chipid;
schnf30 0:352efe1d072f 42 /* Do a power cycle for safer side */
schnf30 0:352efe1d072f 43 Powercycle( FT_TRUE);
schnf30 0:352efe1d072f 44
schnf30 0:352efe1d072f 45 /* Access address 0 to wake up the FT800 */
schnf30 0:352efe1d072f 46 HostCommand( FT_GPU_ACTIVE_M);
schnf30 0:352efe1d072f 47 Sleep(20);
schnf30 0:352efe1d072f 48
schnf30 0:352efe1d072f 49 /* Set the clk to external clock */
schnf30 0:352efe1d072f 50 HostCommand( FT_GPU_EXTERNAL_OSC);
schnf30 0:352efe1d072f 51 Sleep(10);
schnf30 0:352efe1d072f 52
schnf30 0:352efe1d072f 53
schnf30 0:352efe1d072f 54 /* Switch PLL output to 48MHz */
schnf30 0:352efe1d072f 55 HostCommand( FT_GPU_PLL_48M);
schnf30 0:352efe1d072f 56 Sleep(10);
schnf30 0:352efe1d072f 57
schnf30 0:352efe1d072f 58 /* Do a core reset for safer side */
schnf30 0:352efe1d072f 59 HostCommand( FT_GPU_CORE_RESET);
schnf30 0:352efe1d072f 60
schnf30 0:352efe1d072f 61 //Read Register ID to check if FT800 is ready.
schnf30 0:352efe1d072f 62 chipid = Rd8( REG_ID);
schnf30 0:352efe1d072f 63 while(chipid != 0x7C)
schnf30 0:352efe1d072f 64 chipid = Rd8( REG_ID);
schnf30 0:352efe1d072f 65
schnf30 0:352efe1d072f 66
schnf30 0:352efe1d072f 67 // Speed up
schnf30 0:352efe1d072f 68 _spi.frequency(16000000); // 20 Mhz SPI clock
schnf30 0:352efe1d072f 69
schnf30 0:352efe1d072f 70 /* Configuration of LCD display */
schnf30 0:352efe1d072f 71 DispHCycle = my_DispHCycle;
schnf30 0:352efe1d072f 72 Wr16( REG_HCYCLE, DispHCycle);
schnf30 0:352efe1d072f 73 DispHOffset = my_DispHOffset;
schnf30 0:352efe1d072f 74 Wr16( REG_HOFFSET, DispHOffset);
schnf30 0:352efe1d072f 75 DispWidth = my_DispWidth;
schnf30 0:352efe1d072f 76 Wr16( REG_HSIZE, DispWidth);
schnf30 0:352efe1d072f 77 DispHSync0 = my_DispHSync0;
schnf30 0:352efe1d072f 78 Wr16( REG_HSYNC0, DispHSync0);
schnf30 0:352efe1d072f 79 DispHSync1 = my_DispHSync1;
schnf30 0:352efe1d072f 80 Wr16( REG_HSYNC1, DispHSync1);
schnf30 0:352efe1d072f 81 DispVCycle = my_DispVCycle;
schnf30 0:352efe1d072f 82 Wr16( REG_VCYCLE, DispVCycle);
schnf30 0:352efe1d072f 83 DispVOffset = my_DispVOffset;
schnf30 0:352efe1d072f 84 Wr16( REG_VOFFSET, DispVOffset);
schnf30 0:352efe1d072f 85 DispHeight = my_DispHeight;
schnf30 0:352efe1d072f 86 Wr16( REG_VSIZE, DispHeight);
schnf30 0:352efe1d072f 87 DispVSync0 = my_DispVSync0;
schnf30 0:352efe1d072f 88 Wr16( REG_VSYNC0, DispVSync0);
schnf30 0:352efe1d072f 89 DispVSync1 = my_DispVSync1;
schnf30 0:352efe1d072f 90 Wr16( REG_VSYNC1, DispVSync1);
schnf30 0:352efe1d072f 91 DispSwizzle = my_DispSwizzle;
schnf30 0:352efe1d072f 92 Wr8( REG_SWIZZLE, DispSwizzle);
schnf30 0:352efe1d072f 93 DispPCLKPol = my_DispPCLKPol;
schnf30 0:352efe1d072f 94 Wr8( REG_PCLK_POL, DispPCLKPol);
schnf30 0:352efe1d072f 95 Wr8( REG_CSPREAD, 1);
schnf30 0:352efe1d072f 96 DispPCLK = my_DispPCLK;
schnf30 0:352efe1d072f 97 Wr8( REG_PCLK, DispPCLK);//after this display is visible on the LCD
schnf30 0:352efe1d072f 98
schnf30 0:352efe1d072f 99 Wr16( REG_PWM_HZ, 1000);
schnf30 0:352efe1d072f 100
schnf30 0:352efe1d072f 101 #ifdef Inv_Backlite // turn on backlite
schnf30 0:352efe1d072f 102 Wr16( REG_PWM_DUTY, 0);
schnf30 0:352efe1d072f 103 #else
schnf30 0:352efe1d072f 104 Wr16( REG_PWM_DUTY, 100);
schnf30 0:352efe1d072f 105 #endif
schnf30 0:352efe1d072f 106
schnf30 0:352efe1d072f 107 Wr8( REG_GPIO_DIR,0x82); //| Rd8( REG_GPIO_DIR));
schnf30 0:352efe1d072f 108 Wr8( REG_GPIO,0x080); //| Rd8( REG_GPIO));
schnf30 0:352efe1d072f 109
schnf30 0:352efe1d072f 110 Wr32( RAM_DL, CLEAR(1,1,1));
schnf30 0:352efe1d072f 111 Wr32( RAM_DL+4, DISPLAY());
schnf30 0:352efe1d072f 112 Wr32( REG_DLSWAP,1);
schnf30 0:352efe1d072f 113
schnf30 0:352efe1d072f 114 Wr16( REG_PCLK, DispPCLK);
schnf30 0:352efe1d072f 115
schnf30 0:352efe1d072f 116 /* Touch configuration - configure the resistance value to 1200 - this value is specific to customer requirement and derived by experiment */
schnf30 0:352efe1d072f 117 Wr16( REG_TOUCH_RZTHRESH,1200);
schnf30 0:352efe1d072f 118
schnf30 0:352efe1d072f 119 }
schnf30 0:352efe1d072f 120
schnf30 0:352efe1d072f 121
schnf30 0:352efe1d072f 122
schnf30 0:352efe1d072f 123 /* API to initialize the SPI interface */
schnf30 0:352efe1d072f 124 ft_bool_t FT800::Init()
schnf30 0:352efe1d072f 125 {
schnf30 0:352efe1d072f 126 // is done in constructor
schnf30 0:352efe1d072f 127 return 1;
schnf30 0:352efe1d072f 128 }
schnf30 0:352efe1d072f 129
schnf30 0:352efe1d072f 130
schnf30 0:352efe1d072f 131 ft_bool_t FT800::Open()
schnf30 0:352efe1d072f 132 {
schnf30 0:352efe1d072f 133 cmd_fifo_wp = dl_buff_wp = 0;
schnf30 0:352efe1d072f 134 status = OPENED;
schnf30 0:352efe1d072f 135 return 1;
schnf30 0:352efe1d072f 136 }
schnf30 0:352efe1d072f 137
schnf30 0:352efe1d072f 138 ft_void_t FT800::Close( )
schnf30 0:352efe1d072f 139 {
schnf30 0:352efe1d072f 140 status = CLOSED;
schnf30 0:352efe1d072f 141 }
schnf30 0:352efe1d072f 142
schnf30 0:352efe1d072f 143 ft_void_t FT800::DeInit()
schnf30 0:352efe1d072f 144 {
schnf30 0:352efe1d072f 145
schnf30 0:352efe1d072f 146 }
schnf30 0:352efe1d072f 147
schnf30 0:352efe1d072f 148 /*The APIs for reading/writing transfer continuously only with small buffer system*/
schnf30 0:352efe1d072f 149 ft_void_t FT800::StartTransfer( FT_GPU_TRANSFERDIR_T rw,ft_uint32_t addr)
schnf30 0:352efe1d072f 150 {
schnf30 0:352efe1d072f 151 if (FT_GPU_READ == rw){
schnf30 0:352efe1d072f 152 _ss = 0; // cs low
schnf30 0:352efe1d072f 153 _spi.write(addr >> 16);
schnf30 0:352efe1d072f 154 _spi.write(addr >> 8);
schnf30 0:352efe1d072f 155 _spi.write(addr & 0xff);
schnf30 0:352efe1d072f 156 _spi.write(0); //Dummy Read Byte
schnf30 0:352efe1d072f 157 status = READING;
schnf30 0:352efe1d072f 158 }else{
schnf30 0:352efe1d072f 159 _ss = 0; // cs low
schnf30 0:352efe1d072f 160 _spi.write(0x80 | (addr >> 16));
schnf30 0:352efe1d072f 161 _spi.write(addr >> 8);
schnf30 0:352efe1d072f 162 _spi.write(addr & 0xff);
schnf30 0:352efe1d072f 163 status = WRITING;
schnf30 0:352efe1d072f 164 }
schnf30 0:352efe1d072f 165 }
schnf30 0:352efe1d072f 166
schnf30 0:352efe1d072f 167
schnf30 0:352efe1d072f 168 /*The APIs for writing transfer continuously only*/
schnf30 0:352efe1d072f 169 ft_void_t FT800::StartCmdTransfer( FT_GPU_TRANSFERDIR_T rw, ft_uint16_t count)
schnf30 0:352efe1d072f 170 {
schnf30 0:352efe1d072f 171 StartTransfer( rw, cmd_fifo_wp + RAM_CMD);
schnf30 0:352efe1d072f 172 }
schnf30 0:352efe1d072f 173
schnf30 0:352efe1d072f 174 ft_uint8_t FT800::TransferString( const ft_char8_t *string)
schnf30 0:352efe1d072f 175 {
schnf30 0:352efe1d072f 176 ft_uint16_t length = strlen(string);
schnf30 0:352efe1d072f 177 while(length --){
schnf30 0:352efe1d072f 178 Transfer8( *string);
schnf30 0:352efe1d072f 179 string ++;
schnf30 0:352efe1d072f 180 }
schnf30 0:352efe1d072f 181 //Append one null as ending flag
schnf30 0:352efe1d072f 182 Transfer8( 0);
schnf30 0:352efe1d072f 183 return(1);
schnf30 0:352efe1d072f 184 }
schnf30 0:352efe1d072f 185
schnf30 0:352efe1d072f 186
schnf30 0:352efe1d072f 187 ft_uint8_t FT800::Transfer8( ft_uint8_t value)
schnf30 0:352efe1d072f 188 {
schnf30 0:352efe1d072f 189 return _spi.write(value);
schnf30 0:352efe1d072f 190 }
schnf30 0:352efe1d072f 191
schnf30 0:352efe1d072f 192
schnf30 0:352efe1d072f 193 ft_uint16_t FT800::Transfer16( ft_uint16_t value)
schnf30 0:352efe1d072f 194 {
schnf30 0:352efe1d072f 195 ft_uint16_t retVal = 0;
schnf30 0:352efe1d072f 196
schnf30 0:352efe1d072f 197 if (status == WRITING){
schnf30 0:352efe1d072f 198 Transfer8( value & 0xFF);//LSB first
schnf30 0:352efe1d072f 199 Transfer8( (value >> 8) & 0xFF);
schnf30 0:352efe1d072f 200 }else{
schnf30 0:352efe1d072f 201 retVal = Transfer8( 0);
schnf30 0:352efe1d072f 202 retVal |= (ft_uint16_t)Transfer8( 0) << 8;
schnf30 0:352efe1d072f 203 }
schnf30 0:352efe1d072f 204
schnf30 0:352efe1d072f 205 return retVal;
schnf30 0:352efe1d072f 206 }
schnf30 0:352efe1d072f 207
schnf30 0:352efe1d072f 208 ft_uint32_t FT800::Transfer32( ft_uint32_t value)
schnf30 0:352efe1d072f 209 {
schnf30 0:352efe1d072f 210 ft_uint32_t retVal = 0;
schnf30 0:352efe1d072f 211 if (status == WRITING){
schnf30 0:352efe1d072f 212 Transfer16( value & 0xFFFF);//LSB first
schnf30 0:352efe1d072f 213 Transfer16( (value >> 16) & 0xFFFF);
schnf30 0:352efe1d072f 214 }else{
schnf30 0:352efe1d072f 215 retVal = Transfer16( 0);
schnf30 0:352efe1d072f 216 retVal |= (ft_uint32_t)Transfer16( 0) << 16;
schnf30 0:352efe1d072f 217 }
schnf30 0:352efe1d072f 218 return retVal;
schnf30 0:352efe1d072f 219 }
schnf30 0:352efe1d072f 220
schnf30 0:352efe1d072f 221 ft_void_t FT800::EndTransfer( )
schnf30 0:352efe1d072f 222 {
schnf30 0:352efe1d072f 223 _ss = 1;
schnf30 0:352efe1d072f 224 status = OPENED;
schnf30 0:352efe1d072f 225 }
schnf30 0:352efe1d072f 226
schnf30 0:352efe1d072f 227
schnf30 0:352efe1d072f 228 ft_uint8_t FT800::Rd8( ft_uint32_t addr)
schnf30 0:352efe1d072f 229 {
schnf30 0:352efe1d072f 230 ft_uint8_t value;
schnf30 0:352efe1d072f 231 StartTransfer( FT_GPU_READ,addr);
schnf30 0:352efe1d072f 232 value = Transfer8( 0);
schnf30 0:352efe1d072f 233 EndTransfer( );
schnf30 0:352efe1d072f 234 return value;
schnf30 0:352efe1d072f 235 }
schnf30 0:352efe1d072f 236 ft_uint16_t FT800::Rd16( ft_uint32_t addr)
schnf30 0:352efe1d072f 237 {
schnf30 0:352efe1d072f 238 ft_uint16_t value;
schnf30 0:352efe1d072f 239 StartTransfer( FT_GPU_READ,addr);
schnf30 0:352efe1d072f 240 value = Transfer16( 0);
schnf30 0:352efe1d072f 241 EndTransfer( );
schnf30 0:352efe1d072f 242 return value;
schnf30 0:352efe1d072f 243 }
schnf30 0:352efe1d072f 244 ft_uint32_t FT800::Rd32( ft_uint32_t addr)
schnf30 0:352efe1d072f 245 {
schnf30 0:352efe1d072f 246 ft_uint32_t value;
schnf30 0:352efe1d072f 247 StartTransfer( FT_GPU_READ,addr);
schnf30 0:352efe1d072f 248 value = Transfer32( 0);
schnf30 0:352efe1d072f 249 EndTransfer( );
schnf30 0:352efe1d072f 250 return value;
schnf30 0:352efe1d072f 251 }
schnf30 0:352efe1d072f 252
schnf30 0:352efe1d072f 253 ft_void_t FT800::Wr8( ft_uint32_t addr, ft_uint8_t v)
schnf30 0:352efe1d072f 254 {
schnf30 0:352efe1d072f 255 StartTransfer( FT_GPU_WRITE,addr);
schnf30 0:352efe1d072f 256 Transfer8( v);
schnf30 0:352efe1d072f 257 EndTransfer( );
schnf30 0:352efe1d072f 258 }
schnf30 0:352efe1d072f 259 ft_void_t FT800::Wr16( ft_uint32_t addr, ft_uint16_t v)
schnf30 0:352efe1d072f 260 {
schnf30 0:352efe1d072f 261 StartTransfer( FT_GPU_WRITE,addr);
schnf30 0:352efe1d072f 262 Transfer16( v);
schnf30 0:352efe1d072f 263 EndTransfer( );
schnf30 0:352efe1d072f 264 }
schnf30 0:352efe1d072f 265 ft_void_t FT800::Wr32( ft_uint32_t addr, ft_uint32_t v)
schnf30 0:352efe1d072f 266 {
schnf30 0:352efe1d072f 267 StartTransfer( FT_GPU_WRITE,addr);
schnf30 0:352efe1d072f 268 Transfer32( v);
schnf30 0:352efe1d072f 269 EndTransfer( );
schnf30 0:352efe1d072f 270 }
schnf30 0:352efe1d072f 271
schnf30 0:352efe1d072f 272 ft_void_t FT800::HostCommand( ft_uint8_t cmd)
schnf30 0:352efe1d072f 273 {
schnf30 0:352efe1d072f 274 _ss = 0;
schnf30 0:352efe1d072f 275 _spi.write(cmd);
schnf30 0:352efe1d072f 276 _spi.write(0);
schnf30 0:352efe1d072f 277 _spi.write(0);
schnf30 0:352efe1d072f 278 _ss = 1;
schnf30 0:352efe1d072f 279 }
schnf30 0:352efe1d072f 280
schnf30 0:352efe1d072f 281 ft_void_t FT800::ClockSelect( FT_GPU_PLL_SOURCE_T pllsource)
schnf30 0:352efe1d072f 282 {
schnf30 0:352efe1d072f 283 HostCommand( pllsource);
schnf30 0:352efe1d072f 284 }
schnf30 0:352efe1d072f 285
schnf30 0:352efe1d072f 286 ft_void_t FT800::PLL_FreqSelect( FT_GPU_PLL_FREQ_T freq)
schnf30 0:352efe1d072f 287 {
schnf30 0:352efe1d072f 288 HostCommand( freq);
schnf30 0:352efe1d072f 289 }
schnf30 0:352efe1d072f 290
schnf30 0:352efe1d072f 291 ft_void_t FT800::PowerModeSwitch( FT_GPU_POWER_MODE_T pwrmode)
schnf30 0:352efe1d072f 292 {
schnf30 0:352efe1d072f 293 HostCommand( pwrmode);
schnf30 0:352efe1d072f 294 }
schnf30 0:352efe1d072f 295
schnf30 0:352efe1d072f 296 ft_void_t FT800::CoreReset( )
schnf30 0:352efe1d072f 297 {
schnf30 0:352efe1d072f 298 HostCommand( 0x68);
schnf30 0:352efe1d072f 299 }
schnf30 0:352efe1d072f 300
schnf30 0:352efe1d072f 301
schnf30 0:352efe1d072f 302 ft_void_t FT800::Updatecmdfifo( ft_uint16_t count)
schnf30 0:352efe1d072f 303 {
schnf30 0:352efe1d072f 304 cmd_fifo_wp = ( cmd_fifo_wp + count) & 4095;
schnf30 0:352efe1d072f 305 //4 byte alignment
schnf30 0:352efe1d072f 306 cmd_fifo_wp = ( cmd_fifo_wp + 3) & 0xffc;
schnf30 0:352efe1d072f 307 Wr16( REG_CMD_WRITE, cmd_fifo_wp);
schnf30 0:352efe1d072f 308 }
schnf30 0:352efe1d072f 309
schnf30 0:352efe1d072f 310
schnf30 0:352efe1d072f 311 ft_uint16_t FT800::fifo_Freespace( )
schnf30 0:352efe1d072f 312 {
schnf30 0:352efe1d072f 313 ft_uint16_t fullness,retval;
schnf30 0:352efe1d072f 314
schnf30 0:352efe1d072f 315 fullness = ( cmd_fifo_wp - Rd16( REG_CMD_READ)) & 4095;
schnf30 0:352efe1d072f 316 retval = (FT_CMD_FIFO_SIZE - 4) - fullness;
schnf30 0:352efe1d072f 317 return (retval);
schnf30 0:352efe1d072f 318 }
schnf30 0:352efe1d072f 319
schnf30 0:352efe1d072f 320 ft_void_t FT800::WrCmdBuf( ft_uint8_t *buffer,ft_uint16_t count)
schnf30 0:352efe1d072f 321 {
schnf30 0:352efe1d072f 322 ft_uint32_t length =0, SizeTransfered = 0;
schnf30 0:352efe1d072f 323
schnf30 0:352efe1d072f 324 #define MAX_CMD_FIFO_TRANSFER fifo_Freespace( )
schnf30 0:352efe1d072f 325 do {
schnf30 0:352efe1d072f 326 length = count;
schnf30 0:352efe1d072f 327 if (length > MAX_CMD_FIFO_TRANSFER){
schnf30 0:352efe1d072f 328 length = MAX_CMD_FIFO_TRANSFER;
schnf30 0:352efe1d072f 329 }
schnf30 0:352efe1d072f 330 CheckCmdBuffer( length);
schnf30 0:352efe1d072f 331
schnf30 0:352efe1d072f 332 StartCmdTransfer( FT_GPU_WRITE,length);
schnf30 0:352efe1d072f 333
schnf30 0:352efe1d072f 334 SizeTransfered = 0;
schnf30 0:352efe1d072f 335 while (length--) {
schnf30 0:352efe1d072f 336 Transfer8( *buffer);
schnf30 0:352efe1d072f 337 buffer++;
schnf30 0:352efe1d072f 338 SizeTransfered ++;
schnf30 0:352efe1d072f 339 }
schnf30 0:352efe1d072f 340 length = SizeTransfered;
schnf30 0:352efe1d072f 341
schnf30 0:352efe1d072f 342 EndTransfer( );
schnf30 0:352efe1d072f 343 Updatecmdfifo( length);
schnf30 0:352efe1d072f 344
schnf30 0:352efe1d072f 345 WaitCmdfifo_empty( );
schnf30 0:352efe1d072f 346
schnf30 0:352efe1d072f 347 count -= length;
schnf30 0:352efe1d072f 348 }while (count > 0);
schnf30 0:352efe1d072f 349 }
schnf30 0:352efe1d072f 350
schnf30 0:352efe1d072f 351
schnf30 0:352efe1d072f 352 ft_void_t FT800::WrCmdBufFromFlash( FT_PROGMEM ft_prog_uchar8_t *buffer,ft_uint16_t count)
schnf30 0:352efe1d072f 353 {
schnf30 0:352efe1d072f 354 ft_uint32_t length =0, SizeTransfered = 0;
schnf30 0:352efe1d072f 355
schnf30 0:352efe1d072f 356 #define MAX_CMD_FIFO_TRANSFER fifo_Freespace( )
schnf30 0:352efe1d072f 357 do {
schnf30 0:352efe1d072f 358 length = count;
schnf30 0:352efe1d072f 359 if (length > MAX_CMD_FIFO_TRANSFER){
schnf30 0:352efe1d072f 360 length = MAX_CMD_FIFO_TRANSFER;
schnf30 0:352efe1d072f 361 }
schnf30 0:352efe1d072f 362 CheckCmdBuffer( length);
schnf30 0:352efe1d072f 363
schnf30 0:352efe1d072f 364 StartCmdTransfer( FT_GPU_WRITE,length);
schnf30 0:352efe1d072f 365
schnf30 0:352efe1d072f 366
schnf30 0:352efe1d072f 367 SizeTransfered = 0;
schnf30 0:352efe1d072f 368 while (length--) {
schnf30 0:352efe1d072f 369 Transfer8( ft_pgm_read_byte_near(buffer));
schnf30 0:352efe1d072f 370 buffer++;
schnf30 0:352efe1d072f 371 SizeTransfered ++;
schnf30 0:352efe1d072f 372 }
schnf30 0:352efe1d072f 373 length = SizeTransfered;
schnf30 0:352efe1d072f 374
schnf30 0:352efe1d072f 375 EndTransfer( );
schnf30 0:352efe1d072f 376 Updatecmdfifo( length);
schnf30 0:352efe1d072f 377
schnf30 0:352efe1d072f 378 WaitCmdfifo_empty( );
schnf30 0:352efe1d072f 379
schnf30 0:352efe1d072f 380 count -= length;
schnf30 0:352efe1d072f 381 }while (count > 0);
schnf30 0:352efe1d072f 382 }
schnf30 0:352efe1d072f 383
schnf30 0:352efe1d072f 384
schnf30 0:352efe1d072f 385 ft_void_t FT800::CheckCmdBuffer( ft_uint16_t count)
schnf30 0:352efe1d072f 386 {
schnf30 0:352efe1d072f 387 ft_uint16_t getfreespace;
schnf30 0:352efe1d072f 388 do{
schnf30 0:352efe1d072f 389 getfreespace = fifo_Freespace( );
schnf30 0:352efe1d072f 390 }while(getfreespace < count);
schnf30 0:352efe1d072f 391 }
schnf30 0:352efe1d072f 392
schnf30 0:352efe1d072f 393 ft_void_t FT800::WaitCmdfifo_empty( )
schnf30 0:352efe1d072f 394 {
schnf30 0:352efe1d072f 395 while(Rd16( REG_CMD_READ) != Rd16( REG_CMD_WRITE));
schnf30 0:352efe1d072f 396
schnf30 0:352efe1d072f 397 cmd_fifo_wp = Rd16( REG_CMD_WRITE);
schnf30 0:352efe1d072f 398 }
schnf30 0:352efe1d072f 399
schnf30 0:352efe1d072f 400 ft_void_t FT800::WaitLogo_Finish( )
schnf30 0:352efe1d072f 401 {
schnf30 0:352efe1d072f 402 ft_int16_t cmdrdptr,cmdwrptr;
schnf30 0:352efe1d072f 403
schnf30 0:352efe1d072f 404 do{
schnf30 0:352efe1d072f 405 cmdrdptr = Rd16( REG_CMD_READ);
schnf30 0:352efe1d072f 406 cmdwrptr = Rd16( REG_CMD_WRITE);
schnf30 0:352efe1d072f 407 }while ((cmdwrptr != cmdrdptr) || (cmdrdptr != 0));
schnf30 0:352efe1d072f 408 cmd_fifo_wp = 0;
schnf30 0:352efe1d072f 409 }
schnf30 0:352efe1d072f 410
schnf30 0:352efe1d072f 411
schnf30 0:352efe1d072f 412 ft_void_t FT800::ResetCmdFifo( )
schnf30 0:352efe1d072f 413 {
schnf30 0:352efe1d072f 414 cmd_fifo_wp = 0;
schnf30 0:352efe1d072f 415 }
schnf30 0:352efe1d072f 416
schnf30 0:352efe1d072f 417
schnf30 0:352efe1d072f 418 ft_void_t FT800::WrCmd32( ft_uint32_t cmd)
schnf30 0:352efe1d072f 419 {
schnf30 0:352efe1d072f 420 CheckCmdBuffer( sizeof(cmd));
schnf30 0:352efe1d072f 421
schnf30 0:352efe1d072f 422 Wr32( RAM_CMD + cmd_fifo_wp,cmd);
schnf30 0:352efe1d072f 423
schnf30 0:352efe1d072f 424 Updatecmdfifo( sizeof(cmd));
schnf30 0:352efe1d072f 425 }
schnf30 0:352efe1d072f 426
schnf30 0:352efe1d072f 427
schnf30 0:352efe1d072f 428 ft_void_t FT800::ResetDLBuffer( )
schnf30 0:352efe1d072f 429 {
schnf30 0:352efe1d072f 430 dl_buff_wp = 0;
schnf30 0:352efe1d072f 431 }
schnf30 0:352efe1d072f 432
schnf30 0:352efe1d072f 433 /* Toggle PD_N pin of FT800 board for a power cycle*/
schnf30 0:352efe1d072f 434 ft_void_t FT800::Powercycle( ft_bool_t up)
schnf30 0:352efe1d072f 435 {
schnf30 0:352efe1d072f 436 if (up)
schnf30 0:352efe1d072f 437 {
schnf30 0:352efe1d072f 438 //Toggle PD_N from low to high for power up switch
schnf30 0:352efe1d072f 439 _pd = 0;
schnf30 0:352efe1d072f 440 Sleep(20);
schnf30 0:352efe1d072f 441
schnf30 0:352efe1d072f 442 _pd = 1;
schnf30 0:352efe1d072f 443 Sleep(20);
schnf30 0:352efe1d072f 444 }else
schnf30 0:352efe1d072f 445 {
schnf30 0:352efe1d072f 446 //Toggle PD_N from high to low for power down switch
schnf30 0:352efe1d072f 447 _pd = 1;
schnf30 0:352efe1d072f 448 Sleep(20);
schnf30 0:352efe1d072f 449
schnf30 0:352efe1d072f 450 _pd = 0;
schnf30 0:352efe1d072f 451 Sleep(20);
schnf30 0:352efe1d072f 452 }
schnf30 0:352efe1d072f 453 }
schnf30 0:352efe1d072f 454
schnf30 0:352efe1d072f 455 ft_void_t FT800::WrMemFromFlash( ft_uint32_t addr,const ft_prog_uchar8_t *buffer, ft_uint32_t length)
schnf30 0:352efe1d072f 456 {
schnf30 0:352efe1d072f 457 //ft_uint32_t SizeTransfered = 0;
schnf30 0:352efe1d072f 458
schnf30 0:352efe1d072f 459 StartTransfer( FT_GPU_WRITE,addr);
schnf30 0:352efe1d072f 460
schnf30 0:352efe1d072f 461 while (length--) {
schnf30 0:352efe1d072f 462 Transfer8( ft_pgm_read_byte_near(buffer));
schnf30 0:352efe1d072f 463 buffer++;
schnf30 0:352efe1d072f 464 }
schnf30 0:352efe1d072f 465
schnf30 0:352efe1d072f 466 EndTransfer( );
schnf30 0:352efe1d072f 467 }
schnf30 0:352efe1d072f 468
schnf30 0:352efe1d072f 469 ft_void_t FT800::WrMem( ft_uint32_t addr,const ft_uint8_t *buffer, ft_uint32_t length)
schnf30 0:352efe1d072f 470 {
schnf30 0:352efe1d072f 471 //ft_uint32_t SizeTransfered = 0;
schnf30 0:352efe1d072f 472
schnf30 0:352efe1d072f 473 StartTransfer( FT_GPU_WRITE,addr);
schnf30 0:352efe1d072f 474
schnf30 0:352efe1d072f 475 while (length--) {
schnf30 0:352efe1d072f 476 Transfer8( *buffer);
schnf30 0:352efe1d072f 477 buffer++;
schnf30 0:352efe1d072f 478 }
schnf30 0:352efe1d072f 479
schnf30 0:352efe1d072f 480 EndTransfer( );
schnf30 0:352efe1d072f 481 }
schnf30 0:352efe1d072f 482
schnf30 0:352efe1d072f 483
schnf30 0:352efe1d072f 484 ft_void_t FT800::RdMem( ft_uint32_t addr, ft_uint8_t *buffer, ft_uint32_t length)
schnf30 0:352efe1d072f 485 {
schnf30 0:352efe1d072f 486 //ft_uint32_t SizeTransfered = 0;
schnf30 0:352efe1d072f 487
schnf30 0:352efe1d072f 488 StartTransfer( FT_GPU_READ,addr);
schnf30 0:352efe1d072f 489
schnf30 0:352efe1d072f 490 while (length--) {
schnf30 0:352efe1d072f 491 *buffer = Transfer8( 0);
schnf30 0:352efe1d072f 492 buffer++;
schnf30 0:352efe1d072f 493 }
schnf30 0:352efe1d072f 494
schnf30 0:352efe1d072f 495 EndTransfer( );
schnf30 0:352efe1d072f 496 }
schnf30 0:352efe1d072f 497
schnf30 0:352efe1d072f 498 ft_int32_t FT800::Dec2Ascii(ft_char8_t *pSrc,ft_int32_t value)
schnf30 0:352efe1d072f 499 {
schnf30 0:352efe1d072f 500 ft_int16_t Length;
schnf30 0:352efe1d072f 501 ft_char8_t *pdst,charval;
schnf30 0:352efe1d072f 502 ft_int32_t CurrVal = value,tmpval,i;
schnf30 0:352efe1d072f 503 ft_char8_t tmparray[16],idx = 0;
schnf30 0:352efe1d072f 504
schnf30 0:352efe1d072f 505 Length = strlen(pSrc);
schnf30 0:352efe1d072f 506 pdst = pSrc + Length;
schnf30 0:352efe1d072f 507
schnf30 0:352efe1d072f 508 if(0 == value)
schnf30 0:352efe1d072f 509 {
schnf30 0:352efe1d072f 510 *pdst++ = '0';
schnf30 0:352efe1d072f 511 *pdst++ = '\0';
schnf30 0:352efe1d072f 512 return 0;
schnf30 0:352efe1d072f 513 }
schnf30 0:352efe1d072f 514
schnf30 0:352efe1d072f 515 if(CurrVal < 0)
schnf30 0:352efe1d072f 516 {
schnf30 0:352efe1d072f 517 *pdst++ = '-';
schnf30 0:352efe1d072f 518 CurrVal = - CurrVal;
schnf30 0:352efe1d072f 519 }
schnf30 0:352efe1d072f 520 /* insert the value */
schnf30 0:352efe1d072f 521 while(CurrVal > 0){
schnf30 0:352efe1d072f 522 tmpval = CurrVal;
schnf30 0:352efe1d072f 523 CurrVal /= 10;
schnf30 0:352efe1d072f 524 tmpval = tmpval - CurrVal*10;
schnf30 0:352efe1d072f 525 charval = '0' + tmpval;
schnf30 0:352efe1d072f 526 tmparray[idx++] = charval;
schnf30 0:352efe1d072f 527 }
schnf30 0:352efe1d072f 528
schnf30 0:352efe1d072f 529 for(i=0;i<idx;i++)
schnf30 0:352efe1d072f 530 {
schnf30 0:352efe1d072f 531 *pdst++ = tmparray[idx - i - 1];
schnf30 0:352efe1d072f 532 }
schnf30 0:352efe1d072f 533 *pdst++ = '\0';
schnf30 0:352efe1d072f 534
schnf30 0:352efe1d072f 535 return 0;
schnf30 0:352efe1d072f 536 }
schnf30 0:352efe1d072f 537
schnf30 0:352efe1d072f 538
schnf30 0:352efe1d072f 539 ft_void_t FT800::Sleep(ft_uint16_t ms)
schnf30 0:352efe1d072f 540 {
schnf30 0:352efe1d072f 541 wait_ms(ms);
schnf30 0:352efe1d072f 542 }
schnf30 0:352efe1d072f 543
schnf30 0:352efe1d072f 544 ft_void_t FT800::Sound_ON(){
schnf30 0:352efe1d072f 545 Wr8( REG_GPIO, 0x02 | Rd8( REG_GPIO));
schnf30 0:352efe1d072f 546 }
schnf30 0:352efe1d072f 547
schnf30 0:352efe1d072f 548 ft_void_t FT800::Sound_OFF(){
schnf30 0:352efe1d072f 549 Wr8( REG_GPIO, 0xFD & Rd8( REG_GPIO));
schnf30 0:352efe1d072f 550 }
schnf30 0:352efe1d072f 551