Robert Lopez
Aded CMSIS5 DSP and NN folder. Needs some work
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core_cm23.h
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00001 /**************************************************************************//** 00002 * @file core_cm23.h 00003 * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File 00004 * @version V5.0.4 00005 * @date 10. January 2018 00006 ******************************************************************************/ 00007 /* 00008 * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 00009 * 00010 * SPDX-License-Identifier: Apache-2.0 00011 * 00012 * Licensed under the Apache License, Version 2.0 (the License); you may 00013 * not use this file except in compliance with the License. 00014 * You may obtain a copy of the License at 00015 * 00016 * www.apache.org/licenses/LICENSE-2.0 00017 * 00018 * Unless required by applicable law or agreed to in writing, software 00019 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 00020 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 00021 * See the License for the specific language governing permissions and 00022 * limitations under the License. 00023 */ 00024 00025 #if defined ( __ICCARM__ ) 00026 #pragma system_include /* treat file as system include file for MISRA check */ 00027 #elif defined (__clang__) 00028 #pragma clang system_header /* treat file as system include file */ 00029 #endif 00030 00031 #ifndef __CORE_CM23_H_GENERIC 00032 #define __CORE_CM23_H_GENERIC 00033 00034 #include <stdint.h> 00035 00036 #ifdef __cplusplus 00037 extern "C" { 00038 #endif 00039 00040 /** 00041 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 00042 CMSIS violates the following MISRA-C:2004 rules: 00043 00044 \li Required Rule 8.5, object/function definition in header file.<br> 00045 Function definitions in header files are used to allow 'inlining'. 00046 00047 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 00048 Unions are used for effective representation of core registers. 00049 00050 \li Advisory Rule 19.7, Function-like macro defined.<br> 00051 Function-like macros are used to allow more efficient code. 00052 */ 00053 00054 00055 /******************************************************************************* 00056 * CMSIS definitions 00057 ******************************************************************************/ 00058 /** 00059 \ingroup Cortex_M23 00060 @{ 00061 */ 00062 00063 #include "cmsis_version.h" 00064 00065 /* CMSIS definitions */ 00066 #define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ 00067 #define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ 00068 #define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ 00069 __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ 00070 00071 #define __CORTEX_M (23U) /*!< Cortex-M Core */ 00072 00073 /** __FPU_USED indicates whether an FPU is used or not. 00074 This core does not support an FPU at all 00075 */ 00076 #define __FPU_USED 0U 00077 00078 #if defined ( __CC_ARM ) 00079 #if defined __TARGET_FPU_VFP 00080 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00081 #endif 00082 00083 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 00084 #if defined __ARM_PCS_VFP 00085 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00086 #endif 00087 00088 #elif defined ( __GNUC__ ) 00089 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 00090 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00091 #endif 00092 00093 #elif defined ( __ICCARM__ ) 00094 #if defined __ARMVFP__ 00095 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00096 #endif 00097 00098 #elif defined ( __TI_ARM__ ) 00099 #if defined __TI_VFP_SUPPORT__ 00100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00101 #endif 00102 00103 #elif defined ( __TASKING__ ) 00104 #if defined __FPU_VFP__ 00105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00106 #endif 00107 00108 #elif defined ( __CSMC__ ) 00109 #if ( __CSMC__ & 0x400U) 00110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00111 #endif 00112 00113 #endif 00114 00115 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ 00116 00117 00118 #ifdef __cplusplus 00119 } 00120 #endif 00121 00122 #endif /* __CORE_CM23_H_GENERIC */ 00123 00124 #ifndef __CMSIS_GENERIC 00125 00126 #ifndef __CORE_CM23_H_DEPENDANT 00127 #define __CORE_CM23_H_DEPENDANT 00128 00129 #ifdef __cplusplus 00130 extern "C" { 00131 #endif 00132 00133 /* check device defines and use defaults */ 00134 #if defined __CHECK_DEVICE_DEFINES 00135 #ifndef __CM23_REV 00136 #define __CM23_REV 0x0000U 00137 #warning "__CM23_REV not defined in device header file; using default!" 00138 #endif 00139 00140 #ifndef __FPU_PRESENT 00141 #define __FPU_PRESENT 0U 00142 #warning "__FPU_PRESENT not defined in device header file; using default!" 00143 #endif 00144 00145 #ifndef __MPU_PRESENT 00146 #define __MPU_PRESENT 0U 00147 #warning "__MPU_PRESENT not defined in device header file; using default!" 00148 #endif 00149 00150 #ifndef __SAUREGION_PRESENT 00151 #define __SAUREGION_PRESENT 0U 00152 #warning "__SAUREGION_PRESENT not defined in device header file; using default!" 00153 #endif 00154 00155 #ifndef __VTOR_PRESENT 00156 #define __VTOR_PRESENT 0U 00157 #warning "__VTOR_PRESENT not defined in device header file; using default!" 00158 #endif 00159 00160 #ifndef __NVIC_PRIO_BITS 00161 #define __NVIC_PRIO_BITS 2U 00162 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 00163 #endif 00164 00165 #ifndef __Vendor_SysTickConfig 00166 #define __Vendor_SysTickConfig 0U 00167 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 00168 #endif 00169 00170 #ifndef __ETM_PRESENT 00171 #define __ETM_PRESENT 0U 00172 #warning "__ETM_PRESENT not defined in device header file; using default!" 00173 #endif 00174 00175 #ifndef __MTB_PRESENT 00176 #define __MTB_PRESENT 0U 00177 #warning "__MTB_PRESENT not defined in device header file; using default!" 00178 #endif 00179 00180 #endif 00181 00182 /* IO definitions (access restrictions to peripheral registers) */ 00183 /** 00184 \defgroup CMSIS_glob_defs CMSIS Global Defines 00185 00186 <strong>IO Type Qualifiers</strong> are used 00187 \li to specify the access to peripheral variables. 00188 \li for automatic generation of peripheral register debug information. 00189 */ 00190 #ifdef __cplusplus 00191 #define __I volatile /*!< Defines 'read only' permissions */ 00192 #else 00193 #define __I volatile const /*!< Defines 'read only' permissions */ 00194 #endif 00195 #define __O volatile /*!< Defines 'write only' permissions */ 00196 #define __IO volatile /*!< Defines 'read / write' permissions */ 00197 00198 /* following defines should be used for structure members */ 00199 #define __IM volatile const /*! Defines 'read only' structure member permissions */ 00200 #define __OM volatile /*! Defines 'write only' structure member permissions */ 00201 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ 00202 00203 /*@} end of group Cortex_M23 */ 00204 00205 00206 00207 /******************************************************************************* 00208 * Register Abstraction 00209 Core Register contain: 00210 - Core Register 00211 - Core NVIC Register 00212 - Core SCB Register 00213 - Core SysTick Register 00214 - Core Debug Register 00215 - Core MPU Register 00216 - Core SAU Register 00217 ******************************************************************************/ 00218 /** 00219 \defgroup CMSIS_core_register Defines and Type Definitions 00220 \brief Type definitions and defines for Cortex-M processor based devices. 00221 */ 00222 00223 /** 00224 \ingroup CMSIS_core_register 00225 \defgroup CMSIS_CORE Status and Control Registers 00226 \brief Core Register type definitions. 00227 @{ 00228 */ 00229 00230 /** 00231 \brief Union type to access the Application Program Status Register (APSR). 00232 */ 00233 typedef union 00234 { 00235 struct 00236 { 00237 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ 00238 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00239 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00240 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00241 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00242 } b; /*!< Structure used for bit access */ 00243 uint32_t w; /*!< Type used for word access */ 00244 } APSR_Type; 00245 00246 /* APSR Register Definitions */ 00247 #define APSR_N_Pos 31U /*!< APSR: N Position */ 00248 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ 00249 00250 #define APSR_Z_Pos 30U /*!< APSR: Z Position */ 00251 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ 00252 00253 #define APSR_C_Pos 29U /*!< APSR: C Position */ 00254 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ 00255 00256 #define APSR_V_Pos 28U /*!< APSR: V Position */ 00257 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ 00258 00259 00260 /** 00261 \brief Union type to access the Interrupt Program Status Register (IPSR). 00262 */ 00263 typedef union 00264 { 00265 struct 00266 { 00267 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00268 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 00269 } b; /*!< Structure used for bit access */ 00270 uint32_t w; /*!< Type used for word access */ 00271 } IPSR_Type; 00272 00273 /* IPSR Register Definitions */ 00274 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ 00275 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ 00276 00277 00278 /** 00279 \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 00280 */ 00281 typedef union 00282 { 00283 struct 00284 { 00285 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00286 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ 00287 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ 00288 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ 00289 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00290 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00291 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00292 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00293 } b; /*!< Structure used for bit access */ 00294 uint32_t w; /*!< Type used for word access */ 00295 } xPSR_Type; 00296 00297 /* xPSR Register Definitions */ 00298 #define xPSR_N_Pos 31U /*!< xPSR: N Position */ 00299 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ 00300 00301 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ 00302 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ 00303 00304 #define xPSR_C_Pos 29U /*!< xPSR: C Position */ 00305 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ 00306 00307 #define xPSR_V_Pos 28U /*!< xPSR: V Position */ 00308 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ 00309 00310 #define xPSR_T_Pos 24U /*!< xPSR: T Position */ 00311 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ 00312 00313 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ 00314 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ 00315 00316 00317 /** 00318 \brief Union type to access the Control Registers (CONTROL). 00319 */ 00320 typedef union 00321 { 00322 struct 00323 { 00324 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ 00325 uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ 00326 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ 00327 } b; /*!< Structure used for bit access */ 00328 uint32_t w; /*!< Type used for word access */ 00329 } CONTROL_Type; 00330 00331 /* CONTROL Register Definitions */ 00332 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ 00333 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ 00334 00335 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ 00336 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ 00337 00338 /*@} end of group CMSIS_CORE */ 00339 00340 00341 /** 00342 \ingroup CMSIS_core_register 00343 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 00344 \brief Type definitions for the NVIC Registers 00345 @{ 00346 */ 00347 00348 /** 00349 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 00350 */ 00351 typedef struct 00352 { 00353 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 00354 uint32_t RESERVED0[16U]; 00355 __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 00356 uint32_t RSERVED1[16U]; 00357 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 00358 uint32_t RESERVED2[16U]; 00359 __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 00360 uint32_t RESERVED3[16U]; 00361 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ 00362 uint32_t RESERVED4[16U]; 00363 __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ 00364 uint32_t RESERVED5[16U]; 00365 __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ 00366 } NVIC_Type; 00367 00368 /*@} end of group CMSIS_NVIC */ 00369 00370 00371 /** 00372 \ingroup CMSIS_core_register 00373 \defgroup CMSIS_SCB System Control Block (SCB) 00374 \brief Type definitions for the System Control Block Registers 00375 @{ 00376 */ 00377 00378 /** 00379 \brief Structure type to access the System Control Block (SCB). 00380 */ 00381 typedef struct 00382 { 00383 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 00384 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 00385 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 00386 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ 00387 #else 00388 uint32_t RESERVED0; 00389 #endif 00390 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 00391 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 00392 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 00393 uint32_t RESERVED1; 00394 __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ 00395 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 00396 } SCB_Type; 00397 00398 /* SCB CPUID Register Definitions */ 00399 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ 00400 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 00401 00402 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ 00403 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 00404 00405 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ 00406 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 00407 00408 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ 00409 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 00410 00411 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ 00412 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ 00413 00414 /* SCB Interrupt Control State Register Definitions */ 00415 #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ 00416 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ 00417 00418 #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ 00419 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ 00420 00421 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ 00422 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 00423 00424 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ 00425 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 00426 00427 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ 00428 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 00429 00430 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ 00431 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 00432 00433 #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ 00434 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ 00435 00436 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ 00437 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 00438 00439 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ 00440 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 00441 00442 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ 00443 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 00444 00445 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ 00446 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ 00447 00448 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ 00449 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ 00450 00451 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 00452 /* SCB Vector Table Offset Register Definitions */ 00453 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ 00454 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 00455 #endif 00456 00457 /* SCB Application Interrupt and Reset Control Register Definitions */ 00458 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ 00459 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 00460 00461 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ 00462 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 00463 00464 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ 00465 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 00466 00467 #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ 00468 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ 00469 00470 #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ 00471 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ 00472 00473 #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ 00474 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ 00475 00476 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ 00477 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 00478 00479 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ 00480 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 00481 00482 /* SCB System Control Register Definitions */ 00483 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ 00484 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 00485 00486 #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ 00487 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ 00488 00489 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ 00490 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 00491 00492 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ 00493 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 00494 00495 /* SCB Configuration Control Register Definitions */ 00496 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ 00497 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ 00498 00499 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ 00500 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ 00501 00502 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ 00503 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ 00504 00505 #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ 00506 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ 00507 00508 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ 00509 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ 00510 00511 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ 00512 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ 00513 00514 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ 00515 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 00516 00517 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ 00518 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ 00519 00520 /* SCB System Handler Control and State Register Definitions */ 00521 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ 00522 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ 00523 00524 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ 00525 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 00526 00527 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ 00528 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ 00529 00530 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ 00531 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ 00532 00533 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ 00534 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ 00535 00536 #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ 00537 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ 00538 00539 #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ 00540 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ 00541 00542 /*@} end of group CMSIS_SCB */ 00543 00544 00545 /** 00546 \ingroup CMSIS_core_register 00547 \defgroup CMSIS_SysTick System Tick Timer (SysTick) 00548 \brief Type definitions for the System Timer Registers. 00549 @{ 00550 */ 00551 00552 /** 00553 \brief Structure type to access the System Timer (SysTick). 00554 */ 00555 typedef struct 00556 { 00557 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 00558 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 00559 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 00560 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 00561 } SysTick_Type; 00562 00563 /* SysTick Control / Status Register Definitions */ 00564 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ 00565 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 00566 00567 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ 00568 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 00569 00570 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ 00571 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 00572 00573 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ 00574 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ 00575 00576 /* SysTick Reload Register Definitions */ 00577 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ 00578 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ 00579 00580 /* SysTick Current Register Definitions */ 00581 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ 00582 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ 00583 00584 /* SysTick Calibration Register Definitions */ 00585 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ 00586 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 00587 00588 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ 00589 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 00590 00591 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ 00592 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ 00593 00594 /*@} end of group CMSIS_SysTick */ 00595 00596 00597 /** 00598 \ingroup CMSIS_core_register 00599 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) 00600 \brief Type definitions for the Data Watchpoint and Trace (DWT) 00601 @{ 00602 */ 00603 00604 /** 00605 \brief Structure type to access the Data Watchpoint and Trace Register (DWT). 00606 */ 00607 typedef struct 00608 { 00609 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ 00610 uint32_t RESERVED0[6U]; 00611 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ 00612 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ 00613 uint32_t RESERVED1[1U]; 00614 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ 00615 uint32_t RESERVED2[1U]; 00616 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ 00617 uint32_t RESERVED3[1U]; 00618 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ 00619 uint32_t RESERVED4[1U]; 00620 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ 00621 uint32_t RESERVED5[1U]; 00622 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ 00623 uint32_t RESERVED6[1U]; 00624 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ 00625 uint32_t RESERVED7[1U]; 00626 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ 00627 uint32_t RESERVED8[1U]; 00628 __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ 00629 uint32_t RESERVED9[1U]; 00630 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ 00631 uint32_t RESERVED10[1U]; 00632 __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ 00633 uint32_t RESERVED11[1U]; 00634 __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ 00635 uint32_t RESERVED12[1U]; 00636 __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ 00637 uint32_t RESERVED13[1U]; 00638 __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ 00639 uint32_t RESERVED14[1U]; 00640 __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ 00641 uint32_t RESERVED15[1U]; 00642 __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ 00643 uint32_t RESERVED16[1U]; 00644 __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ 00645 uint32_t RESERVED17[1U]; 00646 __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ 00647 uint32_t RESERVED18[1U]; 00648 __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ 00649 uint32_t RESERVED19[1U]; 00650 __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ 00651 uint32_t RESERVED20[1U]; 00652 __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ 00653 uint32_t RESERVED21[1U]; 00654 __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ 00655 uint32_t RESERVED22[1U]; 00656 __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ 00657 uint32_t RESERVED23[1U]; 00658 __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ 00659 uint32_t RESERVED24[1U]; 00660 __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ 00661 uint32_t RESERVED25[1U]; 00662 __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ 00663 uint32_t RESERVED26[1U]; 00664 __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ 00665 uint32_t RESERVED27[1U]; 00666 __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ 00667 uint32_t RESERVED28[1U]; 00668 __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ 00669 uint32_t RESERVED29[1U]; 00670 __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ 00671 uint32_t RESERVED30[1U]; 00672 __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ 00673 uint32_t RESERVED31[1U]; 00674 __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ 00675 } DWT_Type; 00676 00677 /* DWT Control Register Definitions */ 00678 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ 00679 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ 00680 00681 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ 00682 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ 00683 00684 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ 00685 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ 00686 00687 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ 00688 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ 00689 00690 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ 00691 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ 00692 00693 /* DWT Comparator Function Register Definitions */ 00694 #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ 00695 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ 00696 00697 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ 00698 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ 00699 00700 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ 00701 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ 00702 00703 #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ 00704 #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ 00705 00706 #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ 00707 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ 00708 00709 /*@}*/ /* end of group CMSIS_DWT */ 00710 00711 00712 /** 00713 \ingroup CMSIS_core_register 00714 \defgroup CMSIS_TPI Trace Port Interface (TPI) 00715 \brief Type definitions for the Trace Port Interface (TPI) 00716 @{ 00717 */ 00718 00719 /** 00720 \brief Structure type to access the Trace Port Interface Register (TPI). 00721 */ 00722 typedef struct 00723 { 00724 __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ 00725 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ 00726 uint32_t RESERVED0[2U]; 00727 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ 00728 uint32_t RESERVED1[55U]; 00729 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ 00730 uint32_t RESERVED2[131U]; 00731 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ 00732 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ 00733 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ 00734 uint32_t RESERVED3[759U]; 00735 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ 00736 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ 00737 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ 00738 uint32_t RESERVED4[1U]; 00739 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ 00740 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ 00741 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ 00742 uint32_t RESERVED5[39U]; 00743 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ 00744 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ 00745 uint32_t RESERVED7[8U]; 00746 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ 00747 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ 00748 } TPI_Type; 00749 00750 /* TPI Asynchronous Clock Prescaler Register Definitions */ 00751 #define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ 00752 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ 00753 00754 #define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ 00755 #define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ 00756 00757 /* TPI Selected Pin Protocol Register Definitions */ 00758 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ 00759 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ 00760 00761 /* TPI Formatter and Flush Status Register Definitions */ 00762 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ 00763 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ 00764 00765 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ 00766 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ 00767 00768 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ 00769 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ 00770 00771 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ 00772 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ 00773 00774 /* TPI Formatter and Flush Control Register Definitions */ 00775 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ 00776 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ 00777 00778 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ 00779 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ 00780 00781 /* TPI TRIGGER Register Definitions */ 00782 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ 00783 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ 00784 00785 /* TPI Integration ETM Data Register Definitions (FIFO0) */ 00786 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ 00787 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ 00788 00789 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ 00790 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ 00791 00792 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ 00793 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ 00794 00795 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ 00796 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ 00797 00798 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ 00799 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ 00800 00801 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ 00802 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ 00803 00804 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ 00805 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ 00806 00807 /* TPI ITATBCTR2 Register Definitions */ 00808 #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ 00809 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ 00810 00811 /* TPI Integration ITM Data Register Definitions (FIFO1) */ 00812 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ 00813 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ 00814 00815 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ 00816 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ 00817 00818 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ 00819 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ 00820 00821 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ 00822 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ 00823 00824 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ 00825 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ 00826 00827 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ 00828 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ 00829 00830 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ 00831 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ 00832 00833 /* TPI ITATBCTR0 Register Definitions */ 00834 #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ 00835 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ 00836 00837 /* TPI Integration Mode Control Register Definitions */ 00838 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ 00839 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ 00840 00841 /* TPI DEVID Register Definitions */ 00842 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ 00843 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ 00844 00845 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ 00846 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ 00847 00848 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ 00849 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ 00850 00851 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ 00852 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ 00853 00854 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ 00855 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ 00856 00857 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ 00858 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ 00859 00860 /* TPI DEVTYPE Register Definitions */ 00861 #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ 00862 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ 00863 00864 #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ 00865 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ 00866 00867 /*@}*/ /* end of group CMSIS_TPI */ 00868 00869 00870 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 00871 /** 00872 \ingroup CMSIS_core_register 00873 \defgroup CMSIS_MPU Memory Protection Unit (MPU) 00874 \brief Type definitions for the Memory Protection Unit (MPU) 00875 @{ 00876 */ 00877 00878 /** 00879 \brief Structure type to access the Memory Protection Unit (MPU). 00880 */ 00881 typedef struct 00882 { 00883 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ 00884 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ 00885 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ 00886 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ 00887 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ 00888 uint32_t RESERVED0[7U]; 00889 union { 00890 __IOM uint32_t MAIR[2]; 00891 struct { 00892 __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ 00893 __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ 00894 }; 00895 }; 00896 } MPU_Type; 00897 00898 #define MPU_TYPE_RALIASES 1U 00899 00900 /* MPU Type Register Definitions */ 00901 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ 00902 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ 00903 00904 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ 00905 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ 00906 00907 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ 00908 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ 00909 00910 /* MPU Control Register Definitions */ 00911 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ 00912 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ 00913 00914 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ 00915 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ 00916 00917 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ 00918 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ 00919 00920 /* MPU Region Number Register Definitions */ 00921 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ 00922 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ 00923 00924 /* MPU Region Base Address Register Definitions */ 00925 #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ 00926 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ 00927 00928 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ 00929 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ 00930 00931 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ 00932 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ 00933 00934 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ 00935 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ 00936 00937 /* MPU Region Limit Address Register Definitions */ 00938 #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ 00939 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ 00940 00941 #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ 00942 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ 00943 00944 #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ 00945 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ 00946 00947 /* MPU Memory Attribute Indirection Register 0 Definitions */ 00948 #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ 00949 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ 00950 00951 #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ 00952 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ 00953 00954 #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ 00955 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ 00956 00957 #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ 00958 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ 00959 00960 /* MPU Memory Attribute Indirection Register 1 Definitions */ 00961 #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ 00962 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ 00963 00964 #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ 00965 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ 00966 00967 #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ 00968 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ 00969 00970 #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ 00971 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ 00972 00973 /*@} end of group CMSIS_MPU */ 00974 #endif 00975 00976 00977 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 00978 /** 00979 \ingroup CMSIS_core_register 00980 \defgroup CMSIS_SAU Security Attribution Unit (SAU) 00981 \brief Type definitions for the Security Attribution Unit (SAU) 00982 @{ 00983 */ 00984 00985 /** 00986 \brief Structure type to access the Security Attribution Unit (SAU). 00987 */ 00988 typedef struct 00989 { 00990 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ 00991 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ 00992 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) 00993 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ 00994 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ 00995 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ 00996 #endif 00997 } SAU_Type; 00998 00999 /* SAU Control Register Definitions */ 01000 #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ 01001 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ 01002 01003 #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ 01004 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ 01005 01006 /* SAU Type Register Definitions */ 01007 #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ 01008 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ 01009 01010 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) 01011 /* SAU Region Number Register Definitions */ 01012 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ 01013 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ 01014 01015 /* SAU Region Base Address Register Definitions */ 01016 #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ 01017 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ 01018 01019 /* SAU Region Limit Address Register Definitions */ 01020 #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ 01021 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ 01022 01023 #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ 01024 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ 01025 01026 #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ 01027 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ 01028 01029 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ 01030 01031 /*@} end of group CMSIS_SAU */ 01032 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 01033 01034 01035 /** 01036 \ingroup CMSIS_core_register 01037 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 01038 \brief Type definitions for the Core Debug Registers 01039 @{ 01040 */ 01041 01042 /** 01043 \brief Structure type to access the Core Debug Register (CoreDebug). 01044 */ 01045 typedef struct 01046 { 01047 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ 01048 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ 01049 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ 01050 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ 01051 uint32_t RESERVED4[1U]; 01052 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ 01053 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ 01054 } CoreDebug_Type; 01055 01056 /* Debug Halting Control and Status Register Definitions */ 01057 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ 01058 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ 01059 01060 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ 01061 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ 01062 01063 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ 01064 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ 01065 01066 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ 01067 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ 01068 01069 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ 01070 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ 01071 01072 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ 01073 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ 01074 01075 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ 01076 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ 01077 01078 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ 01079 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ 01080 01081 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ 01082 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ 01083 01084 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ 01085 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ 01086 01087 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ 01088 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ 01089 01090 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ 01091 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ 01092 01093 /* Debug Core Register Selector Register Definitions */ 01094 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ 01095 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ 01096 01097 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ 01098 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ 01099 01100 /* Debug Exception and Monitor Control Register */ 01101 #define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ 01102 #define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ 01103 01104 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ 01105 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ 01106 01107 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ 01108 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ 01109 01110 /* Debug Authentication Control Register Definitions */ 01111 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ 01112 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ 01113 01114 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ 01115 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ 01116 01117 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ 01118 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ 01119 01120 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ 01121 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ 01122 01123 /* Debug Security Control and Status Register Definitions */ 01124 #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ 01125 #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ 01126 01127 #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ 01128 #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ 01129 01130 #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ 01131 #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ 01132 01133 /*@} end of group CMSIS_CoreDebug */ 01134 01135 01136 /** 01137 \ingroup CMSIS_core_register 01138 \defgroup CMSIS_core_bitfield Core register bit field macros 01139 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). 01140 @{ 01141 */ 01142 01143 /** 01144 \brief Mask and shift a bit field value for use in a register bit range. 01145 \param[in] field Name of the register bit field. 01146 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. 01147 \return Masked and shifted value. 01148 */ 01149 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) 01150 01151 /** 01152 \brief Mask and shift a register value to extract a bit filed value. 01153 \param[in] field Name of the register bit field. 01154 \param[in] value Value of register. This parameter is interpreted as an uint32_t type. 01155 \return Masked and shifted bit field value. 01156 */ 01157 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) 01158 01159 /*@} end of group CMSIS_core_bitfield */ 01160 01161 01162 /** 01163 \ingroup CMSIS_core_register 01164 \defgroup CMSIS_core_base Core Definitions 01165 \brief Definitions for base addresses, unions, and structures. 01166 @{ 01167 */ 01168 01169 /* Memory mapping of Core Hardware */ 01170 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 01171 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ 01172 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ 01173 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ 01174 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 01175 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 01176 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 01177 01178 01179 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 01180 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 01181 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 01182 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ 01183 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ 01184 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ 01185 01186 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 01187 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ 01188 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ 01189 #endif 01190 01191 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 01192 #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ 01193 #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ 01194 #endif 01195 01196 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 01197 #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ 01198 #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ 01199 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ 01200 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ 01201 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ 01202 01203 #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ 01204 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ 01205 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ 01206 #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ 01207 01208 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 01209 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ 01210 #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ 01211 #endif 01212 01213 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 01214 /*@} */ 01215 01216 01217 01218 /******************************************************************************* 01219 * Hardware Abstraction Layer 01220 Core Function Interface contains: 01221 - Core NVIC Functions 01222 - Core SysTick Functions 01223 - Core Register Access Functions 01224 ******************************************************************************/ 01225 /** 01226 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 01227 */ 01228 01229 01230 01231 /* ########################## NVIC functions #################################### */ 01232 /** 01233 \ingroup CMSIS_Core_FunctionInterface 01234 \defgroup CMSIS_Core_NVICFunctions NVIC Functions 01235 \brief Functions that manage interrupts and exceptions via the NVIC. 01236 @{ 01237 */ 01238 01239 #ifdef CMSIS_NVIC_VIRTUAL 01240 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE 01241 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" 01242 #endif 01243 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE 01244 #else 01245 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ 01246 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ 01247 #define NVIC_EnableIRQ __NVIC_EnableIRQ 01248 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ 01249 #define NVIC_DisableIRQ __NVIC_DisableIRQ 01250 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ 01251 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ 01252 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ 01253 #define NVIC_GetActive __NVIC_GetActive 01254 #define NVIC_SetPriority __NVIC_SetPriority 01255 #define NVIC_GetPriority __NVIC_GetPriority 01256 #define NVIC_SystemReset __NVIC_SystemReset 01257 #endif /* CMSIS_NVIC_VIRTUAL */ 01258 01259 #ifdef CMSIS_VECTAB_VIRTUAL 01260 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE 01261 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" 01262 #endif 01263 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE 01264 #else 01265 #define NVIC_SetVector __NVIC_SetVector 01266 #define NVIC_GetVector __NVIC_GetVector 01267 #endif /* (CMSIS_VECTAB_VIRTUAL) */ 01268 01269 #define NVIC_USER_IRQ_OFFSET 16 01270 01271 01272 /* Interrupt Priorities are WORD accessible only under Armv6-M */ 01273 /* The following MACROS handle generation of the register offset and byte masks */ 01274 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) 01275 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) 01276 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) 01277 01278 01279 /** 01280 \brief Enable Interrupt 01281 \details Enables a device specific interrupt in the NVIC interrupt controller. 01282 \param [in] IRQn Device specific interrupt number. 01283 \note IRQn must not be negative. 01284 */ 01285 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) 01286 { 01287 if ((int32_t)(IRQn) >= 0) 01288 { 01289 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 01290 } 01291 } 01292 01293 01294 /** 01295 \brief Get Interrupt Enable status 01296 \details Returns a device specific interrupt enable status from the NVIC interrupt controller. 01297 \param [in] IRQn Device specific interrupt number. 01298 \return 0 Interrupt is not enabled. 01299 \return 1 Interrupt is enabled. 01300 \note IRQn must not be negative. 01301 */ 01302 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) 01303 { 01304 if ((int32_t)(IRQn) >= 0) 01305 { 01306 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01307 } 01308 else 01309 { 01310 return(0U); 01311 } 01312 } 01313 01314 01315 /** 01316 \brief Disable Interrupt 01317 \details Disables a device specific interrupt in the NVIC interrupt controller. 01318 \param [in] IRQn Device specific interrupt number. 01319 \note IRQn must not be negative. 01320 */ 01321 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) 01322 { 01323 if ((int32_t)(IRQn) >= 0) 01324 { 01325 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 01326 __DSB(); 01327 __ISB(); 01328 } 01329 } 01330 01331 01332 /** 01333 \brief Get Pending Interrupt 01334 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. 01335 \param [in] IRQn Device specific interrupt number. 01336 \return 0 Interrupt status is not pending. 01337 \return 1 Interrupt status is pending. 01338 \note IRQn must not be negative. 01339 */ 01340 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) 01341 { 01342 if ((int32_t)(IRQn) >= 0) 01343 { 01344 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01345 } 01346 else 01347 { 01348 return(0U); 01349 } 01350 } 01351 01352 01353 /** 01354 \brief Set Pending Interrupt 01355 \details Sets the pending bit of a device specific interrupt in the NVIC pending register. 01356 \param [in] IRQn Device specific interrupt number. 01357 \note IRQn must not be negative. 01358 */ 01359 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) 01360 { 01361 if ((int32_t)(IRQn) >= 0) 01362 { 01363 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 01364 } 01365 } 01366 01367 01368 /** 01369 \brief Clear Pending Interrupt 01370 \details Clears the pending bit of a device specific interrupt in the NVIC pending register. 01371 \param [in] IRQn Device specific interrupt number. 01372 \note IRQn must not be negative. 01373 */ 01374 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) 01375 { 01376 if ((int32_t)(IRQn) >= 0) 01377 { 01378 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 01379 } 01380 } 01381 01382 01383 /** 01384 \brief Get Active Interrupt 01385 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. 01386 \param [in] IRQn Device specific interrupt number. 01387 \return 0 Interrupt status is not active. 01388 \return 1 Interrupt status is active. 01389 \note IRQn must not be negative. 01390 */ 01391 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) 01392 { 01393 if ((int32_t)(IRQn) >= 0) 01394 { 01395 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01396 } 01397 else 01398 { 01399 return(0U); 01400 } 01401 } 01402 01403 01404 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 01405 /** 01406 \brief Get Interrupt Target State 01407 \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. 01408 \param [in] IRQn Device specific interrupt number. 01409 \return 0 if interrupt is assigned to Secure 01410 \return 1 if interrupt is assigned to Non Secure 01411 \note IRQn must not be negative. 01412 */ 01413 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) 01414 { 01415 if ((int32_t)(IRQn) >= 0) 01416 { 01417 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01418 } 01419 else 01420 { 01421 return(0U); 01422 } 01423 } 01424 01425 01426 /** 01427 \brief Set Interrupt Target State 01428 \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. 01429 \param [in] IRQn Device specific interrupt number. 01430 \return 0 if interrupt is assigned to Secure 01431 1 if interrupt is assigned to Non Secure 01432 \note IRQn must not be negative. 01433 */ 01434 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) 01435 { 01436 if ((int32_t)(IRQn) >= 0) 01437 { 01438 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); 01439 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01440 } 01441 else 01442 { 01443 return(0U); 01444 } 01445 } 01446 01447 01448 /** 01449 \brief Clear Interrupt Target State 01450 \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. 01451 \param [in] IRQn Device specific interrupt number. 01452 \return 0 if interrupt is assigned to Secure 01453 1 if interrupt is assigned to Non Secure 01454 \note IRQn must not be negative. 01455 */ 01456 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) 01457 { 01458 if ((int32_t)(IRQn) >= 0) 01459 { 01460 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); 01461 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01462 } 01463 else 01464 { 01465 return(0U); 01466 } 01467 } 01468 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 01469 01470 01471 /** 01472 \brief Set Interrupt Priority 01473 \details Sets the priority of a device specific interrupt or a processor exception. 01474 The interrupt number can be positive to specify a device specific interrupt, 01475 or negative to specify a processor exception. 01476 \param [in] IRQn Interrupt number. 01477 \param [in] priority Priority to set. 01478 \note The priority cannot be set for every processor exception. 01479 */ 01480 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 01481 { 01482 if ((int32_t)(IRQn) >= 0) 01483 { 01484 NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 01485 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 01486 } 01487 else 01488 { 01489 SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 01490 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 01491 } 01492 } 01493 01494 01495 /** 01496 \brief Get Interrupt Priority 01497 \details Reads the priority of a device specific interrupt or a processor exception. 01498 The interrupt number can be positive to specify a device specific interrupt, 01499 or negative to specify a processor exception. 01500 \param [in] IRQn Interrupt number. 01501 \return Interrupt Priority. 01502 Value is aligned automatically to the implemented priority bits of the microcontroller. 01503 */ 01504 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) 01505 { 01506 01507 if ((int32_t)(IRQn) >= 0) 01508 { 01509 return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); 01510 } 01511 else 01512 { 01513 return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); 01514 } 01515 } 01516 01517 01518 /** 01519 \brief Set Interrupt Vector 01520 \details Sets an interrupt vector in SRAM based interrupt vector table. 01521 The interrupt number can be positive to specify a device specific interrupt, 01522 or negative to specify a processor exception. 01523 VTOR must been relocated to SRAM before. 01524 If VTOR is not present address 0 must be mapped to SRAM. 01525 \param [in] IRQn Interrupt number 01526 \param [in] vector Address of interrupt handler function 01527 */ 01528 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) 01529 { 01530 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 01531 uint32_t *vectors = (uint32_t *)SCB->VTOR; 01532 #else 01533 uint32_t *vectors = (uint32_t *)0x0U; 01534 #endif 01535 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; 01536 } 01537 01538 01539 /** 01540 \brief Get Interrupt Vector 01541 \details Reads an interrupt vector from interrupt vector table. 01542 The interrupt number can be positive to specify a device specific interrupt, 01543 or negative to specify a processor exception. 01544 \param [in] IRQn Interrupt number. 01545 \return Address of interrupt handler function 01546 */ 01547 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) 01548 { 01549 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 01550 uint32_t *vectors = (uint32_t *)SCB->VTOR; 01551 #else 01552 uint32_t *vectors = (uint32_t *)0x0U; 01553 #endif 01554 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; 01555 } 01556 01557 01558 /** 01559 \brief System Reset 01560 \details Initiates a system reset request to reset the MCU. 01561 */ 01562 __STATIC_INLINE void __NVIC_SystemReset(void) 01563 { 01564 __DSB(); /* Ensure all outstanding memory accesses included 01565 buffered write are completed before reset */ 01566 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 01567 SCB_AIRCR_SYSRESETREQ_Msk); 01568 __DSB(); /* Ensure completion of memory access */ 01569 01570 for(;;) /* wait until reset */ 01571 { 01572 __NOP(); 01573 } 01574 } 01575 01576 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 01577 /** 01578 \brief Enable Interrupt (non-secure) 01579 \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. 01580 \param [in] IRQn Device specific interrupt number. 01581 \note IRQn must not be negative. 01582 */ 01583 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) 01584 { 01585 if ((int32_t)(IRQn) >= 0) 01586 { 01587 NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 01588 } 01589 } 01590 01591 01592 /** 01593 \brief Get Interrupt Enable status (non-secure) 01594 \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. 01595 \param [in] IRQn Device specific interrupt number. 01596 \return 0 Interrupt is not enabled. 01597 \return 1 Interrupt is enabled. 01598 \note IRQn must not be negative. 01599 */ 01600 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) 01601 { 01602 if ((int32_t)(IRQn) >= 0) 01603 { 01604 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01605 } 01606 else 01607 { 01608 return(0U); 01609 } 01610 } 01611 01612 01613 /** 01614 \brief Disable Interrupt (non-secure) 01615 \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. 01616 \param [in] IRQn Device specific interrupt number. 01617 \note IRQn must not be negative. 01618 */ 01619 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) 01620 { 01621 if ((int32_t)(IRQn) >= 0) 01622 { 01623 NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 01624 } 01625 } 01626 01627 01628 /** 01629 \brief Get Pending Interrupt (non-secure) 01630 \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. 01631 \param [in] IRQn Device specific interrupt number. 01632 \return 0 Interrupt status is not pending. 01633 \return 1 Interrupt status is pending. 01634 \note IRQn must not be negative. 01635 */ 01636 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) 01637 { 01638 if ((int32_t)(IRQn) >= 0) 01639 { 01640 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01641 } 01642 else 01643 { 01644 return(0U); 01645 } 01646 } 01647 01648 01649 /** 01650 \brief Set Pending Interrupt (non-secure) 01651 \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. 01652 \param [in] IRQn Device specific interrupt number. 01653 \note IRQn must not be negative. 01654 */ 01655 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) 01656 { 01657 if ((int32_t)(IRQn) >= 0) 01658 { 01659 NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 01660 } 01661 } 01662 01663 01664 /** 01665 \brief Clear Pending Interrupt (non-secure) 01666 \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. 01667 \param [in] IRQn Device specific interrupt number. 01668 \note IRQn must not be negative. 01669 */ 01670 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) 01671 { 01672 if ((int32_t)(IRQn) >= 0) 01673 { 01674 NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 01675 } 01676 } 01677 01678 01679 /** 01680 \brief Get Active Interrupt (non-secure) 01681 \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. 01682 \param [in] IRQn Device specific interrupt number. 01683 \return 0 Interrupt status is not active. 01684 \return 1 Interrupt status is active. 01685 \note IRQn must not be negative. 01686 */ 01687 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) 01688 { 01689 if ((int32_t)(IRQn) >= 0) 01690 { 01691 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01692 } 01693 else 01694 { 01695 return(0U); 01696 } 01697 } 01698 01699 01700 /** 01701 \brief Set Interrupt Priority (non-secure) 01702 \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. 01703 The interrupt number can be positive to specify a device specific interrupt, 01704 or negative to specify a processor exception. 01705 \param [in] IRQn Interrupt number. 01706 \param [in] priority Priority to set. 01707 \note The priority cannot be set for every non-secure processor exception. 01708 */ 01709 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) 01710 { 01711 if ((int32_t)(IRQn) >= 0) 01712 { 01713 NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 01714 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 01715 } 01716 else 01717 { 01718 SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 01719 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 01720 } 01721 } 01722 01723 01724 /** 01725 \brief Get Interrupt Priority (non-secure) 01726 \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. 01727 The interrupt number can be positive to specify a device specific interrupt, 01728 or negative to specify a processor exception. 01729 \param [in] IRQn Interrupt number. 01730 \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. 01731 */ 01732 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) 01733 { 01734 01735 if ((int32_t)(IRQn) >= 0) 01736 { 01737 return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); 01738 } 01739 else 01740 { 01741 return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); 01742 } 01743 } 01744 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ 01745 01746 /*@} end of CMSIS_Core_NVICFunctions */ 01747 01748 /* ########################## MPU functions #################################### */ 01749 01750 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 01751 01752 #include "mpu_armv8.h" 01753 01754 #endif 01755 01756 /* ########################## FPU functions #################################### */ 01757 /** 01758 \ingroup CMSIS_Core_FunctionInterface 01759 \defgroup CMSIS_Core_FpuFunctions FPU Functions 01760 \brief Function that provides FPU type. 01761 @{ 01762 */ 01763 01764 /** 01765 \brief get FPU type 01766 \details returns the FPU type 01767 \returns 01768 - \b 0: No FPU 01769 - \b 1: Single precision FPU 01770 - \b 2: Double + Single precision FPU 01771 */ 01772 __STATIC_INLINE uint32_t SCB_GetFPUType(void) 01773 { 01774 return 0U; /* No FPU */ 01775 } 01776 01777 01778 /*@} end of CMSIS_Core_FpuFunctions */ 01779 01780 01781 01782 /* ########################## SAU functions #################################### */ 01783 /** 01784 \ingroup CMSIS_Core_FunctionInterface 01785 \defgroup CMSIS_Core_SAUFunctions SAU Functions 01786 \brief Functions that configure the SAU. 01787 @{ 01788 */ 01789 01790 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 01791 01792 /** 01793 \brief Enable SAU 01794 \details Enables the Security Attribution Unit (SAU). 01795 */ 01796 __STATIC_INLINE void TZ_SAU_Enable(void) 01797 { 01798 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); 01799 } 01800 01801 01802 01803 /** 01804 \brief Disable SAU 01805 \details Disables the Security Attribution Unit (SAU). 01806 */ 01807 __STATIC_INLINE void TZ_SAU_Disable(void) 01808 { 01809 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); 01810 } 01811 01812 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 01813 01814 /*@} end of CMSIS_Core_SAUFunctions */ 01815 01816 01817 01818 01819 /* ################################## SysTick function ############################################ */ 01820 /** 01821 \ingroup CMSIS_Core_FunctionInterface 01822 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 01823 \brief Functions that configure the System. 01824 @{ 01825 */ 01826 01827 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) 01828 01829 /** 01830 \brief System Tick Configuration 01831 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. 01832 Counter is in free running mode to generate periodic interrupts. 01833 \param [in] ticks Number of ticks between two interrupts. 01834 \return 0 Function succeeded. 01835 \return 1 Function failed. 01836 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 01837 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 01838 must contain a vendor-specific implementation of this function. 01839 */ 01840 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 01841 { 01842 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 01843 { 01844 return (1UL); /* Reload value impossible */ 01845 } 01846 01847 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 01848 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 01849 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 01850 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 01851 SysTick_CTRL_TICKINT_Msk | 01852 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 01853 return (0UL); /* Function successful */ 01854 } 01855 01856 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 01857 /** 01858 \brief System Tick Configuration (non-secure) 01859 \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. 01860 Counter is in free running mode to generate periodic interrupts. 01861 \param [in] ticks Number of ticks between two interrupts. 01862 \return 0 Function succeeded. 01863 \return 1 Function failed. 01864 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 01865 function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b> 01866 must contain a vendor-specific implementation of this function. 01867 01868 */ 01869 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) 01870 { 01871 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 01872 { 01873 return (1UL); /* Reload value impossible */ 01874 } 01875 01876 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 01877 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 01878 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ 01879 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 01880 SysTick_CTRL_TICKINT_Msk | 01881 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 01882 return (0UL); /* Function successful */ 01883 } 01884 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 01885 01886 #endif 01887 01888 /*@} end of CMSIS_Core_SysTickFunctions */ 01889 01890 01891 01892 01893 #ifdef __cplusplus 01894 } 01895 #endif 01896 01897 #endif /* __CORE_CM23_H_DEPENDANT */ 01898 01899 #endif /* __CMSIS_GENERIC */ 01900
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