arm_convolve_HWC_q7_basic.c

00001 /*
00002  * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
00003  *
00004  * SPDX-License-Identifier: Apache-2.0
00005  *
00006  * Licensed under the Apache License, Version 2.0 (the License); you may
00007  * not use this file except in compliance with the License.
00008  * You may obtain a copy of the License at
00009  *
00010  * www.apache.org/licenses/LICENSE-2.0
00011  *
00012  * Unless required by applicable law or agreed to in writing, software
00013  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
00014  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00015  * See the License for the specific language governing permissions and
00016  * limitations under the License.
00017  */
00018 
00019 /* ----------------------------------------------------------------------
00020  * Project:      CMSIS NN Library
00021  * Title:        arm_convolve_HWC_q7_basic.c
00022  * Description:  Q7 version of convolution
00023  *
00024  * $Date:        17. January 2018
00025  * $Revision:    V.1.0.0
00026  *
00027  * Target Processor:  Cortex-M cores
00028  *
00029  * -------------------------------------------------------------------- */
00030 #include "arm_math.h"
00031 #include "arm_nnfunctions.h"
00032 
00033 /**
00034  *  @ingroup groupNN
00035  */
00036 
00037 /**
00038  * @addtogroup NNConv
00039  * @{
00040  */
00041 
00042   /**
00043    * @brief Basic Q7 convolution function
00044    * @param[in]       Im_in       pointer to input tensor
00045    * @param[in]       dim_im_in   input tensor dimention
00046    * @param[in]       ch_im_in    number of input tensor channels
00047    * @param[in]       wt          pointer to kernel weights
00048    * @param[in]       ch_im_out   number of filters, i.e., output tensor channels
00049    * @param[in]       dim_kernel  filter kernel size
00050    * @param[in]       padding     padding sizes
00051    * @param[in]       stride      convolution stride
00052    * @param[in]       bias        pointer to bias
00053    * @param[in]       bias_shift  amount of left-shift for bias
00054    * @param[in]       out_shift   amount of right-shift for output
00055    * @param[in,out]   Im_out      pointer to output tensor
00056    * @param[in]       dim_im_out  output tensor dimension
00057    * @param[in,out]   bufferA     pointer to buffer space for input 
00058    * @param[in,out]   bufferB     pointer to buffer space for output
00059    * @return     The function returns <code>ARM_MATH_SUCCESS</code> 
00060    *
00061    * @details
00062    *
00063    * <b>Buffer size:</b>
00064    *
00065    * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel
00066    *
00067    * bufferB size: 0
00068    *
00069    * This basic version is designed to work for any input tensor and weight
00070    * dimension. 
00071    */
00072 
00073 arm_status
00074 arm_convolve_HWC_q7_basic(const q7_t * Im_in,
00075                           const uint16_t dim_im_in,
00076                           const uint16_t ch_im_in,
00077                           const q7_t * wt,
00078                           const uint16_t ch_im_out,
00079                           const uint16_t dim_kernel,
00080                           const uint16_t padding,
00081                           const uint16_t stride,
00082                           const q7_t * bias,
00083                           const uint16_t bias_shift,
00084                           const uint16_t out_shift,
00085                           q7_t * Im_out, 
00086                           const uint16_t dim_im_out, 
00087                           q15_t * bufferA, 
00088                           q7_t * bufferB)
00089 {
00090 
00091 #if defined (ARM_MATH_DSP)
00092     /* Run the following code for Cortex-M4 and Cortex-M7 */
00093 
00094     int16_t   i_out_y, i_out_x, i_ker_y, i_ker_x;
00095 
00096     /* 
00097      *  Here we use bufferA as q15_t internally as computation are done with q15_t level
00098      *  im2col are done to output in q15_t format from q7_t input
00099      */
00100     q15_t    *pBuffer = bufferA;
00101     q7_t     *pOut = Im_out;
00102 
00103     /* This part implements the im2col function */
00104     for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++)
00105     {
00106         for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++)
00107         {
00108             for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++)
00109             {
00110                 for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++)
00111                 {
00112                     if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in)
00113                     {
00114                         /* Filling 0 for out-of-bound paddings */
00115                         /* arm_fill_q15(0, pBuffer, ch_im_in); */
00116                         memset(pBuffer, 0, sizeof(q15_t)*ch_im_in);
00117                     } else
00118                     {
00119                         /* Copying the pixel data to column */
00120                         arm_q7_to_q15_no_shift((q7_t *)
00121                                                Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in);
00122                     }
00123                     pBuffer += ch_im_in;
00124                 }
00125             }
00126 
00127             /* Computation is filed for every 2 columns */
00128             if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel * dim_kernel)
00129             {
00130                 pOut =
00131                     arm_nn_mat_mult_kernel_q7_q15(wt, bufferA,
00132                                                   ch_im_out,
00133                                                   ch_im_in *
00134                                                   dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut);
00135 
00136                 /* counter reset */
00137                 pBuffer = bufferA;
00138             }
00139         }
00140     }
00141 
00142     /* left-over because odd number of output pixels */
00143     if (pBuffer != bufferA)
00144     {
00145         const q7_t *pA = wt;
00146         int       i;
00147 
00148         for (i = 0; i < ch_im_out; i++)
00149         {
00150             /* Load the accumulator with bias first */
00151             q31_t     sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift);
00152 
00153             /* Point to the beging of the im2col buffer */
00154             q15_t    *pB = bufferA;
00155 
00156             /* Each time it process 4 entries */
00157             uint16_t  colCnt = ch_im_in * dim_kernel * dim_kernel >> 2;
00158 
00159             while (colCnt)
00160             {
00161                 q31_t     inA1, inA2;
00162                 q31_t     inB1, inB2;
00163 
00164                 pA = (q7_t *) read_and_pad((void *)pA, &inA1, &inA2);
00165 
00166                 inB1 = *__SIMD32(pB)++;
00167                 sum = __SMLAD(inA1, inB1, sum);
00168                 inB2 = *__SIMD32(pB)++;
00169                 sum = __SMLAD(inA2, inB2, sum);
00170 
00171                 colCnt--;
00172             }
00173             colCnt = ch_im_in * dim_kernel * dim_kernel & 0x3;
00174             while (colCnt)
00175             {
00176                 q7_t      inA1 = *pA++;
00177                 q15_t     inB1 = *pB++;
00178                 sum += inA1 * inB1;
00179                 colCnt--;
00180             }
00181             *pOut++ = (q7_t) __SSAT((sum >> out_shift), 8);
00182         }
00183     }
00184 #else
00185     /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */
00186 
00187     uint16_t  i, j, k, l, m, n;
00188     int       conv_out;
00189     signed char in_row, in_col;
00190 
00191     for (i = 0; i < ch_im_out; i++)
00192     {
00193         for (j = 0; j < dim_im_out; j++)
00194         {
00195             for (k = 0; k < dim_im_out; k++)
00196             {
00197                 conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift);
00198                 for (m = 0; m < dim_kernel; m++)
00199                 {
00200                     for (n = 0; n < dim_kernel; n++)
00201                     {
00202                         // if-for implementation
00203                         in_row = stride * j + m - padding;
00204                         in_col = stride * k + n - padding;
00205                         if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in)
00206                         {
00207                             for (l = 0; l < ch_im_in; l++)
00208                             {
00209                                 conv_out +=
00210                                     Im_in[(in_row * dim_im_in + in_col) * ch_im_in +
00211                                           l] * wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel +
00212                                                                                             n) * ch_im_in + l];
00213                             }
00214                         }
00215                     }
00216                 }
00217                 Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q7_t) __SSAT((conv_out >> out_shift), 8);
00218             }
00219         }
00220     }
00221 
00222 #endif                          /* ARM_MATH_DSP */
00223 
00224     /* Return to application */
00225     return ARM_MATH_SUCCESS;
00226 }
00227 
00228 /**
00229  * @} end of NNConv group
00230  */
00231