QITH FLAGS
Dependencies: FreescaleIAP mbed-rtos mbed
Fork of TF_conops_BAE1_3 by
beacon.cpp
00001 //switch off the sync!!!!!!! 00002 //switch off the preamble!!!!!!! 00003 /*for crc in tx: 00004 regIrq2(0x28) : 00005 00006 regpacketconfig 1(0x37) : 00007 set crc detection/calc. on : | 0x10 00008 crcautoclearoff : | 0x08 00009 00010 for data whitening : regpacketconfig 1(0x37) :| 0x40 00011 for 00012 00013 00014 00015 */ 00016 // 6CC000 for 435 MHz 00017 //set all values as FF for checking on spectrum analyzer 00018 00019 #include "beacon.h" 00020 #include "EPS.h" 00021 #include "pin_config.h" 00022 Serial pc_bea(USBTX, USBRX); // tx, rx 00023 DigitalOut cs(PIN6); //slave select or chip select 00024 SPI spi(PIN16,PIN17,PIN15); 00025 //DigitalOut cs_bar(PTC11); //slave select or chip select 00026 //InterruptIn button(p9); 00027 //#define TIMES 16 00028 //Timer t; 00029 00030 /*void interrupt_func() 00031 { 00032 pc_bea.printf("INTERRUPT_FUNC TRIGGERED\n wait for 3 secs\n"); 00033 wait(3); 00034 00035 }*/ 00036 00037 /***********************************************global variable declaration***************************************************************/ 00038 extern uint32_t BAE_STATUS; 00039 extern uint32_t BAE_ENABLE; 00040 extern ShortBeacy Shortbeacon; 00041 00042 void writereg(uint8_t reg,uint8_t val) 00043 { 00044 cs = 0;__disable_irq();spi.write(reg | 0x80);spi.write(val);__enable_irq();cs = 1; 00045 } 00046 uint8_t readreg(uint8_t reg) 00047 { 00048 int val;cs = 0;__disable_irq();spi.write(reg & ~0x80);val = spi.write(0);__enable_irq();cs = 1;return val; 00049 } 00050 void clearTxBuf() 00051 { 00052 writereg(RF22_REG_08_OPERATING_MODE2,0x01); 00053 writereg(RF22_REG_08_OPERATING_MODE2,0x00); 00054 } 00055 void clearRxBuf() 00056 { 00057 writereg(RF22_REG_08_OPERATING_MODE2,0x02); 00058 writereg(RF22_REG_08_OPERATING_MODE2,0x00); 00059 } 00060 int setFrequency(float centre,float afcPullInRange) 00061 { 00062 //freq setting begins 00063 uint8_t fbsel = 0x40; 00064 uint8_t afclimiter; 00065 if (centre >= 480.0) { 00066 centre /= 2; 00067 fbsel |= 0x20; 00068 afclimiter = afcPullInRange * 1000000.0 / 1250.0; 00069 } else { 00070 if (afcPullInRange < 0.0 || afcPullInRange > 0.159375) 00071 return false; 00072 afclimiter = afcPullInRange * 1000000.0 / 625.0; 00073 } 00074 centre /= 10.0; 00075 float integerPart = floor(centre); 00076 float fractionalPart = centre - integerPart; 00077 00078 uint8_t fb = (uint8_t)integerPart - 24; // Range 0 to 23 00079 fbsel |= fb; 00080 uint16_t fc = fractionalPart * 64000; 00081 writereg(RF22_REG_73_FREQUENCY_OFFSET1, 0); // REVISIT 00082 writereg(RF22_REG_74_FREQUENCY_OFFSET2, 0); 00083 writereg(RF22_REG_75_FREQUENCY_BAND_SELECT, fbsel); 00084 writereg(RF22_REG_76_NOMINAL_CARRIER_FREQUENCY1, fc >> 8); 00085 writereg(RF22_REG_77_NOMINAL_CARRIER_FREQUENCY0, fc & 0xff); 00086 writereg(RF22_REG_2A_AFC_LIMITER, afclimiter); 00087 return 0; 00088 } 00089 00090 00091 00092 void FCTN_BEA_INIT() 00093 { 00094 BAE_STATUS |= 0x00000004; //set BEA_INIT_STATUS flag 00095 writereg(RF22_REG_07_OPERATING_MODE1,0x80); //sw_reset 00096 wait(1); //takes time to reset 00097 00098 clearTxBuf(); 00099 clearRxBuf(); 00100 //txfifoalmostempty 00101 writereg(RF22_REG_7D_TX_FIFO_CONTROL2,5); 00102 //rxfifoalmostfull 00103 writereg(RF22_REG_7E_RX_FIFO_CONTROL,20); 00104 //Packet-engine registers 00105 writereg(RF22_REG_30_DATA_ACCESS_CONTROL,0x8E); //RF22_REG_30_DATA_ACCESS_CONTROL, RF22_ENPACRX | RF22_ENPACTX | RF22_ENCRC | RF22_CRC_CRC_16_IBM 00106 //&0x77 = diasable packet rx-tx handling 00107 writereg(RF22_REG_32_HEADER_CONTROL1,0x88); //RF22_REG_32_HEADER_CONTROL1, RF22_BCEN_HEADER3 | RF22_HDCH_HEADER3 00108 writereg(RF22_REG_33_HEADER_CONTROL2,0x42); //RF22_REG_33_HEADER_CONTROL2, RF22_HDLEN_4 | RF22_SYNCLEN_2 00109 writereg(RF22_REG_34_PREAMBLE_LENGTH,8); //RF22_REG_34_PREAMBLE_LENGTH, nibbles); preamble length = 8; 00110 writereg(RF22_REG_36_SYNC_WORD3,0x2D); //syncword3=2D 00111 writereg(RF22_REG_37_SYNC_WORD2,0xD4); //syncword2=D4 00112 writereg(RF22_REG_3F_CHECK_HEADER3,0); //RF22_REG_3F_CHECK_HEADER3, RF22_DEFAULT_NODE_ADDRESS 00113 writereg(RF22_REG_3A_TRANSMIT_HEADER3,0xab); //header_to 00114 writereg(RF22_REG_3B_TRANSMIT_HEADER2,0xbc); //header_from 00115 writereg(RF22_REG_3C_TRANSMIT_HEADER1,0xcd); //header_ids 00116 writereg(RF22_REG_3D_TRANSMIT_HEADER0,0xde); //header_flags 00117 writereg(RF22_REG_3F_CHECK_HEADER3,0xab); 00118 writereg(RF22_REG_40_CHECK_HEADER2,0xbc); 00119 writereg(RF22_REG_41_CHECK_HEADER1,0xcd); 00120 writereg(RF22_REG_42_CHECK_HEADER0,0xde); 00121 00122 //RSSI threshold for clear channel indicator 00123 writereg(RF22_REG_27_RSSI_THRESHOLD,0xA5); //55 for -80dBm, 2D for -100dBm, 7D for -60dBm, A5 for -40dBm, CD for -20 dBm 00124 00125 writereg(RF22_REG_0B_GPIO_CONFIGURATION0,0x15); // TX state ?? 00126 writereg(RF22_REG_0C_GPIO_CONFIGURATION1,0x12); // RX state ?? 00127 00128 //interrupts 00129 // spiWrite(RF22_REG_05_INTERRUPT_ENABLE1, RF22_ENTXFFAEM |RF22_ENRXFFAFULL | RF22_ENPKSENT |RF22_ENPKVALID| RF22_ENCRCERROR); 00130 // spiWrite(RF22_REG_06_INTERRUPT_ENABLE2, RF22_ENPREAVAL); 00131 00132 setFrequency(435.0, 0.05); 00133 00134 //return !(statusRead() & RF22_FREQERR); 00135 if((readreg(RF22_REG_02_DEVICE_STATUS)& 0x08)!= 0x00) 00136 printf("frequency not set properly\n"); 00137 //frequency set 00138 00139 //setModemConfig(FSK_Rb2_4Fd36); FSK_Rb2_4Fd36, ///< FSK, No Manchester, Rb = 2.4kbs, Fd = 36kHz 00140 //setmodemregisters 00141 //0x1b, 0x03, 0x41, 0x60, 0x27, 0x52, 0x00, 0x07, 0x40, 0x0a, 0x1e, 0x80, 0x60, 0x13, 0xa9, 0x2c, 0x22, 0x3a = FSK_RB2_4FD36 00142 //0xc8, 0x03, 0x39, 0x20, 0x68, 0xdc, 0x00, 0x6b, 0x2a, 0x08, 0x2a, 0x80, 0x60, 0x13, 0xa9, 0x2c, 0x21, 0x08 = OOK,2.4, 335 00143 writereg(RF22_REG_1C_IF_FILTER_BANDWIDTH,0x2B); 00144 writereg(RF22_REG_1F_CLOCK_RECOVERY_GEARSHIFT_OVERRIDE,0x03); 00145 writereg(RF22_REG_20_CLOCK_RECOVERY_OVERSAMPLING_RATE,0x41); 00146 writereg(RF22_REG_21_CLOCK_RECOVERY_OFFSET2,0x60); 00147 writereg(RF22_REG_22_CLOCK_RECOVERY_OFFSET1,0x27); //updated 20 to 25 reg values from excel sheet for 1.2 Khz freq. deviation,fsk 00148 writereg(RF22_REG_23_CLOCK_RECOVERY_OFFSET0,0x52); 00149 writereg(RF22_REG_24_CLOCK_RECOVERY_TIMING_LOOP_GAIN1,0x00); 00150 writereg(RF22_REG_25_CLOCK_RECOVERY_TIMING_LOOP_GAIN0,0x51); 00151 /*writereg(RF22_REG_2C_OOK_COUNTER_VALUE_1,0x2a); 00152 writereg(RF22_REG_2D_OOK_COUNTER_VALUE_2,0x08);*/ //not required for fsk (OOK counter value) 00153 writereg(RF22_REG_2E_SLICER_PEAK_HOLD,0x1e); //?? 00154 writereg(RF22_REG_58,0x80); 00155 writereg(RF22_REG_69_AGC_OVERRIDE1,0x60); 00156 writereg(RF22_REG_6E_TX_DATA_RATE1,0x09); 00157 writereg(RF22_REG_6F_TX_DATA_RATE0,0xd5); 00158 writereg(RF22_REG_70_MODULATION_CONTROL1,0x2c); 00159 writereg(RF22_REG_71_MODULATION_CONTROL2,0x22);//ook = 0x21 //fsk = 0x22 00160 writereg(RF22_REG_72_FREQUENCY_DEVIATION,0x02); 00161 //set tx power 00162 writereg(RF22_REG_6D_TX_POWER,0x07); //20dbm 00163 writereg(RF22_REG_3E_PACKET_LENGTH,TX_DATA); //packet length 00164 BAE_STATUS &= 0xFFFFFFFB; //clear BEA_INIT_STATUS flag 00165 } 00166 00167 void FCTN_BEA_TX_MAIN() 00168 { 00169 //FCTN_BEA_INIT(); 00170 BAE_STATUS |= 0x00000008; //set BEA_TX_MAIN_STATUS flag 00171 printf("\nBeacon function entered\n"); 00172 wait(1); // wait for POR to complete //change the timing later 00173 cs=1; // chip must be deselected 00174 wait(1); //change the time later 00175 spi.format(8,0); 00176 spi.frequency(10000000); //10MHz SCLK 00177 if (readreg(RF22_REG_00_DEVICE_TYPE) == 0x08) printf("spi connection valid\n"); 00178 else printf("error in spi connection\n"); 00179 00180 00181 00182 //******** 00183 //button.rise(&interrupt_func); //interrupt enabled ( rising edge of pin 9) 00184 wait(0.02); // pl. update this value or even avoid it!!! 00185 //extract values from short_beacon[] 00186 uint8_t byte_counter = 0; 00187 /*struct Short_beacon{ 00188 uint8_t Voltage[1]; 00189 uint8_t AngularSpeed[2]; 00190 uint8_t SubsystemStatus[1]; 00191 uint8_t Temp[3]; 00192 uint8_t ErrorFlag[1]; 00193 }Shortbeacon = { {0x88}, {0x99, 0xAA} , {0xAA},{0xAA,0xDD,0xEE}, {0x00} }; 00194 */ 00195 //filling hk data 00196 uint8_t short_beacon[] = { 0xAB, 0x8A, 0xE2, 0xBB, 0xB8, 0xA2, 0x8E,Shortbeacon.Voltage[0],Shortbeacon.AngularSpeed[0], Shortbeacon.AngularSpeed[1],Shortbeacon.SubsystemStatus[0],Shortbeacon.Temp[0],Shortbeacon.Temp[1],Shortbeacon.Temp[2],Shortbeacon.ErrorFlag[0]}; 00197 00198 for(int i = 0; i < 15 ; i++) 00199 { 00200 printf("0x%X\n",(short_beacon[i])); 00201 } 00202 //tx settings begin 00203 //setModeIdle(); 00204 writereg(RF22_REG_07_OPERATING_MODE1,0x01); //ready mode 00205 //fillTxBuf(data, len); 00206 clearTxBuf(); 00207 00208 //Set to Tx mode 00209 writereg(RF22_REG_07_OPERATING_MODE1,0x09); 00210 00211 while(byte_counter!=15){ 00212 //Check for fifoThresh 00213 while((readreg(RF22_REG_03_INTERRUPT_STATUS1) & 0x20) != 0x20); 00214 //writing again 00215 cs = 0; 00216 spi.write(0xFF); 00217 for(int i=7; i>=0 ;i--) 00218 { 00219 //pc.printf("%d\n",byte_counter); 00220 if((short_beacon[byte_counter] & (uint8_t) pow(2.0,i))!=0) 00221 { 00222 spi.write(0xFF); 00223 spi.write(0xFF); 00224 } 00225 else 00226 { 00227 spi.write(0x00); 00228 spi.write(0x00); 00229 00230 } 00231 } 00232 cs = 1; 00233 byte_counter++; 00234 00235 } 00236 //rf22.waitPacketSent(); 00237 while((readreg(RF22_REG_03_INTERRUPT_STATUS1) & 0x04) != 0x04);//pc.printf(" chck pkt sent!\n"); 00238 printf("\nBeacon function exiting\n"); 00239 BAE_STATUS &= 0xFFFFFFF7; // clear BEA_TX_MAIN_STATUS flag 00240 }
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