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RF_defs.h
00001 /* 00002 * Open HR20 00003 * 00004 * target: ATmega169 @ 4 MHz in Honnywell Rondostat HR20E 00005 * 00006 * compiler: WinAVR-20071221 00007 * avr-libc 1.6.0 00008 * GCC 4.2.2 00009 * 00010 * copyright: 2008 Dario Carluccio (hr20-at-carluccio-dot-de) 00011 * 2008 Jiri Dobry (jdobry-at-centrum-dot-cz) 00012 * 2008 Mario Fischer (MarioFischer-at-gmx-dot-net) 00013 * 2007 Michael Smola (Michael-dot-Smola-at-gmx-dot-net) 00014 * 00015 * license: This program is free software; you can redistribute it and/or 00016 * modify it under the terms of the GNU Library General Public 00017 * License as published by the Free Software Foundation; either 00018 * version 2 of the License, or (at your option) any later version. 00019 * 00020 * This program is distributed in the hope that it will be useful, 00021 * but WITHOUT ANY WARRANTY; without even the implied warranty of 00022 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00023 * GNU General Public License for more details. 00024 * 00025 * You should have received a copy of the GNU General Public License 00026 * along with this program. If not, see http:*www.gnu.org/licenses 00027 */ 00028 00029 /* 00030 * \file rfm.h 00031 * \brief functions to control the RFM12 Radio Transceiver Module 00032 * \author Mario Fischer <MarioFischer-at-gmx-dot-net>; Michael Smola <Michael-dot-Smola-at-gmx-dot-net> 00033 * \date $Date: 2010/04/17 17:57:02 $ 00034 * $Rev: 260 $ 00035 */ 00036 00037 00038 //#pragma once // multi-iclude prevention. gcc knows this pragma 00039 #ifndef rfm_H 00040 #define rfm_H 00041 00042 00043 #define RFM_SPI_16(OUTVAL) rfm_spi16(OUTVAL) //<! a function that gets a uint16_t (clocked out value) and returns a uint16_t (clocked in value) 00044 00045 #define RFM_CLK_OUTPUT 0 00046 00047 /* 00048 #define RFM_TESTPIN_INIT 00049 #define RFM_TESTPIN_ON 00050 #define RFM_TESTPIN_OFF 00051 #define RFM_TESTPIN_TOG 00052 00053 #define RFM_CONFIG_DISABLE 0x00 //<! RFM_CONFIG_*** are combinable flags, what the RFM shold do 00054 #define RFM_CONFIG_BROADCASTSTATUS 0x01 //<! Flag that enables the HR20's status broadcast every minute 00055 00056 #define RFM_CONFIG_ENABLEALL 0xff 00057 */ 00058 00059 00060 /////////////////////////////////////////////////////////////////////////////// 00061 // 00062 // RFM status bits 00063 // 00064 /////////////////////////////////////////////////////////////////////////////// 00065 00066 // Interrupt bits, latched //////////////////////////////////////////////////// 00067 00068 #define RFM_STATUS_FFIT 0x8000 // RX FIFO reached the progr. number of bits 00069 // Cleared by any FIFO read method 00070 00071 #define RFM_STATUS_RGIT 0x8000 // TX register is ready to receive 00072 // Cleared by TX write 00073 00074 #define RFM_STATUS_POR 0x4000 // Power On reset 00075 // Cleared by read status 00076 00077 #define RFM_STATUS_RGUR 0x2000 // TX register underrun, register over write 00078 // Cleared by read status 00079 00080 #define RFM_STATUS_FFOV 0x2000 // RX FIFO overflow 00081 // Cleared by read status 00082 00083 #define RFM_STATUS_WKUP 0x1000 // Wake up timer overflow 00084 // Cleared by read status 00085 00086 #define RFM_STATUS_EXT 0x0800 // Interupt changed to low 00087 // Cleared by read status 00088 00089 #define RFM_STATUS_LBD 0x0400 // Low battery detect 00090 00091 // Status bits //////////////////////////////////////////////////////////////// 00092 00093 #define RFM_STATUS_FFEM 0x0200 // FIFO is empty 00094 #define RFM_STATUS_ATS 0x0100 // TX mode: Strong enough RF signal 00095 #define RFM_STATUS_RSSI 0x0100 // RX mode: signal strength above programmed limit 00096 #define RFM_STATUS_DQD 0x0080 // Data Quality detector output 00097 #define RFM_STATUS_CRL 0x0040 // Clock recovery lock 00098 #define RFM_STATUS_ATGL 0x0020 // Toggling in each AFC cycle 00099 00100 /////////////////////////////////////////////////////////////////////////////// 00101 // 00102 // 1. Configuration Setting Command 00103 // 00104 /////////////////////////////////////////////////////////////////////////////// 00105 00106 #define RFM_CONFIG 0x8000 00107 00108 #define RFM_CONFIG_EL 0x8080 // Enable TX Register 00109 #define RFM_CONFIG_EF 0x8040 // Enable RX FIFO buffer 00110 #define RFM_CONFIG_BAND_315 0x8000 // Frequency band 00111 #define RFM_CONFIG_BAND_433 0x8010 00112 #define RFM_CONFIG_BAND_868 0x8020 00113 #define RFM_CONFIG_BAND_915 0x8030 00114 #define RFM_CONFIG_X_8_5pf 0x8000 // Crystal Load Capacitor 00115 #define RFM_CONFIG_X_9_0pf 0x8001 00116 #define RFM_CONFIG_X_9_5pf 0x8002 00117 #define RFM_CONFIG_X_10_0pf 0x8003 00118 #define RFM_CONFIG_X_10_5pf 0x8004 00119 #define RFM_CONFIG_X_11_0pf 0x8005 00120 #define RFM_CONFIG_X_11_5pf 0x8006 00121 #define RFM_CONFIG_X_12_0pf 0x8007 00122 #define RFM_CONFIG_X_12_5pf 0x8008 00123 #define RFM_CONFIG_X_13_0pf 0x8009 00124 #define RFM_CONFIG_X_13_5pf 0x800A 00125 #define RFM_CONFIG_X_14_0pf 0x800B 00126 #define RFM_CONFIG_X_14_5pf 0x800C 00127 #define RFM_CONFIG_X_15_0pf 0x800D 00128 #define RFM_CONFIG_X_15_5pf 0x800E 00129 #define RFM_CONFIG_X_16_0pf 0x800F 00130 00131 /////////////////////////////////////////////////////////////////////////////// 00132 // 00133 // 2. Power Management Command 00134 // 00135 /////////////////////////////////////////////////////////////////////////////// 00136 00137 #define RFM_POWER_MANAGEMENT 0x8200 00138 00139 #define RFM_POWER_MANAGEMENT_ER 0x8280 // Enable receiver 00140 #define RFM_POWER_MANAGEMENT_EBB 0x8240 // Enable base band block 00141 #define RFM_POWER_MANAGEMENT_ET 0x8220 // Enable transmitter 00142 #define RFM_POWER_MANAGEMENT_ES 0x8210 // Enable synthesizer 00143 #define RFM_POWER_MANAGEMENT_EX 0x8208 // Enable crystal oscillator 00144 #define RFM_POWER_MANAGEMENT_EB 0x8204 // Enable low battery detector 00145 #define RFM_POWER_MANAGEMENT_EW 0x8202 // Enable wake-up timer 00146 #define RFM_POWER_MANAGEMENT_DC 0x8201 // Disable clock output of CLK pin 00147 00148 #ifndef RFM_CLK_OUTPUT 00149 #error RFM_CLK_OUTPUT must be defined to 0 or 1 00150 #endif 00151 #if RFM_CLK_OUTPUT 00152 #define RFM_TX_ON_PRE() RFM_SPI_16( \ 00153 RFM_POWER_MANAGEMENT_ES | \ 00154 RFM_POWER_MANAGEMENT_EX ) 00155 #define RFM_TX_ON() RFM_SPI_16( \ 00156 RFM_POWER_MANAGEMENT_ET | \ 00157 RFM_POWER_MANAGEMENT_ES | \ 00158 RFM_POWER_MANAGEMENT_EX ) 00159 #define RFM_RX_ON() RFM_SPI_16( \ 00160 RFM_POWER_MANAGEMENT_ER | \ 00161 RFM_POWER_MANAGEMENT_EBB | \ 00162 RFM_POWER_MANAGEMENT_ES | \ 00163 RFM_POWER_MANAGEMENT_EX ) 00164 #define RFM_OFF() RFM_SPI_16( \ 00165 RFM_POWER_MANAGEMENT_EX ) 00166 #else 00167 #define RFM_TX_ON_PRE() RFM_SPI_16( \ 00168 RFM_POWER_MANAGEMENT_DC | \ 00169 RFM_POWER_MANAGEMENT_ES | \ 00170 RFM_POWER_MANAGEMENT_EX ) 00171 #define RFM_TX_ON() RFM_SPI_16( \ 00172 RFM_POWER_MANAGEMENT_DC | \ 00173 RFM_POWER_MANAGEMENT_ET | \ 00174 RFM_POWER_MANAGEMENT_ES | \ 00175 RFM_POWER_MANAGEMENT_EX ) 00176 #define RFM_RX_ON() RFM_SPI_16( \ 00177 RFM_POWER_MANAGEMENT_DC | \ 00178 RFM_POWER_MANAGEMENT_ER | \ 00179 RFM_POWER_MANAGEMENT_EBB | \ 00180 RFM_POWER_MANAGEMENT_ES | \ 00181 RFM_POWER_MANAGEMENT_EX ) 00182 #define RFM_OFF() RFM_SPI_16(RFM_POWER_MANAGEMENT_DC) 00183 #endif 00184 /////////////////////////////////////////////////////////////////////////////// 00185 // 00186 // 3. Frequency Setting Command 00187 // 00188 /////////////////////////////////////////////////////////////////////////////// 00189 00190 #define RFM_FREQUENCY 0xA000 00191 00192 #define RFM_FREQ_315Band(v) (uint16_t)((v/10.0-31)*4000) 00193 #define RFM_FREQ_433Band(v) (uint16_t)((v/10.0-43)*4000) 00194 #define RFM_FREQ_868Band(v) (uint16_t)((v/20.0-43)*4000) 00195 #define RFM_FREQ_915Band(v) (uint16_t)((v/30.0-30)*4000) 00196 00197 /////////////////////////////////////////////////////////////////////////////// 00198 // 00199 // 4. Data Rate Command 00200 // 00201 ///////////////////////////////////////////////////////////////////////////////// 00202 00203 #define RFM_BAUD_RATE 9600 00204 00205 #define RFM_DATA_RATE 0xC600 00206 00207 #define RFM_DATA_RATE_CS 0xC680 00208 #define RFM_DATA_RATE_4800 0xC647 00209 #define RFM_DATA_RATE_9600 0xC623 00210 #define RFM_DATA_RATE_19200 0xC611 00211 #define RFM_DATA_RATE_38400 0xC608 00212 #define RFM_DATA_RATE_57600 0xC605 00213 00214 #define RFM_SET_DATARATE(baud) ( ((baud)<5400) ? (RFM_DATA_RATE_CS|((43104/(baud))-1)) : (RFM_DATA_RATE|((344828UL/(baud))-1)) ) 00215 00216 /////////////////////////////////////////////////////////////////////////////// 00217 // 00218 // 5. Receiver Control Command 00219 // 00220 /////////////////////////////////////////////////////////////////////////////// 00221 00222 #define RFM_RX_CONTROL 0x9000 00223 00224 #define RFM_RX_CONTROL_P20_INT 0x9000 // Pin20 = ExternalInt 00225 #define RFM_RX_CONTROL_P20_VDI 0x9400 // Pin20 = VDI out 00226 00227 #define RFM_RX_CONTROL_VDI_FAST 0x9000 // fast VDI Response time 00228 #define RFM_RX_CONTROL_VDI_MED 0x9100 // medium 00229 #define RFM_RX_CONTROL_VDI_SLOW 0x9200 // slow 00230 #define RFM_RX_CONTROL_VDI_ON 0x9300 // Always on 00231 00232 #define RFM_RX_CONTROL_BW_400 0x9020 // bandwidth 400kHz 00233 #define RFM_RX_CONTROL_BW_340 0x9040 // bandwidth 340kHz 00234 #define RFM_RX_CONTROL_BW_270 0x9060 // bandwidth 270kHz 00235 #define RFM_RX_CONTROL_BW_200 0x9080 // bandwidth 200kHz 00236 #define RFM_RX_CONTROL_BW_134 0x90A0 // bandwidth 134kHz 00237 #define RFM_RX_CONTROL_BW_67 0x90C0 // bandwidth 67kHz 00238 00239 #define RFM_RX_CONTROL_GAIN_0 0x9000 // LNA gain 0db 00240 #define RFM_RX_CONTROL_GAIN_6 0x9008 // LNA gain -6db 00241 #define RFM_RX_CONTROL_GAIN_14 0x9010 // LNA gain -14db 00242 #define RFM_RX_CONTROL_GAIN_20 0x9018 // LNA gain -20db 00243 00244 #define RFM_RX_CONTROL_RSSI_103 0x9000 // DRSSI threshold -103dbm 00245 #define RFM_RX_CONTROL_RSSI_97 0x9001 // DRSSI threshold -97dbm 00246 #define RFM_RX_CONTROL_RSSI_91 0x9002 // DRSSI threshold -91dbm 00247 #define RFM_RX_CONTROL_RSSI_85 0x9003 // DRSSI threshold -85dbm 00248 #define RFM_RX_CONTROL_RSSI_79 0x9004 // DRSSI threshold -79dbm 00249 #define RFM_RX_CONTROL_RSSI_73 0x9005 // DRSSI threshold -73dbm 00250 //#define RFM_RX_CONTROL_RSSI_67 0x9006 // DRSSI threshold -67dbm // RF12B reserved 00251 //#define RFM_RX_CONTROL_RSSI_61 0x9007 // DRSSI threshold -61dbm // RF12B reserved 00252 00253 #define RFM_RX_CONTROL_BW(baud) (((baud)<8000) ? \ 00254 RFM_RX_CONTROL_BW_67 : \ 00255 ( \ 00256 ((baud)<30000) ? \ 00257 RFM_RX_CONTROL_BW_134 : \ 00258 RFM_RX_CONTROL_BW_200 \ 00259 )) 00260 00261 /////////////////////////////////////////////////////////////////////////////// 00262 // 00263 // 6. Data Filter Command 00264 // 00265 /////////////////////////////////////////////////////////////////////////////// 00266 00267 #define RFM_DATA_FILTER 0xC228 00268 00269 #define RFM_DATA_FILTER_AL 0xC2A8 // clock recovery auto-lock 00270 #define RFM_DATA_FILTER_ML 0xC268 // clock recovery fast mode 00271 #define RFM_DATA_FILTER_DIG 0xC228 // data filter type digital 00272 #define RFM_DATA_FILTER_ANALOG 0xC238 // data filter type analog 00273 #define RFM_DATA_FILTER_DQD(level) (RFM_DATA_FILTER | (level & 0x7)) 00274 00275 /////////////////////////////////////////////////////////////////////////////// 00276 // 00277 // 7. FIFO and Reset Mode Command 00278 // 00279 /////////////////////////////////////////////////////////////////////////////// 00280 00281 #define RFM_FIFO 0xCA00 00282 00283 #define RFM_FIFO_AL 0xCA04 // FIFO Start condition sync-word/always 00284 #define RFM_FIFO_FF 0xCA02 // Enable FIFO fill 00285 #define RFM_FIFO_DR 0xCA01 // Disable hi sens reset mode 00286 #define RFM_FIFO_IT(level) (RFM_FIFO | (( (level) & 0xF)<<4)) 00287 00288 #define RFM_FIFO_OFF() RFM_SPI_16(RFM_FIFO_IT(8) | RFM_FIFO_DR) 00289 #define RFM_FIFO_ON() RFM_SPI_16(RFM_FIFO_IT(8) | RFM_FIFO_FF | RFM_FIFO_DR) 00290 00291 ///////////////////////////////////////////////////////////////////////////// 00292 // 00293 // 8. Receiver FIFO Read 00294 // 00295 ///////////////////////////////////////////////////////////////////////////// 00296 00297 #define RFM_READ_FIFO() (RFM_SPI_16(0xB000) & 0xFF) 00298 00299 ///////////////////////////////////////////////////////////////////////////// 00300 // 00301 // 9. AFC Command 00302 // 00303 ///////////////////////////////////////////////////////////////////////////// 00304 00305 #define RFM_AFC 0xC400 00306 00307 #define RFM_AFC_EN 0xC401 00308 #define RFM_AFC_OE 0xC402 00309 #define RFM_AFC_FI 0xC404 00310 #define RFM_AFC_ST 0xC408 00311 00312 // Limits the value of the frequency offset register to the next values: 00313 00314 #define RFM_AFC_RANGE_LIMIT_NO 0xC400 // 0: No restriction 00315 #define RFM_AFC_RANGE_LIMIT_15_16 0xC410 // 1: +15 fres to -16 fres 00316 #define RFM_AFC_RANGE_LIMIT_7_8 0xC420 // 2: +7 fres to -8 fres 00317 #define RFM_AFC_RANGE_LIMIT_3_4 0xC430 // 3: +3 fres to -4 fres 00318 00319 // fres=2.5 kHz in 315MHz and 433MHz Bands 00320 // fres=5.0 kHz in 868MHz Band 00321 // fres=7.5 kHz in 915MHz Band 00322 00323 #define RFM_AFC_AUTO_OFF 0xC400 // 0: Auto mode off (Strobe is controlled by microcontroller) 00324 #define RFM_AFC_AUTO_ONCE 0xC440 // 1: Runs only once after each power-up 00325 #define RFM_AFC_AUTO_VDI 0xC480 // 2: Keep the foffset only during receiving(VDI=high) 00326 #define RFM_AFC_AUTO_INDEPENDENT 0xC4C0 // 3: Keep the foffset value independently trom the state of the VDI signal 00327 00328 /////////////////////////////////////////////////////////////////////////////// 00329 // 00330 // 10. TX Configuration Control Command 00331 // 00332 /////////////////////////////////////////////////////////////////////////////// 00333 00334 #define RFM_TX_CONTROL 0x9800 00335 00336 #define RFM_TX_CONTROL_POW_0 0x9800 00337 #define RFM_TX_CONTROL_POW_3 0x9801 00338 #define RFM_TX_CONTROL_POW_6 0x9802 00339 #define RFM_TX_CONTROL_POW_9 0x9803 00340 #define RFM_TX_CONTROL_POW_12 0x9804 00341 #define RFM_TX_CONTROL_POW_15 0x9805 00342 #define RFM_TX_CONTROL_POW_18 0x9806 00343 #define RFM_TX_CONTROL_POW_21 0x9807 00344 #define RFM_TX_CONTROL_MOD_15 0x9800 00345 #define RFM_TX_CONTROL_MOD_30 0x9810 00346 #define RFM_TX_CONTROL_MOD_45 0x9820 00347 #define RFM_TX_CONTROL_MOD_60 0x9830 00348 #define RFM_TX_CONTROL_MOD_75 0x9840 00349 #define RFM_TX_CONTROL_MOD_90 0x9850 00350 #define RFM_TX_CONTROL_MOD_105 0x9860 00351 #define RFM_TX_CONTROL_MOD_120 0x9870 00352 #define RFM_TX_CONTROL_MOD_135 0x9880 00353 #define RFM_TX_CONTROL_MOD_150 0x9890 00354 #define RFM_TX_CONTROL_MOD_165 0x98A0 00355 #define RFM_TX_CONTROL_MOD_180 0x98B0 00356 #define RFM_TX_CONTROL_MOD_195 0x98C0 00357 #define RFM_TX_CONTROL_MOD_210 0x98D0 00358 #define RFM_TX_CONTROL_MOD_225 0x98E0 00359 #define RFM_TX_CONTROL_MOD_240 0x98F0 00360 #define RFM_TX_CONTROL_MP 0x9900 00361 00362 #define RFM_TX_CONTROL_MOD(baud) (((baud)<8000) ? \ 00363 RFM_TX_CONTROL_MOD_45 : \ 00364 ( \ 00365 ((baud)<20000) ? \ 00366 RFM_TX_CONTROL_MOD_60 : \ 00367 ( \ 00368 ((baud)<30000) ? \ 00369 RFM_TX_CONTROL_MOD_75 : \ 00370 ( \ 00371 ((baud)<40000) ? \ 00372 RFM_TX_CONTROL_MOD_90 : \ 00373 RFM_TX_CONTROL_MOD_120 \ 00374 ) \ 00375 ) \ 00376 )) 00377 00378 ///////////////////////////////////////////////////////////////////////////// 00379 // 00380 // 11. Transmitter Register Write Command 00381 // 00382 ///////////////////////////////////////////////////////////////////////////// 00383 00384 //#define RFM_WRITE(byte) RFM_SPI_16(0xB800 | ((byte) & 0xFF)) 00385 #define RFM_WRITE(byte) RFM_SPI_16(0xB800 | (byte) ) 00386 00387 /////////////////////////////////////////////////////////////////////////////// 00388 // 00389 // 12. Wake-up Timer Command 00390 // 00391 /////////////////////////////////////////////////////////////////////////////// 00392 00393 #define RFM_WAKEUP_TIMER 0xE000 00394 #define RFM_WAKEUP_SET(time) RFM_SPI_16(RFM_WAKEUP_TIMER | (time)) 00395 00396 #define RFM_WAKEUP_480s (RFM_WAKEUP_TIMER |(11 << 8)| 234) 00397 #define RFM_WAKEUP_240s (RFM_WAKEUP_TIMER |(10 << 8)| 234) 00398 #define RFM_WAKEUP_120s (RFM_WAKEUP_TIMER |(9 << 8)| 234) 00399 #define RFM_WAKEUP_119s (RFM_WAKEUP_TIMER |(9 << 8)| 232) 00400 00401 #define RFM_WAKEUP_60s (RFM_WAKEUP_TIMER |(8 << 8) | 235) 00402 #define RFM_WAKEUP_59s (RFM_WAKEUP_TIMER |(8 << 8) | 230) 00403 00404 #define RFM_WAKEUP_30s (RFM_WAKEUP_TIMER |(7 << 8) | 235) 00405 #define RFM_WAKEUP_29s (RFM_WAKEUP_TIMER |(7 << 8) | 227) 00406 00407 #define RFM_WAKEUP_8s (RFM_WAKEUP_TIMER |(5 << 8) | 250) 00408 #define RFM_WAKEUP_7s (RFM_WAKEUP_TIMER |(5 << 8) | 219) 00409 #define RFM_WAKEUP_6s (RFM_WAKEUP_TIMER |(6 << 8) | 94) 00410 #define RFM_WAKEUP_5s (RFM_WAKEUP_TIMER |(5 << 8) | 156) 00411 #define RFM_WAKEUP_4s (RFM_WAKEUP_TIMER |(5 << 8) | 125) 00412 #define RFM_WAKEUP_1s (RFM_WAKEUP_TIMER |(2 << 8) | 250) 00413 #define RFM_WAKEUP_900ms (RFM_WAKEUP_TIMER |(2 << 8) | 225) 00414 #define RFM_WAKEUP_800ms (RFM_WAKEUP_TIMER |(2 << 8) | 200) 00415 #define RFM_WAKEUP_700ms (RFM_WAKEUP_TIMER |(2 << 8) | 175) 00416 #define RFM_WAKEUP_600ms (RFM_WAKEUP_TIMER |(2 << 8) | 150) 00417 #define RFM_WAKEUP_500ms (RFM_WAKEUP_TIMER |(2 << 8) | 125) 00418 #define RFM_WAKEUP_400ms (RFM_WAKEUP_TIMER |(2 << 8) | 100) 00419 #define RFM_WAKEUP_300ms (RFM_WAKEUP_TIMER |(2 << 8) | 75) 00420 #define RFM_WAKEUP_200ms (RFM_WAKEUP_TIMER |(2 << 8) | 50) 00421 #define RFM_WAKEUP_100ms (RFM_WAKEUP_TIMER |(2 << 8) | 25) 00422 00423 /////////////////////////////////////////////////////////////////////////////// 00424 // 00425 // 13. Low Duty-Cycle Command 00426 // 00427 /////////////////////////////////////////////////////////////////////////////// 00428 00429 #define RFM_LOW_DUTY_CYCLE 0xC800 00430 00431 /////////////////////////////////////////////////////////////////////////////// 00432 // 00433 // 14. Low Battery Detector Command 00434 // 00435 /////////////////////////////////////////////////////////////////////////////// 00436 00437 #define RFM_LOW_BATT_DETECT 0xC000 00438 #define RFM_LOW_BATT_DETECT_D_1MHZ 0xC000 00439 #define RFM_LOW_BATT_DETECT_D_1_25MHZ 0xC020 00440 #define RFM_LOW_BATT_DETECT_D_1_66MHZ 0xC040 00441 #define RFM_LOW_BATT_DETECT_D_2MHZ 0xC060 00442 #define RFM_LOW_BATT_DETECT_D_2_5MHZ 0xC080 00443 #define RFM_LOW_BATT_DETECT_D_3_33MHZ 0xC0A0 00444 #define RFM_LOW_BATT_DETECT_D_5MHZ 0xC0C0 00445 #define RFM_LOW_BATT_DETECT_D_10MHZ 0xC0E0 00446 00447 /////////////////////////////////////////////////////////////////////////////// 00448 // 00449 // 15. Status Read Command 00450 // 00451 /////////////////////////////////////////////////////////////////////////////// 00452 00453 #define RFM_READ_STATUS() RFM_SPI_16(0x0000) 00454 #define RFM_READ_STATUS_FFIT() SPI_1 (0x00) 00455 #define RFM_READ_STATUS_RGIT RFM_READ_STATUS_FFIT 00456 00457 /////////////////////////////////////////////////////////////////////////////// 00458 00459 // RFM air protocol flags: 00460 00461 #define RFMPROTO_FLAGS_BITASK_PACKETTYPE 0b11000000 //!< the uppermost 2 bits of the flags field encode the packettype 00462 #define RFMPROTO_FLAGS_PACKETTYPE_BROADCAST 0b00000000 //!< broadcast packettype (message from hr20, protocol; step 1) 00463 #define RFMPROTO_FLAGS_PACKETTYPE_COMMAND 0b01000000 //!< command packettype (message to hr20, protocol; step 2) 00464 #define RFMPROTO_FLAGS_PACKETTYPE_REPLY 0b10000000 //!< reply packettype (message from hr20, protocol; step 3) 00465 #define RFMPROTO_FLAGS_PACKETTYPE_SPECIAL 0b11000000 //!< currently unused packettype 00466 00467 #define RFMPROTO_FLAGS_BITASK_DEVICETYPE 0b00011111 //!< the lowermost 5 bytes denote the device type. this way other sensors and actors may coexist 00468 #define RFMPROTO_FLAGS_DEVICETYPE_OPENHR20 0b00010100 //!< topen HR20 device type. 10100 is for decimal 20 00469 00470 #define RFMPROTO_IS_PACKETTYPE_BROADCAST(FLAGS) ( RFMPROTO_FLAGS_PACKETTYPE_BROADCAST == ((FLAGS) & RFMPROTO_FLAGS_BITASK_PACKETTYPE) ) 00471 #define RFMPROTO_IS_PACKETTYPE_COMMAND(FLAGS) ( RFMPROTO_FLAGS_PACKETTYPE_COMMAND == ((FLAGS) & RFMPROTO_FLAGS_BITASK_PACKETTYPE) ) 00472 #define RFMPROTO_IS_PACKETTYPE_REPLY(FLAGS) ( RFMPROTO_FLAGS_PACKETTYPE_REPLY == ((FLAGS) & RFMPROTO_FLAGS_BITASK_PACKETTYPE) ) 00473 #define RFMPROTO_IS_PACKETTYPE_SPECIAL(FLAGS) ( RFMPROTO_FLAGS_PACKETTYPE_SPECIAL == ((FLAGS) & RFMPROTO_FLAGS_BITASK_PACKETTYPE) ) 00474 #define RFMPROTO_IS_DEVICETYPE_OPENHR20(FLAGS) ( RFMPROTO_FLAGS_DEVICETYPE_OPENHR20 == ((FLAGS) & RFMPROTO_FLAGS_BITASK_DEVICETYPE) ) 00475 00476 /////////////////////////////////////////////////////////////////////////////// 00477 00478 #endif
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