RawNAND.cpp

00001 #include "RawNAND.h"
00002 
00003 // TODO: Replace wait_us(int) to wait_ns 
00004 
00005 RawNAND::RawNAND(PinName ceb, PinName cle,
00006                  PinName ale, PinName web,
00007                  PinName reb, PinName wpb,
00008                  PinName rbb, 
00009                  PinName io1, PinName io2,
00010                  PinName io3, PinName io4,
00011                  PinName io5, PinName io6,
00012                  PinName io7, PinName io8)
00013         : _ceb(ceb,1),_cle(cle,1),
00014           _ale(ale,1),_web(web,1),
00015           _reb(reb,1),_wpb(wpb,1),
00016           _rbb(rbb,PullNone),
00017           _io(io1,io2,io3,io4,io5,io6,io7,io8) {
00018           _io.mode(PullNone);
00019           _io.input();
00020               
00021 }
00022 void RawNAND::reset() {
00023     // wait ready
00024     while(_rbb==0){
00025         __NOP();    
00026     }
00027     // RESET COMMAND (0xff)
00028     _ceb = 0;
00029     _cle = 1;
00030     _ale = 0;
00031     _web = 0;
00032     _io=0xff;
00033     _io.output();
00034     // wait setup time : max(tCS,tCLS,tALS,tDS,tWP)
00035     wait_us(tCS_US);
00036     _web = 1;
00037     // wait hold time : max(tCLH,tALH,tDH,tWH,tWB,tCH)
00038     wait_us(tWB_US);
00039     // check tRBB;
00040     while (_rbb==0){
00041         __NOP();
00042     }
00043     _ceb = 1;
00044 }
00045 void RawNAND::idRead(uint8_t * readData) {
00046     // ID READ COMMAND (0x90)
00047     _ceb = 0;
00048     _cle = 1;
00049     _ale = 0;
00050     _web = 0;
00051     _io=0x90;
00052     _io.output();
00053     // wait setup time : max(tCS,tCLS,tALS,tDS,tWP)
00054     wait_us(tCS_US);
00055     _web = 1;
00056     // wait hold time : max(tCLH,tALH,tDH,tWH)
00057     wait_us(tWH_US);
00058     
00059     // IO READ ADDRESS  (0x00)
00060     _cle=0;
00061     _ale=1;
00062     _web=0;
00063     _io=0x00;
00064     // wait setup time : max(tCLS,tALS,tDS,tWP)
00065     wait_us(tCLS_US);
00066     _web=1;
00067     // wait hold time : max(tCLH,tALH,tDH,tWH)
00068     wait_us(tWH_US);
00069 
00070     // ALE low and IO input
00071     _ale=0;
00072     _io.input();
00073     // ALE low to tREB low : tAR
00074     wait_us(tAR_US);
00075 
00076     // IO READ read data
00077     for (int l=0;l<5;l++) {
00078         _reb = 0;
00079         // wait max(tREA,tRP)
00080         wait_us(tREA_US);
00081         *(readData+l)=_io;
00082         _reb = 1;
00083         // wait tREH
00084         wait_us(tREH_US);
00085     }
00086     // wait io hiz
00087     _ceb = 1;
00088     wait_us(tCHZ_US);
00089 }
00090 uint8_t RawNAND::statusRead() {
00091     uint8_t status;
00092     // wait ready
00093     while(_rbb==0){
00094         __NOP();    
00095     }
00096 
00097     // STATUS READ COMMAND (0x70)
00098     _ceb = 0;
00099     _cle = 1;
00100     _ale = 0;
00101     _web = 0;
00102     _io=0x70;
00103     _io.output();
00104     // wait setup time : max(tCS,tCLS,tALS,tDS,tWP)
00105     wait_us(tCS_US);
00106     _web = 1;
00107     // wait hold time : max(tCLH,tDH,tWH)
00108     wait_us(tWH_US);
00109     _cle = 0;
00110     _io.input();
00111     // wait max(tWHR-tWH,tCLR-tWH)
00112     wait_us(tWHR_US-tWH_US);
00113     _reb = 0;
00114     // wait max(tREA,tRP)
00115     wait_us(tREA_US);
00116     status = _io;
00117     _reb = 1;
00118     // wait tREH
00119     wait_us(tREH_US);
00120     _ceb = 1;
00121     wait_us(tCHZ_US);
00122     // wait io hiz
00123     return status;
00124 }
00125 
00126 void RawNAND::setWriteProtect(uint8_t writeProtect){
00127     _wpb = writeProtect;
00128     // wait tWW
00129     wait_us(tWW_US);
00130 }
00131 
00132 void RawNAND::pageRead(uint8_t * readData,uint16_t blockAddress,uint8_t pageAddress,uint16_t columnAddress,uint16_t beats){
00133     // wait ready
00134     while(_rbb==0){
00135         __NOP();    
00136     }
00137 
00138     // 1ST READ COMMAND (0x00)
00139     _ceb = 0;
00140     _cle = 1;
00141     _ale = 0;
00142     _web = 0;
00143     _io=0x00;
00144     _io.output();
00145     // wait setup time : max(tCS,tCLS,tALS,tDS,tWP)
00146     wait_us(tCS_US);
00147 
00148     _web = 1;
00149     // wait hold time : max(tCLH,tDH,tWH)
00150     wait_us(tWH_US);
00151 
00152     // 1st address column [7:0]
00153     _cle = 0;
00154     _ale = 1;
00155     _web = 0;
00156     _io  = columnAddress & 0xff;
00157     // wait setup time : max(tALS,tCLS,tDS,tWP)
00158     wait_us(tWP_US);
00159 
00160     _web = 1;
00161     // wait hold time : max(tCLH,tDH,tWH)
00162     wait_us(tWH_US);   
00163 
00164     // 2nd address column [11:8]
00165     _web = 0;
00166     _io  = (columnAddress>>8) & 0x0f;            
00167     // wait setup time : max(tALS,tCLS,tDS,tWP)
00168     wait_us(tWP_US);
00169 
00170     _web = 1;
00171     // wait hold time : max(tCLH,tDH,tWH)
00172     wait_us(tWH_US);
00173     
00174     // 3rd address  {blockAddress[1:0],pageAddress[5:0]}
00175     _web = 0;
00176     _io  = ((blockAddress<<6) | pageAddress) ;            
00177     // wait setup time : max(tALS,tDS,tWP)
00178     wait_us(tWP_US);
00179 
00180     _web = 1;
00181     // wait hold time : max(tALH,tDH,tWH)
00182     wait_us(tWH_US);
00183     
00184     // 4th address  blockAddress[9:2]
00185     _web = 0;
00186     _io  = (blockAddress>>2) ;   
00187     // wait setup time : max(tALS,tDS,tWP)
00188     wait_us(tWP_US);
00189 
00190     _web = 1;
00191     // wait hold time : max(tALH,tDH,tWH)
00192     wait_us(tWH_US);
00193 
00194     // 2ND READ COMMAND (0x30)
00195     _cle = 1;
00196     _ale = 0;
00197     _web = 0;
00198     _io  = 0x30;
00199     // wait setup time : max(tALS,tCLS,tDS,tWP)
00200     wait_us(tWP_US);
00201 
00202     _web = 1;
00203     // wait hold time : max(tALH,tDH,tWH,tWB)
00204     wait_us(tWB_US);
00205 
00206     _cle = 0;
00207     _io.input();
00208 
00209     // wait ready
00210     while(_rbb==0){
00211         __NOP();    
00212     }
00213 
00214     // wait tRR  ( RBB to REB Low )
00215     wait_us(tRR_US);
00216 
00217     // read sequence
00218     for (int b=0;b<beats;b++){
00219         _reb = 0;
00220         // wait max(tREA,tRP)
00221         wait_us(tREA_US);
00222          *(readData + b)= _io;
00223         _reb = 1;
00224         // wait tREH
00225         wait_us(tREH_US);
00226     }
00227 
00228     _ceb = 1;
00229     // wait io hiz
00230     wait_us(tCHZ_US);
00231 
00232 }
00233 
00234 
00235 uint8_t RawNAND::erase(uint16_t blockAddress){
00236     // wait ready
00237     while(_rbb==0){
00238         __NOP();    
00239     }
00240 
00241     // 1ST ERASE COMMAND (0x60)
00242     _ceb = 0;
00243     _cle = 1;
00244     _ale = 0;
00245     _web = 0;
00246     _io=0x60;
00247     _io.output();
00248     // wait setup time : max(tCS,tCLS,tALS,tDS,tWP)
00249     wait_us(tCS_US);
00250 
00251     _web = 1;
00252     // wait hold time : max(tCLH,tDH,tWH)
00253     wait_us(tWH_US);
00254 
00255 
00256     // 1st page address  {blockAddress[1:0],pageAddress[5:0]}
00257     _cle = 0;
00258     _ale = 1;
00259     _web = 0;
00260     _io  = (blockAddress<<6) ;            
00261     // wait setup time : max(tALS,tDS,tWP)
00262     wait_us(tWP_US);
00263 
00264     _web = 1;
00265     // wait hold time : max(tALH,tDH,tWH)
00266     wait_us(tWH_US);
00267     
00268     // 2nd page address  blockAddress[9:2]
00269     _web = 0;
00270     _io  = (blockAddress>>2) ;   
00271     // wait setup time : max(tALS,tDS,tWP)
00272     wait_us(tWP_US);
00273 
00274     _web = 1;
00275     // wait hold time : max(tALH,tDH,tWH)
00276     wait_us(tWH_US);
00277 
00278     // 2ND ERASE COMMAND (0xD0)
00279     _cle = 1;
00280     _ale = 0;
00281     _web = 0;
00282     _io  = 0xD0;
00283     // wait setup time : max(tALS,tCLS,tDS,tWP)
00284     wait_us(tWP_US);
00285 
00286     _web = 1;
00287     // wait hold time : max(tALH,tDH,tWH,tWB)
00288     wait_us(tWB_US);
00289 
00290     _cle = 0;
00291     _io.input();
00292 
00293     // wait ready
00294     while(_rbb==0){
00295         __NOP();    
00296     }
00297 
00298     return statusRead();
00299 }
00300 
00301 uint8_t RawNAND::pageProgram(const uint8_t * writeData,uint16_t blockAddress,uint8_t pageAddress,uint16_t columnAddress,uint16_t beats){
00302     // wait ready
00303     while(_rbb==0){
00304         __NOP();    
00305     }
00306 
00307     // 1ST PROGRAM COMMAND (0x80)
00308     _ceb = 0;
00309     _cle = 1;
00310     _ale = 0;
00311     _web = 0;
00312     _io  = 0x80;
00313     _io.output();
00314     // wait setup time : max(tCS,tCLS,tALS,tDS,tWP)
00315     wait_us(tCS_US);
00316 
00317     _web = 1;
00318     // wait hold time : max(tCLH,tDH,tWH)
00319     wait_us(tWH_US);
00320 
00321     // 1st address column [7:0]
00322     _cle = 0;
00323     _ale = 1;
00324     _web = 0;
00325     _io  = columnAddress & 0xff;
00326     // wait setup time : max(tALS,tCLS,tDS,tWP)
00327     wait_us(tWP_US);
00328 
00329     _web = 1;
00330     // wait hold time : max(tCLH,tDH,tWH)
00331     wait_us(tWH_US);   
00332 
00333     // 2nd address column [11:8]
00334     _web = 0;
00335     _io  = (columnAddress>>8) & 0x0f;            
00336     // wait setup time : max(tALS,tCLS,tDS,tWP)
00337     wait_us(tWP_US);
00338 
00339     _web = 1;
00340     // wait hold time : max(tCLH,tDH,tWH)
00341     wait_us(tWH_US);
00342     
00343     // 3rd address  {blockAddress[1:0],pageAddress[5:0]}
00344     _web = 0;
00345     _io  = ((blockAddress<<6) | pageAddress) ;            
00346     // wait setup time : max(tALS,tDS,tWP)
00347     wait_us(tWP_US);
00348 
00349     _web = 1;
00350     // wait hold time : max(tALH,tDH,tWH)
00351     wait_us(tWH_US);
00352     
00353     // 4th address  blockAddress[9:2]
00354     _web = 0;
00355     _io  = (blockAddress>>2) ;   
00356     // wait setup time : max(tALS,tDS,tWP)
00357     wait_us(tWP_US);
00358 
00359     _web = 1;
00360     // wait hold time : max(tALH,tDH,tWH)
00361     wait_us(tWH_US);
00362 
00363     // datain
00364     _ale = 0;
00365     for (int b=0;b<beats;b++) {
00366         _io = *(writeData+b);
00367         _web = 0;
00368         // setup
00369         // wait setup time : max(tALS,tCLS,tDS,tWP)
00370         wait_us(tWP_US);
00371         
00372         _web = 1;
00373         // hold
00374         // wait hold time : max(tALH,tDH,tWH)
00375         wait_us(tWH_US);        
00376     }
00377 
00378     // 2ND PROGRAM COMMAND (0x10)
00379     _cle = 1;
00380     _ale = 0;
00381     _io  = 0x10;
00382     _web = 0;
00383     // wait setup time : max(tALS,tCLS,tDS,tWP)
00384     wait_us(tWP_US);
00385 
00386     _web = 1;
00387     // wait hold time : max(tCLH,tDH,tWH,tWB)
00388     wait_us(tWB_US);
00389     
00390     _cle = 0;
00391     _io.input();
00392     
00393     // wait ready
00394     while(_rbb==0){
00395         __NOP();    
00396     }
00397     
00398     return statusRead();
00399 }