500KB USB mass storage
Dependencies: mbed EEPROM USBDevice
RawNAND.cpp
00001 #include "RawNAND.h" 00002 00003 // CEB 00004 // CLE 00005 // ALE 00006 // WEB 00007 // REB 00008 // RBB 00009 // WPB 00010 // IO1 00011 // IO2 00012 // IO3 00013 // IO4 00014 // IO5 00015 // IO6 00016 // IO7 00017 // IO8 00018 00019 00020 RawNAND::RawNAND(PinName ceb, PinName cle, 00021 PinName ale, PinName web, 00022 PinName reb, PinName wpb, 00023 PinName rbb, 00024 PinName io1, PinName io2, 00025 PinName io3, PinName io4, 00026 PinName io5, PinName io6, 00027 PinName io7, PinName io8) 00028 : _ceb(ceb,1),_cle(cle,1), 00029 _ale(ale,1),_web(web,1), 00030 _reb(reb,1),_wpb(wpb,1), 00031 _rbb(rbb,PullNone), 00032 _io(io1,io2,io3,io4,io5,io6,io7,io8) { 00033 _io.mode(PullNone); 00034 _io.input(); 00035 00036 } 00037 void RawNAND::reset() { 00038 // wait ready 00039 while(_rbb==0){ 00040 __NOP(); 00041 } 00042 // RESET COMMAND (0xff) 00043 _ceb = 0; 00044 _cle = 1; 00045 _ale = 0; 00046 _web = 0; 00047 _io=0xff; 00048 _io.output(); 00049 // wait setup time : max(tCS,tCLS,tALS,tDS,tWP) 00050 wait_us(tCS_US); 00051 _web = 1; 00052 // wait hold time : max(tCLH,tALH,tDH,tWH,tWB,tCH) 00053 wait_us(tWB_US); 00054 // check tRBB; 00055 while (_rbb==0){ 00056 __NOP(); 00057 } 00058 _ceb = 1; 00059 } 00060 void RawNAND::idRead(uint8_t * readData) { 00061 // ID READ COMMAND (0x90) 00062 _ceb = 0; 00063 _cle = 1; 00064 _ale = 0; 00065 _web = 0; 00066 _io=0x90; 00067 _io.output(); 00068 // wait setup time : max(tCS,tCLS,tALS,tDS,tWP) 00069 wait_us(tCS_US); 00070 _web = 1; 00071 // wait hold time : max(tCLH,tALH,tDH,tWH) 00072 wait_us(tWH_US); 00073 00074 // IO READ ADDRESS (0x00) 00075 _cle=0; 00076 _ale=1; 00077 _web=0; 00078 _io=0x00; 00079 // wait setup time : max(tCLS,tALS,tDS,tWP) 00080 wait_us(tCLS_US); 00081 _web=1; 00082 // wait hold time : max(tCLH,tALH,tDH,tWH) 00083 wait_us(tWH_US); 00084 00085 // ALE low and IO input 00086 _ale=0; 00087 _io.input(); 00088 // ALE low to tREB low : tAR 00089 wait_us(tAR_US); 00090 00091 // IO READ read data 00092 for (int l=0;l<5;l++) { 00093 _reb = 0; 00094 // wait max(tREA,tRP) 00095 wait_us(tREA_US); 00096 *(readData+l)=_io; 00097 _reb = 1; 00098 // wait tREH 00099 wait_us(tREH_US); 00100 } 00101 // wait io hiz 00102 _ceb = 1; 00103 wait_us(tCHZ_US); 00104 } 00105 uint8_t RawNAND::statusRead() { 00106 uint8_t status; 00107 // wait ready 00108 while(_rbb==0){ 00109 __NOP(); 00110 } 00111 00112 // STATUS READ COMMAND (0x70) 00113 _ceb = 0; 00114 _cle = 1; 00115 _ale = 0; 00116 _web = 0; 00117 _io=0x70; 00118 _io.output(); 00119 // wait setup time : max(tCS,tCLS,tALS,tDS,tWP) 00120 wait_us(tCS_US); 00121 _web = 1; 00122 // wait hold time : max(tCLH,tDH,tWH) 00123 wait_us(tWH_US); 00124 _cle = 0; 00125 _io.input(); 00126 // wait max(tWHR-tWH,tCLR-tWH) 00127 wait_us(tWHR_US-tWH_US); 00128 _reb = 0; 00129 // wait max(tREA,tRP) 00130 wait_us(tREA_US); 00131 status = _io; 00132 _reb = 1; 00133 // wait tREH 00134 wait_us(tREH_US); 00135 _ceb = 1; 00136 wait_us(tCHZ_US); 00137 // wait io hiz 00138 return status; 00139 } 00140 00141 void RawNAND::setWriteProtect(uint8_t writeProtect){ 00142 _wpb = writeProtect; 00143 // wait tWW 00144 wait_us(tWW_US); 00145 } 00146 00147 void RawNAND::pageRead(uint8_t * readData,uint16_t blockAddress,uint8_t pageAddress,uint16_t columnAddress,uint16_t beats){ 00148 // wait ready 00149 while(_rbb==0){ 00150 __NOP(); 00151 } 00152 00153 // 1ST READ COMMAND (0x00) 00154 _ceb = 0; 00155 _cle = 1; 00156 _ale = 0; 00157 _web = 0; 00158 _io=0x00; 00159 _io.output(); 00160 // wait setup time : max(tCS,tCLS,tALS,tDS,tWP) 00161 wait_us(tCS_US); 00162 00163 _web = 1; 00164 // wait hold time : max(tCLH,tDH,tWH) 00165 wait_us(tWH_US); 00166 00167 // 1st address column [7:0] 00168 _cle = 0; 00169 _ale = 1; 00170 _web = 0; 00171 _io = columnAddress & 0xff; 00172 // wait setup time : max(tALS,tCLS,tDS,tWP) 00173 wait_us(tWP_US); 00174 00175 _web = 1; 00176 // wait hold time : max(tCLH,tDH,tWH) 00177 wait_us(tWH_US); 00178 00179 // 2nd address column [11:8] 00180 _web = 0; 00181 _io = (columnAddress>>8) & 0x0f; 00182 // wait setup time : max(tALS,tCLS,tDS,tWP) 00183 wait_us(tWP_US); 00184 00185 _web = 1; 00186 // wait hold time : max(tCLH,tDH,tWH) 00187 wait_us(tWH_US); 00188 00189 // 3rd address {blockAddress[1:0],pageAddress[5:0]} 00190 _web = 0; 00191 _io = ((blockAddress<<6) | pageAddress) ; 00192 // wait setup time : max(tALS,tDS,tWP) 00193 wait_us(tWP_US); 00194 00195 _web = 1; 00196 // wait hold time : max(tALH,tDH,tWH) 00197 wait_us(tWH_US); 00198 00199 // 4th address blockAddress[9:2] 00200 _web = 0; 00201 _io = (blockAddress>>2) ; 00202 // wait setup time : max(tALS,tDS,tWP) 00203 wait_us(tWP_US); 00204 00205 _web = 1; 00206 // wait hold time : max(tALH,tDH,tWH) 00207 wait_us(tWH_US); 00208 00209 // 2ND READ COMMAND (0x30) 00210 _cle = 1; 00211 _ale = 0; 00212 _web = 0; 00213 _io = 0x30; 00214 // wait setup time : max(tALS,tCLS,tDS,tWP) 00215 wait_us(tWP_US); 00216 00217 _web = 1; 00218 // wait hold time : max(tALH,tDH,tWH,tWB) 00219 wait_us(tWB_US); 00220 00221 _cle = 0; 00222 _io.input(); 00223 00224 // wait ready 00225 while(_rbb==0){ 00226 __NOP(); 00227 } 00228 00229 // wait tRR ( RBB to REB Low ) 00230 wait_us(tRR_US); 00231 00232 // read sequence 00233 for (int b=0;b<beats;b++){ 00234 _reb = 0; 00235 // wait max(tREA,tRP) 00236 wait_us(tREA_US); 00237 *(readData + b)= _io; 00238 _reb = 1; 00239 // wait tREH 00240 wait_us(tREH_US); 00241 } 00242 00243 _ceb = 1; 00244 // wait io hiz 00245 wait_us(tCHZ_US); 00246 00247 } 00248 00249 00250 uint8_t RawNAND::erase(uint16_t blockAddress){ 00251 // wait ready 00252 while(_rbb==0){ 00253 __NOP(); 00254 } 00255 00256 // 1ST READ COMMAND (0x60) 00257 _ceb = 0; 00258 _cle = 1; 00259 _ale = 0; 00260 _web = 0; 00261 _io=0x60; 00262 _io.output(); 00263 // wait setup time : max(tCS,tCLS,tALS,tDS,tWP) 00264 wait_us(tCS_US); 00265 00266 _web = 1; 00267 // wait hold time : max(tCLH,tDH,tWH) 00268 wait_us(tWH_US); 00269 00270 00271 // 1st page address {blockAddress[1:0],pageAddress[5:0]} 00272 _cle = 0; 00273 _ale = 1; 00274 _web = 0; 00275 _io = (blockAddress<<6) ; 00276 // wait setup time : max(tALS,tDS,tWP) 00277 wait_us(tWP_US); 00278 00279 _web = 1; 00280 // wait hold time : max(tALH,tDH,tWH) 00281 wait_us(tWH_US); 00282 00283 // 2nd page address blockAddress[9:2] 00284 _web = 0; 00285 _io = (blockAddress>>2) ; 00286 // wait setup time : max(tALS,tDS,tWP) 00287 wait_us(tWP_US); 00288 00289 _web = 1; 00290 // wait hold time : max(tALH,tDH,tWH) 00291 wait_us(tWH_US); 00292 00293 // 2ND READ COMMAND (0xD0) 00294 _cle = 1; 00295 _ale = 0; 00296 _web = 0; 00297 _io = 0xD0; 00298 // wait setup time : max(tALS,tCLS,tDS,tWP) 00299 wait_us(tWP_US); 00300 00301 _web = 1; 00302 // wait hold time : max(tALH,tDH,tWH,tWB) 00303 wait_us(tWB_US); 00304 00305 _cle = 0; 00306 _io.input(); 00307 00308 // wait ready 00309 while(_rbb==0){ 00310 __NOP(); 00311 } 00312 00313 return statusRead(); 00314 } 00315 00316 uint8_t RawNAND::pageProgram(const uint8_t * writeData,uint16_t blockAddress,uint8_t pageAddress,uint16_t columnAddress,uint16_t beats){ 00317 // wait ready 00318 while(_rbb==0){ 00319 __NOP(); 00320 } 00321 00322 // 1ST PROGRAM COMMAND (0x80) 00323 _ceb = 0; 00324 _cle = 1; 00325 _ale = 0; 00326 _web = 0; 00327 _io = 0x80; 00328 _io.output(); 00329 // wait setup time : max(tCS,tCLS,tALS,tDS,tWP) 00330 wait_us(tCS_US); 00331 00332 _web = 1; 00333 // wait hold time : max(tCLH,tDH,tWH) 00334 wait_us(tWH_US); 00335 00336 // 1st address column [7:0] 00337 _cle = 0; 00338 _ale = 1; 00339 _web = 0; 00340 _io = columnAddress & 0xff; 00341 // wait setup time : max(tALS,tCLS,tDS,tWP) 00342 wait_us(tWP_US); 00343 00344 _web = 1; 00345 // wait hold time : max(tCLH,tDH,tWH) 00346 wait_us(tWH_US); 00347 00348 // 2nd address column [11:8] 00349 _web = 0; 00350 _io = (columnAddress>>8) & 0x0f; 00351 // wait setup time : max(tALS,tCLS,tDS,tWP) 00352 wait_us(tWP_US); 00353 00354 _web = 1; 00355 // wait hold time : max(tCLH,tDH,tWH) 00356 wait_us(tWH_US); 00357 00358 // 3rd address {blockAddress[1:0],pageAddress[5:0]} 00359 _web = 0; 00360 _io = ((blockAddress<<6) | pageAddress) ; 00361 // wait setup time : max(tALS,tDS,tWP) 00362 wait_us(tWP_US); 00363 00364 _web = 1; 00365 // wait hold time : max(tALH,tDH,tWH) 00366 wait_us(tWH_US); 00367 00368 // 4th address blockAddress[9:2] 00369 _web = 0; 00370 _io = (blockAddress>>2) ; 00371 // wait setup time : max(tALS,tDS,tWP) 00372 wait_us(tWP_US); 00373 00374 _web = 1; 00375 // wait hold time : max(tALH,tDH,tWH) 00376 wait_us(tWH_US); 00377 00378 // datain 00379 _ale = 0; 00380 for (int b=0;b<beats;b++) { 00381 _io = *(writeData+b); 00382 _web = 0; 00383 // setup 00384 // wait setup time : max(tALS,tCLS,tDS,tWP) 00385 wait_us(tWP_US); 00386 00387 _web = 1; 00388 // hold 00389 // wait hold time : max(tALH,tDH,tWH) 00390 wait_us(tWH_US); 00391 } 00392 00393 // 2ND PROGRAM COMMAND (0x10) 00394 _cle = 1; 00395 _ale = 0; 00396 _io = 0x10; 00397 _web = 0; 00398 // wait setup time : max(tALS,tCLS,tDS,tWP) 00399 wait_us(tWP_US); 00400 00401 _web = 1; 00402 // wait hold time : max(tCLH,tDH,tWH,tWB) 00403 wait_us(tWB_US); 00404 00405 _cle = 0; 00406 _io.input(); 00407 00408 // wait ready 00409 while(_rbb==0){ 00410 __NOP(); 00411 } 00412 00413 return statusRead(); 00414 }
Generated on Thu Jul 14 2022 10:50:52 by 1.7.2