ADE120x Library Files
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ADE120x.h
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00001 /** 00002 @file ADE120x.h 00003 @brief ADE120x library. This file contains all ADE120x library functions. 00004 @version V0.0.1 00005 @author ADI 00006 @date October 2019 00007 00008 Copyright (c) 2017-2019 Analog Devices, Inc. All Rights Reserved. 00009 00010 This software is proprietary to Analog Devices, Inc. and its licensors. 00011 By using this software you agree to the terms of the associated 00012 Analog Devices Software License Agreement. 00013 *****************************************************************************/ 00014 00015 #ifndef _ADE120x_h_ 00016 #define _ADE120x_h_ 00017 00018 #include "stdio.h" 00019 #include "math.h" 00020 #include "string.h" 00021 #include <stdint.h> 00022 00023 #include "mbed.h" 00024 00025 00026 /** 00027 * Structure for configuring threshold levels 00028 */ 00029 typedef struct threshold{ 00030 float BIN_HighThresh; /** Binary channel high threshold */ 00031 float BIN_LowThresh; /** Binary channel low threshold */ 00032 float WARNA_HighThresh; /** WARNA channel high threshold */ 00033 float WARNA_LowThresh; /** WARNA channel Low threshold */ 00034 float WARNB_HighThresh; /** WARNB channel high threshold */ 00035 float WARNB_LowThresh; /** WARNB channel Low threshold */ 00036 float WARNC_HighThresh; /** WARNC channel high threshold */ 00037 float WARNC_LowThresh; /** WARNC channel Low threshold */ 00038 uint8_t BIN_Mode; /** Binary Channel comparator mode */ 00039 uint8_t WARNA_Mode; /** WARNA Channel comparator mode */ 00040 uint8_t WARNB_Mode; /** WARNB Channel comparator mode */ 00041 uint8_t WARNC_Mode; /** WARNC Channel comparator mode */ 00042 uint8_t ADCPga; /** ADC PGA setting */ 00043 float VGain; /** Voltage divider gain */ 00044 }THRESHCfg_Type; 00045 00046 /** 00047 * Structure for setting programmable load 00048 */ 00049 typedef struct{ 00050 uint8_t enable; /** Enable PL */ 00051 uint8_t mode; /** Configure mode, HIGH_IDLE, LOW_IDLE */ 00052 float HighCurrent; /** High current in mA */ 00053 float LowCurrent; /** Low current in mA */ 00054 float HighTime; /** Duration of current pulse in us */ 00055 float VoltThresh; /** VOltage threshold to trigger programmable load */ 00056 uint8_t ADCPga; /** ADC PGA setting */ 00057 float VGain; /** Voltage gain set by external resister divider */ 00058 }PLOADCfg_Type; 00059 00060 /** 00061 * Structure for configuring energy meter 00062 */ 00063 typedef struct{ 00064 uint8_t enable; /** Enable energy meter function */ 00065 float FET_Energy; /** SOA energy of exernal FET used */ 00066 float PulseMagnitude; /** AMplitude of current pulse in mA */ 00067 float PulseTime; /** Length of current pulse in ms */ 00068 float WorkingVoltage; /** Working voltage of system in V*/ 00069 uint32_t AvgADCCode; /** Average ADC code */ 00070 float SampleRate; /** Sample rate, 20us for ADE1202, 10us foe ADE1201 */ 00071 uint8_t Cooldown_TimeStep; /** Set cooldown timestep */ 00072 uint8_t Cooldown_Decr; /* Set cooldown decrement */ 00073 uint8_t Cooldown_Sec; /** Set cooldown period */ 00074 uint8_t Ov_Scale; /** Set over voltage scale factor */ 00075 uint8_t ADCPga; /** ADC PGA setting */ 00076 float VGain; /** Voltage gain set by external resister divider */ 00077 }EnergyMtrCfg_Type; 00078 00079 /** 00080 * Data sreuture for reading back register data 00081 */ 00082 typedef struct{ 00083 uint16_t reg_addr; 00084 uint32_t reg_data; 00085 }RegisterData_Type; 00086 00087 /******* REGISTER DEFINITION ***********/ 00088 00089 #define REG_LOCK 0x000 00090 #define REG_CTRL 0x001 00091 #define REG_BIN_CTRL 0x002 00092 #define REG_BIN_THR 0x003 00093 #define REG_WARNA_THR 0x004 00094 #define REG_WARNB_THR 0x005 00095 #define REG_WARNC_THR 0x006 00096 #define REG_BIN_FILTER 0x007 00097 #define REG_WARNA_FILTER 0x008 00098 #define REG_WARNB_FILTER 0x009 00099 #define REG_WARNC_FILTER 0x00A 00100 #define REG_MASK 0x00B 00101 #define REG_INT_STATUS 0x00C 00102 #define REG_STATUS 0x00D 00103 #define REG_ADC 0x00E 00104 #define REG_ADCDEC 0x00F 00105 #define REG_PL_CTRL 0x010 00106 #define REG_PL_RISE_THR 0x011 00107 #define REG_PL_LOW_CODE 0x012 00108 #define REG_PL_HIGH_CODE 0x013 00109 #define REG_PL_HIGH_TIME 0x014 00110 #define REG_EGY_MTR_CTRL 0x015 00111 #define REG_EGY_MTR_THR 0x016 00112 #define REG_EGY_MTR1 0x017 00113 #define REG_PL_EN 0x200 00114 #define REG_PGA_GAIN 0x201 00115 00116 /**************************************/ 00117 00118 /******** BIT DEFINITION **************/ 00119 /** Config_LOCK **/ 00120 #define DEV_UNLOCK 0xADE0 00121 #define DEV_LOCK 0xADE1 00122 00123 /** CTRL **/ 00124 #define DEV_ADE1201 0x0 00125 #define DEV_ADE1202 0x1000 00126 #define SW_RST 0x10 00127 #define ADDR_RELOAD 0x8 00128 #define ADE1202_IRQ 0x4 00129 #define CRC_EN 0x1 00130 00131 /** BIN_CTRL **/ 00132 #define Mode_Hysteretic 0 00133 #define Mode_Inbetween 1 00134 #define Mode_Greater 2 00135 #define Mode_LessEqual 3 00136 #define Decrate_Bypass 0 00137 #define Decrate_2 1 00138 #define Decrate_4 2 00139 #define Decrate_8 3 00140 00141 /** xxx_FILTER **/ 00142 #define Filter_En (1<<15) 00143 #define Filter_UpDown (1<<14) 00144 00145 /** Interrupt source selection. These sources are defined as bit mask. 00146 * They are available for register INT_STATUS and STATUS **/ 00147 #define INTSRC_DOUT1 0x0001 /**< Bit0, DOUT1 */ 00148 #define INTSRC_WARNA1 0x0002 /**< Bit1, Warning A from channel 1 */ 00149 #define INTSRC_WARNB1 0x0004 /**< Bit2, Warning B from channel 1 */ 00150 #define INTSRC_WARNC1 0x0008 /**< Bit3, Warning C from channel 1 */ 00151 #define INTSRC_DOUT2 0x0010 /**< Bit4, DOUT2 */ 00152 #define INTSRC_WARNA2 0x0020 /**< Bit5, Warning A from channel 2 */ 00153 #define INTSRC_WARNB2 0x0040 /**< Bit6, Warning B from channel 2 */ 00154 #define INTSRC_WARNC2 0x0080 /**< Bit7, Warning C from channel 2 */ 00155 #define INTSRC_MEMFLT 0x0100 /**< Bit8, Memory fault. After a memory fault is detected the user could reconfigure the device. */ 00156 #define INTSRC_COMFLT 0x0200 /**< Bit9, Communication fault */ 00157 #define INTSRC_TSD 0x0400 /**< Bit10, Thermal shutdown detected */ 00158 #define INTSRC_COOLDOWN1 0x0800 /**< Bit12, Channel 1 is in Cooldown mode */ 00159 #define INTSRC_COOLDOWN2 0x1000 /**< Bit13, Channel 2 is in Cooldown mode */ 00160 #define INTSRC_BUSY 0x2000 /**< Bit13, During busy assertion, internal communication is in progress. Once busy is deasserted, an irq can be triggered which indicates normal operation has resumed */ 00161 #define INTSRC_RSTDONE 0x4000 /**< Bit14, Indicates that the device has reset and is ready to be programmed or begin default normal operation */ 00162 #define INTSRC_ALL 0x7FFF /**< All bits. Used to clear all interrupt sources */ 00163 00164 /** ADC **/ 00165 #define ADC_RAW 0 00166 #define ADC_DECIMATOR 1 00167 00168 /** PL_CTRL **/ 00169 #define LOW_IDLE 0 00170 #define HIGH_IDLE 1 00171 00172 /** EGY_MTR_CTRL **/ 00173 #define OV_SCALE_1 0 00174 #define OV_SCALE_4 1 00175 #define OV_SCALE_8 2 00176 #define OV_SCALE_16 3 00177 00178 00179 typedef enum 00180 { 00181 COOLDOWN_TS_10us = 0, 00182 COOLDOWN_TS_20us = 1, 00183 COOLDOWN_TS_40us = 2, 00184 COOLDOWN_TS_80us = 3 00185 }COOLDOWN_TIMESTAMP; 00186 00187 #define CH1_Enable 1 00188 #define CH2_Enable 2 00189 #define CH1_CH2_Enable 3 00190 #define CH1_Disable 0 00191 #define CH2_disable 0 00192 #define CH1_CH2_Disable 0 00193 00194 /** PL_EN **/ 00195 #define PL_CH2_ENABLE (1<<15) 00196 #define PL_CH1_ENABLE (1<<14) 00197 #define PL_CH2_DISABLE (0<<15) 00198 #define PL_CH1_DISABLE (0<<14) 00199 00200 /** PGA_GAIN **/ 00201 #define ADCPGA_1 1 00202 #define ADCPGA_2 3 00203 #define ADCPGA_5 7 00204 #define ADCPGA_10 0xF 00205 00206 00207 /** 00208 * Method to identify ADE120x 00209 * [15:14][13:12][11:9] [8:5] 00210 * [ RES ][MODEL][Addr][RevIf] 00211 * 00212 */ 00213 #define ADE120x_Model(data) ((((uint32_t)data)>>12)&0x3) /**< Return model. 0: ADE1201, 1:ADE1202 */ 00214 #define ADE120x_ChipAddr(data) ((((uint32_t)data)>>9)&0x7) /**< Return Chip address*/ 00215 #define ADE120x_RevId(data) ((((uint32_t)data)>>5)&0xf) /**< Return silicon rev ID */ 00216 00217 class ADE120x{ 00218 public: 00219 ADE120x(PinName mosi, PinName miso, PinName sclk, PinName cs); 00220 00221 void WriteReg(uint8_t addr, uint32_t reg_addr, uint32_t data); 00222 uint32_t ReadReg(uint8_t addr, uint32_t reg_addr); 00223 00224 00225 uint8_t Reset(uint8_t addr); 00226 uint16_t GetDevID(uint8_t addr); 00227 void UnLock(uint8_t addr); 00228 void Lock(uint8_t addr); 00229 uint8_t DefaultConfig(uint8_t addr); 00230 00231 void ClearIntStatus(uint8_t addr, uint16_t IntSrcSel); 00232 uint16_t GetIntStatus(uint8_t addr); 00233 void SetInt(uint8_t addr, uint16_t IntSrcSel); 00234 00235 void SetBinaryThresh(uint8_t addr, uint16_t thresh); 00236 uint8_t CalculateThreshCode(float V_Thresh, uint8_t ADCPga, float V_Gain); 00237 uint8_t ThresholdCfg(uint8_t addr, THRESHCfg_Type *pCfg); 00238 uint8_t ProgrammableLoadCfg(uint8_t addr, PLOADCfg_Type *pCfg); 00239 uint8_t EnergyMtrCfg(uint8_t addr, EnergyMtrCfg_Type *pCfg); 00240 00241 void SetPgaGain(uint8_t addr, uint16_t gain); 00242 uint8_t ReadADC(uint8_t addr, int8_t src); 00243 float ADCCode2Volt(uint32_t ADCCode, uint8_t ADCPga, float VOLTAGE_Gain); 00244 void GetRegisterData(uint8_t addr, RegisterData_Type *pBuff); 00245 private: 00246 SPI spi_; 00247 DigitalOut nCS_; 00248 00249 }; 00250 00251 #endif
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