rmiiif.h

00001 #ifndef RMIIIF_H
00002 #define RMIIIF_H
00003 
00004 //The right place for some variables.
00005 #define ACC_BROADCAST 0x0002    /* [1]-accept broadcast */
00006 #define ACC_MATCH     0x0020    /* [5]accept perfect  */
00007 #define ACC_MULTICAST 0x0005    /* Accept Multicast */
00008 #define ACC_UNICAST   0x0001    /* Accept Multicast */
00009 #define ACC_HASH      0x0018    /* Hashing enabled  */
00010 
00011 // PHY Registers (National PHY)
00012 #define PHY_BMCR        0x0000
00013 #define PHY_BMSR        0x0001
00014 #define PHY_PHYIDR1     0x0002
00015 #define PHY_PHYIDR2     0x0003
00016 #define PHY_ANAR        0x0004
00017 #define PHY_ANLPAR      0x0005
00018 #define PHY_ANLPARNP    0x0005
00019 #define PHY_ANER        0x0006
00020 #define PHY_ANNPTR      0x0007
00021 
00022 #define PHY_PHYSTS      0x0010
00023 #define PHY_MICR        0x0011
00024 #define PHY_MISR        0x0012
00025 #define PHY_RESERVED1   0x0013
00026 #define PHY_FCSCR       0x0014
00027 #define PHY_RECR        0x0015
00028 #define PHY_PCSR        0x0016
00029 #define PHY_RBR         0x0017
00030 #define PHY_LEDCR       0x0018
00031 #define PHY_PHYCR       0x0019
00032 #define PHY_10BTSCR     0x001A
00033 #define PHY_CDCTRL1     0x001B
00034 #define PHY_RESERVED2   0x001C
00035 #define PHY_EDCR        0x001D
00036 
00037 // PHY Flags
00038 #define PHY_ADDR        (0x0001 << 8) // for National PHY
00039 
00040 /* BMCR flags */
00041 #define BMCR_RESET          0x8000
00042 #define BMCR_LOOPBACK       0x4000
00043 #define BMCR_SPEED_100      0x2000
00044 #define BMCR_AN             0x1000
00045 #define BMCR_POWERDOWN      0x0800
00046 #define BMCR_ISOLATE        0x0400
00047 #define BMCR_RE_AN          0x0200
00048 #define BMCR_DUPLEX         0x0100
00049 
00050 #define MII_BMSR_TIMEOUT    0x1000000
00051 
00052 #define PHILIPS_EMAC_MODULE_ID  ((0x3902 << 16) | 0x2000)
00053 
00054 /* BMSR flags */
00055 #define BMSR_100BE_T4       0x8000
00056 #define BMSR_100TX_FULL     0x4000
00057 #define BMSR_100TX_HALF     0x2000
00058 #define BMSR_10BE_FULL      0x1000
00059 #define BMSR_10BE_HALF      0x0800
00060 #define BMSR_AUTO_DONE      0x0020
00061 #define BMSR_REMOTE_FAULT   0x0010
00062 #define BMSR_NO_AUTO        0x0008
00063 #define BMSR_LINK_ESTABLISHED   0x0004
00064 
00065 
00066 /* MAC registers and parameters */
00067 #define PCONP_EMAC_CLOCK    0x40000000
00068 
00069 #define SPEED_100           1
00070 #define SPEED_10            0
00071 #define FULL_DUPLEX         1
00072 #define HALF_DUPLEX         0
00073 
00074 #define EMAC_RAM_ADDR       0x7FE00000
00075 #define EMAC_RAM_SIZE       0x00004000
00076 #define EMAC_RAM_END        EMAC_RAM_ADDR + EMAC_RAM_SIZE
00077 
00078 
00079 /*
00080 The Ethernet RAM is configured as below, the starting of EMAC_DESCRIPTOR_ADDR depends
00081 on the EMAC_DESCRIPTOR_COUNT or the TOTAL_DESCRIPTOR_SIZE, at this point, the 
00082 EMAC_DESCRIPTOR_COUNT for both TX and RX is set to 16:
00083 
00084    EMAC_RAM_ADDR    0x7FE00000
00085    EMAC_DMA_ADDR    0x7FE00000
00086    .
00087    EMAC_DMA_END     EMAC_RAM_ADDR + EMAC_RAM_SIZE - TOTAL_DESCRIPTOR_SIZE 
00088    TX_DESCRIPTOR_ADDR = EMAC_DESCRIPTOR_ADDR = EMAC_RAM_END(EMAC_RAM_ADDR+EMAC_RAM_SIZE) - TOTAL_DESCRIPTOR 
00089    TX_STATUS_ADDR = TX_DESCRIPTOR_ADDR + TX_DESCRIPTOR_SIZE
00090    RX_DESCRIPTOR_ADDR = TX_DESCRIPTOR_ADDR + TX_DESCRIPTOR_SIZE + TX_STATUS_SIZE
00091    RX_STATUS_ADDR = RX_DESCRIPTOR_ADDR + RX_STATUS_SIZE
00092    ( RX_STATUS_ADDR + RX_STATUS_SIZE = EMAC_RAM_END )!!!!!
00093    EMAX_RAM_END 0x7FE04000
00094 
00095    Please note that, the descriptors have to be aligned to the 32 bit boundary!!!
00096    Below descriptor addresses have been carefully aligned to the 32-bit boundary. 
00097    If not, the descriptors have to be re-aligned!!! 
00098 */
00099 
00100 #define EMAC_TX_DESCRIPTOR_COUNT    0x0003
00101 #define EMAC_RX_DESCRIPTOR_COUNT    0x0005
00102 
00103 #define TX_DESCRIPTOR_SIZE  (EMAC_TX_DESCRIPTOR_COUNT * 8)
00104 #define RX_DESCRIPTOR_SIZE  (EMAC_RX_DESCRIPTOR_COUNT * 8)
00105 #define TX_STATUS_SIZE      (EMAC_TX_DESCRIPTOR_COUNT * 4)
00106 #define RX_STATUS_SIZE      (EMAC_RX_DESCRIPTOR_COUNT * 8)
00107 #define TOTAL_DESCRIPTOR_SIZE   (TX_DESCRIPTOR_SIZE + RX_DESCRIPTOR_SIZE + TX_STATUS_SIZE + RX_STATUS_SIZE)
00108 #define EMAC_DESCRIPTOR_ADDR    (EMAC_RAM_ADDR + EMAC_RAM_SIZE - TOTAL_DESCRIPTOR_SIZE) 
00109 
00110 #define TX_DESCRIPTOR_ADDR  EMAC_DESCRIPTOR_ADDR
00111 #define TX_STATUS_ADDR      (EMAC_DESCRIPTOR_ADDR + TX_DESCRIPTOR_SIZE)
00112 #define RX_DESCRIPTOR_ADDR  (TX_STATUS_ADDR + TX_STATUS_SIZE)
00113 #define RX_STATUS_ADDR      (RX_DESCRIPTOR_ADDR + RX_DESCRIPTOR_SIZE)
00114 
00115 //#define EMAC_DMA_ADDR     EMAC_RAM_ADDR
00116 //#define EMAC_DMA_END      EMAC_RAM_ADDR + EMAC_RAM_SIZE - TOTAL_DESCRIPTOR_SIZE
00117 //#define EMAC_DMA_SIZE     EMAC_RAM_SIZE - TOTAL_DESCRIPTOR_SIZE
00118 
00119 /* 
00120 For EMAC TX and RX buffer, the fixed block size is EMAC_BLOCK_SIZE, there will 
00121 EMAC_TX_BLOCK_NUM and EMAC_RX_BLOCK_NUM blocks for TX and RX, the total RAM size used 
00122 is EMAC_BLOCK * (EMAC_TX_BLOCK_NUM + EMAC_RX_BLOCK_NUM) = 15360, the TOTAL_DESCRIPTOR_SIZE 
00123 is 448, the total RAM, 16384 bytes, is just big enough for buffers and descriptors, 
00124 EMA_BUFFER_SIZE + TOTAL_DESCRIPTOR_SIZE = 16256.
00125 
00126 Please note, 
00127  (1) if the EMAC_DESCRIPTOR_COUNT increases, the EMAC_BUFFER_SIZE needs to be decreased accordingly!!!!
00128  (2) if the TOTAL_EMAC_BLOCK_SIZE increases, the EMAC_BLOCK_NUM needs to be decreased accordingly as well!!! 
00129 */
00130 #define EMAC_BLOCK_SIZE         0x300
00131 //0x600
00132 #define EMAC_TX_BLOCK_NUM       EMAC_TX_DESCRIPTOR_COUNT
00133 #define EMAC_RX_BLOCK_NUM       EMAC_RX_DESCRIPTOR_COUNT
00134 #define TOTAL_EMAC_BLOCK_NUM    (EMAC_TX_BLOCK_NUM + EMAC_RX_BLOCK_NUM)
00135 
00136 #define EMAC_BUFFER_SIZE        (EMAC_BLOCK_SIZE * (EMAC_TX_BLOCK_NUM + EMAC_RX_BLOCK_NUM ))
00137 #define EMAC_TX_BUFFER_ADDR     EMAC_RAM_ADDR
00138 #define EMAC_RX_BUFFER_ADDR     (EMAC_RAM_ADDR + EMAC_BLOCK_SIZE * EMAC_TX_BLOCK_NUM)
00139 #define EMAC_MEM_ADDR           (EMAC_RAM_ADDR + EMAC_BLOCK_SIZE * TOTAL_EMAC_BLOCK_NUM)
00140 #define EMAC_MEM_SIZE           (EMAC_DESCRIPTOR_ADDR - EMAC_MEM_ADDR)
00141 
00142 /* EMAC TX DMA Descriptor */
00143 typedef struct _EMAC_TX_DESCRIPTOR {
00144     unsigned long TXPacketAddr;     /* TX DMA Buffer Address */
00145     unsigned long TXControl;
00146 } EMAC_TX_DESCRIPTOR;
00147 
00148 typedef struct _EMAC_RX_DESCRIPTOR {
00149     unsigned long RXPacketAddr;     /* RX DMA Buffer Address */
00150     unsigned long RXControl;
00151 } EMAC_RX_DESCRIPTOR;
00152 
00153 #define RX_DESCRIPTOR_PACKET(i) (*(unsigned int *)(RX_DESCRIPTOR_ADDR    + 8*i))
00154 #define RX_DESCRIPTOR_CTRL(i)   (*(unsigned int *)(RX_DESCRIPTOR_ADDR+4  + 8*i))
00155 #define RX_STATUS_INFO(i)       (*(unsigned int *)(RX_STATUS_ADDR        + 8*i))
00156 #define RX_STATUS_HASHCRC(i)    (*(unsigned int *)(RX_STATUS_ADDR     +4 + 8*i))
00157 #define TX_DESCRIPTOR_PACKET(i) (*(unsigned int *)(TX_DESCRIPTOR_ADDR    + 8*i))
00158 #define TX_DESCRIPTOR_CTRL(i)   (*(unsigned int *)(TX_DESCRIPTOR_ADDR +4 + 8*i))
00159 #define TX_STATUS_INFO(i)       (*(unsigned int *)(TX_STATUS_ADDR        + 4*i))
00160 #define EMAC_RX_BUFFER(i)       (EMAC_RX_BUFFER_ADDR + EMAC_BLOCK_SIZE*i)
00161 #define EMAC_TX_BUFFER(i)       (EMAC_TX_BUFFER_ADDR + EMAC_BLOCK_SIZE*i)
00162 
00163 /* EMAC Descriptor TX and RX Control fields */
00164 #define EMAC_TX_DESC_INT        0x80000000
00165 #define EMAC_TX_DESC_LAST       0x40000000
00166 #define EMAC_TX_DESC_CRC        0x20000000
00167 #define EMAC_TX_DESC_PAD        0x10000000
00168 #define EMAC_TX_DESC_HUGE       0x08000000
00169 #define EMAC_TX_DESC_OVERRIDE   0x04000000
00170 
00171 #define EMAC_RX_DESC_INT        0x80000000
00172 
00173 /* EMAC Descriptor status related definition */
00174 #define TX_DESC_STATUS_ERR      0x80000000
00175 #define TX_DESC_STATUS_NODESC   0x40000000
00176 #define TX_DESC_STATUS_UNDERRUN 0x20000000
00177 #define TX_DESC_STATUS_LCOL     0x10000000
00178 #define TX_DESC_STATUS_ECOL     0x08000000
00179 #define TX_DESC_STATUS_EDEFER   0x04000000
00180 #define TX_DESC_STATUS_DEFER    0x02000000
00181 #define TX_DESC_STATUS_COLCNT   0x01E00000  /* four bits, it's a mask, not exact count */
00182 
00183 #define RX_DESC_STATUS_ERR      0x80000000
00184 #define RX_DESC_STATUS_LAST     0x40000000
00185 #define RX_DESC_STATUS_NODESC   0x20000000
00186 #define RX_DESC_STATUS_OVERRUN  0x10000000
00187 #define RX_DESC_STATUS_ALGNERR  0x08000000
00188 #define RX_DESC_STATUS_RNGERR   0x04000000
00189 #define RX_DESC_STATUS_LENERR   0x02000000
00190 #define RX_DESC_STATUS_SYMERR   0x01000000
00191 #define RX_DESC_STATUS_CRCERR   0x00800000
00192 #define RX_DESC_STATUS_BCAST    0x00400000
00193 #define RX_DESC_STATUS_MCAST    0x00200000
00194 #define RX_DESC_STATUS_FAILFLT  0x00100000
00195 #define RX_DESC_STATUS_VLAN     0x00080000
00196 #define RX_DESC_STATUS_CTLFRAM  0x00040000
00197 
00198 #define DESC_SIZE_MASK          0x000007FF  /* 11 bits for both TX and RX */
00199 
00200 /* EMAC interrupt controller related definition */
00201 #define EMAC_INT_RXOVERRUN  0x01 << 0
00202 #define EMAC_INT_RXERROR    0x01 << 1 
00203 #define EMAC_INT_RXFINISHED 0x01 << 2
00204 #define EMAC_INT_RXDONE     0x01 << 3 
00205 #define EMAC_INT_TXUNDERRUN 0x01 << 4
00206 #define EMAC_INT_TXERROR    0x01 << 5 
00207 #define EMAC_INT_TXFINISHED 0x01 << 6
00208 #define EMAC_INT_TXDONE     0x01 << 7 
00209 #define EMAC_INT_SOFTINT    0x01 << 12
00210 #define EMAC_INT_WOL        0x01 << 13 
00211 
00212 #define MAX_PACKET_SIZE     0x600
00213 #define EMAC_HEADER_LENGTH  14
00214 
00215 #define I_Bit           0x80
00216 #define F_Bit           0x40
00217 
00218 #define SYS32Mode       0x1F
00219 #define IRQ32Mode       0x12
00220 #define FIQ32Mode       0x11
00221 
00222 #endif