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mbed library sources. Supersedes mbed-src.

Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_system.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3
Parent:: 180:96ed750bd169

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	156:95d6b41a828b	1	/**
<>	156:95d6b41a828b	2	******************************************************************************
<>	156:95d6b41a828b	3	* @file stm32f0xx_ll_system.h
<>	156:95d6b41a828b	4	* @author MCD Application Team
<>	156:95d6b41a828b	5	* @brief Header file of SYSTEM LL module.
<>	156:95d6b41a828b	6	@verbatim
<>	156:95d6b41a828b	7	==============================================================================
<>	156:95d6b41a828b	8	##### How to use this driver #####
<>	156:95d6b41a828b	9	==============================================================================
<>	156:95d6b41a828b	10	[..]
<>	156:95d6b41a828b	11	The LL SYSTEM driver contains a set of generic APIs that can be
<>	156:95d6b41a828b	12	used by user:
<>	156:95d6b41a828b	13	(+) Some of the FLASH features need to be handled in the SYSTEM file.
<>	156:95d6b41a828b	14	(+) Access to DBGCMU registers
<>	156:95d6b41a828b	15	(+) Access to SYSCFG registers
<>	156:95d6b41a828b	16
<>	156:95d6b41a828b	17	@endverbatim
<>	156:95d6b41a828b	18	******************************************************************************
<>	156:95d6b41a828b	19	* @attention
<>	156:95d6b41a828b	20	*
<>	156:95d6b41a828b	21	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	156:95d6b41a828b	22	*
<>	156:95d6b41a828b	23	* Redistribution and use in source and binary forms, with or without modification,
<>	156:95d6b41a828b	24	* are permitted provided that the following conditions are met:
<>	156:95d6b41a828b	25	* 1. Redistributions of source code must retain the above copyright notice,
<>	156:95d6b41a828b	26	* this list of conditions and the following disclaimer.
<>	156:95d6b41a828b	27	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	156:95d6b41a828b	28	* this list of conditions and the following disclaimer in the documentation
<>	156:95d6b41a828b	29	* and/or other materials provided with the distribution.
<>	156:95d6b41a828b	30	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	156:95d6b41a828b	31	* may be used to endorse or promote products derived from this software
<>	156:95d6b41a828b	32	* without specific prior written permission.
<>	156:95d6b41a828b	33	*
<>	156:95d6b41a828b	34	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	156:95d6b41a828b	35	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	156:95d6b41a828b	36	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	156:95d6b41a828b	37	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	156:95d6b41a828b	38	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	156:95d6b41a828b	39	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	156:95d6b41a828b	40	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	156:95d6b41a828b	41	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	156:95d6b41a828b	42	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	156:95d6b41a828b	43	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	156:95d6b41a828b	44	*
<>	156:95d6b41a828b	45	******************************************************************************
<>	156:95d6b41a828b	46	*/
<>	156:95d6b41a828b	47
<>	156:95d6b41a828b	48	/* Define to prevent recursive inclusion -------------------------------------*/
<>	156:95d6b41a828b	49	#ifndef __STM32F0xx_LL_SYSTEM_H
<>	156:95d6b41a828b	50	#define __STM32F0xx_LL_SYSTEM_H
<>	156:95d6b41a828b	51
<>	156:95d6b41a828b	52	#ifdef __cplusplus
<>	156:95d6b41a828b	53	extern "C" {
<>	156:95d6b41a828b	54	#endif
<>	156:95d6b41a828b	55
<>	156:95d6b41a828b	56	/* Includes ------------------------------------------------------------------*/
<>	156:95d6b41a828b	57	#include "stm32f0xx.h"
<>	156:95d6b41a828b	58
<>	156:95d6b41a828b	59	/** @addtogroup STM32F0xx_LL_Driver
<>	156:95d6b41a828b	60	* @{
<>	156:95d6b41a828b	61	*/
<>	156:95d6b41a828b	62
<>	156:95d6b41a828b	63	#if defined (FLASH) \|\| defined (SYSCFG) \|\| defined (DBGMCU)
<>	156:95d6b41a828b	64
<>	156:95d6b41a828b	65	/** @defgroup SYSTEM_LL SYSTEM
<>	156:95d6b41a828b	66	* @{
<>	156:95d6b41a828b	67	*/
<>	156:95d6b41a828b	68
<>	156:95d6b41a828b	69	/* Private types -------------------------------------------------------------*/
<>	156:95d6b41a828b	70	/* Private variables ---------------------------------------------------------*/
<>	156:95d6b41a828b	71
<>	156:95d6b41a828b	72	/* Private constants ---------------------------------------------------------*/
<>	156:95d6b41a828b	73	/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
<>	156:95d6b41a828b	74	* @{
<>	156:95d6b41a828b	75	*/
<>	156:95d6b41a828b	76
<>	156:95d6b41a828b	77	/**
<>	156:95d6b41a828b	78	* @}
<>	156:95d6b41a828b	79	*/
<>	156:95d6b41a828b	80
<>	156:95d6b41a828b	81	/* Private macros ------------------------------------------------------------*/
<>	156:95d6b41a828b	82
<>	156:95d6b41a828b	83	/* Exported types ------------------------------------------------------------*/
<>	156:95d6b41a828b	84	/* Exported constants --------------------------------------------------------*/
<>	156:95d6b41a828b	85	/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
<>	156:95d6b41a828b	86	* @{
<>	156:95d6b41a828b	87	*/
<>	156:95d6b41a828b	88
<>	156:95d6b41a828b	89	/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG Remap
<>	156:95d6b41a828b	90	* @{
<>	156:95d6b41a828b	91	*/
<>	156:95d6b41a828b	92	#define LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000U /!< Main Flash memory mapped at 0x00000000 /
<>	156:95d6b41a828b	93	#define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0 /!< System Flash memory mapped at 0x00000000 /
<>	156:95d6b41a828b	94	#define LL_SYSCFG_REMAP_SRAM (SYSCFG_CFGR1_MEM_MODE_1 \| SYSCFG_CFGR1_MEM_MODE_0) /!< Embedded SRAM mapped at 0x00000000 /
<>	156:95d6b41a828b	95	/**
<>	156:95d6b41a828b	96	* @}
<>	156:95d6b41a828b	97	*/
<>	156:95d6b41a828b	98
<>	156:95d6b41a828b	99	#if defined(SYSCFG_CFGR1_IR_MOD)
<>	156:95d6b41a828b	100	/** @defgroup SYSTEM_LL_EC_IR_MOD SYSCFG IR Modulation
<>	156:95d6b41a828b	101	* @{
<>	156:95d6b41a828b	102	*/
<>	156:95d6b41a828b	103	#define LL_SYSCFG_IR_MOD_TIM16 (SYSCFG_CFGR1_IR_MOD_0 & SYSCFG_CFGR1_IR_MOD_1) /!< Timer16 is selected as IR Modulation enveloppe source /
<>	156:95d6b41a828b	104	#define LL_SYSCFG_IR_MOD_USART1 (SYSCFG_CFGR1_IR_MOD_0) /!< USART1 is selected as IR Modulation enveloppe source /
<>	156:95d6b41a828b	105	#define LL_SYSCFG_IR_MOD_USART4 (SYSCFG_CFGR1_IR_MOD_1) /!< USART4 is selected as IR Modulation enveloppe source /
<>	156:95d6b41a828b	106	/**
<>	156:95d6b41a828b	107	* @}
<>	156:95d6b41a828b	108	*/
<>	156:95d6b41a828b	109
<>	156:95d6b41a828b	110	#endif /* SYSCFG_CFGR1_IR_MOD */
<>	156:95d6b41a828b	111
<>	156:95d6b41a828b	112	#if defined(SYSCFG_CFGR1_USART1TX_DMA_RMP) \|\| defined(SYSCFG_CFGR1_USART1RX_DMA_RMP) \|\| defined(SYSCFG_CFGR1_USART2_DMA_RMP) \|\| defined(SYSCFG_CFGR1_USART3_DMA_RMP)
<>	156:95d6b41a828b	113	/** @defgroup SYSTEM_LL_EC_USART1TX_RMP SYSCFG USART DMA Remap
<>	156:95d6b41a828b	114	* @{
<>	156:95d6b41a828b	115	*/
<>	156:95d6b41a828b	116	#if defined (SYSCFG_CFGR1_USART1TX_DMA_RMP)
<>	156:95d6b41a828b	117	#define LL_SYSCFG_USART1TX_RMP_DMA1CH2 ((SYSCFG_CFGR1_USART1TX_DMA_RMP >> 8U) \| (uint32_t)0x00000000U) /!< USART1_TX DMA request mapped on DMA channel 2U /
<>	156:95d6b41a828b	118	#define LL_SYSCFG_USART1TX_RMP_DMA1CH4 ((SYSCFG_CFGR1_USART1TX_DMA_RMP >> 8U) \| SYSCFG_CFGR1_USART1TX_DMA_RMP) /!< USART1_TX DMA request mapped on DMA channel 4U /
<>	156:95d6b41a828b	119	#endif /SYSCFG_CFGR1_USART1TX_DMA_RMP/
<>	156:95d6b41a828b	120	#if defined (SYSCFG_CFGR1_USART1RX_DMA_RMP)
<>	156:95d6b41a828b	121	#define LL_SYSCFG_USART1RX_RMP_DMA1CH3 ((SYSCFG_CFGR1_USART1RX_DMA_RMP >> 8U) \| (uint32_t)0x00000000U) /!< USART1_RX DMA request mapped on DMA channel 3U /
<>	156:95d6b41a828b	122	#define LL_SYSCFG_USART1RX_RMP_DMA1CH5 ((SYSCFG_CFGR1_USART1RX_DMA_RMP >> 8U) \| SYSCFG_CFGR1_USART1RX_DMA_RMP) /!< USART1_RX DMA request mapped on DMA channel 5 /
<>	156:95d6b41a828b	123	#endif /SYSCFG_CFGR1_USART1RX_DMA_RMP/
<>	156:95d6b41a828b	124	#if defined (SYSCFG_CFGR1_USART2_DMA_RMP)
<>	156:95d6b41a828b	125	#define LL_SYSCFG_USART2_RMP_DMA1CH54 ((SYSCFG_CFGR1_USART2_DMA_RMP >> 8U) \| (uint32_t)0x00000000U) /!< USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4U respectively /
<>	156:95d6b41a828b	126	#define LL_SYSCFG_USART2_RMP_DMA1CH67 ((SYSCFG_CFGR1_USART2_DMA_RMP >> 8U) \| SYSCFG_CFGR1_USART2_DMA_RMP) /!< USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively /
<>	156:95d6b41a828b	127	#endif /SYSCFG_CFGR1_USART2_DMA_RMP/
<>	156:95d6b41a828b	128	#if defined (SYSCFG_CFGR1_USART3_DMA_RMP)
<>	156:95d6b41a828b	129	#define LL_SYSCFG_USART3_RMP_DMA1CH67 ((SYSCFG_CFGR1_USART3_DMA_RMP >> 8U) \| (uint32_t)0x00000000U) /!< USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively /
<>	156:95d6b41a828b	130	#define LL_SYSCFG_USART3_RMP_DMA1CH32 ((SYSCFG_CFGR1_USART3_DMA_RMP >> 8U) \| SYSCFG_CFGR1_USART3_DMA_RMP) /!< USART3_RX and USART3_TX DMA requests mapped on DMA channel 3U and 2U respectively /
<>	156:95d6b41a828b	131	#endif /* SYSCFG_CFGR1_USART3_DMA_RMP */
<>	156:95d6b41a828b	132	/**
<>	156:95d6b41a828b	133	* @}
<>	156:95d6b41a828b	134	*/
<>	156:95d6b41a828b	135	#endif /* SYSCFG_CFGR1_USART1TX_DMA_RMP \|\| SYSCFG_CFGR1_USART1RX_DMA_RMP \|\| SYSCFG_CFGR1_USART2_DMA_RMP \|\| SYSCFG_CFGR1_USART3_DMA_RMP */
<>	156:95d6b41a828b	136
<>	156:95d6b41a828b	137	#if defined (SYSCFG_CFGR1_SPI2_DMA_RMP)
<>	156:95d6b41a828b	138	/** @defgroup SYSTEM_LL_EC_SPI2_RMP_DMA1 SYSCFG SPI2 DMA Remap
<>	156:95d6b41a828b	139	* @{
<>	156:95d6b41a828b	140	*/
<>	156:95d6b41a828b	141	#define LL_SYSCFG_SPI2_RMP_DMA1_CH45 (uint32_t)0x00000000U /!< SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4U and 5 respectively /
<>	156:95d6b41a828b	142	#define LL_SYSCFG_SPI2_RMP_DMA1_CH67 SYSCFG_CFGR1_SPI2_DMA_RMP /!< SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively /
<>	156:95d6b41a828b	143	/**
<>	156:95d6b41a828b	144	* @}
<>	156:95d6b41a828b	145	*/
<>	156:95d6b41a828b	146
<>	156:95d6b41a828b	147	#endif /SYSCFG_CFGR1_SPI2_DMA_RMP/
<>	156:95d6b41a828b	148
<>	156:95d6b41a828b	149	#if defined (SYSCFG_CFGR1_I2C1_DMA_RMP)
<>	156:95d6b41a828b	150	/** @defgroup SYSTEM_LL_EC_I2C1_RMP_DMA1 SYSCFG I2C1 DMA Remap
<>	156:95d6b41a828b	151	* @{
<>	156:95d6b41a828b	152	*/
<>	156:95d6b41a828b	153	#define LL_SYSCFG_I2C1_RMP_DMA1_CH32 (uint32_t)0x00000000U /!< I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3U and 2U respectively /
<>	156:95d6b41a828b	154	#define LL_SYSCFG_I2C1_RMP_DMA1_CH76 SYSCFG_CFGR1_I2C1_DMA_RMP /!< I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively /
<>	156:95d6b41a828b	155	/**
<>	156:95d6b41a828b	156	* @}
<>	156:95d6b41a828b	157	*/
<>	156:95d6b41a828b	158
<>	156:95d6b41a828b	159	#endif /SYSCFG_CFGR1_I2C1_DMA_RMP/
<>	156:95d6b41a828b	160
<>	156:95d6b41a828b	161	#if defined(SYSCFG_CFGR1_ADC_DMA_RMP)
<>	156:95d6b41a828b	162	/** @defgroup SYSTEM_LL_EC_ADC1_RMP_DMA1 SYSCFG ADC1 DMA Remap
<>	156:95d6b41a828b	163	* @{
<>	156:95d6b41a828b	164	*/
<>	156:95d6b41a828b	165	#define LL_SYSCFG_ADC1_RMP_DMA1_CH1 (uint32_t)0x00000000U /!< ADC DMA request mapped on DMA channel 1U /
<>	156:95d6b41a828b	166	#define LL_SYSCFG_ADC1_RMP_DMA1_CH2 SYSCFG_CFGR1_ADC_DMA_RMP /!< ADC DMA request mapped on DMA channel 2U /
<>	156:95d6b41a828b	167	/**
<>	156:95d6b41a828b	168	* @}
<>	156:95d6b41a828b	169	*/
<>	156:95d6b41a828b	170
<>	156:95d6b41a828b	171	#endif /* SYSCFG_CFGR1_ADC_DMA_RMP */
<>	156:95d6b41a828b	172
<>	156:95d6b41a828b	173	#if defined(SYSCFG_CFGR1_TIM16_DMA_RMP) \|\| defined(SYSCFG_CFGR1_TIM17_DMA_RMP) \|\| defined(SYSCFG_CFGR1_TIM1_DMA_RMP) \|\| defined(SYSCFG_CFGR1_TIM2_DMA_RMP) \|\| defined(SYSCFG_CFGR1_TIM3_DMA_RMP)
<>	156:95d6b41a828b	174	/** @defgroup SYSTEM_LL_EC_TIM16_RMP_DMA1 SYSCFG TIM DMA Remap
<>	156:95d6b41a828b	175	* @{
<>	156:95d6b41a828b	176	*/
<>	156:95d6b41a828b	177	#if defined(SYSCFG_CFGR1_TIM16_DMA_RMP)
<>	156:95d6b41a828b	178	#if defined (SYSCFG_CFGR1_TIM16_DMA_RMP2)
<>	156:95d6b41a828b	179	#define LL_SYSCFG_TIM16_RMP_DMA1_CH3 (((SYSCFG_CFGR1_TIM16_DMA_RMP \| SYSCFG_CFGR1_TIM16_DMA_RMP2) >> 8U) \| (uint32_t)0x00000000U) /!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3 /
<>	156:95d6b41a828b	180	#define LL_SYSCFG_TIM16_RMP_DMA1_CH4 (((SYSCFG_CFGR1_TIM16_DMA_RMP \| SYSCFG_CFGR1_TIM16_DMA_RMP2) >> 8U) \| SYSCFG_CFGR1_TIM16_DMA_RMP) /!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4 /
<>	156:95d6b41a828b	181	#define LL_SYSCFG_TIM16_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM16_DMA_RMP2 >> 8U) \| SYSCFG_CFGR1_TIM16_DMA_RMP2) /!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 6 /
<>	156:95d6b41a828b	182	#else
<>	156:95d6b41a828b	183	#define LL_SYSCFG_TIM16_RMP_DMA1_CH3 ((SYSCFG_CFGR1_TIM16_DMA_RMP >> 8U) \| (uint32_t)0x00000000U) /!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3 /
<>	156:95d6b41a828b	184	#define LL_SYSCFG_TIM16_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM16_DMA_RMP >> 8U) \| SYSCFG_CFGR1_TIM16_DMA_RMP) /!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4 /
<>	156:95d6b41a828b	185	#endif /* SYSCFG_CFGR1_TIM16_DMA_RMP2 */
<>	156:95d6b41a828b	186	#endif /* SYSCFG_CFGR1_TIM16_DMA_RMP */
<>	156:95d6b41a828b	187	#if defined(SYSCFG_CFGR1_TIM17_DMA_RMP)
<>	156:95d6b41a828b	188	#if defined (SYSCFG_CFGR1_TIM17_DMA_RMP2)
<>	156:95d6b41a828b	189	#define LL_SYSCFG_TIM17_RMP_DMA1_CH1 (((SYSCFG_CFGR1_TIM17_DMA_RMP \| SYSCFG_CFGR1_TIM17_DMA_RMP2) >> 8U) \| (uint32_t)0x00000000U) /!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1 /
<>	156:95d6b41a828b	190	#define LL_SYSCFG_TIM17_RMP_DMA1_CH2 (((SYSCFG_CFGR1_TIM17_DMA_RMP \| SYSCFG_CFGR1_TIM17_DMA_RMP2) >> 8U) \| SYSCFG_CFGR1_TIM17_DMA_RMP) /!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2 /
<>	156:95d6b41a828b	191	#define LL_SYSCFG_TIM17_RMP_DMA1_CH7 ((SYSCFG_CFGR1_TIM17_DMA_RMP2 >> 8U) \| SYSCFG_CFGR1_TIM17_DMA_RMP2) /!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 7 /
<>	156:95d6b41a828b	192	#else
<>	156:95d6b41a828b	193	#define LL_SYSCFG_TIM17_RMP_DMA1_CH1 ((SYSCFG_CFGR1_TIM17_DMA_RMP >> 8U) \| (uint32_t)0x00000000U) /!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1 /
<>	156:95d6b41a828b	194	#define LL_SYSCFG_TIM17_RMP_DMA1_CH2 ((SYSCFG_CFGR1_TIM17_DMA_RMP >> 8U) \| SYSCFG_CFGR1_TIM17_DMA_RMP) /!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2 /
<>	156:95d6b41a828b	195	#endif /* SYSCFG_CFGR1_TIM17_DMA_RMP2 */
<>	156:95d6b41a828b	196	#endif /* SYSCFG_CFGR1_TIM17_DMA_RMP */
<>	156:95d6b41a828b	197	#if defined (SYSCFG_CFGR1_TIM1_DMA_RMP)
<>	156:95d6b41a828b	198	#define LL_SYSCFG_TIM1_RMP_DMA1_CH234 ((SYSCFG_CFGR1_TIM1_DMA_RMP >> 8U) \| (uint32_t)0x00000000U) /!< TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMAchannel 2, 3 and 4 respectively /
<>	156:95d6b41a828b	199	#define LL_SYSCFG_TIM1_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM1_DMA_RMP >> 8U) \| SYSCFG_CFGR1_TIM1_DMA_RMP) /!< TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6 /
<>	156:95d6b41a828b	200	#endif /SYSCFG_CFGR1_TIM1_DMA_RMP/
<>	156:95d6b41a828b	201	#if defined (SYSCFG_CFGR1_TIM2_DMA_RMP)
<>	156:95d6b41a828b	202	#define LL_SYSCFG_TIM2_RMP_DMA1_CH34 ((SYSCFG_CFGR1_TIM2_DMA_RMP >> 8U) \| (uint32_t)0x00000000U) /!< TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively /
<>	156:95d6b41a828b	203	#define LL_SYSCFG_TIM2_RMP_DMA1_CH7 ((SYSCFG_CFGR1_TIM2_DMA_RMP >> 8U) \| SYSCFG_CFGR1_TIM2_DMA_RMP) /!< TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 /
<>	156:95d6b41a828b	204	#endif /SYSCFG_CFGR1_TIM2_DMA_RMP/
<>	156:95d6b41a828b	205	#if defined (SYSCFG_CFGR1_TIM3_DMA_RMP)
<>	156:95d6b41a828b	206	#define LL_SYSCFG_TIM3_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM3_DMA_RMP >> 8U) \| (uint32_t)0x00000000U) /!< TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4 /
<>	156:95d6b41a828b	207	#define LL_SYSCFG_TIM3_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM3_DMA_RMP >> 8U) \| SYSCFG_CFGR1_TIM3_DMA_RMP) /!< TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6 /
<>	156:95d6b41a828b	208	#endif /SYSCFG_CFGR1_TIM3_DMA_RMP/
<>	156:95d6b41a828b	209	/**
<>	156:95d6b41a828b	210	* @}
<>	156:95d6b41a828b	211	*/
<>	156:95d6b41a828b	212
<>	156:95d6b41a828b	213	#endif /* SYSCFG_CFGR1_TIM16_DMA_RMP \|\| SYSCFG_CFGR1_TIM17_DMA_RMP \|\| SYSCFG_CFGR1_TIM1_DMA_RMP \|\| SYSCFG_CFGR1_TIM2_DMA_RMP \|\| SYSCFG_CFGR1_TIM3_DMA_RMP */
<>	156:95d6b41a828b	214
<>	156:95d6b41a828b	215	/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
<>	156:95d6b41a828b	216	* @{
<>	156:95d6b41a828b	217	*/
<>	156:95d6b41a828b	218	#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /!< I2C PB6 Fast mode plus /
<>	156:95d6b41a828b	219	#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /!< I2C PB7 Fast mode plus /
<>	156:95d6b41a828b	220	#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /!< I2C PB8 Fast mode plus /
<>	156:95d6b41a828b	221	#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /!< I2C PB9 Fast mode plus /
<>	156:95d6b41a828b	222	#if defined(SYSCFG_CFGR1_I2C_FMP_I2C1)
<>	156:95d6b41a828b	223	#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C_FMP_I2C1 /!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 /
<>	156:95d6b41a828b	224	#endif /SYSCFG_CFGR1_I2C_FMP_I2C1/
<>	156:95d6b41a828b	225	#if defined(SYSCFG_CFGR1_I2C_FMP_I2C2)
<>	156:95d6b41a828b	226	#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C_FMP_I2C2 /!< Enable I2C2 Fast mode plus /
<>	156:95d6b41a828b	227	#endif /SYSCFG_CFGR1_I2C_FMP_I2C2/
<>	156:95d6b41a828b	228	#if defined(SYSCFG_CFGR1_I2C_FMP_PA9)
<>	156:95d6b41a828b	229	#define LL_SYSCFG_I2C_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /!< Enable Fast Mode Plus on PA9 /
<>	156:95d6b41a828b	230	#endif /SYSCFG_CFGR1_I2C_FMP_PA9/
<>	156:95d6b41a828b	231	#if defined(SYSCFG_CFGR1_I2C_FMP_PA10)
<>	156:95d6b41a828b	232	#define LL_SYSCFG_I2C_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_FMP_PA10 /!< Enable Fast Mode Plus on PA10 /
<>	156:95d6b41a828b	233	#endif /SYSCFG_CFGR1_I2C_FMP_PA10/
<>	156:95d6b41a828b	234	/**
<>	156:95d6b41a828b	235	* @}
<>	156:95d6b41a828b	236	*/
<>	156:95d6b41a828b	237
<>	156:95d6b41a828b	238	/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
<>	156:95d6b41a828b	239	* @{
<>	156:95d6b41a828b	240	*/
<>	156:95d6b41a828b	241	#define LL_SYSCFG_EXTI_PORTA (uint32_t)0U /!< EXTI PORT A /
<>	156:95d6b41a828b	242	#define LL_SYSCFG_EXTI_PORTB (uint32_t)1U /!< EXTI PORT B /
<>	156:95d6b41a828b	243	#define LL_SYSCFG_EXTI_PORTC (uint32_t)2U /!< EXTI PORT C /
<>	156:95d6b41a828b	244	#if defined(GPIOD_BASE)
<>	156:95d6b41a828b	245	#define LL_SYSCFG_EXTI_PORTD (uint32_t)3U /!< EXTI PORT D /
<>	156:95d6b41a828b	246	#endif /GPIOD_BASE/
<>	156:95d6b41a828b	247	#if defined(GPIOE_BASE)
<>	156:95d6b41a828b	248	#define LL_SYSCFG_EXTI_PORTE (uint32_t)4U /!< EXTI PORT E /
<>	156:95d6b41a828b	249	#endif /GPIOE_BASE/
<>	156:95d6b41a828b	250	#define LL_SYSCFG_EXTI_PORTF (uint32_t)5U /!< EXTI PORT F /
<>	156:95d6b41a828b	251	/**
<>	156:95d6b41a828b	252	* @}
<>	156:95d6b41a828b	253	*/
<>	156:95d6b41a828b	254
<>	156:95d6b41a828b	255	/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
<>	156:95d6b41a828b	256	* @{
<>	156:95d6b41a828b	257	*/
<>	156:95d6b41a828b	258	#define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0U << 16U \| 0U) /!< EXTI_POSITION_0 \| EXTICR[0] /
<>	156:95d6b41a828b	259	#define LL_SYSCFG_EXTI_LINE1 (uint32_t)(4U << 16U \| 0U) /!< EXTI_POSITION_4 \| EXTICR[0] /
<>	156:95d6b41a828b	260	#define LL_SYSCFG_EXTI_LINE2 (uint32_t)(8U << 16U \| 0U) /!< EXTI_POSITION_8 \| EXTICR[0] /
<>	156:95d6b41a828b	261	#define LL_SYSCFG_EXTI_LINE3 (uint32_t)(12U << 16U \| 0U) /!< EXTI_POSITION_12 \| EXTICR[0] /
<>	156:95d6b41a828b	262	#define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0U << 16U \| 1U) /!< EXTI_POSITION_0 \| EXTICR[1] /
<>	156:95d6b41a828b	263	#define LL_SYSCFG_EXTI_LINE5 (uint32_t)(4U << 16U \| 1U) /!< EXTI_POSITION_4 \| EXTICR[1] /
<>	156:95d6b41a828b	264	#define LL_SYSCFG_EXTI_LINE6 (uint32_t)(8U << 16U \| 1U) /!< EXTI_POSITION_8 \| EXTICR[1] /
<>	156:95d6b41a828b	265	#define LL_SYSCFG_EXTI_LINE7 (uint32_t)(12U << 16U \| 1U) /!< EXTI_POSITION_12 \| EXTICR[1] /
<>	156:95d6b41a828b	266	#define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0U << 16U \| 2U) /!< EXTI_POSITION_0 \| EXTICR[2] /
<>	156:95d6b41a828b	267	#define LL_SYSCFG_EXTI_LINE9 (uint32_t)(4U << 16U \| 2U) /!< EXTI_POSITION_4 \| EXTICR[2] /
<>	156:95d6b41a828b	268	#define LL_SYSCFG_EXTI_LINE10 (uint32_t)(8U << 16U \| 2U) /!< EXTI_POSITION_8 \| EXTICR[2] /
<>	156:95d6b41a828b	269	#define LL_SYSCFG_EXTI_LINE11 (uint32_t)(12U << 16U \| 2U) /!< EXTI_POSITION_12 \| EXTICR[2] /
<>	156:95d6b41a828b	270	#define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0U << 16U \| 3U) /!< EXTI_POSITION_0 \| EXTICR[3] /
<>	156:95d6b41a828b	271	#define LL_SYSCFG_EXTI_LINE13 (uint32_t)(4U << 16U \| 3U) /!< EXTI_POSITION_4 \| EXTICR[3] /
<>	156:95d6b41a828b	272	#define LL_SYSCFG_EXTI_LINE14 (uint32_t)(8U << 16U \| 3U) /!< EXTI_POSITION_8 \| EXTICR[3] /
<>	156:95d6b41a828b	273	#define LL_SYSCFG_EXTI_LINE15 (uint32_t)(12U << 16U \| 3U) /!< EXTI_POSITION_12 \| EXTICR[3] /
<>	156:95d6b41a828b	274	/**
<>	156:95d6b41a828b	275	* @}
<>	156:95d6b41a828b	276	*/
<>	156:95d6b41a828b	277
<>	156:95d6b41a828b	278	/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
<>	156:95d6b41a828b	279	* @{
<>	156:95d6b41a828b	280	*/
<>	156:95d6b41a828b	281	#if defined(SYSCFG_CFGR2_PVD_LOCK)
<>	156:95d6b41a828b	282	#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Enables and locks the PVD connection
<>	156:95d6b41a828b	283	with TIM1/15/16U/17 Break Input and also
<>	156:95d6b41a828b	284	the PVDE and PLS bits of the Power Control Interface */
<>	156:95d6b41a828b	285	#endif /SYSCFG_CFGR2_PVD_LOCK/
<>	156:95d6b41a828b	286	#define LL_SYSCFG_TIMBREAK_SRAM_PARITY SYSCFG_CFGR2_SRAM_PARITY_LOCK /*!< Enables and locks the SRAM_PARITY error signal
<>	156:95d6b41a828b	287	with Break Input of TIM1/15/16/17 */
<>	156:95d6b41a828b	288	#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_LOCKUP_LOCK /*!< Enables and locks the LOCKUP (Hardfault) output of
<>	156:95d6b41a828b	289	CortexM0 with Break Input of TIM1/15/16/17 */
<>	156:95d6b41a828b	290	/**
<>	156:95d6b41a828b	291	* @}
<>	156:95d6b41a828b	292	*/
<>	156:95d6b41a828b	293
<>	156:95d6b41a828b	294	/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
<>	156:95d6b41a828b	295	* @{
<>	156:95d6b41a828b	296	*/
<>	156:95d6b41a828b	297	#if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)
<>	156:95d6b41a828b	298	#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /!< TIM2 counter stopped when core is halted /
<>	156:95d6b41a828b	299	#endif /DBGMCU_APB1_FZ_DBG_TIM2_STOP/
<>	156:95d6b41a828b	300	#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /!< TIM3 counter stopped when core is halted /
<>	156:95d6b41a828b	301	#if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)
<>	156:95d6b41a828b	302	#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /!< TIM6 counter stopped when core is halted /
<>	156:95d6b41a828b	303	#endif /DBGMCU_APB1_FZ_DBG_TIM6_STOP/
<>	156:95d6b41a828b	304	#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
<>	156:95d6b41a828b	305	#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /!< TIM7 counter stopped when core is halted /
<>	156:95d6b41a828b	306	#endif /DBGMCU_APB1_FZ_DBG_TIM7_STOP/
<>	156:95d6b41a828b	307	#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP /!< TIM14 counter stopped when core is halted /
<>	156:95d6b41a828b	308	#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP /!< RTC Calendar frozen when core is halted /
<>	156:95d6b41a828b	309	#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP /!< Debug Window Watchdog stopped when Core is halted /
<>	156:95d6b41a828b	310	#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /!< Debug Independent Watchdog stopped when Core is halted /
<>	156:95d6b41a828b	311	#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /!< I2C1 SMBUS timeout mode stopped when Core is halted /
<>	156:95d6b41a828b	312	#if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP)
<>	156:95d6b41a828b	313	#define LL_DBGMCU_APB1_GRP1_CAN_STOP DBGMCU_APB1_FZ_DBG_CAN_STOP /!< CAN debug stopped when Core is halted /
<>	156:95d6b41a828b	314	#endif /DBGMCU_APB1_FZ_DBG_CAN_STOP/
<>	156:95d6b41a828b	315	/**
<>	156:95d6b41a828b	316	* @}
<>	156:95d6b41a828b	317	*/
<>	156:95d6b41a828b	318
<>	156:95d6b41a828b	319	/** @defgroup SYSTEM_LL_EC_APB1 GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP
<>	156:95d6b41a828b	320	* @{
<>	156:95d6b41a828b	321	*/
<>	156:95d6b41a828b	322	#define LL_DBGMCU_APB1_GRP2_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP /!< TIM1 counter stopped when core is halted /
<>	156:95d6b41a828b	323	#if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP)
<>	156:95d6b41a828b	324	#define LL_DBGMCU_APB1_GRP2_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP /!< TIM15 counter stopped when core is halted /
<>	156:95d6b41a828b	325	#endif /DBGMCU_APB2_FZ_DBG_TIM15_STOP/
<>	156:95d6b41a828b	326	#define LL_DBGMCU_APB1_GRP2_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP /!< TIM16 counter stopped when core is halted /
<>	156:95d6b41a828b	327	#define LL_DBGMCU_APB1_GRP2_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP /!< TIM17 counter stopped when core is halted /
<>	156:95d6b41a828b	328	/**
<>	156:95d6b41a828b	329	* @}
<>	156:95d6b41a828b	330	*/
<>	156:95d6b41a828b	331
<>	156:95d6b41a828b	332	/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
<>	156:95d6b41a828b	333	* @{
<>	156:95d6b41a828b	334	*/
Anna Bridge	180:96ed750bd169	335	#define LL_FLASH_LATENCY_0 0x00000000U /!< FLASH Zero Latency cycle /
<>	156:95d6b41a828b	336	#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY /!< FLASH One Latency cycle /
<>	156:95d6b41a828b	337	/**
<>	156:95d6b41a828b	338	* @}
<>	156:95d6b41a828b	339	*/
<>	156:95d6b41a828b	340
<>	156:95d6b41a828b	341	/**
<>	156:95d6b41a828b	342	* @}
<>	156:95d6b41a828b	343	*/
<>	156:95d6b41a828b	344
<>	156:95d6b41a828b	345	/* Exported macro ------------------------------------------------------------*/
<>	156:95d6b41a828b	346
<>	156:95d6b41a828b	347	/* Exported functions --------------------------------------------------------*/
<>	156:95d6b41a828b	348	/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
<>	156:95d6b41a828b	349	* @{
<>	156:95d6b41a828b	350	*/
<>	156:95d6b41a828b	351
<>	156:95d6b41a828b	352	/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
<>	156:95d6b41a828b	353	* @{
<>	156:95d6b41a828b	354	*/
<>	156:95d6b41a828b	355
<>	156:95d6b41a828b	356	/**
<>	156:95d6b41a828b	357	* @brief Set memory mapping at address 0x00000000
<>	156:95d6b41a828b	358	* @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_SetRemapMemory
<>	156:95d6b41a828b	359	* @param Memory This parameter can be one of the following values:
<>	156:95d6b41a828b	360	* @arg @ref LL_SYSCFG_REMAP_FLASH
<>	156:95d6b41a828b	361	* @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
<>	156:95d6b41a828b	362	* @arg @ref LL_SYSCFG_REMAP_SRAM
<>	156:95d6b41a828b	363	* @retval None
<>	156:95d6b41a828b	364	*/
<>	156:95d6b41a828b	365	__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
<>	156:95d6b41a828b	366	{
<>	156:95d6b41a828b	367	MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, Memory);
<>	156:95d6b41a828b	368	}
<>	156:95d6b41a828b	369
<>	156:95d6b41a828b	370	/**
<>	156:95d6b41a828b	371	* @brief Get memory mapping at address 0x00000000
<>	156:95d6b41a828b	372	* @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_GetRemapMemory
<>	156:95d6b41a828b	373	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	374	* @arg @ref LL_SYSCFG_REMAP_FLASH
<>	156:95d6b41a828b	375	* @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
<>	156:95d6b41a828b	376	* @arg @ref LL_SYSCFG_REMAP_SRAM
<>	156:95d6b41a828b	377	*/
<>	156:95d6b41a828b	378	__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
<>	156:95d6b41a828b	379	{
<>	156:95d6b41a828b	380	return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE));
<>	156:95d6b41a828b	381	}
<>	156:95d6b41a828b	382
<>	156:95d6b41a828b	383	#if defined(SYSCFG_CFGR1_IR_MOD)
<>	156:95d6b41a828b	384	/**
<>	156:95d6b41a828b	385	* @brief Set IR Modulation Envelope signal source.
<>	156:95d6b41a828b	386	* @rmtoll SYSCFG_CFGR1 IR_MOD LL_SYSCFG_SetIRModEnvelopeSignal
<>	156:95d6b41a828b	387	* @param Source This parameter can be one of the following values:
<>	156:95d6b41a828b	388	* @arg @ref LL_SYSCFG_IR_MOD_TIM16
<>	156:95d6b41a828b	389	* @arg @ref LL_SYSCFG_IR_MOD_USART1
<>	156:95d6b41a828b	390	* @arg @ref LL_SYSCFG_IR_MOD_USART4
<>	156:95d6b41a828b	391	* @retval None
<>	156:95d6b41a828b	392	*/
<>	156:95d6b41a828b	393	__STATIC_INLINE void LL_SYSCFG_SetIRModEnvelopeSignal(uint32_t Source)
<>	156:95d6b41a828b	394	{
<>	156:95d6b41a828b	395	MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD, Source);
<>	156:95d6b41a828b	396	}
<>	156:95d6b41a828b	397
<>	156:95d6b41a828b	398	/**
<>	156:95d6b41a828b	399	* @brief Get IR Modulation Envelope signal source.
<>	156:95d6b41a828b	400	* @rmtoll SYSCFG_CFGR1 IR_MOD LL_SYSCFG_GetIRModEnvelopeSignal
<>	156:95d6b41a828b	401	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	402	* @arg @ref LL_SYSCFG_IR_MOD_TIM16
<>	156:95d6b41a828b	403	* @arg @ref LL_SYSCFG_IR_MOD_USART1
<>	156:95d6b41a828b	404	* @arg @ref LL_SYSCFG_IR_MOD_USART4
<>	156:95d6b41a828b	405	*/
<>	156:95d6b41a828b	406	__STATIC_INLINE uint32_t LL_SYSCFG_GetIRModEnvelopeSignal(void)
<>	156:95d6b41a828b	407	{
<>	156:95d6b41a828b	408	return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD));
<>	156:95d6b41a828b	409	}
<>	156:95d6b41a828b	410	#endif /* SYSCFG_CFGR1_IR_MOD */
<>	156:95d6b41a828b	411
<>	156:95d6b41a828b	412	#if defined(SYSCFG_CFGR1_USART1TX_DMA_RMP) \|\| defined(SYSCFG_CFGR1_USART1RX_DMA_RMP) \|\| defined(SYSCFG_CFGR1_USART2_DMA_RMP) \|\| defined(SYSCFG_CFGR1_USART3_DMA_RMP)
<>	156:95d6b41a828b	413	/**
<>	156:95d6b41a828b	414	* @brief Set DMA request remapping bits for USART
<>	156:95d6b41a828b	415	* @rmtoll SYSCFG_CFGR1 USART1TX_DMA_RMP LL_SYSCFG_SetRemapDMA_USART\n
<>	156:95d6b41a828b	416	* SYSCFG_CFGR1 USART1RX_DMA_RMP LL_SYSCFG_SetRemapDMA_USART\n
<>	156:95d6b41a828b	417	* SYSCFG_CFGR1 USART2_DMA_RMP LL_SYSCFG_SetRemapDMA_USART\n
<>	156:95d6b41a828b	418	* SYSCFG_CFGR1 USART3_DMA_RMP LL_SYSCFG_SetRemapDMA_USART
<>	156:95d6b41a828b	419	* @param Remap This parameter can be one of the following values:
<>	156:95d6b41a828b	420	* @arg @ref LL_SYSCFG_USART1TX_RMP_DMA1CH2 (*)
<>	156:95d6b41a828b	421	* @arg @ref LL_SYSCFG_USART1TX_RMP_DMA1CH4 (*)
<>	156:95d6b41a828b	422	* @arg @ref LL_SYSCFG_USART1RX_RMP_DMA1CH3 (*)
<>	156:95d6b41a828b	423	* @arg @ref LL_SYSCFG_USART1RX_RMP_DMA1CH5 (*)
<>	156:95d6b41a828b	424	* @arg @ref LL_SYSCFG_USART2_RMP_DMA1CH54 (*)
<>	156:95d6b41a828b	425	* @arg @ref LL_SYSCFG_USART2_RMP_DMA1CH67 (*)
<>	156:95d6b41a828b	426	* @arg @ref LL_SYSCFG_USART3_RMP_DMA1CH67 (*)
<>	156:95d6b41a828b	427	* @arg @ref LL_SYSCFG_USART3_RMP_DMA1CH32 (*)
<>	156:95d6b41a828b	428	*
<>	156:95d6b41a828b	429	* (*) value not defined in all devices.
<>	156:95d6b41a828b	430	* @retval None
<>	156:95d6b41a828b	431	*/
<>	156:95d6b41a828b	432	__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_USART(uint32_t Remap)
<>	156:95d6b41a828b	433	{
<>	156:95d6b41a828b	434	MODIFY_REG(SYSCFG->CFGR1, (Remap & 0x00FF00FFU) << 8U, (Remap & 0xFF00FF00U));
<>	156:95d6b41a828b	435	}
<>	156:95d6b41a828b	436	#endif /* SYSCFG_CFGR1_USART1TX_DMA_RMP \|\| SYSCFG_CFGR1_USART1RX_DMA_RMP \|\| SYSCFG_CFGR1_USART2_DMA_RMP \|\| SYSCFG_CFGR1_USART3_DMA_RMP */
<>	156:95d6b41a828b	437
<>	156:95d6b41a828b	438	#if defined(SYSCFG_CFGR1_SPI2_DMA_RMP)
<>	156:95d6b41a828b	439	/**
<>	156:95d6b41a828b	440	* @brief Set DMA request remapping bits for SPI
<>	156:95d6b41a828b	441	* @rmtoll SYSCFG_CFGR1 SPI2_DMA_RMP LL_SYSCFG_SetRemapDMA_SPI
<>	156:95d6b41a828b	442	* @param Remap This parameter can be one of the following values:
<>	156:95d6b41a828b	443	* @arg @ref LL_SYSCFG_SPI2_RMP_DMA1_CH45
<>	156:95d6b41a828b	444	* @arg @ref LL_SYSCFG_SPI2_RMP_DMA1_CH67
<>	156:95d6b41a828b	445	* @retval None
<>	156:95d6b41a828b	446	*/
<>	156:95d6b41a828b	447	__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_SPI(uint32_t Remap)
<>	156:95d6b41a828b	448	{
<>	156:95d6b41a828b	449	MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_SPI2_DMA_RMP, Remap);
<>	156:95d6b41a828b	450	}
<>	156:95d6b41a828b	451	#endif /* SYSCFG_CFGR1_SPI2_DMA_RMP */
<>	156:95d6b41a828b	452
<>	156:95d6b41a828b	453	#if defined(SYSCFG_CFGR1_I2C1_DMA_RMP)
<>	156:95d6b41a828b	454	/**
<>	156:95d6b41a828b	455	* @brief Set DMA request remapping bits for I2C
<>	156:95d6b41a828b	456	* @rmtoll SYSCFG_CFGR1 I2C1_DMA_RMP LL_SYSCFG_SetRemapDMA_I2C
<>	156:95d6b41a828b	457	* @param Remap This parameter can be one of the following values:
<>	156:95d6b41a828b	458	* @arg @ref LL_SYSCFG_I2C1_RMP_DMA1_CH32
<>	156:95d6b41a828b	459	* @arg @ref LL_SYSCFG_I2C1_RMP_DMA1_CH76
<>	156:95d6b41a828b	460	* @retval None
<>	156:95d6b41a828b	461	*/
<>	156:95d6b41a828b	462	__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_I2C(uint32_t Remap)
<>	156:95d6b41a828b	463	{
<>	156:95d6b41a828b	464	MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_I2C1_DMA_RMP, Remap);
<>	156:95d6b41a828b	465	}
<>	156:95d6b41a828b	466	#endif /* SYSCFG_CFGR1_I2C1_DMA_RMP */
<>	156:95d6b41a828b	467
<>	156:95d6b41a828b	468	#if defined(SYSCFG_CFGR1_ADC_DMA_RMP)
<>	156:95d6b41a828b	469	/**
<>	156:95d6b41a828b	470	* @brief Set DMA request remapping bits for ADC
<>	156:95d6b41a828b	471	* @rmtoll SYSCFG_CFGR1 ADC_DMA_RMP LL_SYSCFG_SetRemapDMA_ADC
<>	156:95d6b41a828b	472	* @param Remap This parameter can be one of the following values:
<>	156:95d6b41a828b	473	* @arg @ref LL_SYSCFG_ADC1_RMP_DMA1_CH1
<>	156:95d6b41a828b	474	* @arg @ref LL_SYSCFG_ADC1_RMP_DMA1_CH2
<>	156:95d6b41a828b	475	* @retval None
<>	156:95d6b41a828b	476	*/
<>	156:95d6b41a828b	477	__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_ADC(uint32_t Remap)
<>	156:95d6b41a828b	478	{
<>	156:95d6b41a828b	479	MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_ADC_DMA_RMP, Remap);
<>	156:95d6b41a828b	480	}
<>	156:95d6b41a828b	481	#endif /* SYSCFG_CFGR1_ADC_DMA_RMP */
<>	156:95d6b41a828b	482
<>	156:95d6b41a828b	483	#if defined(SYSCFG_CFGR1_TIM16_DMA_RMP) \|\| defined(SYSCFG_CFGR1_TIM17_DMA_RMP) \|\| defined(SYSCFG_CFGR1_TIM1_DMA_RMP) \|\| defined(SYSCFG_CFGR1_TIM2_DMA_RMP) \|\| defined(SYSCFG_CFGR1_TIM3_DMA_RMP)
<>	156:95d6b41a828b	484	/**
<>	156:95d6b41a828b	485	* @brief Set DMA request remapping bits for TIM
<>	156:95d6b41a828b	486	* @rmtoll SYSCFG_CFGR1 TIM16_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
<>	156:95d6b41a828b	487	* SYSCFG_CFGR1 TIM17_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
<>	156:95d6b41a828b	488	* SYSCFG_CFGR1 TIM16_DMA_RMP2 LL_SYSCFG_SetRemapDMA_TIM\n
<>	156:95d6b41a828b	489	* SYSCFG_CFGR1 TIM17_DMA_RMP2 LL_SYSCFG_SetRemapDMA_TIM\n
<>	156:95d6b41a828b	490	* SYSCFG_CFGR1 TIM1_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
<>	156:95d6b41a828b	491	* SYSCFG_CFGR1 TIM2_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
<>	156:95d6b41a828b	492	* SYSCFG_CFGR1 TIM3_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM
<>	156:95d6b41a828b	493	* @param Remap This parameter can be one of the following values:
<>	156:95d6b41a828b	494	* @arg @ref LL_SYSCFG_TIM16_RMP_DMA1_CH3 (*)
<>	156:95d6b41a828b	495	* @arg @ref LL_SYSCFG_TIM16_RMP_DMA1_CH4 (*)
<>	156:95d6b41a828b	496	* @arg @ref LL_SYSCFG_TIM16_RMP_DMA1_CH6 (*)
<>	156:95d6b41a828b	497	* @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH1 (*)
<>	156:95d6b41a828b	498	* @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH2 (*)
<>	156:95d6b41a828b	499	* @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH7 (*)
<>	156:95d6b41a828b	500	* @arg @ref LL_SYSCFG_TIM1_RMP_DMA1_CH234 (*)
<>	156:95d6b41a828b	501	* @arg @ref LL_SYSCFG_TIM1_RMP_DMA1_CH6 (*)
<>	156:95d6b41a828b	502	* @arg @ref LL_SYSCFG_TIM2_RMP_DMA1_CH34 (*)
<>	156:95d6b41a828b	503	* @arg @ref LL_SYSCFG_TIM2_RMP_DMA1_CH7 (*)
<>	156:95d6b41a828b	504	* @arg @ref LL_SYSCFG_TIM3_RMP_DMA1_CH4 (*)
<>	156:95d6b41a828b	505	* @arg @ref LL_SYSCFG_TIM3_RMP_DMA1_CH6 (*)
<>	156:95d6b41a828b	506	*
<>	156:95d6b41a828b	507	* (*) value not defined in all devices.
<>	156:95d6b41a828b	508	* @retval None
<>	156:95d6b41a828b	509	*/
<>	156:95d6b41a828b	510	__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_TIM(uint32_t Remap)
<>	156:95d6b41a828b	511	{
<>	156:95d6b41a828b	512	MODIFY_REG(SYSCFG->CFGR1, (Remap & 0x00FF00FFU) << 8U, (Remap & 0xFF00FF00U));
<>	156:95d6b41a828b	513	}
<>	156:95d6b41a828b	514	#endif /* SYSCFG_CFGR1_TIM16_DMA_RMP \|\| SYSCFG_CFGR1_TIM17_DMA_RMP \|\| SYSCFG_CFGR1_TIM1_DMA_RMP \|\| SYSCFG_CFGR1_TIM2_DMA_RMP \|\| SYSCFG_CFGR1_TIM3_DMA_RMP */
<>	156:95d6b41a828b	515
<>	156:95d6b41a828b	516	#if defined(SYSCFG_CFGR1_PA11_PA12_RMP)
<>	156:95d6b41a828b	517	/**
<>	156:95d6b41a828b	518	* @brief Enable PIN pair PA11/12 mapped instead of PA9/10 (control the mapping of either
<>	156:95d6b41a828b	519	* PA9/10 or PA11/12 pin pair on small pin-count packages)
<>	156:95d6b41a828b	520	* @rmtoll SYSCFG_CFGR1 PA11_PA12_RMP LL_SYSCFG_EnablePinRemap
<>	156:95d6b41a828b	521	* @retval None
<>	156:95d6b41a828b	522	*/
<>	156:95d6b41a828b	523	__STATIC_INLINE void LL_SYSCFG_EnablePinRemap(void)
<>	156:95d6b41a828b	524	{
<>	156:95d6b41a828b	525	SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_PA11_PA12_RMP);
<>	156:95d6b41a828b	526	}
<>	156:95d6b41a828b	527
<>	156:95d6b41a828b	528	/**
<>	156:95d6b41a828b	529	* @brief Disable PIN pair PA11/12 mapped instead of PA9/10 (control the mapping of either
<>	156:95d6b41a828b	530	* PA9/10 or PA11/12 pin pair on small pin-count packages)
<>	156:95d6b41a828b	531	* @rmtoll SYSCFG_CFGR1 PA11_PA12_RMP LL_SYSCFG_DisablePinRemap
<>	156:95d6b41a828b	532	* @retval None
<>	156:95d6b41a828b	533	*/
<>	156:95d6b41a828b	534	__STATIC_INLINE void LL_SYSCFG_DisablePinRemap(void)
<>	156:95d6b41a828b	535	{
<>	156:95d6b41a828b	536	CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_PA11_PA12_RMP);
<>	156:95d6b41a828b	537	}
<>	156:95d6b41a828b	538	#endif /* SYSCFG_CFGR1_PA11_PA12_RMP */
<>	156:95d6b41a828b	539
<>	156:95d6b41a828b	540	/**
<>	156:95d6b41a828b	541	* @brief Enable the I2C fast mode plus driving capability.
<>	156:95d6b41a828b	542	* @rmtoll SYSCFG_CFGR1 I2C_FMP_PB6 LL_SYSCFG_EnableFastModePlus\n
<>	156:95d6b41a828b	543	* SYSCFG_CFGR1 I2C_FMP_PB7 LL_SYSCFG_EnableFastModePlus\n
<>	156:95d6b41a828b	544	* SYSCFG_CFGR1 I2C_FMP_PB8 LL_SYSCFG_EnableFastModePlus\n
<>	156:95d6b41a828b	545	* SYSCFG_CFGR1 I2C_FMP_PB9 LL_SYSCFG_EnableFastModePlus\n
<>	156:95d6b41a828b	546	* SYSCFG_CFGR1 I2C_FMP_I2C1 LL_SYSCFG_EnableFastModePlus\n
<>	156:95d6b41a828b	547	* SYSCFG_CFGR1 I2C_FMP_I2C2 LL_SYSCFG_EnableFastModePlus\n
<>	156:95d6b41a828b	548	* SYSCFG_CFGR1 I2C_FMP_PA9 LL_SYSCFG_EnableFastModePlus\n
<>	156:95d6b41a828b	549	* SYSCFG_CFGR1 I2C_FMP_PA10 LL_SYSCFG_EnableFastModePlus
<>	156:95d6b41a828b	550	* @param ConfigFastModePlus This parameter can be a combination of the following values:
<>	156:95d6b41a828b	551	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
<>	156:95d6b41a828b	552	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
<>	156:95d6b41a828b	553	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
<>	156:95d6b41a828b	554	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
<>	156:95d6b41a828b	555	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 (*)
<>	156:95d6b41a828b	556	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
<>	156:95d6b41a828b	557	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA9 (*)
<>	156:95d6b41a828b	558	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA10 (*)
<>	156:95d6b41a828b	559	*
<>	156:95d6b41a828b	560	* (*) value not defined in all devices
<>	156:95d6b41a828b	561	* @retval None
<>	156:95d6b41a828b	562	*/
<>	156:95d6b41a828b	563	__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
<>	156:95d6b41a828b	564	{
<>	156:95d6b41a828b	565	SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
<>	156:95d6b41a828b	566	}
<>	156:95d6b41a828b	567
<>	156:95d6b41a828b	568	/**
<>	156:95d6b41a828b	569	* @brief Disable the I2C fast mode plus driving capability.
<>	156:95d6b41a828b	570	* @rmtoll SYSCFG_CFGR1 I2C_FMP_PB6 LL_SYSCFG_DisableFastModePlus\n
<>	156:95d6b41a828b	571	* SYSCFG_CFGR1 I2C_FMP_PB7 LL_SYSCFG_DisableFastModePlus\n
<>	156:95d6b41a828b	572	* SYSCFG_CFGR1 I2C_FMP_PB8 LL_SYSCFG_DisableFastModePlus\n
<>	156:95d6b41a828b	573	* SYSCFG_CFGR1 I2C_FMP_PB9 LL_SYSCFG_DisableFastModePlus\n
<>	156:95d6b41a828b	574	* SYSCFG_CFGR1 I2C_FMP_I2C1 LL_SYSCFG_DisableFastModePlus\n
<>	156:95d6b41a828b	575	* SYSCFG_CFGR1 I2C_FMP_I2C2 LL_SYSCFG_DisableFastModePlus\n
<>	156:95d6b41a828b	576	* SYSCFG_CFGR1 I2C_FMP_PA9 LL_SYSCFG_DisableFastModePlus\n
<>	156:95d6b41a828b	577	* SYSCFG_CFGR1 I2C_FMP_PA10 LL_SYSCFG_DisableFastModePlus
<>	156:95d6b41a828b	578	* @param ConfigFastModePlus This parameter can be a combination of the following values:
<>	156:95d6b41a828b	579	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
<>	156:95d6b41a828b	580	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
<>	156:95d6b41a828b	581	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
<>	156:95d6b41a828b	582	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
<>	156:95d6b41a828b	583	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 (*)
<>	156:95d6b41a828b	584	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
<>	156:95d6b41a828b	585	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA9 (*)
<>	156:95d6b41a828b	586	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA10 (*)
<>	156:95d6b41a828b	587	*
<>	156:95d6b41a828b	588	* (*) value not defined in all devices
<>	156:95d6b41a828b	589	* @retval None
<>	156:95d6b41a828b	590	*/
<>	156:95d6b41a828b	591	__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
<>	156:95d6b41a828b	592	{
<>	156:95d6b41a828b	593	CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
<>	156:95d6b41a828b	594	}
<>	156:95d6b41a828b	595
<>	156:95d6b41a828b	596	/**
<>	156:95d6b41a828b	597	* @brief Configure source input for the EXTI external interrupt.
<>	156:95d6b41a828b	598	* @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_SetEXTISource\n
<>	156:95d6b41a828b	599	* SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_SetEXTISource\n
<>	156:95d6b41a828b	600	* SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_SetEXTISource\n
<>	156:95d6b41a828b	601	* SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_SetEXTISource\n
<>	156:95d6b41a828b	602	* SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_SetEXTISource\n
<>	156:95d6b41a828b	603	* SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_SetEXTISource\n
<>	156:95d6b41a828b	604	* SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_SetEXTISource\n
<>	156:95d6b41a828b	605	* SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_SetEXTISource\n
<>	156:95d6b41a828b	606	* SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_SetEXTISource\n
<>	156:95d6b41a828b	607	* SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_SetEXTISource\n
<>	156:95d6b41a828b	608	* SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_SetEXTISource\n
<>	156:95d6b41a828b	609	* SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_SetEXTISource\n
<>	156:95d6b41a828b	610	* SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_SetEXTISource\n
<>	156:95d6b41a828b	611	* SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_SetEXTISource\n
<>	156:95d6b41a828b	612	* SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_SetEXTISource\n
<>	156:95d6b41a828b	613	* SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_SetEXTISource
<>	156:95d6b41a828b	614	* @param Port This parameter can be one of the following values:
<>	156:95d6b41a828b	615	* @arg @ref LL_SYSCFG_EXTI_PORTA
<>	156:95d6b41a828b	616	* @arg @ref LL_SYSCFG_EXTI_PORTB
<>	156:95d6b41a828b	617	* @arg @ref LL_SYSCFG_EXTI_PORTC
<>	156:95d6b41a828b	618	* @arg @ref LL_SYSCFG_EXTI_PORTD (*)
<>	156:95d6b41a828b	619	* @arg @ref LL_SYSCFG_EXTI_PORTE (*)
<>	156:95d6b41a828b	620	* @arg @ref LL_SYSCFG_EXTI_PORTF
<>	156:95d6b41a828b	621	*
<>	156:95d6b41a828b	622	* (*) value not defined in all devices
<>	156:95d6b41a828b	623	* @param Line This parameter can be one of the following values:
<>	156:95d6b41a828b	624	* @arg @ref LL_SYSCFG_EXTI_LINE0
<>	156:95d6b41a828b	625	* @arg @ref LL_SYSCFG_EXTI_LINE1
<>	156:95d6b41a828b	626	* @arg @ref LL_SYSCFG_EXTI_LINE2
<>	156:95d6b41a828b	627	* @arg @ref LL_SYSCFG_EXTI_LINE3
<>	156:95d6b41a828b	628	* @arg @ref LL_SYSCFG_EXTI_LINE4
<>	156:95d6b41a828b	629	* @arg @ref LL_SYSCFG_EXTI_LINE5
<>	156:95d6b41a828b	630	* @arg @ref LL_SYSCFG_EXTI_LINE6
<>	156:95d6b41a828b	631	* @arg @ref LL_SYSCFG_EXTI_LINE7
<>	156:95d6b41a828b	632	* @arg @ref LL_SYSCFG_EXTI_LINE8
<>	156:95d6b41a828b	633	* @arg @ref LL_SYSCFG_EXTI_LINE9
<>	156:95d6b41a828b	634	* @arg @ref LL_SYSCFG_EXTI_LINE10
<>	156:95d6b41a828b	635	* @arg @ref LL_SYSCFG_EXTI_LINE11
<>	156:95d6b41a828b	636	* @arg @ref LL_SYSCFG_EXTI_LINE12
<>	156:95d6b41a828b	637	* @arg @ref LL_SYSCFG_EXTI_LINE13
<>	156:95d6b41a828b	638	* @arg @ref LL_SYSCFG_EXTI_LINE14
<>	156:95d6b41a828b	639	* @arg @ref LL_SYSCFG_EXTI_LINE15
<>	156:95d6b41a828b	640	* @retval None
<>	156:95d6b41a828b	641	*/
<>	156:95d6b41a828b	642	__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
<>	156:95d6b41a828b	643	{
<>	156:95d6b41a828b	644	MODIFY_REG(SYSCFG->EXTICR[Line & 0xFF], SYSCFG_EXTICR1_EXTI0 << (Line >> 16), Port << (Line >> 16));
<>	156:95d6b41a828b	645	}
<>	156:95d6b41a828b	646
<>	156:95d6b41a828b	647	/**
<>	156:95d6b41a828b	648	* @brief Get the configured defined for specific EXTI Line
<>	156:95d6b41a828b	649	* @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_SetEXTISource\n
<>	156:95d6b41a828b	650	* SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_SetEXTISource\n
<>	156:95d6b41a828b	651	* SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_SetEXTISource\n
<>	156:95d6b41a828b	652	* SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_SetEXTISource\n
<>	156:95d6b41a828b	653	* SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_SetEXTISource\n
<>	156:95d6b41a828b	654	* SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_SetEXTISource\n
<>	156:95d6b41a828b	655	* SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_SetEXTISource\n
<>	156:95d6b41a828b	656	* SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_SetEXTISource\n
<>	156:95d6b41a828b	657	* SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_SetEXTISource\n
<>	156:95d6b41a828b	658	* SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_SetEXTISource\n
<>	156:95d6b41a828b	659	* SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_SetEXTISource\n
<>	156:95d6b41a828b	660	* SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_SetEXTISource\n
<>	156:95d6b41a828b	661	* SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_SetEXTISource\n
<>	156:95d6b41a828b	662	* SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_SetEXTISource\n
<>	156:95d6b41a828b	663	* SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_SetEXTISource\n
<>	156:95d6b41a828b	664	* SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_SetEXTISource
<>	156:95d6b41a828b	665	* @param Line This parameter can be one of the following values:
<>	156:95d6b41a828b	666	* @arg @ref LL_SYSCFG_EXTI_LINE0
<>	156:95d6b41a828b	667	* @arg @ref LL_SYSCFG_EXTI_LINE1
<>	156:95d6b41a828b	668	* @arg @ref LL_SYSCFG_EXTI_LINE2
<>	156:95d6b41a828b	669	* @arg @ref LL_SYSCFG_EXTI_LINE3
<>	156:95d6b41a828b	670	* @arg @ref LL_SYSCFG_EXTI_LINE4
<>	156:95d6b41a828b	671	* @arg @ref LL_SYSCFG_EXTI_LINE5
<>	156:95d6b41a828b	672	* @arg @ref LL_SYSCFG_EXTI_LINE6
<>	156:95d6b41a828b	673	* @arg @ref LL_SYSCFG_EXTI_LINE7
<>	156:95d6b41a828b	674	* @arg @ref LL_SYSCFG_EXTI_LINE8
<>	156:95d6b41a828b	675	* @arg @ref LL_SYSCFG_EXTI_LINE9
<>	156:95d6b41a828b	676	* @arg @ref LL_SYSCFG_EXTI_LINE10
<>	156:95d6b41a828b	677	* @arg @ref LL_SYSCFG_EXTI_LINE11
<>	156:95d6b41a828b	678	* @arg @ref LL_SYSCFG_EXTI_LINE12
<>	156:95d6b41a828b	679	* @arg @ref LL_SYSCFG_EXTI_LINE13
<>	156:95d6b41a828b	680	* @arg @ref LL_SYSCFG_EXTI_LINE14
<>	156:95d6b41a828b	681	* @arg @ref LL_SYSCFG_EXTI_LINE15
<>	156:95d6b41a828b	682	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	683	* @arg @ref LL_SYSCFG_EXTI_PORTA
<>	156:95d6b41a828b	684	* @arg @ref LL_SYSCFG_EXTI_PORTB
<>	156:95d6b41a828b	685	* @arg @ref LL_SYSCFG_EXTI_PORTC
<>	156:95d6b41a828b	686	* @arg @ref LL_SYSCFG_EXTI_PORTD (*)
<>	156:95d6b41a828b	687	* @arg @ref LL_SYSCFG_EXTI_PORTE (*)
<>	156:95d6b41a828b	688	* @arg @ref LL_SYSCFG_EXTI_PORTF
<>	156:95d6b41a828b	689	*
<>	156:95d6b41a828b	690	* (*) value not defined in all devices
<>	156:95d6b41a828b	691	*/
<>	156:95d6b41a828b	692	__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
<>	156:95d6b41a828b	693	{
<>	156:95d6b41a828b	694	return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFF], (SYSCFG_EXTICR1_EXTI0 << (Line >> 16))) >> (Line >> 16));
<>	156:95d6b41a828b	695	}
<>	156:95d6b41a828b	696
<>	156:95d6b41a828b	697	#if defined(SYSCFG_ITLINE0_SR_EWDG)
<>	156:95d6b41a828b	698	/**
<>	156:95d6b41a828b	699	* @brief Check if Window watchdog interrupt occurred or not.
<>	156:95d6b41a828b	700	* @rmtoll SYSCFG_ITLINE0 SR_EWDG LL_SYSCFG_IsActiveFlag_WWDG
<>	156:95d6b41a828b	701	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	702	*/
<>	156:95d6b41a828b	703	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_WWDG(void)
<>	156:95d6b41a828b	704	{
<>	156:95d6b41a828b	705	return (READ_BIT(SYSCFG->IT_LINE_SR[0], SYSCFG_ITLINE0_SR_EWDG) == (SYSCFG_ITLINE0_SR_EWDG));
<>	156:95d6b41a828b	706	}
<>	156:95d6b41a828b	707	#endif /* SYSCFG_ITLINE0_SR_EWDG */
<>	156:95d6b41a828b	708
<>	156:95d6b41a828b	709	#if defined(SYSCFG_ITLINE1_SR_PVDOUT)
<>	156:95d6b41a828b	710	/**
<>	156:95d6b41a828b	711	* @brief Check if PVD supply monitoring interrupt occurred or not (EXTI line 16).
<>	156:95d6b41a828b	712	* @rmtoll SYSCFG_ITLINE1 SR_PVDOUT LL_SYSCFG_IsActiveFlag_PVDOUT
<>	156:95d6b41a828b	713	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	714	*/
<>	156:95d6b41a828b	715	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_PVDOUT(void)
<>	156:95d6b41a828b	716	{
<>	156:95d6b41a828b	717	return (READ_BIT(SYSCFG->IT_LINE_SR[1], SYSCFG_ITLINE1_SR_PVDOUT) == (SYSCFG_ITLINE1_SR_PVDOUT));
<>	156:95d6b41a828b	718	}
<>	156:95d6b41a828b	719	#endif /* SYSCFG_ITLINE1_SR_PVDOUT */
<>	156:95d6b41a828b	720
<>	156:95d6b41a828b	721	#if defined(SYSCFG_ITLINE1_SR_VDDIO2)
<>	156:95d6b41a828b	722	/**
<>	156:95d6b41a828b	723	* @brief Check if VDDIO2 supply monitoring interrupt occurred or not (EXTI line 31).
<>	156:95d6b41a828b	724	* @rmtoll SYSCFG_ITLINE1 SR_VDDIO2 LL_SYSCFG_IsActiveFlag_VDDIO2
<>	156:95d6b41a828b	725	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	726	*/
<>	156:95d6b41a828b	727	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VDDIO2(void)
<>	156:95d6b41a828b	728	{
<>	156:95d6b41a828b	729	return (READ_BIT(SYSCFG->IT_LINE_SR[1], SYSCFG_ITLINE1_SR_VDDIO2) == (SYSCFG_ITLINE1_SR_VDDIO2));
<>	156:95d6b41a828b	730	}
<>	156:95d6b41a828b	731	#endif /* SYSCFG_ITLINE1_SR_VDDIO2 */
<>	156:95d6b41a828b	732
<>	156:95d6b41a828b	733	#if defined(SYSCFG_ITLINE2_SR_RTC_WAKEUP)
<>	156:95d6b41a828b	734	/**
<>	156:95d6b41a828b	735	* @brief Check if RTC Wake Up interrupt occurred or not (EXTI line 20).
<>	156:95d6b41a828b	736	* @rmtoll SYSCFG_ITLINE2 SR_RTC_WAKEUP LL_SYSCFG_IsActiveFlag_RTC_WAKEUP
<>	156:95d6b41a828b	737	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	738	*/
<>	156:95d6b41a828b	739	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RTC_WAKEUP(void)
<>	156:95d6b41a828b	740	{
<>	156:95d6b41a828b	741	return (READ_BIT(SYSCFG->IT_LINE_SR[2], SYSCFG_ITLINE2_SR_RTC_WAKEUP) == (SYSCFG_ITLINE2_SR_RTC_WAKEUP));
<>	156:95d6b41a828b	742	}
<>	156:95d6b41a828b	743	#endif /* SYSCFG_ITLINE2_SR_RTC_WAKEUP */
<>	156:95d6b41a828b	744
<>	156:95d6b41a828b	745	#if defined(SYSCFG_ITLINE2_SR_RTC_TSTAMP)
<>	156:95d6b41a828b	746	/**
<>	156:95d6b41a828b	747	* @brief Check if RTC Tamper and TimeStamp interrupt occurred or not (EXTI line 19).
<>	156:95d6b41a828b	748	* @rmtoll SYSCFG_ITLINE2 SR_RTC_TSTAMP LL_SYSCFG_IsActiveFlag_RTC_TSTAMP
<>	156:95d6b41a828b	749	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	750	*/
<>	156:95d6b41a828b	751	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RTC_TSTAMP(void)
<>	156:95d6b41a828b	752	{
<>	156:95d6b41a828b	753	return (READ_BIT(SYSCFG->IT_LINE_SR[2], SYSCFG_ITLINE2_SR_RTC_TSTAMP) == (SYSCFG_ITLINE2_SR_RTC_TSTAMP));
<>	156:95d6b41a828b	754	}
<>	156:95d6b41a828b	755	#endif /* SYSCFG_ITLINE2_SR_RTC_TSTAMP */
<>	156:95d6b41a828b	756
<>	156:95d6b41a828b	757	#if defined(SYSCFG_ITLINE2_SR_RTC_ALRA)
<>	156:95d6b41a828b	758	/**
<>	156:95d6b41a828b	759	* @brief Check if RTC Alarm interrupt occurred or not (EXTI line 17).
<>	156:95d6b41a828b	760	* @rmtoll SYSCFG_ITLINE2 SR_RTC_ALRA LL_SYSCFG_IsActiveFlag_RTC_ALRA
<>	156:95d6b41a828b	761	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	762	*/
<>	156:95d6b41a828b	763	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RTC_ALRA(void)
<>	156:95d6b41a828b	764	{
<>	156:95d6b41a828b	765	return (READ_BIT(SYSCFG->IT_LINE_SR[2], SYSCFG_ITLINE2_SR_RTC_ALRA) == (SYSCFG_ITLINE2_SR_RTC_ALRA));
<>	156:95d6b41a828b	766	}
<>	156:95d6b41a828b	767	#endif /* SYSCFG_ITLINE2_SR_RTC_ALRA */
<>	156:95d6b41a828b	768
<>	156:95d6b41a828b	769	#if defined(SYSCFG_ITLINE3_SR_FLASH_ITF)
<>	156:95d6b41a828b	770	/**
<>	156:95d6b41a828b	771	* @brief Check if Flash interface interrupt occurred or not.
<>	156:95d6b41a828b	772	* @rmtoll SYSCFG_ITLINE3 SR_FLASH_ITF LL_SYSCFG_IsActiveFlag_FLASH_ITF
<>	156:95d6b41a828b	773	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	774	*/
<>	156:95d6b41a828b	775	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_FLASH_ITF(void)
<>	156:95d6b41a828b	776	{
<>	156:95d6b41a828b	777	return (READ_BIT(SYSCFG->IT_LINE_SR[3], SYSCFG_ITLINE3_SR_FLASH_ITF) == (SYSCFG_ITLINE3_SR_FLASH_ITF));
<>	156:95d6b41a828b	778	}
<>	156:95d6b41a828b	779	#endif /* SYSCFG_ITLINE3_SR_FLASH_ITF */
<>	156:95d6b41a828b	780
<>	156:95d6b41a828b	781	#if defined(SYSCFG_ITLINE4_SR_CRS)
<>	156:95d6b41a828b	782	/**
<>	156:95d6b41a828b	783	* @brief Check if Clock recovery system interrupt occurred or not.
<>	156:95d6b41a828b	784	* @rmtoll SYSCFG_ITLINE4 SR_CRS LL_SYSCFG_IsActiveFlag_CRS
<>	156:95d6b41a828b	785	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	786	*/
<>	156:95d6b41a828b	787	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CRS(void)
<>	156:95d6b41a828b	788	{
<>	156:95d6b41a828b	789	return (READ_BIT(SYSCFG->IT_LINE_SR[4], SYSCFG_ITLINE4_SR_CRS) == (SYSCFG_ITLINE4_SR_CRS));
<>	156:95d6b41a828b	790	}
<>	156:95d6b41a828b	791	#endif /* SYSCFG_ITLINE4_SR_CRS */
<>	156:95d6b41a828b	792
<>	156:95d6b41a828b	793	#if defined(SYSCFG_ITLINE4_SR_CLK_CTRL)
<>	156:95d6b41a828b	794	/**
<>	156:95d6b41a828b	795	* @brief Check if Reset and clock control interrupt occurred or not.
<>	156:95d6b41a828b	796	* @rmtoll SYSCFG_ITLINE4 SR_CLK_CTRL LL_SYSCFG_IsActiveFlag_CLK_CTRL
<>	156:95d6b41a828b	797	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	798	*/
<>	156:95d6b41a828b	799	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CLK_CTRL(void)
<>	156:95d6b41a828b	800	{
<>	156:95d6b41a828b	801	return (READ_BIT(SYSCFG->IT_LINE_SR[4], SYSCFG_ITLINE4_SR_CLK_CTRL) == (SYSCFG_ITLINE4_SR_CLK_CTRL));
<>	156:95d6b41a828b	802	}
<>	156:95d6b41a828b	803	#endif /* SYSCFG_ITLINE4_SR_CLK_CTRL */
<>	156:95d6b41a828b	804
<>	156:95d6b41a828b	805	#if defined(SYSCFG_ITLINE5_SR_EXTI0)
<>	156:95d6b41a828b	806	/**
<>	156:95d6b41a828b	807	* @brief Check if EXTI line 0 interrupt occurred or not.
<>	156:95d6b41a828b	808	* @rmtoll SYSCFG_ITLINE5 SR_EXTI0 LL_SYSCFG_IsActiveFlag_EXTI0
<>	156:95d6b41a828b	809	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	810	*/
<>	156:95d6b41a828b	811	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI0(void)
<>	156:95d6b41a828b	812	{
<>	156:95d6b41a828b	813	return (READ_BIT(SYSCFG->IT_LINE_SR[5], SYSCFG_ITLINE5_SR_EXTI0) == (SYSCFG_ITLINE5_SR_EXTI0));
<>	156:95d6b41a828b	814	}
<>	156:95d6b41a828b	815	#endif /* SYSCFG_ITLINE5_SR_EXTI0 */
<>	156:95d6b41a828b	816
<>	156:95d6b41a828b	817	#if defined(SYSCFG_ITLINE5_SR_EXTI1)
<>	156:95d6b41a828b	818	/**
<>	156:95d6b41a828b	819	* @brief Check if EXTI line 1 interrupt occurred or not.
<>	156:95d6b41a828b	820	* @rmtoll SYSCFG_ITLINE5 SR_EXTI1 LL_SYSCFG_IsActiveFlag_EXTI1
<>	156:95d6b41a828b	821	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	822	*/
<>	156:95d6b41a828b	823	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI1(void)
<>	156:95d6b41a828b	824	{
<>	156:95d6b41a828b	825	return (READ_BIT(SYSCFG->IT_LINE_SR[5], SYSCFG_ITLINE5_SR_EXTI1) == (SYSCFG_ITLINE5_SR_EXTI1));
<>	156:95d6b41a828b	826	}
<>	156:95d6b41a828b	827	#endif /* SYSCFG_ITLINE5_SR_EXTI1 */
<>	156:95d6b41a828b	828
<>	156:95d6b41a828b	829	#if defined(SYSCFG_ITLINE6_SR_EXTI2)
<>	156:95d6b41a828b	830	/**
<>	156:95d6b41a828b	831	* @brief Check if EXTI line 2 interrupt occurred or not.
<>	156:95d6b41a828b	832	* @rmtoll SYSCFG_ITLINE6 SR_EXTI2 LL_SYSCFG_IsActiveFlag_EXTI2
<>	156:95d6b41a828b	833	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	834	*/
<>	156:95d6b41a828b	835	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI2(void)
<>	156:95d6b41a828b	836	{
<>	156:95d6b41a828b	837	return (READ_BIT(SYSCFG->IT_LINE_SR[6], SYSCFG_ITLINE6_SR_EXTI2) == (SYSCFG_ITLINE6_SR_EXTI2));
<>	156:95d6b41a828b	838	}
<>	156:95d6b41a828b	839	#endif /* SYSCFG_ITLINE6_SR_EXTI2 */
<>	156:95d6b41a828b	840
<>	156:95d6b41a828b	841	#if defined(SYSCFG_ITLINE6_SR_EXTI3)
<>	156:95d6b41a828b	842	/**
<>	156:95d6b41a828b	843	* @brief Check if EXTI line 3 interrupt occurred or not.
<>	156:95d6b41a828b	844	* @rmtoll SYSCFG_ITLINE6 SR_EXTI3 LL_SYSCFG_IsActiveFlag_EXTI3
<>	156:95d6b41a828b	845	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	846	*/
<>	156:95d6b41a828b	847	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI3(void)
<>	156:95d6b41a828b	848	{
<>	156:95d6b41a828b	849	return (READ_BIT(SYSCFG->IT_LINE_SR[6], SYSCFG_ITLINE6_SR_EXTI3) == (SYSCFG_ITLINE6_SR_EXTI3));
<>	156:95d6b41a828b	850	}
<>	156:95d6b41a828b	851	#endif /* SYSCFG_ITLINE6_SR_EXTI3 */
<>	156:95d6b41a828b	852
<>	156:95d6b41a828b	853	#if defined(SYSCFG_ITLINE7_SR_EXTI4)
<>	156:95d6b41a828b	854	/**
<>	156:95d6b41a828b	855	* @brief Check if EXTI line 4 interrupt occurred or not.
<>	156:95d6b41a828b	856	* @rmtoll SYSCFG_ITLINE7 SR_EXTI4 LL_SYSCFG_IsActiveFlag_EXTI4
<>	156:95d6b41a828b	857	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	858	*/
<>	156:95d6b41a828b	859	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI4(void)
<>	156:95d6b41a828b	860	{
<>	156:95d6b41a828b	861	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI4) == (SYSCFG_ITLINE7_SR_EXTI4));
<>	156:95d6b41a828b	862	}
<>	156:95d6b41a828b	863	#endif /* SYSCFG_ITLINE7_SR_EXTI4 */
<>	156:95d6b41a828b	864
<>	156:95d6b41a828b	865	#if defined(SYSCFG_ITLINE7_SR_EXTI5)
<>	156:95d6b41a828b	866	/**
<>	156:95d6b41a828b	867	* @brief Check if EXTI line 5 interrupt occurred or not.
<>	156:95d6b41a828b	868	* @rmtoll SYSCFG_ITLINE7 SR_EXTI5 LL_SYSCFG_IsActiveFlag_EXTI5
<>	156:95d6b41a828b	869	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	870	*/
<>	156:95d6b41a828b	871	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI5(void)
<>	156:95d6b41a828b	872	{
<>	156:95d6b41a828b	873	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI5) == (SYSCFG_ITLINE7_SR_EXTI5));
<>	156:95d6b41a828b	874	}
<>	156:95d6b41a828b	875	#endif /* SYSCFG_ITLINE7_SR_EXTI5 */
<>	156:95d6b41a828b	876
<>	156:95d6b41a828b	877	#if defined(SYSCFG_ITLINE7_SR_EXTI6)
<>	156:95d6b41a828b	878	/**
<>	156:95d6b41a828b	879	* @brief Check if EXTI line 6 interrupt occurred or not.
<>	156:95d6b41a828b	880	* @rmtoll SYSCFG_ITLINE7 SR_EXTI6 LL_SYSCFG_IsActiveFlag_EXTI6
<>	156:95d6b41a828b	881	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	882	*/
<>	156:95d6b41a828b	883	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI6(void)
<>	156:95d6b41a828b	884	{
<>	156:95d6b41a828b	885	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI6) == (SYSCFG_ITLINE7_SR_EXTI6));
<>	156:95d6b41a828b	886	}
<>	156:95d6b41a828b	887	#endif /* SYSCFG_ITLINE7_SR_EXTI6 */
<>	156:95d6b41a828b	888
<>	156:95d6b41a828b	889	#if defined(SYSCFG_ITLINE7_SR_EXTI7)
<>	156:95d6b41a828b	890	/**
<>	156:95d6b41a828b	891	* @brief Check if EXTI line 7 interrupt occurred or not.
<>	156:95d6b41a828b	892	* @rmtoll SYSCFG_ITLINE7 SR_EXTI7 LL_SYSCFG_IsActiveFlag_EXTI7
<>	156:95d6b41a828b	893	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	894	*/
<>	156:95d6b41a828b	895	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI7(void)
<>	156:95d6b41a828b	896	{
<>	156:95d6b41a828b	897	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI7) == (SYSCFG_ITLINE7_SR_EXTI7));
<>	156:95d6b41a828b	898	}
<>	156:95d6b41a828b	899	#endif /* SYSCFG_ITLINE7_SR_EXTI7 */
<>	156:95d6b41a828b	900
<>	156:95d6b41a828b	901	#if defined(SYSCFG_ITLINE7_SR_EXTI8)
<>	156:95d6b41a828b	902	/**
<>	156:95d6b41a828b	903	* @brief Check if EXTI line 8 interrupt occurred or not.
<>	156:95d6b41a828b	904	* @rmtoll SYSCFG_ITLINE7 SR_EXTI8 LL_SYSCFG_IsActiveFlag_EXTI8
<>	156:95d6b41a828b	905	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	906	*/
<>	156:95d6b41a828b	907	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI8(void)
<>	156:95d6b41a828b	908	{
<>	156:95d6b41a828b	909	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI8) == (SYSCFG_ITLINE7_SR_EXTI8));
<>	156:95d6b41a828b	910	}
<>	156:95d6b41a828b	911	#endif /* SYSCFG_ITLINE7_SR_EXTI8 */
<>	156:95d6b41a828b	912
<>	156:95d6b41a828b	913	#if defined(SYSCFG_ITLINE7_SR_EXTI9)
<>	156:95d6b41a828b	914	/**
<>	156:95d6b41a828b	915	* @brief Check if EXTI line 9 interrupt occurred or not.
<>	156:95d6b41a828b	916	* @rmtoll SYSCFG_ITLINE7 SR_EXTI9 LL_SYSCFG_IsActiveFlag_EXTI9
<>	156:95d6b41a828b	917	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	918	*/
<>	156:95d6b41a828b	919	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI9(void)
<>	156:95d6b41a828b	920	{
<>	156:95d6b41a828b	921	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI9) == (SYSCFG_ITLINE7_SR_EXTI9));
<>	156:95d6b41a828b	922	}
<>	156:95d6b41a828b	923	#endif /* SYSCFG_ITLINE7_SR_EXTI9 */
<>	156:95d6b41a828b	924
<>	156:95d6b41a828b	925	#if defined(SYSCFG_ITLINE7_SR_EXTI10)
<>	156:95d6b41a828b	926	/**
<>	156:95d6b41a828b	927	* @brief Check if EXTI line 10 interrupt occurred or not.
<>	156:95d6b41a828b	928	* @rmtoll SYSCFG_ITLINE7 SR_EXTI10 LL_SYSCFG_IsActiveFlag_EXTI10
<>	156:95d6b41a828b	929	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	930	*/
<>	156:95d6b41a828b	931	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI10(void)
<>	156:95d6b41a828b	932	{
<>	156:95d6b41a828b	933	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI10) == (SYSCFG_ITLINE7_SR_EXTI10));
<>	156:95d6b41a828b	934	}
<>	156:95d6b41a828b	935	#endif /* SYSCFG_ITLINE7_SR_EXTI10 */
<>	156:95d6b41a828b	936
<>	156:95d6b41a828b	937	#if defined(SYSCFG_ITLINE7_SR_EXTI11)
<>	156:95d6b41a828b	938	/**
<>	156:95d6b41a828b	939	* @brief Check if EXTI line 11 interrupt occurred or not.
<>	156:95d6b41a828b	940	* @rmtoll SYSCFG_ITLINE7 SR_EXTI11 LL_SYSCFG_IsActiveFlag_EXTI11
<>	156:95d6b41a828b	941	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	942	*/
<>	156:95d6b41a828b	943	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI11(void)
<>	156:95d6b41a828b	944	{
<>	156:95d6b41a828b	945	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI11) == (SYSCFG_ITLINE7_SR_EXTI11));
<>	156:95d6b41a828b	946	}
<>	156:95d6b41a828b	947	#endif /* SYSCFG_ITLINE7_SR_EXTI11 */
<>	156:95d6b41a828b	948
<>	156:95d6b41a828b	949	#if defined(SYSCFG_ITLINE7_SR_EXTI12)
<>	156:95d6b41a828b	950	/**
<>	156:95d6b41a828b	951	* @brief Check if EXTI line 12 interrupt occurred or not.
<>	156:95d6b41a828b	952	* @rmtoll SYSCFG_ITLINE7 SR_EXTI12 LL_SYSCFG_IsActiveFlag_EXTI12
<>	156:95d6b41a828b	953	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	954	*/
<>	156:95d6b41a828b	955	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI12(void)
<>	156:95d6b41a828b	956	{
<>	156:95d6b41a828b	957	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI12) == (SYSCFG_ITLINE7_SR_EXTI12));
<>	156:95d6b41a828b	958	}
<>	156:95d6b41a828b	959	#endif /* SYSCFG_ITLINE7_SR_EXTI12 */
<>	156:95d6b41a828b	960
<>	156:95d6b41a828b	961	#if defined(SYSCFG_ITLINE7_SR_EXTI13)
<>	156:95d6b41a828b	962	/**
<>	156:95d6b41a828b	963	* @brief Check if EXTI line 13 interrupt occurred or not.
<>	156:95d6b41a828b	964	* @rmtoll SYSCFG_ITLINE7 SR_EXTI13 LL_SYSCFG_IsActiveFlag_EXTI13
<>	156:95d6b41a828b	965	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	966	*/
<>	156:95d6b41a828b	967	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI13(void)
<>	156:95d6b41a828b	968	{
<>	156:95d6b41a828b	969	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI13) == (SYSCFG_ITLINE7_SR_EXTI13));
<>	156:95d6b41a828b	970	}
<>	156:95d6b41a828b	971	#endif /* SYSCFG_ITLINE7_SR_EXTI13 */
<>	156:95d6b41a828b	972
<>	156:95d6b41a828b	973	#if defined(SYSCFG_ITLINE7_SR_EXTI14)
<>	156:95d6b41a828b	974	/**
<>	156:95d6b41a828b	975	* @brief Check if EXTI line 14 interrupt occurred or not.
<>	156:95d6b41a828b	976	* @rmtoll SYSCFG_ITLINE7 SR_EXTI14 LL_SYSCFG_IsActiveFlag_EXTI14
<>	156:95d6b41a828b	977	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	978	*/
<>	156:95d6b41a828b	979	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI14(void)
<>	156:95d6b41a828b	980	{
<>	156:95d6b41a828b	981	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI14) == (SYSCFG_ITLINE7_SR_EXTI14));
<>	156:95d6b41a828b	982	}
<>	156:95d6b41a828b	983	#endif /* SYSCFG_ITLINE7_SR_EXTI14 */
<>	156:95d6b41a828b	984
<>	156:95d6b41a828b	985	#if defined(SYSCFG_ITLINE7_SR_EXTI15)
<>	156:95d6b41a828b	986	/**
<>	156:95d6b41a828b	987	* @brief Check if EXTI line 15 interrupt occurred or not.
<>	156:95d6b41a828b	988	* @rmtoll SYSCFG_ITLINE7 SR_EXTI15 LL_SYSCFG_IsActiveFlag_EXTI15
<>	156:95d6b41a828b	989	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	990	*/
<>	156:95d6b41a828b	991	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI15(void)
<>	156:95d6b41a828b	992	{
<>	156:95d6b41a828b	993	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI15) == (SYSCFG_ITLINE7_SR_EXTI15));
<>	156:95d6b41a828b	994	}
<>	156:95d6b41a828b	995	#endif /* SYSCFG_ITLINE7_SR_EXTI15 */
<>	156:95d6b41a828b	996
<>	156:95d6b41a828b	997	#if defined(SYSCFG_ITLINE8_SR_TSC_EOA)
<>	156:95d6b41a828b	998	/**
<>	156:95d6b41a828b	999	* @brief Check if Touch sensing controller end of acquisition interrupt occurred or not.
<>	156:95d6b41a828b	1000	* @rmtoll SYSCFG_ITLINE8 SR_TSC_EOA LL_SYSCFG_IsActiveFlag_TSC_EOA
<>	156:95d6b41a828b	1001	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1002	*/
<>	156:95d6b41a828b	1003	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TSC_EOA(void)
<>	156:95d6b41a828b	1004	{
<>	156:95d6b41a828b	1005	return (READ_BIT(SYSCFG->IT_LINE_SR[8], SYSCFG_ITLINE8_SR_TSC_EOA) == (SYSCFG_ITLINE8_SR_TSC_EOA));
<>	156:95d6b41a828b	1006	}
<>	156:95d6b41a828b	1007	#endif /* SYSCFG_ITLINE8_SR_TSC_EOA */
<>	156:95d6b41a828b	1008
<>	156:95d6b41a828b	1009	#if defined(SYSCFG_ITLINE8_SR_TSC_MCE)
<>	156:95d6b41a828b	1010	/**
<>	156:95d6b41a828b	1011	* @brief Check if Touch sensing controller max counterror interrupt occurred or not.
<>	156:95d6b41a828b	1012	* @rmtoll SYSCFG_ITLINE8 SR_TSC_MCE LL_SYSCFG_IsActiveFlag_TSC_MCE
<>	156:95d6b41a828b	1013	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1014	*/
<>	156:95d6b41a828b	1015	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TSC_MCE(void)
<>	156:95d6b41a828b	1016	{
<>	156:95d6b41a828b	1017	return (READ_BIT(SYSCFG->IT_LINE_SR[8], SYSCFG_ITLINE8_SR_TSC_MCE) == (SYSCFG_ITLINE8_SR_TSC_MCE));
<>	156:95d6b41a828b	1018	}
<>	156:95d6b41a828b	1019	#endif /* SYSCFG_ITLINE8_SR_TSC_MCE */
<>	156:95d6b41a828b	1020
<>	156:95d6b41a828b	1021	#if defined(SYSCFG_ITLINE9_SR_DMA1_CH1)
<>	156:95d6b41a828b	1022	/**
<>	156:95d6b41a828b	1023	* @brief Check if DMA1 channel 1 interrupt occurred or not.
<>	156:95d6b41a828b	1024	* @rmtoll SYSCFG_ITLINE9 SR_DMA1_CH1 LL_SYSCFG_IsActiveFlag_DMA1_CH1
<>	156:95d6b41a828b	1025	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1026	*/
<>	156:95d6b41a828b	1027	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH1(void)
<>	156:95d6b41a828b	1028	{
<>	156:95d6b41a828b	1029	return (READ_BIT(SYSCFG->IT_LINE_SR[9], SYSCFG_ITLINE9_SR_DMA1_CH1) == (SYSCFG_ITLINE9_SR_DMA1_CH1));
<>	156:95d6b41a828b	1030	}
<>	156:95d6b41a828b	1031	#endif /* SYSCFG_ITLINE9_SR_DMA1_CH1 */
<>	156:95d6b41a828b	1032
<>	156:95d6b41a828b	1033	#if defined(SYSCFG_ITLINE10_SR_DMA1_CH2)
<>	156:95d6b41a828b	1034	/**
<>	156:95d6b41a828b	1035	* @brief Check if DMA1 channel 2 interrupt occurred or not.
<>	156:95d6b41a828b	1036	* @rmtoll SYSCFG_ITLINE10 SR_DMA1_CH2 LL_SYSCFG_IsActiveFlag_DMA1_CH2
<>	156:95d6b41a828b	1037	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1038	*/
<>	156:95d6b41a828b	1039	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH2(void)
<>	156:95d6b41a828b	1040	{
<>	156:95d6b41a828b	1041	return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA1_CH2) == (SYSCFG_ITLINE10_SR_DMA1_CH2));
<>	156:95d6b41a828b	1042	}
<>	156:95d6b41a828b	1043	#endif /* SYSCFG_ITLINE10_SR_DMA1_CH2 */
<>	156:95d6b41a828b	1044
<>	156:95d6b41a828b	1045	#if defined(SYSCFG_ITLINE10_SR_DMA1_CH3)
<>	156:95d6b41a828b	1046	/**
<>	156:95d6b41a828b	1047	* @brief Check if DMA1 channel 3 interrupt occurred or not.
<>	156:95d6b41a828b	1048	* @rmtoll SYSCFG_ITLINE10 SR_DMA1_CH3 LL_SYSCFG_IsActiveFlag_DMA1_CH3
<>	156:95d6b41a828b	1049	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1050	*/
<>	156:95d6b41a828b	1051	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH3(void)
<>	156:95d6b41a828b	1052	{
<>	156:95d6b41a828b	1053	return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA1_CH3) == (SYSCFG_ITLINE10_SR_DMA1_CH3));
<>	156:95d6b41a828b	1054	}
<>	156:95d6b41a828b	1055	#endif /* SYSCFG_ITLINE10_SR_DMA1_CH3 */
<>	156:95d6b41a828b	1056
<>	156:95d6b41a828b	1057	#if defined(SYSCFG_ITLINE10_SR_DMA2_CH1)
<>	156:95d6b41a828b	1058	/**
<>	156:95d6b41a828b	1059	* @brief Check if DMA2 channel 1 interrupt occurred or not.
<>	156:95d6b41a828b	1060	* @rmtoll SYSCFG_ITLINE10 SR_DMA2_CH1 LL_SYSCFG_IsActiveFlag_DMA2_CH1
<>	156:95d6b41a828b	1061	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1062	*/
<>	156:95d6b41a828b	1063	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH1(void)
<>	156:95d6b41a828b	1064	{
<>	156:95d6b41a828b	1065	return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA2_CH1) == (SYSCFG_ITLINE10_SR_DMA2_CH1));
<>	156:95d6b41a828b	1066	}
<>	156:95d6b41a828b	1067	#endif /* SYSCFG_ITLINE10_SR_DMA2_CH1 */
<>	156:95d6b41a828b	1068
<>	156:95d6b41a828b	1069	#if defined(SYSCFG_ITLINE10_SR_DMA2_CH2)
<>	156:95d6b41a828b	1070	/**
<>	156:95d6b41a828b	1071	* @brief Check if DMA2 channel 2 interrupt occurred or not.
<>	156:95d6b41a828b	1072	* @rmtoll SYSCFG_ITLINE10 SR_DMA2_CH2 LL_SYSCFG_IsActiveFlag_DMA2_CH2
<>	156:95d6b41a828b	1073	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1074	*/
<>	156:95d6b41a828b	1075	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH2(void)
<>	156:95d6b41a828b	1076	{
<>	156:95d6b41a828b	1077	return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA2_CH2) == (SYSCFG_ITLINE10_SR_DMA2_CH2));
<>	156:95d6b41a828b	1078	}
<>	156:95d6b41a828b	1079	#endif /* SYSCFG_ITLINE10_SR_DMA2_CH2 */
<>	156:95d6b41a828b	1080
<>	156:95d6b41a828b	1081	#if defined(SYSCFG_ITLINE11_SR_DMA1_CH4)
<>	156:95d6b41a828b	1082	/**
<>	156:95d6b41a828b	1083	* @brief Check if DMA1 channel 4 interrupt occurred or not.
<>	156:95d6b41a828b	1084	* @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH4 LL_SYSCFG_IsActiveFlag_DMA1_CH4
<>	156:95d6b41a828b	1085	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1086	*/
<>	156:95d6b41a828b	1087	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH4(void)
<>	156:95d6b41a828b	1088	{
<>	156:95d6b41a828b	1089	return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH4) == (SYSCFG_ITLINE11_SR_DMA1_CH4));
<>	156:95d6b41a828b	1090	}
<>	156:95d6b41a828b	1091	#endif /* SYSCFG_ITLINE11_SR_DMA1_CH4 */
<>	156:95d6b41a828b	1092
<>	156:95d6b41a828b	1093	#if defined(SYSCFG_ITLINE11_SR_DMA1_CH5)
<>	156:95d6b41a828b	1094	/**
<>	156:95d6b41a828b	1095	* @brief Check if DMA1 channel 5 interrupt occurred or not.
<>	156:95d6b41a828b	1096	* @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH5 LL_SYSCFG_IsActiveFlag_DMA1_CH5
<>	156:95d6b41a828b	1097	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1098	*/
<>	156:95d6b41a828b	1099	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH5(void)
<>	156:95d6b41a828b	1100	{
<>	156:95d6b41a828b	1101	return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH5) == (SYSCFG_ITLINE11_SR_DMA1_CH5));
<>	156:95d6b41a828b	1102	}
<>	156:95d6b41a828b	1103	#endif /* SYSCFG_ITLINE11_SR_DMA1_CH5 */
<>	156:95d6b41a828b	1104
<>	156:95d6b41a828b	1105	#if defined(SYSCFG_ITLINE11_SR_DMA1_CH6)
<>	156:95d6b41a828b	1106	/**
<>	156:95d6b41a828b	1107	* @brief Check if DMA1 channel 6 interrupt occurred or not.
<>	156:95d6b41a828b	1108	* @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH6 LL_SYSCFG_IsActiveFlag_DMA1_CH6
<>	156:95d6b41a828b	1109	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1110	*/
<>	156:95d6b41a828b	1111	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH6(void)
<>	156:95d6b41a828b	1112	{
<>	156:95d6b41a828b	1113	return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH6) == (SYSCFG_ITLINE11_SR_DMA1_CH6));
<>	156:95d6b41a828b	1114	}
<>	156:95d6b41a828b	1115	#endif /* SYSCFG_ITLINE11_SR_DMA1_CH6 */
<>	156:95d6b41a828b	1116
<>	156:95d6b41a828b	1117	#if defined(SYSCFG_ITLINE11_SR_DMA1_CH7)
<>	156:95d6b41a828b	1118	/**
<>	156:95d6b41a828b	1119	* @brief Check if DMA1 channel 7 interrupt occurred or not.
<>	156:95d6b41a828b	1120	* @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH7 LL_SYSCFG_IsActiveFlag_DMA1_CH7
<>	156:95d6b41a828b	1121	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1122	*/
<>	156:95d6b41a828b	1123	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH7(void)
<>	156:95d6b41a828b	1124	{
<>	156:95d6b41a828b	1125	return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH7) == (SYSCFG_ITLINE11_SR_DMA1_CH7));
<>	156:95d6b41a828b	1126	}
<>	156:95d6b41a828b	1127	#endif /* SYSCFG_ITLINE11_SR_DMA1_CH7 */
<>	156:95d6b41a828b	1128
<>	156:95d6b41a828b	1129	#if defined(SYSCFG_ITLINE11_SR_DMA2_CH3)
<>	156:95d6b41a828b	1130	/**
<>	156:95d6b41a828b	1131	* @brief Check if DMA2 channel 3 interrupt occurred or not.
<>	156:95d6b41a828b	1132	* @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH3 LL_SYSCFG_IsActiveFlag_DMA2_CH3
<>	156:95d6b41a828b	1133	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1134	*/
<>	156:95d6b41a828b	1135	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH3(void)
<>	156:95d6b41a828b	1136	{
<>	156:95d6b41a828b	1137	return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH3) == (SYSCFG_ITLINE11_SR_DMA2_CH3));
<>	156:95d6b41a828b	1138	}
<>	156:95d6b41a828b	1139	#endif /* SYSCFG_ITLINE11_SR_DMA2_CH3 */
<>	156:95d6b41a828b	1140
<>	156:95d6b41a828b	1141	#if defined(SYSCFG_ITLINE11_SR_DMA2_CH4)
<>	156:95d6b41a828b	1142	/**
<>	156:95d6b41a828b	1143	* @brief Check if DMA2 channel 4 interrupt occurred or not.
<>	156:95d6b41a828b	1144	* @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH4 LL_SYSCFG_IsActiveFlag_DMA2_CH4
<>	156:95d6b41a828b	1145	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1146	*/
<>	156:95d6b41a828b	1147	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH4(void)
<>	156:95d6b41a828b	1148	{
<>	156:95d6b41a828b	1149	return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH4) == (SYSCFG_ITLINE11_SR_DMA2_CH4));
<>	156:95d6b41a828b	1150	}
<>	156:95d6b41a828b	1151	#endif /* SYSCFG_ITLINE11_SR_DMA2_CH4 */
<>	156:95d6b41a828b	1152
<>	156:95d6b41a828b	1153	#if defined(SYSCFG_ITLINE11_SR_DMA2_CH5)
<>	156:95d6b41a828b	1154	/**
<>	156:95d6b41a828b	1155	* @brief Check if DMA2 channel 5 interrupt occurred or not.
<>	156:95d6b41a828b	1156	* @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH5 LL_SYSCFG_IsActiveFlag_DMA2_CH5
<>	156:95d6b41a828b	1157	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1158	*/
<>	156:95d6b41a828b	1159	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH5(void)
<>	156:95d6b41a828b	1160	{
<>	156:95d6b41a828b	1161	return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH5) == (SYSCFG_ITLINE11_SR_DMA2_CH5));
<>	156:95d6b41a828b	1162	}
<>	156:95d6b41a828b	1163	#endif /* SYSCFG_ITLINE11_SR_DMA2_CH5 */
<>	156:95d6b41a828b	1164
<>	156:95d6b41a828b	1165	#if defined(SYSCFG_ITLINE12_SR_ADC)
<>	156:95d6b41a828b	1166	/**
<>	156:95d6b41a828b	1167	* @brief Check if ADC interrupt occurred or not.
<>	156:95d6b41a828b	1168	* @rmtoll SYSCFG_ITLINE12 SR_ADC LL_SYSCFG_IsActiveFlag_ADC
<>	156:95d6b41a828b	1169	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1170	*/
<>	156:95d6b41a828b	1171	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_ADC(void)
<>	156:95d6b41a828b	1172	{
<>	156:95d6b41a828b	1173	return (READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_ADC) == (SYSCFG_ITLINE12_SR_ADC));
<>	156:95d6b41a828b	1174	}
<>	156:95d6b41a828b	1175	#endif /* SYSCFG_ITLINE12_SR_ADC */
<>	156:95d6b41a828b	1176
<>	156:95d6b41a828b	1177	#if defined(SYSCFG_ITLINE12_SR_COMP1)
<>	156:95d6b41a828b	1178	/**
<>	156:95d6b41a828b	1179	* @brief Check if Comparator 1 interrupt occurred or not (EXTI line 21).
<>	156:95d6b41a828b	1180	* @rmtoll SYSCFG_ITLINE12 SR_COMP1 LL_SYSCFG_IsActiveFlag_COMP1
<>	156:95d6b41a828b	1181	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1182	*/
<>	156:95d6b41a828b	1183	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_COMP1(void)
<>	156:95d6b41a828b	1184	{
<>	156:95d6b41a828b	1185	return (READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_COMP1) == (SYSCFG_ITLINE12_SR_COMP1));
<>	156:95d6b41a828b	1186	}
<>	156:95d6b41a828b	1187	#endif /* SYSCFG_ITLINE12_SR_COMP1 */
<>	156:95d6b41a828b	1188
<>	156:95d6b41a828b	1189	#if defined(SYSCFG_ITLINE12_SR_COMP2)
<>	156:95d6b41a828b	1190	/**
<>	156:95d6b41a828b	1191	* @brief Check if Comparator 2 interrupt occurred or not (EXTI line 22).
<>	156:95d6b41a828b	1192	* @rmtoll SYSCFG_ITLINE12 SR_COMP2 LL_SYSCFG_IsActiveFlag_COMP2
<>	156:95d6b41a828b	1193	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1194	*/
<>	156:95d6b41a828b	1195	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_COMP2(void)
<>	156:95d6b41a828b	1196	{
<>	156:95d6b41a828b	1197	return (READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_COMP2) == (SYSCFG_ITLINE12_SR_COMP2));
<>	156:95d6b41a828b	1198	}
<>	156:95d6b41a828b	1199	#endif /* SYSCFG_ITLINE12_SR_COMP2 */
<>	156:95d6b41a828b	1200
<>	156:95d6b41a828b	1201	#if defined(SYSCFG_ITLINE13_SR_TIM1_BRK)
<>	156:95d6b41a828b	1202	/**
<>	156:95d6b41a828b	1203	* @brief Check if Timer 1 break interrupt occurred or not.
<>	156:95d6b41a828b	1204	* @rmtoll SYSCFG_ITLINE13 SR_TIM1_BRK LL_SYSCFG_IsActiveFlag_TIM1_BRK
<>	156:95d6b41a828b	1205	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1206	*/
<>	156:95d6b41a828b	1207	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_BRK(void)
<>	156:95d6b41a828b	1208	{
<>	156:95d6b41a828b	1209	return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_BRK) == (SYSCFG_ITLINE13_SR_TIM1_BRK));
<>	156:95d6b41a828b	1210	}
<>	156:95d6b41a828b	1211	#endif /* SYSCFG_ITLINE13_SR_TIM1_BRK */
<>	156:95d6b41a828b	1212
<>	156:95d6b41a828b	1213	#if defined(SYSCFG_ITLINE13_SR_TIM1_UPD)
<>	156:95d6b41a828b	1214	/**
<>	156:95d6b41a828b	1215	* @brief Check if Timer 1 update interrupt occurred or not.
<>	156:95d6b41a828b	1216	* @rmtoll SYSCFG_ITLINE13 SR_TIM1_UPD LL_SYSCFG_IsActiveFlag_TIM1_UPD
<>	156:95d6b41a828b	1217	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1218	*/
<>	156:95d6b41a828b	1219	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_UPD(void)
<>	156:95d6b41a828b	1220	{
<>	156:95d6b41a828b	1221	return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_UPD) == (SYSCFG_ITLINE13_SR_TIM1_UPD));
<>	156:95d6b41a828b	1222	}
<>	156:95d6b41a828b	1223	#endif /* SYSCFG_ITLINE13_SR_TIM1_UPD */
<>	156:95d6b41a828b	1224
<>	156:95d6b41a828b	1225	#if defined(SYSCFG_ITLINE13_SR_TIM1_TRG)
<>	156:95d6b41a828b	1226	/**
<>	156:95d6b41a828b	1227	* @brief Check if Timer 1 trigger interrupt occurred or not.
<>	156:95d6b41a828b	1228	* @rmtoll SYSCFG_ITLINE13 SR_TIM1_TRG LL_SYSCFG_IsActiveFlag_TIM1_TRG
<>	156:95d6b41a828b	1229	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1230	*/
<>	156:95d6b41a828b	1231	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_TRG(void)
<>	156:95d6b41a828b	1232	{
<>	156:95d6b41a828b	1233	return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_TRG) == (SYSCFG_ITLINE13_SR_TIM1_TRG));
<>	156:95d6b41a828b	1234	}
<>	156:95d6b41a828b	1235	#endif /* SYSCFG_ITLINE13_SR_TIM1_TRG */
<>	156:95d6b41a828b	1236
<>	156:95d6b41a828b	1237	#if defined(SYSCFG_ITLINE13_SR_TIM1_CCU)
<>	156:95d6b41a828b	1238	/**
<>	156:95d6b41a828b	1239	* @brief Check if Timer 1 commutation interrupt occurred or not.
<>	156:95d6b41a828b	1240	* @rmtoll SYSCFG_ITLINE13 SR_TIM1_CCU LL_SYSCFG_IsActiveFlag_TIM1_CCU
<>	156:95d6b41a828b	1241	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1242	*/
<>	156:95d6b41a828b	1243	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_CCU(void)
<>	156:95d6b41a828b	1244	{
<>	156:95d6b41a828b	1245	return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_CCU) == (SYSCFG_ITLINE13_SR_TIM1_CCU));
<>	156:95d6b41a828b	1246	}
<>	156:95d6b41a828b	1247	#endif /* SYSCFG_ITLINE13_SR_TIM1_CCU */
<>	156:95d6b41a828b	1248
<>	156:95d6b41a828b	1249	#if defined(SYSCFG_ITLINE14_SR_TIM1_CC)
<>	156:95d6b41a828b	1250	/**
<>	156:95d6b41a828b	1251	* @brief Check if Timer 1 capture compare interrupt occurred or not.
<>	156:95d6b41a828b	1252	* @rmtoll SYSCFG_ITLINE14 SR_TIM1_CC LL_SYSCFG_IsActiveFlag_TIM1_CC
<>	156:95d6b41a828b	1253	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1254	*/
<>	156:95d6b41a828b	1255	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_CC(void)
<>	156:95d6b41a828b	1256	{
<>	156:95d6b41a828b	1257	return (READ_BIT(SYSCFG->IT_LINE_SR[14], SYSCFG_ITLINE14_SR_TIM1_CC) == (SYSCFG_ITLINE14_SR_TIM1_CC));
<>	156:95d6b41a828b	1258	}
<>	156:95d6b41a828b	1259	#endif /* SYSCFG_ITLINE14_SR_TIM1_CC */
<>	156:95d6b41a828b	1260
<>	156:95d6b41a828b	1261	#if defined(SYSCFG_ITLINE15_SR_TIM2_GLB)
<>	156:95d6b41a828b	1262	/**
<>	156:95d6b41a828b	1263	* @brief Check if Timer 2 interrupt occurred or not.
<>	156:95d6b41a828b	1264	* @rmtoll SYSCFG_ITLINE15 SR_TIM2_GLB LL_SYSCFG_IsActiveFlag_TIM2
<>	156:95d6b41a828b	1265	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1266	*/
<>	156:95d6b41a828b	1267	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM2(void)
<>	156:95d6b41a828b	1268	{
<>	156:95d6b41a828b	1269	return (READ_BIT(SYSCFG->IT_LINE_SR[15], SYSCFG_ITLINE15_SR_TIM2_GLB) == (SYSCFG_ITLINE15_SR_TIM2_GLB));
<>	156:95d6b41a828b	1270	}
<>	156:95d6b41a828b	1271	#endif /* SYSCFG_ITLINE15_SR_TIM2_GLB */
<>	156:95d6b41a828b	1272
<>	156:95d6b41a828b	1273	#if defined(SYSCFG_ITLINE16_SR_TIM3_GLB)
<>	156:95d6b41a828b	1274	/**
<>	156:95d6b41a828b	1275	* @brief Check if Timer 3 interrupt occurred or not.
<>	156:95d6b41a828b	1276	* @rmtoll SYSCFG_ITLINE16 SR_TIM3_GLB LL_SYSCFG_IsActiveFlag_TIM3
<>	156:95d6b41a828b	1277	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1278	*/
<>	156:95d6b41a828b	1279	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM3(void)
<>	156:95d6b41a828b	1280	{
<>	156:95d6b41a828b	1281	return (READ_BIT(SYSCFG->IT_LINE_SR[16], SYSCFG_ITLINE16_SR_TIM3_GLB) == (SYSCFG_ITLINE16_SR_TIM3_GLB));
<>	156:95d6b41a828b	1282	}
<>	156:95d6b41a828b	1283	#endif /* SYSCFG_ITLINE16_SR_TIM3_GLB */
<>	156:95d6b41a828b	1284
<>	156:95d6b41a828b	1285	#if defined(SYSCFG_ITLINE17_SR_DAC)
<>	156:95d6b41a828b	1286	/**
<>	156:95d6b41a828b	1287	* @brief Check if DAC underrun interrupt occurred or not.
<>	156:95d6b41a828b	1288	* @rmtoll SYSCFG_ITLINE17 SR_DAC LL_SYSCFG_IsActiveFlag_DAC
<>	156:95d6b41a828b	1289	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1290	*/
<>	156:95d6b41a828b	1291	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DAC(void)
<>	156:95d6b41a828b	1292	{
<>	156:95d6b41a828b	1293	return (READ_BIT(SYSCFG->IT_LINE_SR[17], SYSCFG_ITLINE17_SR_DAC) == (SYSCFG_ITLINE17_SR_DAC));
<>	156:95d6b41a828b	1294	}
<>	156:95d6b41a828b	1295	#endif /* SYSCFG_ITLINE17_SR_DAC */
<>	156:95d6b41a828b	1296
<>	156:95d6b41a828b	1297	#if defined(SYSCFG_ITLINE17_SR_TIM6_GLB)
<>	156:95d6b41a828b	1298	/**
<>	156:95d6b41a828b	1299	* @brief Check if Timer 6 interrupt occurred or not.
<>	156:95d6b41a828b	1300	* @rmtoll SYSCFG_ITLINE17 SR_TIM6_GLB LL_SYSCFG_IsActiveFlag_TIM6
<>	156:95d6b41a828b	1301	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1302	*/
<>	156:95d6b41a828b	1303	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM6(void)
<>	156:95d6b41a828b	1304	{
<>	156:95d6b41a828b	1305	return (READ_BIT(SYSCFG->IT_LINE_SR[17], SYSCFG_ITLINE17_SR_TIM6_GLB) == (SYSCFG_ITLINE17_SR_TIM6_GLB));
<>	156:95d6b41a828b	1306	}
<>	156:95d6b41a828b	1307	#endif /* SYSCFG_ITLINE17_SR_TIM6_GLB */
<>	156:95d6b41a828b	1308
<>	156:95d6b41a828b	1309	#if defined(SYSCFG_ITLINE18_SR_TIM7_GLB)
<>	156:95d6b41a828b	1310	/**
<>	156:95d6b41a828b	1311	* @brief Check if Timer 7 interrupt occurred or not.
<>	156:95d6b41a828b	1312	* @rmtoll SYSCFG_ITLINE18 SR_TIM7_GLB LL_SYSCFG_IsActiveFlag_TIM7
<>	156:95d6b41a828b	1313	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1314	*/
<>	156:95d6b41a828b	1315	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM7(void)
<>	156:95d6b41a828b	1316	{
<>	156:95d6b41a828b	1317	return (READ_BIT(SYSCFG->IT_LINE_SR[18], SYSCFG_ITLINE18_SR_TIM7_GLB) == (SYSCFG_ITLINE18_SR_TIM7_GLB));
<>	156:95d6b41a828b	1318	}
<>	156:95d6b41a828b	1319	#endif /* SYSCFG_ITLINE18_SR_TIM7_GLB */
<>	156:95d6b41a828b	1320
<>	156:95d6b41a828b	1321	#if defined(SYSCFG_ITLINE19_SR_TIM14_GLB)
<>	156:95d6b41a828b	1322	/**
<>	156:95d6b41a828b	1323	* @brief Check if Timer 14 interrupt occurred or not.
<>	156:95d6b41a828b	1324	* @rmtoll SYSCFG_ITLINE19 SR_TIM14_GLB LL_SYSCFG_IsActiveFlag_TIM14
<>	156:95d6b41a828b	1325	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1326	*/
<>	156:95d6b41a828b	1327	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM14(void)
<>	156:95d6b41a828b	1328	{
<>	156:95d6b41a828b	1329	return (READ_BIT(SYSCFG->IT_LINE_SR[19], SYSCFG_ITLINE19_SR_TIM14_GLB) == (SYSCFG_ITLINE19_SR_TIM14_GLB));
<>	156:95d6b41a828b	1330	}
<>	156:95d6b41a828b	1331	#endif /* SYSCFG_ITLINE19_SR_TIM14_GLB */
<>	156:95d6b41a828b	1332
<>	156:95d6b41a828b	1333	#if defined(SYSCFG_ITLINE20_SR_TIM15_GLB)
<>	156:95d6b41a828b	1334	/**
<>	156:95d6b41a828b	1335	* @brief Check if Timer 15 interrupt occurred or not.
<>	156:95d6b41a828b	1336	* @rmtoll SYSCFG_ITLINE20 SR_TIM15_GLB LL_SYSCFG_IsActiveFlag_TIM15
<>	156:95d6b41a828b	1337	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1338	*/
<>	156:95d6b41a828b	1339	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM15(void)
<>	156:95d6b41a828b	1340	{
<>	156:95d6b41a828b	1341	return (READ_BIT(SYSCFG->IT_LINE_SR[20], SYSCFG_ITLINE20_SR_TIM15_GLB) == (SYSCFG_ITLINE20_SR_TIM15_GLB));
<>	156:95d6b41a828b	1342	}
<>	156:95d6b41a828b	1343	#endif /* SYSCFG_ITLINE20_SR_TIM15_GLB */
<>	156:95d6b41a828b	1344
<>	156:95d6b41a828b	1345	#if defined(SYSCFG_ITLINE21_SR_TIM16_GLB)
<>	156:95d6b41a828b	1346	/**
<>	156:95d6b41a828b	1347	* @brief Check if Timer 16 interrupt occurred or not.
<>	156:95d6b41a828b	1348	* @rmtoll SYSCFG_ITLINE21 SR_TIM16_GLB LL_SYSCFG_IsActiveFlag_TIM16
<>	156:95d6b41a828b	1349	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1350	*/
<>	156:95d6b41a828b	1351	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM16(void)
<>	156:95d6b41a828b	1352	{
<>	156:95d6b41a828b	1353	return (READ_BIT(SYSCFG->IT_LINE_SR[21], SYSCFG_ITLINE21_SR_TIM16_GLB) == (SYSCFG_ITLINE21_SR_TIM16_GLB));
<>	156:95d6b41a828b	1354	}
<>	156:95d6b41a828b	1355	#endif /* SYSCFG_ITLINE21_SR_TIM16_GLB */
<>	156:95d6b41a828b	1356
<>	156:95d6b41a828b	1357	#if defined(SYSCFG_ITLINE22_SR_TIM17_GLB)
<>	156:95d6b41a828b	1358	/**
<>	156:95d6b41a828b	1359	* @brief Check if Timer 17 interrupt occurred or not.
<>	156:95d6b41a828b	1360	* @rmtoll SYSCFG_ITLINE22 SR_TIM17_GLB LL_SYSCFG_IsActiveFlag_TIM17
<>	156:95d6b41a828b	1361	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1362	*/
<>	156:95d6b41a828b	1363	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM17(void)
<>	156:95d6b41a828b	1364	{
<>	156:95d6b41a828b	1365	return (READ_BIT(SYSCFG->IT_LINE_SR[22], SYSCFG_ITLINE22_SR_TIM17_GLB) == (SYSCFG_ITLINE22_SR_TIM17_GLB));
<>	156:95d6b41a828b	1366	}
<>	156:95d6b41a828b	1367	#endif /* SYSCFG_ITLINE22_SR_TIM17_GLB */
<>	156:95d6b41a828b	1368
<>	156:95d6b41a828b	1369	#if defined(SYSCFG_ITLINE23_SR_I2C1_GLB)
<>	156:95d6b41a828b	1370	/**
<>	156:95d6b41a828b	1371	* @brief Check if I2C1 interrupt occurred or not, combined with EXTI line 23.
<>	156:95d6b41a828b	1372	* @rmtoll SYSCFG_ITLINE23 SR_I2C1_GLB LL_SYSCFG_IsActiveFlag_I2C1
<>	156:95d6b41a828b	1373	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1374	*/
<>	156:95d6b41a828b	1375	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_I2C1(void)
<>	156:95d6b41a828b	1376	{
<>	156:95d6b41a828b	1377	return (READ_BIT(SYSCFG->IT_LINE_SR[23], SYSCFG_ITLINE23_SR_I2C1_GLB) == (SYSCFG_ITLINE23_SR_I2C1_GLB));
<>	156:95d6b41a828b	1378	}
<>	156:95d6b41a828b	1379	#endif /* SYSCFG_ITLINE23_SR_I2C1_GLB */
<>	156:95d6b41a828b	1380
<>	156:95d6b41a828b	1381	#if defined(SYSCFG_ITLINE24_SR_I2C2_GLB)
<>	156:95d6b41a828b	1382	/**
<>	156:95d6b41a828b	1383	* @brief Check if I2C2 interrupt occurred or not.
<>	156:95d6b41a828b	1384	* @rmtoll SYSCFG_ITLINE24 SR_I2C2_GLB LL_SYSCFG_IsActiveFlag_I2C2
<>	156:95d6b41a828b	1385	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1386	*/
<>	156:95d6b41a828b	1387	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_I2C2(void)
<>	156:95d6b41a828b	1388	{
<>	156:95d6b41a828b	1389	return (READ_BIT(SYSCFG->IT_LINE_SR[24], SYSCFG_ITLINE24_SR_I2C2_GLB) == (SYSCFG_ITLINE24_SR_I2C2_GLB));
<>	156:95d6b41a828b	1390	}
<>	156:95d6b41a828b	1391	#endif /* SYSCFG_ITLINE24_SR_I2C2_GLB */
<>	156:95d6b41a828b	1392
<>	156:95d6b41a828b	1393	#if defined(SYSCFG_ITLINE25_SR_SPI1)
<>	156:95d6b41a828b	1394	/**
<>	156:95d6b41a828b	1395	* @brief Check if SPI1 interrupt occurred or not.
<>	156:95d6b41a828b	1396	* @rmtoll SYSCFG_ITLINE25 SR_SPI1 LL_SYSCFG_IsActiveFlag_SPI1
<>	156:95d6b41a828b	1397	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1398	*/
<>	156:95d6b41a828b	1399	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SPI1(void)
<>	156:95d6b41a828b	1400	{
<>	156:95d6b41a828b	1401	return (READ_BIT(SYSCFG->IT_LINE_SR[25], SYSCFG_ITLINE25_SR_SPI1) == (SYSCFG_ITLINE25_SR_SPI1));
<>	156:95d6b41a828b	1402	}
<>	156:95d6b41a828b	1403	#endif /* SYSCFG_ITLINE25_SR_SPI1 */
<>	156:95d6b41a828b	1404
<>	156:95d6b41a828b	1405	#if defined(SYSCFG_ITLINE26_SR_SPI2)
<>	156:95d6b41a828b	1406	/**
<>	156:95d6b41a828b	1407	* @brief Check if SPI2 interrupt occurred or not.
<>	156:95d6b41a828b	1408	* @rmtoll SYSCFG_ITLINE26 SR_SPI2 LL_SYSCFG_IsActiveFlag_SPI2
<>	156:95d6b41a828b	1409	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1410	*/
<>	156:95d6b41a828b	1411	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SPI2(void)
<>	156:95d6b41a828b	1412	{
<>	156:95d6b41a828b	1413	return (READ_BIT(SYSCFG->IT_LINE_SR[26], SYSCFG_ITLINE26_SR_SPI2) == (SYSCFG_ITLINE26_SR_SPI2));
<>	156:95d6b41a828b	1414	}
<>	156:95d6b41a828b	1415	#endif /* SYSCFG_ITLINE26_SR_SPI2 */
<>	156:95d6b41a828b	1416
<>	156:95d6b41a828b	1417	#if defined(SYSCFG_ITLINE27_SR_USART1_GLB)
<>	156:95d6b41a828b	1418	/**
<>	156:95d6b41a828b	1419	* @brief Check if USART1 interrupt occurred or not, combined with EXTI line 25.
<>	156:95d6b41a828b	1420	* @rmtoll SYSCFG_ITLINE27 SR_USART1_GLB LL_SYSCFG_IsActiveFlag_USART1
<>	156:95d6b41a828b	1421	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1422	*/
<>	156:95d6b41a828b	1423	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART1(void)
<>	156:95d6b41a828b	1424	{
<>	156:95d6b41a828b	1425	return (READ_BIT(SYSCFG->IT_LINE_SR[27], SYSCFG_ITLINE27_SR_USART1_GLB) == (SYSCFG_ITLINE27_SR_USART1_GLB));
<>	156:95d6b41a828b	1426	}
<>	156:95d6b41a828b	1427	#endif /* SYSCFG_ITLINE27_SR_USART1_GLB */
<>	156:95d6b41a828b	1428
<>	156:95d6b41a828b	1429	#if defined(SYSCFG_ITLINE28_SR_USART2_GLB)
<>	156:95d6b41a828b	1430	/**
<>	156:95d6b41a828b	1431	* @brief Check if USART2 interrupt occurred or not, combined with EXTI line 26.
<>	156:95d6b41a828b	1432	* @rmtoll SYSCFG_ITLINE28 SR_USART2_GLB LL_SYSCFG_IsActiveFlag_USART2
<>	156:95d6b41a828b	1433	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1434	*/
<>	156:95d6b41a828b	1435	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART2(void)
<>	156:95d6b41a828b	1436	{
<>	156:95d6b41a828b	1437	return (READ_BIT(SYSCFG->IT_LINE_SR[28], SYSCFG_ITLINE28_SR_USART2_GLB) == (SYSCFG_ITLINE28_SR_USART2_GLB));
<>	156:95d6b41a828b	1438	}
<>	156:95d6b41a828b	1439	#endif /* SYSCFG_ITLINE28_SR_USART2_GLB */
<>	156:95d6b41a828b	1440
<>	156:95d6b41a828b	1441	#if defined(SYSCFG_ITLINE29_SR_USART3_GLB)
<>	156:95d6b41a828b	1442	/**
<>	156:95d6b41a828b	1443	* @brief Check if USART3 interrupt occurred or not, combined with EXTI line 28.
<>	156:95d6b41a828b	1444	* @rmtoll SYSCFG_ITLINE29 SR_USART3_GLB LL_SYSCFG_IsActiveFlag_USART3
<>	156:95d6b41a828b	1445	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1446	*/
<>	156:95d6b41a828b	1447	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART3(void)
<>	156:95d6b41a828b	1448	{
<>	156:95d6b41a828b	1449	return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART3_GLB) == (SYSCFG_ITLINE29_SR_USART3_GLB));
<>	156:95d6b41a828b	1450	}
<>	156:95d6b41a828b	1451	#endif /* SYSCFG_ITLINE29_SR_USART3_GLB */
<>	156:95d6b41a828b	1452
<>	156:95d6b41a828b	1453	#if defined(SYSCFG_ITLINE29_SR_USART4_GLB)
<>	156:95d6b41a828b	1454	/**
<>	156:95d6b41a828b	1455	* @brief Check if USART4 interrupt occurred or not.
<>	156:95d6b41a828b	1456	* @rmtoll SYSCFG_ITLINE29 SR_USART4_GLB LL_SYSCFG_IsActiveFlag_USART4
<>	156:95d6b41a828b	1457	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1458	*/
<>	156:95d6b41a828b	1459	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART4(void)
<>	156:95d6b41a828b	1460	{
<>	156:95d6b41a828b	1461	return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART4_GLB) == (SYSCFG_ITLINE29_SR_USART4_GLB));
<>	156:95d6b41a828b	1462	}
<>	156:95d6b41a828b	1463	#endif /* SYSCFG_ITLINE29_SR_USART4_GLB */
<>	156:95d6b41a828b	1464
<>	156:95d6b41a828b	1465	#if defined(SYSCFG_ITLINE29_SR_USART5_GLB)
<>	156:95d6b41a828b	1466	/**
<>	156:95d6b41a828b	1467	* @brief Check if USART5 interrupt occurred or not.
<>	156:95d6b41a828b	1468	* @rmtoll SYSCFG_ITLINE29 SR_USART5_GLB LL_SYSCFG_IsActiveFlag_USART5
<>	156:95d6b41a828b	1469	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1470	*/
<>	156:95d6b41a828b	1471	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART5(void)
<>	156:95d6b41a828b	1472	{
<>	156:95d6b41a828b	1473	return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART5_GLB) == (SYSCFG_ITLINE29_SR_USART5_GLB));
<>	156:95d6b41a828b	1474	}
<>	156:95d6b41a828b	1475	#endif /* SYSCFG_ITLINE29_SR_USART5_GLB */
<>	156:95d6b41a828b	1476
<>	156:95d6b41a828b	1477	#if defined(SYSCFG_ITLINE29_SR_USART6_GLB)
<>	156:95d6b41a828b	1478	/**
<>	156:95d6b41a828b	1479	* @brief Check if USART6 interrupt occurred or not.
<>	156:95d6b41a828b	1480	* @rmtoll SYSCFG_ITLINE29 SR_USART6_GLB LL_SYSCFG_IsActiveFlag_USART6
<>	156:95d6b41a828b	1481	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1482	*/
<>	156:95d6b41a828b	1483	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART6(void)
<>	156:95d6b41a828b	1484	{
<>	156:95d6b41a828b	1485	return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART6_GLB) == (SYSCFG_ITLINE29_SR_USART6_GLB));
<>	156:95d6b41a828b	1486	}
<>	156:95d6b41a828b	1487	#endif /* SYSCFG_ITLINE29_SR_USART6_GLB */
<>	156:95d6b41a828b	1488
<>	156:95d6b41a828b	1489	#if defined(SYSCFG_ITLINE29_SR_USART7_GLB)
<>	156:95d6b41a828b	1490	/**
<>	156:95d6b41a828b	1491	* @brief Check if USART7 interrupt occurred or not.
<>	156:95d6b41a828b	1492	* @rmtoll SYSCFG_ITLINE29 SR_USART7_GLB LL_SYSCFG_IsActiveFlag_USART7
<>	156:95d6b41a828b	1493	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1494	*/
<>	156:95d6b41a828b	1495	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART7(void)
<>	156:95d6b41a828b	1496	{
<>	156:95d6b41a828b	1497	return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART7_GLB) == (SYSCFG_ITLINE29_SR_USART7_GLB));
<>	156:95d6b41a828b	1498	}
<>	156:95d6b41a828b	1499	#endif /* SYSCFG_ITLINE29_SR_USART7_GLB */
<>	156:95d6b41a828b	1500
<>	156:95d6b41a828b	1501	#if defined(SYSCFG_ITLINE29_SR_USART8_GLB)
<>	156:95d6b41a828b	1502	/**
<>	156:95d6b41a828b	1503	* @brief Check if USART8 interrupt occurred or not.
<>	156:95d6b41a828b	1504	* @rmtoll SYSCFG_ITLINE29 SR_USART8_GLB LL_SYSCFG_IsActiveFlag_USART8
<>	156:95d6b41a828b	1505	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1506	*/
<>	156:95d6b41a828b	1507	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART8(void)
<>	156:95d6b41a828b	1508	{
<>	156:95d6b41a828b	1509	return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART8_GLB) == (SYSCFG_ITLINE29_SR_USART8_GLB));
<>	156:95d6b41a828b	1510	}
<>	156:95d6b41a828b	1511	#endif /* SYSCFG_ITLINE29_SR_USART8_GLB */
<>	156:95d6b41a828b	1512
<>	156:95d6b41a828b	1513	#if defined(SYSCFG_ITLINE30_SR_CAN)
<>	156:95d6b41a828b	1514	/**
<>	156:95d6b41a828b	1515	* @brief Check if CAN interrupt occurred or not.
<>	156:95d6b41a828b	1516	* @rmtoll SYSCFG_ITLINE30 SR_CAN LL_SYSCFG_IsActiveFlag_CAN
<>	156:95d6b41a828b	1517	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1518	*/
<>	156:95d6b41a828b	1519	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CAN(void)
<>	156:95d6b41a828b	1520	{
<>	156:95d6b41a828b	1521	return (READ_BIT(SYSCFG->IT_LINE_SR[30], SYSCFG_ITLINE30_SR_CAN) == (SYSCFG_ITLINE30_SR_CAN));
<>	156:95d6b41a828b	1522	}
<>	156:95d6b41a828b	1523	#endif /* SYSCFG_ITLINE30_SR_CAN */
<>	156:95d6b41a828b	1524
<>	156:95d6b41a828b	1525	#if defined(SYSCFG_ITLINE30_SR_CEC)
<>	156:95d6b41a828b	1526	/**
<>	156:95d6b41a828b	1527	* @brief Check if CEC interrupt occurred or not, combined with EXTI line 27.
<>	156:95d6b41a828b	1528	* @rmtoll SYSCFG_ITLINE30 SR_CEC LL_SYSCFG_IsActiveFlag_CEC
<>	156:95d6b41a828b	1529	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1530	*/
<>	156:95d6b41a828b	1531	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CEC(void)
<>	156:95d6b41a828b	1532	{
<>	156:95d6b41a828b	1533	return (READ_BIT(SYSCFG->IT_LINE_SR[30], SYSCFG_ITLINE30_SR_CEC) == (SYSCFG_ITLINE30_SR_CEC));
<>	156:95d6b41a828b	1534	}
<>	156:95d6b41a828b	1535	#endif /* SYSCFG_ITLINE30_SR_CEC */
<>	156:95d6b41a828b	1536
<>	156:95d6b41a828b	1537	/**
<>	156:95d6b41a828b	1538	* @brief Set connections to TIMx Break inputs
<>	156:95d6b41a828b	1539	* @rmtoll SYSCFG_CFGR2 LOCKUP_LOCK LL_SYSCFG_SetTIMBreakInputs\n
<>	156:95d6b41a828b	1540	* SYSCFG_CFGR2 SRAM_PARITY_LOCK LL_SYSCFG_SetTIMBreakInputs\n
<>	156:95d6b41a828b	1541	* SYSCFG_CFGR2 PVD_LOCK LL_SYSCFG_SetTIMBreakInputs
<>	156:95d6b41a828b	1542	* @param Break This parameter can be a combination of the following values:
<>	156:95d6b41a828b	1543	* @arg @ref LL_SYSCFG_TIMBREAK_PVD (*)
<>	156:95d6b41a828b	1544	* @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY
<>	156:95d6b41a828b	1545	* @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
<>	156:95d6b41a828b	1546	*
<>	156:95d6b41a828b	1547	* (*) value not defined in all devices
<>	156:95d6b41a828b	1548	* @retval None
<>	156:95d6b41a828b	1549	*/
<>	156:95d6b41a828b	1550	__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
<>	156:95d6b41a828b	1551	{
<>	156:95d6b41a828b	1552	#if defined(SYSCFG_CFGR2_PVD_LOCK)
<>	156:95d6b41a828b	1553	MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK \| SYSCFG_CFGR2_SRAM_PARITY_LOCK \| SYSCFG_CFGR2_PVD_LOCK, Break);
<>	156:95d6b41a828b	1554	#else
<>	156:95d6b41a828b	1555	MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK \| SYSCFG_CFGR2_SRAM_PARITY_LOCK, Break);
<>	156:95d6b41a828b	1556	#endif /SYSCFG_CFGR2_PVD_LOCK/
<>	156:95d6b41a828b	1557	}
<>	156:95d6b41a828b	1558
<>	156:95d6b41a828b	1559	/**
<>	156:95d6b41a828b	1560	* @brief Get connections to TIMx Break inputs
<>	156:95d6b41a828b	1561	* @rmtoll SYSCFG_CFGR2 LOCKUP_LOCK LL_SYSCFG_GetTIMBreakInputs\n
<>	156:95d6b41a828b	1562	* SYSCFG_CFGR2 SRAM_PARITY_LOCK LL_SYSCFG_GetTIMBreakInputs\n
<>	156:95d6b41a828b	1563	* SYSCFG_CFGR2 PVD_LOCK LL_SYSCFG_GetTIMBreakInputs
<>	156:95d6b41a828b	1564	* @retval Returned value can be can be a combination of the following values:
<>	156:95d6b41a828b	1565	* @arg @ref LL_SYSCFG_TIMBREAK_PVD (*)
<>	156:95d6b41a828b	1566	* @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY
<>	156:95d6b41a828b	1567	* @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
<>	156:95d6b41a828b	1568	*
<>	156:95d6b41a828b	1569	* (*) value not defined in all devices
<>	156:95d6b41a828b	1570	*/
<>	156:95d6b41a828b	1571	__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
<>	156:95d6b41a828b	1572	{
<>	156:95d6b41a828b	1573	#if defined(SYSCFG_CFGR2_PVD_LOCK)
<>	156:95d6b41a828b	1574	return (uint32_t)(READ_BIT(SYSCFG->CFGR2,
<>	156:95d6b41a828b	1575	SYSCFG_CFGR2_LOCKUP_LOCK \| SYSCFG_CFGR2_SRAM_PARITY_LOCK \| SYSCFG_CFGR2_PVD_LOCK));
<>	156:95d6b41a828b	1576	#else
<>	156:95d6b41a828b	1577	return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK \| SYSCFG_CFGR2_SRAM_PARITY_LOCK));
<>	156:95d6b41a828b	1578	#endif /SYSCFG_CFGR2_PVD_LOCK/
<>	156:95d6b41a828b	1579	}
<>	156:95d6b41a828b	1580
<>	156:95d6b41a828b	1581	/**
<>	156:95d6b41a828b	1582	* @brief Check if SRAM parity error detected
<>	156:95d6b41a828b	1583	* @rmtoll SYSCFG_CFGR2 SRAM_PEF LL_SYSCFG_IsActiveFlag_SP
<>	156:95d6b41a828b	1584	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1585	*/
<>	156:95d6b41a828b	1586	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void)
<>	156:95d6b41a828b	1587	{
<>	156:95d6b41a828b	1588	return (READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PEF) == (SYSCFG_CFGR2_SRAM_PEF));
<>	156:95d6b41a828b	1589	}
<>	156:95d6b41a828b	1590
<>	156:95d6b41a828b	1591	/**
<>	156:95d6b41a828b	1592	* @brief Clear SRAM parity error flag
<>	156:95d6b41a828b	1593	* @rmtoll SYSCFG_CFGR2 SRAM_PEF LL_SYSCFG_ClearFlag_SP
<>	156:95d6b41a828b	1594	* @retval None
<>	156:95d6b41a828b	1595	*/
<>	156:95d6b41a828b	1596	__STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void)
<>	156:95d6b41a828b	1597	{
<>	156:95d6b41a828b	1598	SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PEF);
<>	156:95d6b41a828b	1599	}
<>	156:95d6b41a828b	1600
<>	156:95d6b41a828b	1601	/**
<>	156:95d6b41a828b	1602	* @}
<>	156:95d6b41a828b	1603	*/
<>	156:95d6b41a828b	1604
<>	156:95d6b41a828b	1605	/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
<>	156:95d6b41a828b	1606	* @{
<>	156:95d6b41a828b	1607	*/
<>	156:95d6b41a828b	1608
<>	156:95d6b41a828b	1609	/**
<>	156:95d6b41a828b	1610	* @brief Return the device identifier
<>	156:95d6b41a828b	1611	* @note For STM32F03x devices, the device ID is 0x444
<>	156:95d6b41a828b	1612	* @note For STM32F04x devices, the device ID is 0x445.
<>	156:95d6b41a828b	1613	* @note For STM32F05x devices, the device ID is 0x440
<>	156:95d6b41a828b	1614	* @note For STM32F07x devices, the device ID is 0x448
<>	156:95d6b41a828b	1615	* @note For STM32F09x devices, the device ID is 0x442
<>	156:95d6b41a828b	1616	* @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
<>	156:95d6b41a828b	1617	* @retval Values between Min_Data=0x00 and Max_Data=0xFFF
<>	156:95d6b41a828b	1618	*/
<>	156:95d6b41a828b	1619	__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
<>	156:95d6b41a828b	1620	{
<>	156:95d6b41a828b	1621	return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
<>	156:95d6b41a828b	1622	}
<>	156:95d6b41a828b	1623
<>	156:95d6b41a828b	1624	/**
<>	156:95d6b41a828b	1625	* @brief Return the device revision identifier
<>	156:95d6b41a828b	1626	* @note This field indicates the revision of the device.
<>	156:95d6b41a828b	1627	For example, it is read as 0x1000 for Revision 1.0.
<>	156:95d6b41a828b	1628	* @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
<>	156:95d6b41a828b	1629	* @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
<>	156:95d6b41a828b	1630	*/
<>	156:95d6b41a828b	1631	__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
<>	156:95d6b41a828b	1632	{
Anna Bridge	180:96ed750bd169	1633	return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
<>	156:95d6b41a828b	1634	}
<>	156:95d6b41a828b	1635
<>	156:95d6b41a828b	1636	/**
<>	156:95d6b41a828b	1637	* @brief Enable the Debug Module during STOP mode
<>	156:95d6b41a828b	1638	* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
<>	156:95d6b41a828b	1639	* @retval None
<>	156:95d6b41a828b	1640	*/
<>	156:95d6b41a828b	1641	__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
<>	156:95d6b41a828b	1642	{
<>	156:95d6b41a828b	1643	SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
<>	156:95d6b41a828b	1644	}
<>	156:95d6b41a828b	1645
<>	156:95d6b41a828b	1646	/**
<>	156:95d6b41a828b	1647	* @brief Disable the Debug Module during STOP mode
<>	156:95d6b41a828b	1648	* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
<>	156:95d6b41a828b	1649	* @retval None
<>	156:95d6b41a828b	1650	*/
<>	156:95d6b41a828b	1651	__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
<>	156:95d6b41a828b	1652	{
<>	156:95d6b41a828b	1653	CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
<>	156:95d6b41a828b	1654	}
<>	156:95d6b41a828b	1655
<>	156:95d6b41a828b	1656	/**
<>	156:95d6b41a828b	1657	* @brief Enable the Debug Module during STANDBY mode
<>	156:95d6b41a828b	1658	* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
<>	156:95d6b41a828b	1659	* @retval None
<>	156:95d6b41a828b	1660	*/
<>	156:95d6b41a828b	1661	__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
<>	156:95d6b41a828b	1662	{
<>	156:95d6b41a828b	1663	SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
<>	156:95d6b41a828b	1664	}
<>	156:95d6b41a828b	1665
<>	156:95d6b41a828b	1666	/**
<>	156:95d6b41a828b	1667	* @brief Disable the Debug Module during STANDBY mode
<>	156:95d6b41a828b	1668	* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
<>	156:95d6b41a828b	1669	* @retval None
<>	156:95d6b41a828b	1670	*/
<>	156:95d6b41a828b	1671	__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
<>	156:95d6b41a828b	1672	{
<>	156:95d6b41a828b	1673	CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
<>	156:95d6b41a828b	1674	}
<>	156:95d6b41a828b	1675
<>	156:95d6b41a828b	1676	/**
<>	156:95d6b41a828b	1677	* @brief Freeze APB1 peripherals (group1 peripherals)
<>	156:95d6b41a828b	1678	* @rmtoll DBGMCU_APB1FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<>	156:95d6b41a828b	1679	* DBGMCU_APB1FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<>	156:95d6b41a828b	1680	* DBGMCU_APB1FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<>	156:95d6b41a828b	1681	* DBGMCU_APB1FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<>	156:95d6b41a828b	1682	* DBGMCU_APB1FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<>	156:95d6b41a828b	1683	* DBGMCU_APB1FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<>	156:95d6b41a828b	1684	* DBGMCU_APB1FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<>	156:95d6b41a828b	1685	* DBGMCU_APB1FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<>	156:95d6b41a828b	1686	* DBGMCU_APB1FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<>	156:95d6b41a828b	1687	* DBGMCU_APB1FZ DBG_CAN_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
<>	156:95d6b41a828b	1688	* @param Periphs This parameter can be a combination of the following values:
<>	156:95d6b41a828b	1689	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*)
<>	156:95d6b41a828b	1690	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
<>	156:95d6b41a828b	1691	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
<>	156:95d6b41a828b	1692	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
<>	156:95d6b41a828b	1693	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
<>	156:95d6b41a828b	1694	* @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
<>	156:95d6b41a828b	1695	* @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
<>	156:95d6b41a828b	1696	* @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
<>	156:95d6b41a828b	1697	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
<>	156:95d6b41a828b	1698	* @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP (*)
<>	156:95d6b41a828b	1699	*
<>	156:95d6b41a828b	1700	* (*) value not defined in all devices
<>	156:95d6b41a828b	1701	* @retval None
<>	156:95d6b41a828b	1702	*/
<>	156:95d6b41a828b	1703	__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
<>	156:95d6b41a828b	1704	{
<>	156:95d6b41a828b	1705	SET_BIT(DBGMCU->APB1FZ, Periphs);
<>	156:95d6b41a828b	1706	}
<>	156:95d6b41a828b	1707
<>	156:95d6b41a828b	1708	/**
<>	156:95d6b41a828b	1709	* @brief Unfreeze APB1 peripherals (group1 peripherals)
<>	156:95d6b41a828b	1710	* @rmtoll DBGMCU_APB1FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<>	156:95d6b41a828b	1711	* DBGMCU_APB1FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<>	156:95d6b41a828b	1712	* DBGMCU_APB1FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<>	156:95d6b41a828b	1713	* DBGMCU_APB1FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<>	156:95d6b41a828b	1714	* DBGMCU_APB1FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<>	156:95d6b41a828b	1715	* DBGMCU_APB1FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<>	156:95d6b41a828b	1716	* DBGMCU_APB1FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<>	156:95d6b41a828b	1717	* DBGMCU_APB1FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<>	156:95d6b41a828b	1718	* DBGMCU_APB1FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<>	156:95d6b41a828b	1719	* DBGMCU_APB1FZ DBG_CAN_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
<>	156:95d6b41a828b	1720	* @param Periphs This parameter can be a combination of the following values:
<>	156:95d6b41a828b	1721	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*)
<>	156:95d6b41a828b	1722	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
<>	156:95d6b41a828b	1723	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
<>	156:95d6b41a828b	1724	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
<>	156:95d6b41a828b	1725	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
<>	156:95d6b41a828b	1726	* @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
<>	156:95d6b41a828b	1727	* @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
<>	156:95d6b41a828b	1728	* @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
<>	156:95d6b41a828b	1729	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
<>	156:95d6b41a828b	1730	* @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP (*)
<>	156:95d6b41a828b	1731	*
<>	156:95d6b41a828b	1732	* (*) value not defined in all devices
<>	156:95d6b41a828b	1733	* @retval None
<>	156:95d6b41a828b	1734	*/
<>	156:95d6b41a828b	1735	__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
<>	156:95d6b41a828b	1736	{
<>	156:95d6b41a828b	1737	CLEAR_BIT(DBGMCU->APB1FZ, Periphs);
<>	156:95d6b41a828b	1738	}
<>	156:95d6b41a828b	1739
<>	156:95d6b41a828b	1740	/**
<>	156:95d6b41a828b	1741	* @brief Freeze APB1 peripherals (group2 peripherals)
<>	156:95d6b41a828b	1742	* @rmtoll DBGMCU_APB2FZ DBG_TIM1_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph\n
<>	156:95d6b41a828b	1743	* DBGMCU_APB2FZ DBG_TIM15_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph\n
<>	156:95d6b41a828b	1744	* DBGMCU_APB2FZ DBG_TIM16_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph\n
<>	156:95d6b41a828b	1745	* DBGMCU_APB2FZ DBG_TIM17_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph
<>	156:95d6b41a828b	1746	* @param Periphs This parameter can be a combination of the following values:
<>	156:95d6b41a828b	1747	* @arg @ref LL_DBGMCU_APB1_GRP2_TIM1_STOP
<>	156:95d6b41a828b	1748	* @arg @ref LL_DBGMCU_APB1_GRP2_TIM15_STOP (*)
<>	156:95d6b41a828b	1749	* @arg @ref LL_DBGMCU_APB1_GRP2_TIM16_STOP
<>	156:95d6b41a828b	1750	* @arg @ref LL_DBGMCU_APB1_GRP2_TIM17_STOP
<>	156:95d6b41a828b	1751	*
<>	156:95d6b41a828b	1752	* (*) value not defined in all devices
<>	156:95d6b41a828b	1753	* @retval None
<>	156:95d6b41a828b	1754	*/
<>	156:95d6b41a828b	1755	__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
<>	156:95d6b41a828b	1756	{
<>	156:95d6b41a828b	1757	SET_BIT(DBGMCU->APB2FZ, Periphs);
<>	156:95d6b41a828b	1758	}
<>	156:95d6b41a828b	1759
<>	156:95d6b41a828b	1760	/**
<>	156:95d6b41a828b	1761	* @brief Unfreeze APB1 peripherals (group2 peripherals)
<>	156:95d6b41a828b	1762	* @rmtoll DBGMCU_APB2FZ DBG_TIM1_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n
<>	156:95d6b41a828b	1763	* DBGMCU_APB2FZ DBG_TIM15_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n
<>	156:95d6b41a828b	1764	* DBGMCU_APB2FZ DBG_TIM16_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n
<>	156:95d6b41a828b	1765	* DBGMCU_APB2FZ DBG_TIM17_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph
<>	156:95d6b41a828b	1766	* @param Periphs This parameter can be a combination of the following values:
<>	156:95d6b41a828b	1767	* @arg @ref LL_DBGMCU_APB1_GRP2_TIM1_STOP
<>	156:95d6b41a828b	1768	* @arg @ref LL_DBGMCU_APB1_GRP2_TIM15_STOP (*)
<>	156:95d6b41a828b	1769	* @arg @ref LL_DBGMCU_APB1_GRP2_TIM16_STOP
<>	156:95d6b41a828b	1770	* @arg @ref LL_DBGMCU_APB1_GRP2_TIM17_STOP
<>	156:95d6b41a828b	1771	*
<>	156:95d6b41a828b	1772	* (*) value not defined in all devices
<>	156:95d6b41a828b	1773	* @retval None
<>	156:95d6b41a828b	1774	*/
<>	156:95d6b41a828b	1775	__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
<>	156:95d6b41a828b	1776	{
<>	156:95d6b41a828b	1777	CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
<>	156:95d6b41a828b	1778	}
<>	156:95d6b41a828b	1779	/**
<>	156:95d6b41a828b	1780	* @}
<>	156:95d6b41a828b	1781	*/
<>	156:95d6b41a828b	1782
<>	156:95d6b41a828b	1783	/** @defgroup SYSTEM_LL_EF_FLASH FLASH
<>	156:95d6b41a828b	1784	* @{
<>	156:95d6b41a828b	1785	*/
<>	156:95d6b41a828b	1786
<>	156:95d6b41a828b	1787	/**
<>	156:95d6b41a828b	1788	* @brief Set FLASH Latency
<>	156:95d6b41a828b	1789	* @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
<>	156:95d6b41a828b	1790	* @param Latency This parameter can be one of the following values:
<>	156:95d6b41a828b	1791	* @arg @ref LL_FLASH_LATENCY_0
<>	156:95d6b41a828b	1792	* @arg @ref LL_FLASH_LATENCY_1
<>	156:95d6b41a828b	1793	* @retval None
<>	156:95d6b41a828b	1794	*/
<>	156:95d6b41a828b	1795	__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
<>	156:95d6b41a828b	1796	{
<>	156:95d6b41a828b	1797	MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
<>	156:95d6b41a828b	1798	}
<>	156:95d6b41a828b	1799
<>	156:95d6b41a828b	1800	/**
<>	156:95d6b41a828b	1801	* @brief Get FLASH Latency
<>	156:95d6b41a828b	1802	* @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
<>	156:95d6b41a828b	1803	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	1804	* @arg @ref LL_FLASH_LATENCY_0
<>	156:95d6b41a828b	1805	* @arg @ref LL_FLASH_LATENCY_1
<>	156:95d6b41a828b	1806	*/
<>	156:95d6b41a828b	1807	__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
<>	156:95d6b41a828b	1808	{
<>	156:95d6b41a828b	1809	return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
<>	156:95d6b41a828b	1810	}
<>	156:95d6b41a828b	1811
<>	156:95d6b41a828b	1812	/**
<>	156:95d6b41a828b	1813	* @brief Enable Prefetch
<>	156:95d6b41a828b	1814	* @rmtoll FLASH_ACR PRFTBE LL_FLASH_EnablePrefetch
<>	156:95d6b41a828b	1815	* @retval None
<>	156:95d6b41a828b	1816	*/
<>	156:95d6b41a828b	1817	__STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
<>	156:95d6b41a828b	1818	{
<>	156:95d6b41a828b	1819	SET_BIT(FLASH->ACR, FLASH_ACR_PRFTBE);
<>	156:95d6b41a828b	1820	}
<>	156:95d6b41a828b	1821
<>	156:95d6b41a828b	1822	/**
<>	156:95d6b41a828b	1823	* @brief Disable Prefetch
<>	156:95d6b41a828b	1824	* @rmtoll FLASH_ACR PRFTBE LL_FLASH_DisablePrefetch
<>	156:95d6b41a828b	1825	* @retval None
<>	156:95d6b41a828b	1826	*/
<>	156:95d6b41a828b	1827	__STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
<>	156:95d6b41a828b	1828	{
<>	156:95d6b41a828b	1829	CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTBE);
<>	156:95d6b41a828b	1830	}
<>	156:95d6b41a828b	1831
<>	156:95d6b41a828b	1832	/**
<>	156:95d6b41a828b	1833	* @brief Check if Prefetch buffer is enabled
<>	156:95d6b41a828b	1834	* @rmtoll FLASH_ACR PRFTBS LL_FLASH_IsPrefetchEnabled
<>	156:95d6b41a828b	1835	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1836	*/
<>	156:95d6b41a828b	1837	__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
<>	156:95d6b41a828b	1838	{
<>	156:95d6b41a828b	1839	return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTBS) == (FLASH_ACR_PRFTBS));
<>	156:95d6b41a828b	1840	}
<>	156:95d6b41a828b	1841
<>	156:95d6b41a828b	1842
<>	156:95d6b41a828b	1843
<>	156:95d6b41a828b	1844	/**
<>	156:95d6b41a828b	1845	* @}
<>	156:95d6b41a828b	1846	*/
<>	156:95d6b41a828b	1847
<>	156:95d6b41a828b	1848	/**
<>	156:95d6b41a828b	1849	* @}
<>	156:95d6b41a828b	1850	*/
<>	156:95d6b41a828b	1851
<>	156:95d6b41a828b	1852	/**
<>	156:95d6b41a828b	1853	* @}
<>	156:95d6b41a828b	1854	*/
<>	156:95d6b41a828b	1855
<>	156:95d6b41a828b	1856	#endif /* defined (FLASH) \|\| defined (SYSCFG) \|\| defined (DBGMCU) */
<>	156:95d6b41a828b	1857
<>	156:95d6b41a828b	1858	/**
<>	156:95d6b41a828b	1859	* @}
<>	156:95d6b41a828b	1860	*/
<>	156:95d6b41a828b	1861
<>	156:95d6b41a828b	1862	#ifdef __cplusplus
<>	156:95d6b41a828b	1863	}
<>	156:95d6b41a828b	1864	#endif
<>	156:95d6b41a828b	1865
<>	156:95d6b41a828b	1866	#endif /* __STM32F0xx_LL_SYSTEM_H */
<>	156:95d6b41a828b	1867
<>	156:95d6b41a828b	1868	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/