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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_spi.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3
Parent:: 186:707f6e361f3e

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	156:95d6b41a828b	1	/**
<>	156:95d6b41a828b	2	******************************************************************************
<>	156:95d6b41a828b	3	* @file stm32f0xx_ll_spi.h
<>	156:95d6b41a828b	4	* @author MCD Application Team
<>	156:95d6b41a828b	5	* @brief Header file of SPI LL module.
<>	156:95d6b41a828b	6	******************************************************************************
<>	156:95d6b41a828b	7	* @attention
<>	156:95d6b41a828b	8	*
<>	156:95d6b41a828b	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	156:95d6b41a828b	10	*
<>	156:95d6b41a828b	11	* Redistribution and use in source and binary forms, with or without modification,
<>	156:95d6b41a828b	12	* are permitted provided that the following conditions are met:
<>	156:95d6b41a828b	13	* 1. Redistributions of source code must retain the above copyright notice,
<>	156:95d6b41a828b	14	* this list of conditions and the following disclaimer.
<>	156:95d6b41a828b	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	156:95d6b41a828b	16	* this list of conditions and the following disclaimer in the documentation
<>	156:95d6b41a828b	17	* and/or other materials provided with the distribution.
<>	156:95d6b41a828b	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	156:95d6b41a828b	19	* may be used to endorse or promote products derived from this software
<>	156:95d6b41a828b	20	* without specific prior written permission.
<>	156:95d6b41a828b	21	*
<>	156:95d6b41a828b	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	156:95d6b41a828b	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	156:95d6b41a828b	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	156:95d6b41a828b	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	156:95d6b41a828b	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	156:95d6b41a828b	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	156:95d6b41a828b	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	156:95d6b41a828b	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	156:95d6b41a828b	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	156:95d6b41a828b	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	156:95d6b41a828b	32	*
<>	156:95d6b41a828b	33	******************************************************************************
<>	156:95d6b41a828b	34	*/
<>	156:95d6b41a828b	35
<>	156:95d6b41a828b	36	/* Define to prevent recursive inclusion -------------------------------------*/
<>	156:95d6b41a828b	37	#ifndef __STM32F0xx_LL_SPI_H
<>	156:95d6b41a828b	38	#define __STM32F0xx_LL_SPI_H
<>	156:95d6b41a828b	39
<>	156:95d6b41a828b	40	#ifdef __cplusplus
<>	156:95d6b41a828b	41	extern "C" {
<>	156:95d6b41a828b	42	#endif
<>	156:95d6b41a828b	43
<>	156:95d6b41a828b	44	/* Includes ------------------------------------------------------------------*/
<>	156:95d6b41a828b	45	#include "stm32f0xx.h"
<>	156:95d6b41a828b	46
<>	156:95d6b41a828b	47	/** @addtogroup STM32F0xx_LL_Driver
<>	156:95d6b41a828b	48	* @{
<>	156:95d6b41a828b	49	*/
<>	156:95d6b41a828b	50
<>	156:95d6b41a828b	51	#if defined (SPI1) \|\| defined (SPI2)
<>	156:95d6b41a828b	52
<>	156:95d6b41a828b	53	/** @defgroup SPI_LL SPI
<>	156:95d6b41a828b	54	* @{
<>	156:95d6b41a828b	55	*/
<>	156:95d6b41a828b	56
<>	156:95d6b41a828b	57	/* Private types -------------------------------------------------------------*/
<>	156:95d6b41a828b	58	/* Private variables ---------------------------------------------------------*/
<>	156:95d6b41a828b	59	/* Private macros ------------------------------------------------------------*/
<>	156:95d6b41a828b	60
<>	156:95d6b41a828b	61	/* Exported types ------------------------------------------------------------*/
<>	156:95d6b41a828b	62	#if defined(USE_FULL_LL_DRIVER)
<>	156:95d6b41a828b	63	/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
<>	156:95d6b41a828b	64	* @{
<>	156:95d6b41a828b	65	*/
<>	156:95d6b41a828b	66
<>	156:95d6b41a828b	67	/**
<>	156:95d6b41a828b	68	* @brief SPI Init structures definition
<>	156:95d6b41a828b	69	*/
<>	156:95d6b41a828b	70	typedef struct
<>	156:95d6b41a828b	71	{
<>	156:95d6b41a828b	72	uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
<>	156:95d6b41a828b	73	This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
<>	156:95d6b41a828b	74
<>	156:95d6b41a828b	75	This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
<>	156:95d6b41a828b	76
<>	156:95d6b41a828b	77	uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
<>	156:95d6b41a828b	78	This parameter can be a value of @ref SPI_LL_EC_MODE.
<>	156:95d6b41a828b	79
<>	156:95d6b41a828b	80	This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
<>	156:95d6b41a828b	81
<>	156:95d6b41a828b	82	uint32_t DataWidth; /*!< Specifies the SPI data width.
<>	156:95d6b41a828b	83	This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
<>	156:95d6b41a828b	84
<>	156:95d6b41a828b	85	This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
<>	156:95d6b41a828b	86
<>	156:95d6b41a828b	87	uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
<>	156:95d6b41a828b	88	This parameter can be a value of @ref SPI_LL_EC_POLARITY.
<>	156:95d6b41a828b	89
<>	156:95d6b41a828b	90	This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
<>	156:95d6b41a828b	91
<>	156:95d6b41a828b	92	uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
<>	156:95d6b41a828b	93	This parameter can be a value of @ref SPI_LL_EC_PHASE.
<>	156:95d6b41a828b	94
<>	156:95d6b41a828b	95	This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
<>	156:95d6b41a828b	96
<>	156:95d6b41a828b	97	uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
<>	156:95d6b41a828b	98	This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
<>	156:95d6b41a828b	99
<>	156:95d6b41a828b	100	This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
<>	156:95d6b41a828b	101
<>	156:95d6b41a828b	102	uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
<>	156:95d6b41a828b	103	This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
<>	156:95d6b41a828b	104	@note The communication clock is derived from the master clock. The slave clock does not need to be set.
<>	156:95d6b41a828b	105
<>	156:95d6b41a828b	106	This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
<>	156:95d6b41a828b	107
<>	156:95d6b41a828b	108	uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
<>	156:95d6b41a828b	109	This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
<>	156:95d6b41a828b	110
<>	156:95d6b41a828b	111	This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
<>	156:95d6b41a828b	112
<>	156:95d6b41a828b	113	uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
<>	156:95d6b41a828b	114	This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
<>	156:95d6b41a828b	115
<>	156:95d6b41a828b	116	This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
<>	156:95d6b41a828b	117
<>	156:95d6b41a828b	118	uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
<>	156:95d6b41a828b	119	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
<>	156:95d6b41a828b	120
<>	156:95d6b41a828b	121	This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
<>	156:95d6b41a828b	122
<>	156:95d6b41a828b	123	} LL_SPI_InitTypeDef;
<>	156:95d6b41a828b	124
<>	156:95d6b41a828b	125	/**
<>	156:95d6b41a828b	126	* @}
<>	156:95d6b41a828b	127	*/
<>	156:95d6b41a828b	128	#endif /* USE_FULL_LL_DRIVER */
<>	156:95d6b41a828b	129
<>	156:95d6b41a828b	130	/* Exported constants --------------------------------------------------------*/
<>	156:95d6b41a828b	131	/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
<>	156:95d6b41a828b	132	* @{
<>	156:95d6b41a828b	133	*/
<>	156:95d6b41a828b	134
<>	156:95d6b41a828b	135	/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
<>	156:95d6b41a828b	136	* @brief Flags defines which can be used with LL_SPI_ReadReg function
<>	156:95d6b41a828b	137	* @{
<>	156:95d6b41a828b	138	*/
<>	156:95d6b41a828b	139	#define LL_SPI_SR_RXNE SPI_SR_RXNE /!< Rx buffer not empty flag /
<>	156:95d6b41a828b	140	#define LL_SPI_SR_TXE SPI_SR_TXE /!< Tx buffer empty flag /
<>	156:95d6b41a828b	141	#define LL_SPI_SR_BSY SPI_SR_BSY /!< Busy flag /
<>	156:95d6b41a828b	142	#define LL_SPI_SR_CRCERR SPI_SR_CRCERR /!< CRC error flag /
<>	156:95d6b41a828b	143	#define LL_SPI_SR_MODF SPI_SR_MODF /!< Mode fault flag /
<>	156:95d6b41a828b	144	#define LL_SPI_SR_OVR SPI_SR_OVR /!< Overrun flag /
<>	156:95d6b41a828b	145	#define LL_SPI_SR_FRE SPI_SR_FRE /!< TI mode frame format error flag /
<>	156:95d6b41a828b	146	/**
<>	156:95d6b41a828b	147	* @}
<>	156:95d6b41a828b	148	*/
<>	156:95d6b41a828b	149
<>	156:95d6b41a828b	150	/** @defgroup SPI_LL_EC_IT IT Defines
<>	156:95d6b41a828b	151	* @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
<>	156:95d6b41a828b	152	* @{
<>	156:95d6b41a828b	153	*/
<>	156:95d6b41a828b	154	#define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /!< Rx buffer not empty interrupt enable /
<>	156:95d6b41a828b	155	#define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /!< Tx buffer empty interrupt enable /
<>	156:95d6b41a828b	156	#define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /!< Error interrupt enable /
<>	156:95d6b41a828b	157	/**
<>	156:95d6b41a828b	158	* @}
<>	156:95d6b41a828b	159	*/
<>	156:95d6b41a828b	160
<>	156:95d6b41a828b	161	/** @defgroup SPI_LL_EC_MODE Operation Mode
<>	156:95d6b41a828b	162	* @{
<>	156:95d6b41a828b	163	*/
<>	156:95d6b41a828b	164	#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR \| SPI_CR1_SSI) /!< Master configuration /
Anna Bridge	180:96ed750bd169	165	#define LL_SPI_MODE_SLAVE 0x00000000U /!< Slave configuration /
<>	156:95d6b41a828b	166	/**
<>	156:95d6b41a828b	167	* @}
<>	156:95d6b41a828b	168	*/
<>	156:95d6b41a828b	169
<>	156:95d6b41a828b	170	/** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
<>	156:95d6b41a828b	171	* @{
<>	156:95d6b41a828b	172	*/
Anna Bridge	180:96ed750bd169	173	#define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /!< Motorola mode. Used as default value /
<>	156:95d6b41a828b	174	#define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /!< TI mode /
<>	156:95d6b41a828b	175	/**
<>	156:95d6b41a828b	176	* @}
<>	156:95d6b41a828b	177	*/
<>	156:95d6b41a828b	178
<>	156:95d6b41a828b	179	/** @defgroup SPI_LL_EC_PHASE Clock Phase
<>	156:95d6b41a828b	180	* @{
<>	156:95d6b41a828b	181	*/
Anna Bridge	180:96ed750bd169	182	#define LL_SPI_PHASE_1EDGE 0x00000000U /!< First clock transition is the first data capture edge /
<>	156:95d6b41a828b	183	#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /!< Second clock transition is the first data capture edge /
<>	156:95d6b41a828b	184	/**
<>	156:95d6b41a828b	185	* @}
<>	156:95d6b41a828b	186	*/
<>	156:95d6b41a828b	187
<>	156:95d6b41a828b	188	/** @defgroup SPI_LL_EC_POLARITY Clock Polarity
<>	156:95d6b41a828b	189	* @{
<>	156:95d6b41a828b	190	*/
Anna Bridge	180:96ed750bd169	191	#define LL_SPI_POLARITY_LOW 0x00000000U /!< Clock to 0 when idle /
<>	156:95d6b41a828b	192	#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /!< Clock to 1 when idle /
<>	156:95d6b41a828b	193	/**
<>	156:95d6b41a828b	194	* @}
<>	156:95d6b41a828b	195	*/
<>	156:95d6b41a828b	196
<>	156:95d6b41a828b	197	/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
<>	156:95d6b41a828b	198	* @{
<>	156:95d6b41a828b	199	*/
Anna Bridge	180:96ed750bd169	200	#define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /!< BaudRate control equal to fPCLK/2 /
<>	156:95d6b41a828b	201	#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/4 /
<>	156:95d6b41a828b	202	#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /!< BaudRate control equal to fPCLK/8 /
<>	156:95d6b41a828b	203	#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/16 /
<>	156:95d6b41a828b	204	#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /!< BaudRate control equal to fPCLK/32 /
<>	156:95d6b41a828b	205	#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/64 /
<>	156:95d6b41a828b	206	#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 \| SPI_CR1_BR_1) /!< BaudRate control equal to fPCLK/128 /
<>	156:95d6b41a828b	207	#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 \| SPI_CR1_BR_1 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/256 /
<>	156:95d6b41a828b	208	/**
<>	156:95d6b41a828b	209	* @}
<>	156:95d6b41a828b	210	*/
<>	156:95d6b41a828b	211
<>	156:95d6b41a828b	212	/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
<>	156:95d6b41a828b	213	* @{
<>	156:95d6b41a828b	214	*/
<>	156:95d6b41a828b	215	#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /!< Data is transmitted/received with the LSB first /
Anna Bridge	180:96ed750bd169	216	#define LL_SPI_MSB_FIRST 0x00000000U /!< Data is transmitted/received with the MSB first /
<>	156:95d6b41a828b	217	/**
<>	156:95d6b41a828b	218	* @}
<>	156:95d6b41a828b	219	*/
<>	156:95d6b41a828b	220
<>	156:95d6b41a828b	221	/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
<>	156:95d6b41a828b	222	* @{
<>	156:95d6b41a828b	223	*/
Anna Bridge	180:96ed750bd169	224	#define LL_SPI_FULL_DUPLEX 0x00000000U /!< Full-Duplex mode. Rx and Tx transfer on 2 lines /
<>	156:95d6b41a828b	225	#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /!< Simplex Rx mode. Rx transfer only on 1 line /
<>	156:95d6b41a828b	226	#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /!< Half-Duplex Rx mode. Rx transfer on 1 line /
<>	156:95d6b41a828b	227	#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE) /!< Half-Duplex Tx mode. Tx transfer on 1 line /
<>	156:95d6b41a828b	228	/**
<>	156:95d6b41a828b	229	* @}
<>	156:95d6b41a828b	230	*/
<>	156:95d6b41a828b	231
<>	156:95d6b41a828b	232	/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
<>	156:95d6b41a828b	233	* @{
<>	156:95d6b41a828b	234	*/
<>	156:95d6b41a828b	235	#define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /!< NSS managed internally. NSS pin not used and free /
Anna Bridge	180:96ed750bd169	236	#define LL_SPI_NSS_HARD_INPUT 0x00000000U /!< NSS pin used in Input. Only used in Master mode /
<>	156:95d6b41a828b	237	#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /!< NSS pin used in Output. Only used in Slave mode as chip select /
<>	156:95d6b41a828b	238	/**
<>	156:95d6b41a828b	239	* @}
<>	156:95d6b41a828b	240	*/
<>	156:95d6b41a828b	241
<>	156:95d6b41a828b	242	/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
<>	156:95d6b41a828b	243	* @{
<>	156:95d6b41a828b	244	*/
<>	156:95d6b41a828b	245	#define LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 \| SPI_CR2_DS_1) /!< Data length for SPI transfer: 4 bits /
<>	156:95d6b41a828b	246	#define LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2) /!< Data length for SPI transfer: 5 bits /
<>	156:95d6b41a828b	247	#define LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 6 bits /
<>	156:95d6b41a828b	248	#define LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 \| SPI_CR2_DS_1) /!< Data length for SPI transfer: 7 bits /
<>	156:95d6b41a828b	249	#define LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 \| SPI_CR2_DS_1 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 8 bits /
<>	156:95d6b41a828b	250	#define LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3) /!< Data length for SPI transfer: 9 bits /
<>	156:95d6b41a828b	251	#define LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 10 bits /
<>	156:95d6b41a828b	252	#define LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_1) /!< Data length for SPI transfer: 11 bits /
<>	156:95d6b41a828b	253	#define LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_1 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 12 bits /
<>	156:95d6b41a828b	254	#define LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_2) /!< Data length for SPI transfer: 13 bits /
<>	156:95d6b41a828b	255	#define LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_2 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 14 bits /
<>	156:95d6b41a828b	256	#define LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_2 \| SPI_CR2_DS_1) /!< Data length for SPI transfer: 15 bits /
<>	156:95d6b41a828b	257	#define LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_2 \| SPI_CR2_DS_1 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 16 bits /
<>	156:95d6b41a828b	258	/**
<>	156:95d6b41a828b	259	* @}
<>	156:95d6b41a828b	260	*/
<>	156:95d6b41a828b	261	#if defined(USE_FULL_LL_DRIVER)
<>	156:95d6b41a828b	262
<>	156:95d6b41a828b	263	/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
<>	156:95d6b41a828b	264	* @{
<>	156:95d6b41a828b	265	*/
Anna Bridge	180:96ed750bd169	266	#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /!< CRC calculation disabled /
<>	156:95d6b41a828b	267	#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /!< CRC calculation enabled /
<>	156:95d6b41a828b	268	/**
<>	156:95d6b41a828b	269	* @}
<>	156:95d6b41a828b	270	*/
<>	156:95d6b41a828b	271	#endif /* USE_FULL_LL_DRIVER */
<>	156:95d6b41a828b	272
<>	156:95d6b41a828b	273	/** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length
<>	156:95d6b41a828b	274	* @{
<>	156:95d6b41a828b	275	*/
Anna Bridge	180:96ed750bd169	276	#define LL_SPI_CRC_8BIT 0x00000000U /!< 8-bit CRC length /
<>	156:95d6b41a828b	277	#define LL_SPI_CRC_16BIT (SPI_CR1_CRCL) /!< 16-bit CRC length /
<>	156:95d6b41a828b	278	/**
<>	156:95d6b41a828b	279	* @}
<>	156:95d6b41a828b	280	*/
<>	156:95d6b41a828b	281
<>	156:95d6b41a828b	282	/** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold
<>	156:95d6b41a828b	283	* @{
<>	156:95d6b41a828b	284	*/
Anna Bridge	180:96ed750bd169	285	#define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /!< RXNE event is generated if FIFO level is greater than or equel to 1/2 (16-bit) /
<>	156:95d6b41a828b	286	#define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /!< RXNE event is generated if FIFO level is greater than or equel to 1/4 (8-bit) /
<>	156:95d6b41a828b	287	/**
<>	156:95d6b41a828b	288	* @}
<>	156:95d6b41a828b	289	*/
<>	156:95d6b41a828b	290
<>	156:95d6b41a828b	291	/** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level
<>	156:95d6b41a828b	292	* @{
<>	156:95d6b41a828b	293	*/
Anna Bridge	180:96ed750bd169	294	#define LL_SPI_RX_FIFO_EMPTY 0x00000000U /!< FIFO reception empty /
<>	156:95d6b41a828b	295	#define LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0) /!< FIFO reception 1/4 /
<>	156:95d6b41a828b	296	#define LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1) /!< FIFO reception 1/2 /
<>	156:95d6b41a828b	297	#define LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 \| SPI_SR_FRLVL_0) /!< FIFO reception full /
<>	156:95d6b41a828b	298	/**
<>	156:95d6b41a828b	299	* @}
<>	156:95d6b41a828b	300	*/
<>	156:95d6b41a828b	301
<>	156:95d6b41a828b	302	/** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level
<>	156:95d6b41a828b	303	* @{
<>	156:95d6b41a828b	304	*/
Anna Bridge	180:96ed750bd169	305	#define LL_SPI_TX_FIFO_EMPTY 0x00000000U /!< FIFO transmission empty /
<>	156:95d6b41a828b	306	#define LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0) /!< FIFO transmission 1/4 /
<>	156:95d6b41a828b	307	#define LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1) /!< FIFO transmission 1/2 /
<>	156:95d6b41a828b	308	#define LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 \| SPI_SR_FTLVL_0) /!< FIFO transmission full /
<>	156:95d6b41a828b	309	/**
<>	156:95d6b41a828b	310	* @}
<>	156:95d6b41a828b	311	*/
<>	156:95d6b41a828b	312
<>	156:95d6b41a828b	313	/** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity
<>	156:95d6b41a828b	314	* @{
<>	156:95d6b41a828b	315	*/
Anna Bridge	180:96ed750bd169	316	#define LL_SPI_DMA_PARITY_EVEN 0x00000000U /!< Select DMA parity Even /
Anna Bridge	180:96ed750bd169	317	#define LL_SPI_DMA_PARITY_ODD 0x00000001U /!< Select DMA parity Odd /
<>	156:95d6b41a828b	318
<>	156:95d6b41a828b	319	/**
<>	156:95d6b41a828b	320	* @}
<>	156:95d6b41a828b	321	*/
<>	156:95d6b41a828b	322
<>	156:95d6b41a828b	323	/**
<>	156:95d6b41a828b	324	* @}
<>	156:95d6b41a828b	325	*/
<>	156:95d6b41a828b	326
<>	156:95d6b41a828b	327	/* Exported macro ------------------------------------------------------------*/
<>	156:95d6b41a828b	328	/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
<>	156:95d6b41a828b	329	* @{
<>	156:95d6b41a828b	330	*/
<>	156:95d6b41a828b	331
<>	156:95d6b41a828b	332	/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
<>	156:95d6b41a828b	333	* @{
<>	156:95d6b41a828b	334	*/
<>	156:95d6b41a828b	335
<>	156:95d6b41a828b	336	/**
<>	156:95d6b41a828b	337	* @brief Write a value in SPI register
<>	156:95d6b41a828b	338	* @param __INSTANCE__ SPI Instance
<>	156:95d6b41a828b	339	* @param __REG__ Register to be written
<>	156:95d6b41a828b	340	* @param __VALUE__ Value to be written in the register
<>	156:95d6b41a828b	341	* @retval None
<>	156:95d6b41a828b	342	*/
<>	156:95d6b41a828b	343	#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<>	156:95d6b41a828b	344
<>	156:95d6b41a828b	345	/**
<>	156:95d6b41a828b	346	* @brief Read a value in SPI register
<>	156:95d6b41a828b	347	* @param __INSTANCE__ SPI Instance
<>	156:95d6b41a828b	348	* @param __REG__ Register to be read
<>	156:95d6b41a828b	349	* @retval Register value
<>	156:95d6b41a828b	350	*/
<>	156:95d6b41a828b	351	#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<>	156:95d6b41a828b	352	/**
<>	156:95d6b41a828b	353	* @}
<>	156:95d6b41a828b	354	*/
<>	156:95d6b41a828b	355
<>	156:95d6b41a828b	356	/**
<>	156:95d6b41a828b	357	* @}
<>	156:95d6b41a828b	358	*/
<>	156:95d6b41a828b	359
<>	156:95d6b41a828b	360	/* Exported functions --------------------------------------------------------*/
<>	156:95d6b41a828b	361	/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
<>	156:95d6b41a828b	362	* @{
<>	156:95d6b41a828b	363	*/
<>	156:95d6b41a828b	364
<>	156:95d6b41a828b	365	/** @defgroup SPI_LL_EF_Configuration Configuration
<>	156:95d6b41a828b	366	* @{
<>	156:95d6b41a828b	367	*/
<>	156:95d6b41a828b	368
<>	156:95d6b41a828b	369	/**
<>	156:95d6b41a828b	370	* @brief Enable SPI peripheral
<>	156:95d6b41a828b	371	* @rmtoll CR1 SPE LL_SPI_Enable
<>	156:95d6b41a828b	372	* @param SPIx SPI Instance
<>	156:95d6b41a828b	373	* @retval None
<>	156:95d6b41a828b	374	*/
<>	156:95d6b41a828b	375	__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	376	{
<>	156:95d6b41a828b	377	SET_BIT(SPIx->CR1, SPI_CR1_SPE);
<>	156:95d6b41a828b	378	}
<>	156:95d6b41a828b	379
<>	156:95d6b41a828b	380	/**
<>	156:95d6b41a828b	381	* @brief Disable SPI peripheral
<>	156:95d6b41a828b	382	* @note When disabling the SPI, follow the procedure described in the Reference Manual.
<>	156:95d6b41a828b	383	* @rmtoll CR1 SPE LL_SPI_Disable
<>	156:95d6b41a828b	384	* @param SPIx SPI Instance
<>	156:95d6b41a828b	385	* @retval None
<>	156:95d6b41a828b	386	*/
<>	156:95d6b41a828b	387	__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	388	{
<>	156:95d6b41a828b	389	CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
<>	156:95d6b41a828b	390	}
<>	156:95d6b41a828b	391
<>	156:95d6b41a828b	392	/**
<>	156:95d6b41a828b	393	* @brief Check if SPI peripheral is enabled
<>	156:95d6b41a828b	394	* @rmtoll CR1 SPE LL_SPI_IsEnabled
<>	156:95d6b41a828b	395	* @param SPIx SPI Instance
<>	156:95d6b41a828b	396	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	397	*/
<>	156:95d6b41a828b	398	__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	399	{
<>	156:95d6b41a828b	400	return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE));
<>	156:95d6b41a828b	401	}
<>	156:95d6b41a828b	402
<>	156:95d6b41a828b	403	/**
<>	156:95d6b41a828b	404	* @brief Set SPI operation mode to Master or Slave
<>	156:95d6b41a828b	405	* @note This bit should not be changed when communication is ongoing.
<>	156:95d6b41a828b	406	* @rmtoll CR1 MSTR LL_SPI_SetMode\n
<>	156:95d6b41a828b	407	* CR1 SSI LL_SPI_SetMode
<>	156:95d6b41a828b	408	* @param SPIx SPI Instance
<>	156:95d6b41a828b	409	* @param Mode This parameter can be one of the following values:
<>	156:95d6b41a828b	410	* @arg @ref LL_SPI_MODE_MASTER
<>	156:95d6b41a828b	411	* @arg @ref LL_SPI_MODE_SLAVE
<>	156:95d6b41a828b	412	* @retval None
<>	156:95d6b41a828b	413	*/
<>	156:95d6b41a828b	414	__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
<>	156:95d6b41a828b	415	{
<>	156:95d6b41a828b	416	MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR \| SPI_CR1_SSI, Mode);
<>	156:95d6b41a828b	417	}
<>	156:95d6b41a828b	418
<>	156:95d6b41a828b	419	/**
<>	156:95d6b41a828b	420	* @brief Get SPI operation mode (Master or Slave)
<>	156:95d6b41a828b	421	* @rmtoll CR1 MSTR LL_SPI_GetMode\n
<>	156:95d6b41a828b	422	* CR1 SSI LL_SPI_GetMode
<>	156:95d6b41a828b	423	* @param SPIx SPI Instance
<>	156:95d6b41a828b	424	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	425	* @arg @ref LL_SPI_MODE_MASTER
<>	156:95d6b41a828b	426	* @arg @ref LL_SPI_MODE_SLAVE
<>	156:95d6b41a828b	427	*/
<>	156:95d6b41a828b	428	__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	429	{
<>	156:95d6b41a828b	430	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR \| SPI_CR1_SSI));
<>	156:95d6b41a828b	431	}
<>	156:95d6b41a828b	432
<>	156:95d6b41a828b	433	/**
<>	156:95d6b41a828b	434	* @brief Set serial protocol used
<>	156:95d6b41a828b	435	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
<>	156:95d6b41a828b	436	* @rmtoll CR2 FRF LL_SPI_SetStandard
<>	156:95d6b41a828b	437	* @param SPIx SPI Instance
<>	156:95d6b41a828b	438	* @param Standard This parameter can be one of the following values:
<>	156:95d6b41a828b	439	* @arg @ref LL_SPI_PROTOCOL_MOTOROLA
<>	156:95d6b41a828b	440	* @arg @ref LL_SPI_PROTOCOL_TI
<>	156:95d6b41a828b	441	* @retval None
<>	156:95d6b41a828b	442	*/
<>	156:95d6b41a828b	443	__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
<>	156:95d6b41a828b	444	{
<>	156:95d6b41a828b	445	MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
<>	156:95d6b41a828b	446	}
<>	156:95d6b41a828b	447
<>	156:95d6b41a828b	448	/**
<>	156:95d6b41a828b	449	* @brief Get serial protocol used
<>	156:95d6b41a828b	450	* @rmtoll CR2 FRF LL_SPI_GetStandard
<>	156:95d6b41a828b	451	* @param SPIx SPI Instance
<>	156:95d6b41a828b	452	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	453	* @arg @ref LL_SPI_PROTOCOL_MOTOROLA
<>	156:95d6b41a828b	454	* @arg @ref LL_SPI_PROTOCOL_TI
<>	156:95d6b41a828b	455	*/
<>	156:95d6b41a828b	456	__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	457	{
<>	156:95d6b41a828b	458	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
<>	156:95d6b41a828b	459	}
<>	156:95d6b41a828b	460
<>	156:95d6b41a828b	461	/**
<>	156:95d6b41a828b	462	* @brief Set clock phase
<>	156:95d6b41a828b	463	* @note This bit should not be changed when communication is ongoing.
<>	156:95d6b41a828b	464	* This bit is not used in SPI TI mode.
<>	156:95d6b41a828b	465	* @rmtoll CR1 CPHA LL_SPI_SetClockPhase
<>	156:95d6b41a828b	466	* @param SPIx SPI Instance
<>	156:95d6b41a828b	467	* @param ClockPhase This parameter can be one of the following values:
<>	156:95d6b41a828b	468	* @arg @ref LL_SPI_PHASE_1EDGE
<>	156:95d6b41a828b	469	* @arg @ref LL_SPI_PHASE_2EDGE
<>	156:95d6b41a828b	470	* @retval None
<>	156:95d6b41a828b	471	*/
<>	156:95d6b41a828b	472	__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
<>	156:95d6b41a828b	473	{
<>	156:95d6b41a828b	474	MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
<>	156:95d6b41a828b	475	}
<>	156:95d6b41a828b	476
<>	156:95d6b41a828b	477	/**
<>	156:95d6b41a828b	478	* @brief Get clock phase
<>	156:95d6b41a828b	479	* @rmtoll CR1 CPHA LL_SPI_GetClockPhase
<>	156:95d6b41a828b	480	* @param SPIx SPI Instance
<>	156:95d6b41a828b	481	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	482	* @arg @ref LL_SPI_PHASE_1EDGE
<>	156:95d6b41a828b	483	* @arg @ref LL_SPI_PHASE_2EDGE
<>	156:95d6b41a828b	484	*/
<>	156:95d6b41a828b	485	__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	486	{
<>	156:95d6b41a828b	487	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
<>	156:95d6b41a828b	488	}
<>	156:95d6b41a828b	489
<>	156:95d6b41a828b	490	/**
<>	156:95d6b41a828b	491	* @brief Set clock polarity
<>	156:95d6b41a828b	492	* @note This bit should not be changed when communication is ongoing.
<>	156:95d6b41a828b	493	* This bit is not used in SPI TI mode.
<>	156:95d6b41a828b	494	* @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
<>	156:95d6b41a828b	495	* @param SPIx SPI Instance
<>	156:95d6b41a828b	496	* @param ClockPolarity This parameter can be one of the following values:
<>	156:95d6b41a828b	497	* @arg @ref LL_SPI_POLARITY_LOW
<>	156:95d6b41a828b	498	* @arg @ref LL_SPI_POLARITY_HIGH
<>	156:95d6b41a828b	499	* @retval None
<>	156:95d6b41a828b	500	*/
<>	156:95d6b41a828b	501	__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
<>	156:95d6b41a828b	502	{
<>	156:95d6b41a828b	503	MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
<>	156:95d6b41a828b	504	}
<>	156:95d6b41a828b	505
<>	156:95d6b41a828b	506	/**
<>	156:95d6b41a828b	507	* @brief Get clock polarity
<>	156:95d6b41a828b	508	* @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
<>	156:95d6b41a828b	509	* @param SPIx SPI Instance
<>	156:95d6b41a828b	510	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	511	* @arg @ref LL_SPI_POLARITY_LOW
<>	156:95d6b41a828b	512	* @arg @ref LL_SPI_POLARITY_HIGH
<>	156:95d6b41a828b	513	*/
<>	156:95d6b41a828b	514	__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	515	{
<>	156:95d6b41a828b	516	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
<>	156:95d6b41a828b	517	}
<>	156:95d6b41a828b	518
<>	156:95d6b41a828b	519	/**
<>	156:95d6b41a828b	520	* @brief Set baud rate prescaler
<>	156:95d6b41a828b	521	* @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
<>	156:95d6b41a828b	522	* @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
<>	156:95d6b41a828b	523	* @param SPIx SPI Instance
<>	156:95d6b41a828b	524	* @param BaudRate This parameter can be one of the following values:
<>	156:95d6b41a828b	525	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
<>	156:95d6b41a828b	526	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
<>	156:95d6b41a828b	527	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
<>	156:95d6b41a828b	528	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
<>	156:95d6b41a828b	529	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
<>	156:95d6b41a828b	530	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
<>	156:95d6b41a828b	531	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
<>	156:95d6b41a828b	532	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
<>	156:95d6b41a828b	533	* @retval None
<>	156:95d6b41a828b	534	*/
<>	156:95d6b41a828b	535	__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
<>	156:95d6b41a828b	536	{
<>	156:95d6b41a828b	537	MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
<>	156:95d6b41a828b	538	}
<>	156:95d6b41a828b	539
<>	156:95d6b41a828b	540	/**
<>	156:95d6b41a828b	541	* @brief Get baud rate prescaler
<>	156:95d6b41a828b	542	* @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
<>	156:95d6b41a828b	543	* @param SPIx SPI Instance
<>	156:95d6b41a828b	544	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	545	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
<>	156:95d6b41a828b	546	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
<>	156:95d6b41a828b	547	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
<>	156:95d6b41a828b	548	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
<>	156:95d6b41a828b	549	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
<>	156:95d6b41a828b	550	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
<>	156:95d6b41a828b	551	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
<>	156:95d6b41a828b	552	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
<>	156:95d6b41a828b	553	*/
<>	156:95d6b41a828b	554	__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	555	{
<>	156:95d6b41a828b	556	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
<>	156:95d6b41a828b	557	}
<>	156:95d6b41a828b	558
<>	156:95d6b41a828b	559	/**
<>	156:95d6b41a828b	560	* @brief Set transfer bit order
<>	156:95d6b41a828b	561	* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
<>	156:95d6b41a828b	562	* @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
<>	156:95d6b41a828b	563	* @param SPIx SPI Instance
<>	156:95d6b41a828b	564	* @param BitOrder This parameter can be one of the following values:
<>	156:95d6b41a828b	565	* @arg @ref LL_SPI_LSB_FIRST
<>	156:95d6b41a828b	566	* @arg @ref LL_SPI_MSB_FIRST
<>	156:95d6b41a828b	567	* @retval None
<>	156:95d6b41a828b	568	*/
<>	156:95d6b41a828b	569	__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
<>	156:95d6b41a828b	570	{
<>	156:95d6b41a828b	571	MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
<>	156:95d6b41a828b	572	}
<>	156:95d6b41a828b	573
<>	156:95d6b41a828b	574	/**
<>	156:95d6b41a828b	575	* @brief Get transfer bit order
<>	156:95d6b41a828b	576	* @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
<>	156:95d6b41a828b	577	* @param SPIx SPI Instance
<>	156:95d6b41a828b	578	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	579	* @arg @ref LL_SPI_LSB_FIRST
<>	156:95d6b41a828b	580	* @arg @ref LL_SPI_MSB_FIRST
<>	156:95d6b41a828b	581	*/
<>	156:95d6b41a828b	582	__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	583	{
<>	156:95d6b41a828b	584	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
<>	156:95d6b41a828b	585	}
<>	156:95d6b41a828b	586
<>	156:95d6b41a828b	587	/**
<>	156:95d6b41a828b	588	* @brief Set transfer direction mode
<>	156:95d6b41a828b	589	* @note For Half-Duplex mode, Rx Direction is set by default.
<>	156:95d6b41a828b	590	* In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
<>	156:95d6b41a828b	591	* @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
<>	156:95d6b41a828b	592	* CR1 BIDIMODE LL_SPI_SetTransferDirection\n
<>	156:95d6b41a828b	593	* CR1 BIDIOE LL_SPI_SetTransferDirection
<>	156:95d6b41a828b	594	* @param SPIx SPI Instance
<>	156:95d6b41a828b	595	* @param TransferDirection This parameter can be one of the following values:
<>	156:95d6b41a828b	596	* @arg @ref LL_SPI_FULL_DUPLEX
<>	156:95d6b41a828b	597	* @arg @ref LL_SPI_SIMPLEX_RX
<>	156:95d6b41a828b	598	* @arg @ref LL_SPI_HALF_DUPLEX_RX
<>	156:95d6b41a828b	599	* @arg @ref LL_SPI_HALF_DUPLEX_TX
<>	156:95d6b41a828b	600	* @retval None
<>	156:95d6b41a828b	601	*/
<>	156:95d6b41a828b	602	__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
<>	156:95d6b41a828b	603	{
<>	156:95d6b41a828b	604	MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY \| SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE, TransferDirection);
<>	156:95d6b41a828b	605	}
<>	156:95d6b41a828b	606
<>	156:95d6b41a828b	607	/**
<>	156:95d6b41a828b	608	* @brief Get transfer direction mode
<>	156:95d6b41a828b	609	* @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
<>	156:95d6b41a828b	610	* CR1 BIDIMODE LL_SPI_GetTransferDirection\n
<>	156:95d6b41a828b	611	* CR1 BIDIOE LL_SPI_GetTransferDirection
<>	156:95d6b41a828b	612	* @param SPIx SPI Instance
<>	156:95d6b41a828b	613	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	614	* @arg @ref LL_SPI_FULL_DUPLEX
<>	156:95d6b41a828b	615	* @arg @ref LL_SPI_SIMPLEX_RX
<>	156:95d6b41a828b	616	* @arg @ref LL_SPI_HALF_DUPLEX_RX
<>	156:95d6b41a828b	617	* @arg @ref LL_SPI_HALF_DUPLEX_TX
<>	156:95d6b41a828b	618	*/
<>	156:95d6b41a828b	619	__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	620	{
<>	156:95d6b41a828b	621	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY \| SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE));
<>	156:95d6b41a828b	622	}
<>	156:95d6b41a828b	623
<>	156:95d6b41a828b	624	/**
<>	156:95d6b41a828b	625	* @brief Set frame data width
<>	156:95d6b41a828b	626	* @rmtoll CR2 DS LL_SPI_SetDataWidth
<>	156:95d6b41a828b	627	* @param SPIx SPI Instance
<>	156:95d6b41a828b	628	* @param DataWidth This parameter can be one of the following values:
<>	156:95d6b41a828b	629	* @arg @ref LL_SPI_DATAWIDTH_4BIT
<>	156:95d6b41a828b	630	* @arg @ref LL_SPI_DATAWIDTH_5BIT
<>	156:95d6b41a828b	631	* @arg @ref LL_SPI_DATAWIDTH_6BIT
<>	156:95d6b41a828b	632	* @arg @ref LL_SPI_DATAWIDTH_7BIT
<>	156:95d6b41a828b	633	* @arg @ref LL_SPI_DATAWIDTH_8BIT
<>	156:95d6b41a828b	634	* @arg @ref LL_SPI_DATAWIDTH_9BIT
<>	156:95d6b41a828b	635	* @arg @ref LL_SPI_DATAWIDTH_10BIT
<>	156:95d6b41a828b	636	* @arg @ref LL_SPI_DATAWIDTH_11BIT
<>	156:95d6b41a828b	637	* @arg @ref LL_SPI_DATAWIDTH_12BIT
<>	156:95d6b41a828b	638	* @arg @ref LL_SPI_DATAWIDTH_13BIT
<>	156:95d6b41a828b	639	* @arg @ref LL_SPI_DATAWIDTH_14BIT
<>	156:95d6b41a828b	640	* @arg @ref LL_SPI_DATAWIDTH_15BIT
<>	156:95d6b41a828b	641	* @arg @ref LL_SPI_DATAWIDTH_16BIT
<>	156:95d6b41a828b	642	* @retval None
<>	156:95d6b41a828b	643	*/
<>	156:95d6b41a828b	644	__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
<>	156:95d6b41a828b	645	{
<>	156:95d6b41a828b	646	MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth);
<>	156:95d6b41a828b	647	}
<>	156:95d6b41a828b	648
<>	156:95d6b41a828b	649	/**
<>	156:95d6b41a828b	650	* @brief Get frame data width
<>	156:95d6b41a828b	651	* @rmtoll CR2 DS LL_SPI_GetDataWidth
<>	156:95d6b41a828b	652	* @param SPIx SPI Instance
<>	156:95d6b41a828b	653	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	654	* @arg @ref LL_SPI_DATAWIDTH_4BIT
<>	156:95d6b41a828b	655	* @arg @ref LL_SPI_DATAWIDTH_5BIT
<>	156:95d6b41a828b	656	* @arg @ref LL_SPI_DATAWIDTH_6BIT
<>	156:95d6b41a828b	657	* @arg @ref LL_SPI_DATAWIDTH_7BIT
<>	156:95d6b41a828b	658	* @arg @ref LL_SPI_DATAWIDTH_8BIT
<>	156:95d6b41a828b	659	* @arg @ref LL_SPI_DATAWIDTH_9BIT
<>	156:95d6b41a828b	660	* @arg @ref LL_SPI_DATAWIDTH_10BIT
<>	156:95d6b41a828b	661	* @arg @ref LL_SPI_DATAWIDTH_11BIT
<>	156:95d6b41a828b	662	* @arg @ref LL_SPI_DATAWIDTH_12BIT
<>	156:95d6b41a828b	663	* @arg @ref LL_SPI_DATAWIDTH_13BIT
<>	156:95d6b41a828b	664	* @arg @ref LL_SPI_DATAWIDTH_14BIT
<>	156:95d6b41a828b	665	* @arg @ref LL_SPI_DATAWIDTH_15BIT
<>	156:95d6b41a828b	666	* @arg @ref LL_SPI_DATAWIDTH_16BIT
<>	156:95d6b41a828b	667	*/
<>	156:95d6b41a828b	668	__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	669	{
<>	156:95d6b41a828b	670	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS));
<>	156:95d6b41a828b	671	}
<>	156:95d6b41a828b	672
<>	156:95d6b41a828b	673	/**
<>	156:95d6b41a828b	674	* @brief Set threshold of RXFIFO that triggers an RXNE event
<>	156:95d6b41a828b	675	* @rmtoll CR2 FRXTH LL_SPI_SetRxFIFOThreshold
<>	156:95d6b41a828b	676	* @param SPIx SPI Instance
<>	156:95d6b41a828b	677	* @param Threshold This parameter can be one of the following values:
<>	156:95d6b41a828b	678	* @arg @ref LL_SPI_RX_FIFO_TH_HALF
<>	156:95d6b41a828b	679	* @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
<>	156:95d6b41a828b	680	* @retval None
<>	156:95d6b41a828b	681	*/
<>	156:95d6b41a828b	682	__STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
<>	156:95d6b41a828b	683	{
<>	156:95d6b41a828b	684	MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold);
<>	156:95d6b41a828b	685	}
<>	156:95d6b41a828b	686
<>	156:95d6b41a828b	687	/**
<>	156:95d6b41a828b	688	* @brief Get threshold of RXFIFO that triggers an RXNE event
<>	156:95d6b41a828b	689	* @rmtoll CR2 FRXTH LL_SPI_GetRxFIFOThreshold
<>	156:95d6b41a828b	690	* @param SPIx SPI Instance
<>	156:95d6b41a828b	691	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	692	* @arg @ref LL_SPI_RX_FIFO_TH_HALF
<>	156:95d6b41a828b	693	* @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
<>	156:95d6b41a828b	694	*/
<>	156:95d6b41a828b	695	__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	696	{
<>	156:95d6b41a828b	697	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH));
<>	156:95d6b41a828b	698	}
<>	156:95d6b41a828b	699
<>	156:95d6b41a828b	700	/**
<>	156:95d6b41a828b	701	* @}
<>	156:95d6b41a828b	702	*/
<>	156:95d6b41a828b	703
<>	156:95d6b41a828b	704	/** @defgroup SPI_LL_EF_CRC_Management CRC Management
<>	156:95d6b41a828b	705	* @{
<>	156:95d6b41a828b	706	*/
<>	156:95d6b41a828b	707
<>	156:95d6b41a828b	708	/**
<>	156:95d6b41a828b	709	* @brief Enable CRC
<>	156:95d6b41a828b	710	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
<>	156:95d6b41a828b	711	* @rmtoll CR1 CRCEN LL_SPI_EnableCRC
<>	156:95d6b41a828b	712	* @param SPIx SPI Instance
<>	156:95d6b41a828b	713	* @retval None
<>	156:95d6b41a828b	714	*/
<>	156:95d6b41a828b	715	__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	716	{
<>	156:95d6b41a828b	717	SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
<>	156:95d6b41a828b	718	}
<>	156:95d6b41a828b	719
<>	156:95d6b41a828b	720	/**
<>	156:95d6b41a828b	721	* @brief Disable CRC
<>	156:95d6b41a828b	722	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
<>	156:95d6b41a828b	723	* @rmtoll CR1 CRCEN LL_SPI_DisableCRC
<>	156:95d6b41a828b	724	* @param SPIx SPI Instance
<>	156:95d6b41a828b	725	* @retval None
<>	156:95d6b41a828b	726	*/
<>	156:95d6b41a828b	727	__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	728	{
<>	156:95d6b41a828b	729	CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
<>	156:95d6b41a828b	730	}
<>	156:95d6b41a828b	731
<>	156:95d6b41a828b	732	/**
<>	156:95d6b41a828b	733	* @brief Check if CRC is enabled
<>	156:95d6b41a828b	734	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
<>	156:95d6b41a828b	735	* @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
<>	156:95d6b41a828b	736	* @param SPIx SPI Instance
<>	156:95d6b41a828b	737	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	738	*/
<>	156:95d6b41a828b	739	__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	740	{
<>	156:95d6b41a828b	741	return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN));
<>	156:95d6b41a828b	742	}
<>	156:95d6b41a828b	743
<>	156:95d6b41a828b	744	/**
<>	156:95d6b41a828b	745	* @brief Set CRC Length
<>	156:95d6b41a828b	746	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
<>	156:95d6b41a828b	747	* @rmtoll CR1 CRCL LL_SPI_SetCRCWidth
<>	156:95d6b41a828b	748	* @param SPIx SPI Instance
<>	156:95d6b41a828b	749	* @param CRCLength This parameter can be one of the following values:
<>	156:95d6b41a828b	750	* @arg @ref LL_SPI_CRC_8BIT
<>	156:95d6b41a828b	751	* @arg @ref LL_SPI_CRC_16BIT
<>	156:95d6b41a828b	752	* @retval None
<>	156:95d6b41a828b	753	*/
<>	156:95d6b41a828b	754	__STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
<>	156:95d6b41a828b	755	{
<>	156:95d6b41a828b	756	MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength);
<>	156:95d6b41a828b	757	}
<>	156:95d6b41a828b	758
<>	156:95d6b41a828b	759	/**
<>	156:95d6b41a828b	760	* @brief Get CRC Length
<>	156:95d6b41a828b	761	* @rmtoll CR1 CRCL LL_SPI_GetCRCWidth
<>	156:95d6b41a828b	762	* @param SPIx SPI Instance
<>	156:95d6b41a828b	763	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	764	* @arg @ref LL_SPI_CRC_8BIT
<>	156:95d6b41a828b	765	* @arg @ref LL_SPI_CRC_16BIT
<>	156:95d6b41a828b	766	*/
<>	156:95d6b41a828b	767	__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	768	{
<>	156:95d6b41a828b	769	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL));
<>	156:95d6b41a828b	770	}
<>	156:95d6b41a828b	771
<>	156:95d6b41a828b	772	/**
<>	156:95d6b41a828b	773	* @brief Set CRCNext to transfer CRC on the line
<>	156:95d6b41a828b	774	* @note This bit has to be written as soon as the last data is written in the SPIx_DR register.
<>	156:95d6b41a828b	775	* @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
<>	156:95d6b41a828b	776	* @param SPIx SPI Instance
<>	156:95d6b41a828b	777	* @retval None
<>	156:95d6b41a828b	778	*/
<>	156:95d6b41a828b	779	__STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	780	{
<>	156:95d6b41a828b	781	SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
<>	156:95d6b41a828b	782	}
<>	156:95d6b41a828b	783
<>	156:95d6b41a828b	784	/**
<>	156:95d6b41a828b	785	* @brief Set polynomial for CRC calculation
<>	156:95d6b41a828b	786	* @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
<>	156:95d6b41a828b	787	* @param SPIx SPI Instance
<>	156:95d6b41a828b	788	* @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
<>	156:95d6b41a828b	789	* @retval None
<>	156:95d6b41a828b	790	*/
<>	156:95d6b41a828b	791	__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
<>	156:95d6b41a828b	792	{
<>	156:95d6b41a828b	793	WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
<>	156:95d6b41a828b	794	}
<>	156:95d6b41a828b	795
<>	156:95d6b41a828b	796	/**
<>	156:95d6b41a828b	797	* @brief Get polynomial for CRC calculation
<>	156:95d6b41a828b	798	* @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
<>	156:95d6b41a828b	799	* @param SPIx SPI Instance
<>	156:95d6b41a828b	800	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
<>	156:95d6b41a828b	801	*/
<>	156:95d6b41a828b	802	__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	803	{
<>	156:95d6b41a828b	804	return (uint32_t)(READ_REG(SPIx->CRCPR));
<>	156:95d6b41a828b	805	}
<>	156:95d6b41a828b	806
<>	156:95d6b41a828b	807	/**
<>	156:95d6b41a828b	808	* @brief Get Rx CRC
<>	156:95d6b41a828b	809	* @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
<>	156:95d6b41a828b	810	* @param SPIx SPI Instance
<>	156:95d6b41a828b	811	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
<>	156:95d6b41a828b	812	*/
<>	156:95d6b41a828b	813	__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	814	{
<>	156:95d6b41a828b	815	return (uint32_t)(READ_REG(SPIx->RXCRCR));
<>	156:95d6b41a828b	816	}
<>	156:95d6b41a828b	817
<>	156:95d6b41a828b	818	/**
<>	156:95d6b41a828b	819	* @brief Get Tx CRC
<>	156:95d6b41a828b	820	* @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
<>	156:95d6b41a828b	821	* @param SPIx SPI Instance
<>	156:95d6b41a828b	822	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
<>	156:95d6b41a828b	823	*/
<>	156:95d6b41a828b	824	__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	825	{
<>	156:95d6b41a828b	826	return (uint32_t)(READ_REG(SPIx->TXCRCR));
<>	156:95d6b41a828b	827	}
<>	156:95d6b41a828b	828
<>	156:95d6b41a828b	829	/**
<>	156:95d6b41a828b	830	* @}
<>	156:95d6b41a828b	831	*/
<>	156:95d6b41a828b	832
<>	156:95d6b41a828b	833	/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
<>	156:95d6b41a828b	834	* @{
<>	156:95d6b41a828b	835	*/
<>	156:95d6b41a828b	836
<>	156:95d6b41a828b	837	/**
<>	156:95d6b41a828b	838	* @brief Set NSS mode
<>	156:95d6b41a828b	839	* @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
<>	156:95d6b41a828b	840	* @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
<>	156:95d6b41a828b	841	* @rmtoll CR2 SSOE LL_SPI_SetNSSMode
<>	156:95d6b41a828b	842	* @param SPIx SPI Instance
<>	156:95d6b41a828b	843	* @param NSS This parameter can be one of the following values:
<>	156:95d6b41a828b	844	* @arg @ref LL_SPI_NSS_SOFT
<>	156:95d6b41a828b	845	* @arg @ref LL_SPI_NSS_HARD_INPUT
<>	156:95d6b41a828b	846	* @arg @ref LL_SPI_NSS_HARD_OUTPUT
<>	156:95d6b41a828b	847	* @retval None
<>	156:95d6b41a828b	848	*/
<>	156:95d6b41a828b	849	__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
<>	156:95d6b41a828b	850	{
<>	156:95d6b41a828b	851	MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
<>	156:95d6b41a828b	852	MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
<>	156:95d6b41a828b	853	}
<>	156:95d6b41a828b	854
<>	156:95d6b41a828b	855	/**
<>	156:95d6b41a828b	856	* @brief Get NSS mode
<>	156:95d6b41a828b	857	* @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
<>	156:95d6b41a828b	858	* @rmtoll CR2 SSOE LL_SPI_GetNSSMode
<>	156:95d6b41a828b	859	* @param SPIx SPI Instance
<>	156:95d6b41a828b	860	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	861	* @arg @ref LL_SPI_NSS_SOFT
<>	156:95d6b41a828b	862	* @arg @ref LL_SPI_NSS_HARD_INPUT
<>	156:95d6b41a828b	863	* @arg @ref LL_SPI_NSS_HARD_OUTPUT
<>	156:95d6b41a828b	864	*/
<>	156:95d6b41a828b	865	__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	866	{
<>	156:95d6b41a828b	867	register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
<>	156:95d6b41a828b	868	register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
<>	156:95d6b41a828b	869	return (Ssm \| Ssoe);
<>	156:95d6b41a828b	870	}
<>	156:95d6b41a828b	871
<>	156:95d6b41a828b	872	/**
<>	156:95d6b41a828b	873	* @brief Enable NSS pulse management
<>	156:95d6b41a828b	874	* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
<>	156:95d6b41a828b	875	* @rmtoll CR2 NSSP LL_SPI_EnableNSSPulseMgt
<>	156:95d6b41a828b	876	* @param SPIx SPI Instance
<>	156:95d6b41a828b	877	* @retval None
<>	156:95d6b41a828b	878	*/
<>	156:95d6b41a828b	879	__STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	880	{
<>	156:95d6b41a828b	881	SET_BIT(SPIx->CR2, SPI_CR2_NSSP);
<>	156:95d6b41a828b	882	}
<>	156:95d6b41a828b	883
<>	156:95d6b41a828b	884	/**
<>	156:95d6b41a828b	885	* @brief Disable NSS pulse management
<>	156:95d6b41a828b	886	* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
<>	156:95d6b41a828b	887	* @rmtoll CR2 NSSP LL_SPI_DisableNSSPulseMgt
<>	156:95d6b41a828b	888	* @param SPIx SPI Instance
<>	156:95d6b41a828b	889	* @retval None
<>	156:95d6b41a828b	890	*/
<>	156:95d6b41a828b	891	__STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	892	{
<>	156:95d6b41a828b	893	CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP);
<>	156:95d6b41a828b	894	}
<>	156:95d6b41a828b	895
<>	156:95d6b41a828b	896	/**
<>	156:95d6b41a828b	897	* @brief Check if NSS pulse is enabled
<>	156:95d6b41a828b	898	* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
<>	156:95d6b41a828b	899	* @rmtoll CR2 NSSP LL_SPI_IsEnabledNSSPulse
<>	156:95d6b41a828b	900	* @param SPIx SPI Instance
<>	156:95d6b41a828b	901	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	902	*/
<>	156:95d6b41a828b	903	__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	904	{
<>	156:95d6b41a828b	905	return (READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP));
<>	156:95d6b41a828b	906	}
<>	156:95d6b41a828b	907
<>	156:95d6b41a828b	908	/**
<>	156:95d6b41a828b	909	* @}
<>	156:95d6b41a828b	910	*/
<>	156:95d6b41a828b	911
<>	156:95d6b41a828b	912	/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
<>	156:95d6b41a828b	913	* @{
<>	156:95d6b41a828b	914	*/
<>	156:95d6b41a828b	915
<>	156:95d6b41a828b	916	/**
<>	156:95d6b41a828b	917	* @brief Check if Rx buffer is not empty
<>	156:95d6b41a828b	918	* @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
<>	156:95d6b41a828b	919	* @param SPIx SPI Instance
<>	156:95d6b41a828b	920	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	921	*/
<>	156:95d6b41a828b	922	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	923	{
<>	156:95d6b41a828b	924	return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE));
<>	156:95d6b41a828b	925	}
<>	156:95d6b41a828b	926
<>	156:95d6b41a828b	927	/**
<>	156:95d6b41a828b	928	* @brief Check if Tx buffer is empty
<>	156:95d6b41a828b	929	* @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
<>	156:95d6b41a828b	930	* @param SPIx SPI Instance
<>	156:95d6b41a828b	931	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	932	*/
<>	156:95d6b41a828b	933	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	934	{
<>	156:95d6b41a828b	935	return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE));
<>	156:95d6b41a828b	936	}
<>	156:95d6b41a828b	937
<>	156:95d6b41a828b	938	/**
<>	156:95d6b41a828b	939	* @brief Get CRC error flag
<>	156:95d6b41a828b	940	* @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
<>	156:95d6b41a828b	941	* @param SPIx SPI Instance
<>	156:95d6b41a828b	942	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	943	*/
<>	156:95d6b41a828b	944	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	945	{
<>	156:95d6b41a828b	946	return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR));
<>	156:95d6b41a828b	947	}
<>	156:95d6b41a828b	948
<>	156:95d6b41a828b	949	/**
<>	156:95d6b41a828b	950	* @brief Get mode fault error flag
<>	156:95d6b41a828b	951	* @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
<>	156:95d6b41a828b	952	* @param SPIx SPI Instance
<>	156:95d6b41a828b	953	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	954	*/
<>	156:95d6b41a828b	955	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	956	{
<>	156:95d6b41a828b	957	return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF));
<>	156:95d6b41a828b	958	}
<>	156:95d6b41a828b	959
<>	156:95d6b41a828b	960	/**
<>	156:95d6b41a828b	961	* @brief Get overrun error flag
<>	156:95d6b41a828b	962	* @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
<>	156:95d6b41a828b	963	* @param SPIx SPI Instance
<>	156:95d6b41a828b	964	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	965	*/
<>	156:95d6b41a828b	966	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	967	{
<>	156:95d6b41a828b	968	return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR));
<>	156:95d6b41a828b	969	}
<>	156:95d6b41a828b	970
<>	156:95d6b41a828b	971	/**
<>	156:95d6b41a828b	972	* @brief Get busy flag
<>	156:95d6b41a828b	973	* @note The BSY flag is cleared under any one of the following conditions:
<>	156:95d6b41a828b	974	* -When the SPI is correctly disabled
<>	156:95d6b41a828b	975	* -When a fault is detected in Master mode (MODF bit set to 1)
<>	156:95d6b41a828b	976	* -In Master mode, when it finishes a data transmission and no new data is ready to be
<>	156:95d6b41a828b	977	* sent
<>	156:95d6b41a828b	978	* -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
<>	156:95d6b41a828b	979	* each data transfer.
<>	156:95d6b41a828b	980	* @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
<>	156:95d6b41a828b	981	* @param SPIx SPI Instance
<>	156:95d6b41a828b	982	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	983	*/
<>	156:95d6b41a828b	984	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	985	{
<>	156:95d6b41a828b	986	return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY));
<>	156:95d6b41a828b	987	}
<>	156:95d6b41a828b	988
<>	156:95d6b41a828b	989	/**
<>	156:95d6b41a828b	990	* @brief Get frame format error flag
<>	156:95d6b41a828b	991	* @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE
<>	156:95d6b41a828b	992	* @param SPIx SPI Instance
<>	156:95d6b41a828b	993	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	994	*/
<>	156:95d6b41a828b	995	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	996	{
<>	156:95d6b41a828b	997	return (READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE));
<>	156:95d6b41a828b	998	}
<>	156:95d6b41a828b	999
<>	156:95d6b41a828b	1000	/**
<>	156:95d6b41a828b	1001	* @brief Get FIFO reception Level
<>	156:95d6b41a828b	1002	* @rmtoll SR FRLVL LL_SPI_GetRxFIFOLevel
<>	156:95d6b41a828b	1003	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1004	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	1005	* @arg @ref LL_SPI_RX_FIFO_EMPTY
<>	156:95d6b41a828b	1006	* @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL
<>	156:95d6b41a828b	1007	* @arg @ref LL_SPI_RX_FIFO_HALF_FULL
<>	156:95d6b41a828b	1008	* @arg @ref LL_SPI_RX_FIFO_FULL
<>	156:95d6b41a828b	1009	*/
<>	156:95d6b41a828b	1010	__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	1011	{
<>	156:95d6b41a828b	1012	return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL));
<>	156:95d6b41a828b	1013	}
<>	156:95d6b41a828b	1014
<>	156:95d6b41a828b	1015	/**
<>	156:95d6b41a828b	1016	* @brief Get FIFO Transmission Level
<>	156:95d6b41a828b	1017	* @rmtoll SR FTLVL LL_SPI_GetTxFIFOLevel
<>	156:95d6b41a828b	1018	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1019	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	1020	* @arg @ref LL_SPI_TX_FIFO_EMPTY
<>	156:95d6b41a828b	1021	* @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL
<>	156:95d6b41a828b	1022	* @arg @ref LL_SPI_TX_FIFO_HALF_FULL
<>	156:95d6b41a828b	1023	* @arg @ref LL_SPI_TX_FIFO_FULL
<>	156:95d6b41a828b	1024	*/
<>	156:95d6b41a828b	1025	__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	1026	{
<>	156:95d6b41a828b	1027	return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL));
<>	156:95d6b41a828b	1028	}
<>	156:95d6b41a828b	1029
<>	156:95d6b41a828b	1030	/**
<>	156:95d6b41a828b	1031	* @brief Clear CRC error flag
<>	156:95d6b41a828b	1032	* @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
<>	156:95d6b41a828b	1033	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1034	* @retval None
<>	156:95d6b41a828b	1035	*/
<>	156:95d6b41a828b	1036	__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	1037	{
<>	156:95d6b41a828b	1038	CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
<>	156:95d6b41a828b	1039	}
<>	156:95d6b41a828b	1040
<>	156:95d6b41a828b	1041	/**
<>	156:95d6b41a828b	1042	* @brief Clear mode fault error flag
<>	156:95d6b41a828b	1043	* @note Clearing this flag is done by a read access to the SPIx_SR
<>	156:95d6b41a828b	1044	* register followed by a write access to the SPIx_CR1 register
<>	156:95d6b41a828b	1045	* @rmtoll SR MODF LL_SPI_ClearFlag_MODF
<>	156:95d6b41a828b	1046	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1047	* @retval None
<>	156:95d6b41a828b	1048	*/
<>	156:95d6b41a828b	1049	__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	1050	{
<>	156:95d6b41a828b	1051	__IO uint32_t tmpreg;
<>	156:95d6b41a828b	1052	tmpreg = SPIx->SR;
<>	156:95d6b41a828b	1053	(void) tmpreg;
<>	156:95d6b41a828b	1054	tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
<>	156:95d6b41a828b	1055	(void) tmpreg;
<>	156:95d6b41a828b	1056	}
<>	156:95d6b41a828b	1057
<>	156:95d6b41a828b	1058	/**
<>	156:95d6b41a828b	1059	* @brief Clear overrun error flag
<>	156:95d6b41a828b	1060	* @note Clearing this flag is done by a read access to the SPIx_DR
<>	156:95d6b41a828b	1061	* register followed by a read access to the SPIx_SR register
<>	156:95d6b41a828b	1062	* @rmtoll SR OVR LL_SPI_ClearFlag_OVR
<>	156:95d6b41a828b	1063	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1064	* @retval None
<>	156:95d6b41a828b	1065	*/
<>	156:95d6b41a828b	1066	__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	1067	{
<>	156:95d6b41a828b	1068	__IO uint32_t tmpreg;
<>	156:95d6b41a828b	1069	tmpreg = SPIx->DR;
<>	156:95d6b41a828b	1070	(void) tmpreg;
<>	156:95d6b41a828b	1071	tmpreg = SPIx->SR;
<>	156:95d6b41a828b	1072	(void) tmpreg;
<>	156:95d6b41a828b	1073	}
<>	156:95d6b41a828b	1074
<>	156:95d6b41a828b	1075	/**
<>	156:95d6b41a828b	1076	* @brief Clear frame format error flag
<>	156:95d6b41a828b	1077	* @note Clearing this flag is done by reading SPIx_SR register
<>	156:95d6b41a828b	1078	* @rmtoll SR FRE LL_SPI_ClearFlag_FRE
<>	156:95d6b41a828b	1079	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1080	* @retval None
<>	156:95d6b41a828b	1081	*/
<>	156:95d6b41a828b	1082	__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	1083	{
<>	156:95d6b41a828b	1084	__IO uint32_t tmpreg;
<>	156:95d6b41a828b	1085	tmpreg = SPIx->SR;
<>	156:95d6b41a828b	1086	(void) tmpreg;
<>	156:95d6b41a828b	1087	}
<>	156:95d6b41a828b	1088
<>	156:95d6b41a828b	1089	/**
<>	156:95d6b41a828b	1090	* @}
<>	156:95d6b41a828b	1091	*/
<>	156:95d6b41a828b	1092
<>	156:95d6b41a828b	1093	/** @defgroup SPI_LL_EF_IT_Management Interrupt Management
<>	156:95d6b41a828b	1094	* @{
<>	156:95d6b41a828b	1095	*/
<>	156:95d6b41a828b	1096
<>	156:95d6b41a828b	1097	/**
<>	156:95d6b41a828b	1098	* @brief Enable error interrupt
<>	156:95d6b41a828b	1099	* @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
<>	156:95d6b41a828b	1100	* @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
<>	156:95d6b41a828b	1101	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1102	* @retval None
<>	156:95d6b41a828b	1103	*/
<>	156:95d6b41a828b	1104	__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	1105	{
<>	156:95d6b41a828b	1106	SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
<>	156:95d6b41a828b	1107	}
<>	156:95d6b41a828b	1108
<>	156:95d6b41a828b	1109	/**
<>	156:95d6b41a828b	1110	* @brief Enable Rx buffer not empty interrupt
<>	156:95d6b41a828b	1111	* @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
<>	156:95d6b41a828b	1112	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1113	* @retval None
<>	156:95d6b41a828b	1114	*/
<>	156:95d6b41a828b	1115	__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	1116	{
<>	156:95d6b41a828b	1117	SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
<>	156:95d6b41a828b	1118	}
<>	156:95d6b41a828b	1119
<>	156:95d6b41a828b	1120	/**
<>	156:95d6b41a828b	1121	* @brief Enable Tx buffer empty interrupt
<>	156:95d6b41a828b	1122	* @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
<>	156:95d6b41a828b	1123	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1124	* @retval None
<>	156:95d6b41a828b	1125	*/
<>	156:95d6b41a828b	1126	__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	1127	{
<>	156:95d6b41a828b	1128	SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
<>	156:95d6b41a828b	1129	}
<>	156:95d6b41a828b	1130
<>	156:95d6b41a828b	1131	/**
<>	156:95d6b41a828b	1132	* @brief Disable error interrupt
<>	156:95d6b41a828b	1133	* @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
<>	156:95d6b41a828b	1134	* @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
<>	156:95d6b41a828b	1135	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1136	* @retval None
<>	156:95d6b41a828b	1137	*/
<>	156:95d6b41a828b	1138	__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	1139	{
<>	156:95d6b41a828b	1140	CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
<>	156:95d6b41a828b	1141	}
<>	156:95d6b41a828b	1142
<>	156:95d6b41a828b	1143	/**
<>	156:95d6b41a828b	1144	* @brief Disable Rx buffer not empty interrupt
<>	156:95d6b41a828b	1145	* @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
<>	156:95d6b41a828b	1146	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1147	* @retval None
<>	156:95d6b41a828b	1148	*/
<>	156:95d6b41a828b	1149	__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	1150	{
<>	156:95d6b41a828b	1151	CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
<>	156:95d6b41a828b	1152	}
<>	156:95d6b41a828b	1153
<>	156:95d6b41a828b	1154	/**
<>	156:95d6b41a828b	1155	* @brief Disable Tx buffer empty interrupt
<>	156:95d6b41a828b	1156	* @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
<>	156:95d6b41a828b	1157	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1158	* @retval None
<>	156:95d6b41a828b	1159	*/
<>	156:95d6b41a828b	1160	__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	1161	{
<>	156:95d6b41a828b	1162	CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
<>	156:95d6b41a828b	1163	}
<>	156:95d6b41a828b	1164
<>	156:95d6b41a828b	1165	/**
<>	156:95d6b41a828b	1166	* @brief Check if error interrupt is enabled
<>	156:95d6b41a828b	1167	* @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
<>	156:95d6b41a828b	1168	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1169	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1170	*/
<>	156:95d6b41a828b	1171	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	1172	{
<>	156:95d6b41a828b	1173	return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE));
<>	156:95d6b41a828b	1174	}
<>	156:95d6b41a828b	1175
<>	156:95d6b41a828b	1176	/**
<>	156:95d6b41a828b	1177	* @brief Check if Rx buffer not empty interrupt is enabled
<>	156:95d6b41a828b	1178	* @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
<>	156:95d6b41a828b	1179	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1180	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1181	*/
<>	156:95d6b41a828b	1182	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	1183	{
<>	156:95d6b41a828b	1184	return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE));
<>	156:95d6b41a828b	1185	}
<>	156:95d6b41a828b	1186
<>	156:95d6b41a828b	1187	/**
<>	156:95d6b41a828b	1188	* @brief Check if Tx buffer empty interrupt
<>	156:95d6b41a828b	1189	* @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
<>	156:95d6b41a828b	1190	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1191	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1192	*/
<>	156:95d6b41a828b	1193	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	1194	{
<>	156:95d6b41a828b	1195	return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE));
<>	156:95d6b41a828b	1196	}
<>	156:95d6b41a828b	1197
<>	156:95d6b41a828b	1198	/**
<>	156:95d6b41a828b	1199	* @}
<>	156:95d6b41a828b	1200	*/
<>	156:95d6b41a828b	1201
<>	156:95d6b41a828b	1202	/** @defgroup SPI_LL_EF_DMA_Management DMA Management
<>	156:95d6b41a828b	1203	* @{
<>	156:95d6b41a828b	1204	*/
<>	156:95d6b41a828b	1205
<>	156:95d6b41a828b	1206	/**
<>	156:95d6b41a828b	1207	* @brief Enable DMA Rx
<>	156:95d6b41a828b	1208	* @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
<>	156:95d6b41a828b	1209	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1210	* @retval None
<>	156:95d6b41a828b	1211	*/
<>	156:95d6b41a828b	1212	__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	1213	{
<>	156:95d6b41a828b	1214	SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
<>	156:95d6b41a828b	1215	}
<>	156:95d6b41a828b	1216
<>	156:95d6b41a828b	1217	/**
<>	156:95d6b41a828b	1218	* @brief Disable DMA Rx
<>	156:95d6b41a828b	1219	* @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
<>	156:95d6b41a828b	1220	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1221	* @retval None
<>	156:95d6b41a828b	1222	*/
<>	156:95d6b41a828b	1223	__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	1224	{
<>	156:95d6b41a828b	1225	CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
<>	156:95d6b41a828b	1226	}
<>	156:95d6b41a828b	1227
<>	156:95d6b41a828b	1228	/**
<>	156:95d6b41a828b	1229	* @brief Check if DMA Rx is enabled
<>	156:95d6b41a828b	1230	* @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
<>	156:95d6b41a828b	1231	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1232	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1233	*/
<>	156:95d6b41a828b	1234	__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	1235	{
<>	156:95d6b41a828b	1236	return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN));
<>	156:95d6b41a828b	1237	}
<>	156:95d6b41a828b	1238
<>	156:95d6b41a828b	1239	/**
<>	156:95d6b41a828b	1240	* @brief Enable DMA Tx
<>	156:95d6b41a828b	1241	* @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
<>	156:95d6b41a828b	1242	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1243	* @retval None
<>	156:95d6b41a828b	1244	*/
<>	156:95d6b41a828b	1245	__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	1246	{
<>	156:95d6b41a828b	1247	SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
<>	156:95d6b41a828b	1248	}
<>	156:95d6b41a828b	1249
<>	156:95d6b41a828b	1250	/**
<>	156:95d6b41a828b	1251	* @brief Disable DMA Tx
<>	156:95d6b41a828b	1252	* @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
<>	156:95d6b41a828b	1253	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1254	* @retval None
<>	156:95d6b41a828b	1255	*/
<>	156:95d6b41a828b	1256	__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	1257	{
<>	156:95d6b41a828b	1258	CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
<>	156:95d6b41a828b	1259	}
<>	156:95d6b41a828b	1260
<>	156:95d6b41a828b	1261	/**
<>	156:95d6b41a828b	1262	* @brief Check if DMA Tx is enabled
<>	156:95d6b41a828b	1263	* @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
<>	156:95d6b41a828b	1264	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1265	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1266	*/
<>	156:95d6b41a828b	1267	__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	1268	{
<>	156:95d6b41a828b	1269	return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN));
<>	156:95d6b41a828b	1270	}
<>	156:95d6b41a828b	1271
<>	156:95d6b41a828b	1272	/**
<>	156:95d6b41a828b	1273	* @brief Set parity of Last DMA reception
<>	156:95d6b41a828b	1274	* @rmtoll CR2 LDMARX LL_SPI_SetDMAParity_RX
<>	156:95d6b41a828b	1275	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1276	* @param Parity This parameter can be one of the following values:
<>	156:95d6b41a828b	1277	* @arg @ref LL_SPI_DMA_PARITY_ODD
<>	156:95d6b41a828b	1278	* @arg @ref LL_SPI_DMA_PARITY_EVEN
<>	156:95d6b41a828b	1279	* @retval None
<>	156:95d6b41a828b	1280	*/
<>	156:95d6b41a828b	1281	__STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity)
<>	156:95d6b41a828b	1282	{
Anna Bridge	180:96ed750bd169	1283	MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << SPI_CR2_LDMARX_Pos));
<>	156:95d6b41a828b	1284	}
<>	156:95d6b41a828b	1285
<>	156:95d6b41a828b	1286	/**
<>	156:95d6b41a828b	1287	* @brief Get parity configuration for Last DMA reception
<>	156:95d6b41a828b	1288	* @rmtoll CR2 LDMARX LL_SPI_GetDMAParity_RX
<>	156:95d6b41a828b	1289	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1290	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	1291	* @arg @ref LL_SPI_DMA_PARITY_ODD
<>	156:95d6b41a828b	1292	* @arg @ref LL_SPI_DMA_PARITY_EVEN
<>	156:95d6b41a828b	1293	*/
<>	156:95d6b41a828b	1294	__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	1295	{
Anna Bridge	180:96ed750bd169	1296	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos);
<>	156:95d6b41a828b	1297	}
<>	156:95d6b41a828b	1298
<>	156:95d6b41a828b	1299	/**
<>	156:95d6b41a828b	1300	* @brief Set parity of Last DMA transmission
<>	156:95d6b41a828b	1301	* @rmtoll CR2 LDMATX LL_SPI_SetDMAParity_TX
<>	156:95d6b41a828b	1302	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1303	* @param Parity This parameter can be one of the following values:
<>	156:95d6b41a828b	1304	* @arg @ref LL_SPI_DMA_PARITY_ODD
<>	156:95d6b41a828b	1305	* @arg @ref LL_SPI_DMA_PARITY_EVEN
<>	156:95d6b41a828b	1306	* @retval None
<>	156:95d6b41a828b	1307	*/
<>	156:95d6b41a828b	1308	__STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity)
<>	156:95d6b41a828b	1309	{
Anna Bridge	180:96ed750bd169	1310	MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << SPI_CR2_LDMATX_Pos));
<>	156:95d6b41a828b	1311	}
<>	156:95d6b41a828b	1312
<>	156:95d6b41a828b	1313	/**
<>	156:95d6b41a828b	1314	* @brief Get parity configuration for Last DMA transmission
<>	156:95d6b41a828b	1315	* @rmtoll CR2 LDMATX LL_SPI_GetDMAParity_TX
<>	156:95d6b41a828b	1316	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1317	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	1318	* @arg @ref LL_SPI_DMA_PARITY_ODD
<>	156:95d6b41a828b	1319	* @arg @ref LL_SPI_DMA_PARITY_EVEN
<>	156:95d6b41a828b	1320	*/
<>	156:95d6b41a828b	1321	__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	1322	{
Anna Bridge	180:96ed750bd169	1323	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos);
<>	156:95d6b41a828b	1324	}
<>	156:95d6b41a828b	1325
<>	156:95d6b41a828b	1326	/**
<>	156:95d6b41a828b	1327	* @brief Get the data register address used for DMA transfer
<>	156:95d6b41a828b	1328	* @rmtoll DR DR LL_SPI_DMA_GetRegAddr
<>	156:95d6b41a828b	1329	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1330	* @retval Address of data register
<>	156:95d6b41a828b	1331	*/
<>	156:95d6b41a828b	1332	__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	1333	{
<>	156:95d6b41a828b	1334	return (uint32_t) & (SPIx->DR);
<>	156:95d6b41a828b	1335	}
<>	156:95d6b41a828b	1336
<>	156:95d6b41a828b	1337	/**
<>	156:95d6b41a828b	1338	* @}
<>	156:95d6b41a828b	1339	*/
<>	156:95d6b41a828b	1340
<>	156:95d6b41a828b	1341	/** @defgroup SPI_LL_EF_DATA_Management DATA Management
<>	156:95d6b41a828b	1342	* @{
<>	156:95d6b41a828b	1343	*/
<>	156:95d6b41a828b	1344
<>	156:95d6b41a828b	1345	/**
<>	156:95d6b41a828b	1346	* @brief Read 8-Bits in the data register
<>	156:95d6b41a828b	1347	* @rmtoll DR DR LL_SPI_ReceiveData8
<>	156:95d6b41a828b	1348	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1349	* @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
<>	156:95d6b41a828b	1350	*/
<>	156:95d6b41a828b	1351	__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	1352	{
<>	156:95d6b41a828b	1353	return (uint8_t)(READ_REG(SPIx->DR));
<>	156:95d6b41a828b	1354	}
<>	156:95d6b41a828b	1355
<>	156:95d6b41a828b	1356	/**
<>	156:95d6b41a828b	1357	* @brief Read 16-Bits in the data register
<>	156:95d6b41a828b	1358	* @rmtoll DR DR LL_SPI_ReceiveData16
<>	156:95d6b41a828b	1359	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1360	* @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
<>	156:95d6b41a828b	1361	*/
<>	156:95d6b41a828b	1362	__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	1363	{
<>	156:95d6b41a828b	1364	return (uint16_t)(READ_REG(SPIx->DR));
<>	156:95d6b41a828b	1365	}
<>	156:95d6b41a828b	1366
<>	156:95d6b41a828b	1367	/**
<>	156:95d6b41a828b	1368	* @brief Write 8-Bits in the data register
<>	156:95d6b41a828b	1369	* @rmtoll DR DR LL_SPI_TransmitData8
<>	156:95d6b41a828b	1370	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1371	* @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
<>	156:95d6b41a828b	1372	* @retval None
<>	156:95d6b41a828b	1373	*/
<>	156:95d6b41a828b	1374	__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
<>	156:95d6b41a828b	1375	{
<>	156:95d6b41a828b	1376	((__IO uint8_t )&SPIx->DR) = TxData;
<>	156:95d6b41a828b	1377	}
<>	156:95d6b41a828b	1378
Anna Bridge	186:707f6e361f3e	1379	#if __GNUC__
Anna Bridge	186:707f6e361f3e	1380	# define MAY_ALIAS __attribute__ ((__may_alias__))
Anna Bridge	186:707f6e361f3e	1381	#else
Anna Bridge	186:707f6e361f3e	1382	# define MAY_ALIAS
Anna Bridge	186:707f6e361f3e	1383	#endif
Anna Bridge	186:707f6e361f3e	1384
Anna Bridge	186:707f6e361f3e	1385	typedef __IO uint16_t MAY_ALIAS uint16_io_t;
Anna Bridge	186:707f6e361f3e	1386
<>	156:95d6b41a828b	1387	/**
<>	156:95d6b41a828b	1388	* @brief Write 16-Bits in the data register
<>	156:95d6b41a828b	1389	* @rmtoll DR DR LL_SPI_TransmitData16
<>	156:95d6b41a828b	1390	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1391	* @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
<>	156:95d6b41a828b	1392	* @retval None
<>	156:95d6b41a828b	1393	*/
<>	156:95d6b41a828b	1394	__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
<>	156:95d6b41a828b	1395	{
Anna Bridge	186:707f6e361f3e	1396	((uint16_io_t)&SPIx->DR) = TxData;
<>	156:95d6b41a828b	1397	}
<>	156:95d6b41a828b	1398
<>	156:95d6b41a828b	1399	/**
<>	156:95d6b41a828b	1400	* @}
<>	156:95d6b41a828b	1401	*/
<>	156:95d6b41a828b	1402	#if defined(USE_FULL_LL_DRIVER)
<>	156:95d6b41a828b	1403	/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
<>	156:95d6b41a828b	1404	* @{
<>	156:95d6b41a828b	1405	*/
<>	156:95d6b41a828b	1406
<>	156:95d6b41a828b	1407	ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
<>	156:95d6b41a828b	1408	ErrorStatus LL_SPI_Init(SPI_TypeDef SPIx, LL_SPI_InitTypeDef SPI_InitStruct);
<>	156:95d6b41a828b	1409	void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
<>	156:95d6b41a828b	1410
<>	156:95d6b41a828b	1411	/**
<>	156:95d6b41a828b	1412	* @}
<>	156:95d6b41a828b	1413	*/
<>	156:95d6b41a828b	1414	#endif /* USE_FULL_LL_DRIVER */
<>	156:95d6b41a828b	1415	/**
<>	156:95d6b41a828b	1416	* @}
<>	156:95d6b41a828b	1417	*/
<>	156:95d6b41a828b	1418
<>	156:95d6b41a828b	1419	/**
<>	156:95d6b41a828b	1420	* @}
<>	156:95d6b41a828b	1421	*/
<>	156:95d6b41a828b	1422
<>	156:95d6b41a828b	1423	#if defined(SPI_I2S_SUPPORT)
<>	156:95d6b41a828b	1424	/** @defgroup I2S_LL I2S
<>	156:95d6b41a828b	1425	* @{
<>	156:95d6b41a828b	1426	*/
<>	156:95d6b41a828b	1427
<>	156:95d6b41a828b	1428	/* Private variables ---------------------------------------------------------*/
<>	156:95d6b41a828b	1429	/* Private constants ---------------------------------------------------------*/
<>	156:95d6b41a828b	1430	/* Private macros ------------------------------------------------------------*/
<>	156:95d6b41a828b	1431
<>	156:95d6b41a828b	1432	/* Exported types ------------------------------------------------------------*/
<>	156:95d6b41a828b	1433	#if defined(USE_FULL_LL_DRIVER)
<>	156:95d6b41a828b	1434	/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
<>	156:95d6b41a828b	1435	* @{
<>	156:95d6b41a828b	1436	*/
<>	156:95d6b41a828b	1437
<>	156:95d6b41a828b	1438	/**
<>	156:95d6b41a828b	1439	* @brief I2S Init structure definition
<>	156:95d6b41a828b	1440	*/
<>	156:95d6b41a828b	1441
<>	156:95d6b41a828b	1442	typedef struct
<>	156:95d6b41a828b	1443	{
<>	156:95d6b41a828b	1444	uint32_t Mode; /*!< Specifies the I2S operating mode.
<>	156:95d6b41a828b	1445	This parameter can be a value of @ref I2S_LL_EC_MODE
<>	156:95d6b41a828b	1446
<>	156:95d6b41a828b	1447	This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
<>	156:95d6b41a828b	1448
<>	156:95d6b41a828b	1449	uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
<>	156:95d6b41a828b	1450	This parameter can be a value of @ref I2S_LL_EC_STANDARD
<>	156:95d6b41a828b	1451
<>	156:95d6b41a828b	1452	This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
<>	156:95d6b41a828b	1453
<>	156:95d6b41a828b	1454
<>	156:95d6b41a828b	1455	uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
<>	156:95d6b41a828b	1456	This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
<>	156:95d6b41a828b	1457
<>	156:95d6b41a828b	1458	This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
<>	156:95d6b41a828b	1459
<>	156:95d6b41a828b	1460
<>	156:95d6b41a828b	1461	uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
<>	156:95d6b41a828b	1462	This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
<>	156:95d6b41a828b	1463
<>	156:95d6b41a828b	1464	This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
<>	156:95d6b41a828b	1465
<>	156:95d6b41a828b	1466
<>	156:95d6b41a828b	1467	uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
<>	156:95d6b41a828b	1468	This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
<>	156:95d6b41a828b	1469
<>	156:95d6b41a828b	1470	Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
<>	156:95d6b41a828b	1471	and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
<>	156:95d6b41a828b	1472
<>	156:95d6b41a828b	1473
<>	156:95d6b41a828b	1474	uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
<>	156:95d6b41a828b	1475	This parameter can be a value of @ref I2S_LL_EC_POLARITY
<>	156:95d6b41a828b	1476
<>	156:95d6b41a828b	1477	This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
<>	156:95d6b41a828b	1478
<>	156:95d6b41a828b	1479	} LL_I2S_InitTypeDef;
<>	156:95d6b41a828b	1480
<>	156:95d6b41a828b	1481	/**
<>	156:95d6b41a828b	1482	* @}
<>	156:95d6b41a828b	1483	*/
<>	156:95d6b41a828b	1484	#endif /USE_FULL_LL_DRIVER/
<>	156:95d6b41a828b	1485
<>	156:95d6b41a828b	1486	/* Exported constants --------------------------------------------------------*/
<>	156:95d6b41a828b	1487	/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
<>	156:95d6b41a828b	1488	* @{
<>	156:95d6b41a828b	1489	*/
<>	156:95d6b41a828b	1490
<>	156:95d6b41a828b	1491	/** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
<>	156:95d6b41a828b	1492	* @brief Flags defines which can be used with LL_I2S_ReadReg function
<>	156:95d6b41a828b	1493	* @{
<>	156:95d6b41a828b	1494	*/
<>	156:95d6b41a828b	1495	#define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /!< Rx buffer not empty flag /
<>	156:95d6b41a828b	1496	#define LL_I2S_SR_TXE LL_SPI_SR_TXE /!< Tx buffer empty flag /
<>	156:95d6b41a828b	1497	#define LL_I2S_SR_BSY LL_SPI_SR_BSY /!< Busy flag /
Anna Bridge	180:96ed750bd169	1498	#define LL_I2S_SR_UDR SPI_SR_UDR /!< Underrun flag /
<>	156:95d6b41a828b	1499	#define LL_I2S_SR_OVR LL_SPI_SR_OVR /!< Overrun flag /
<>	156:95d6b41a828b	1500	#define LL_I2S_SR_FRE LL_SPI_SR_FRE /!< TI mode frame format error flag /
<>	156:95d6b41a828b	1501	/**
<>	156:95d6b41a828b	1502	* @}
<>	156:95d6b41a828b	1503	*/
<>	156:95d6b41a828b	1504
<>	156:95d6b41a828b	1505	/** @defgroup SPI_LL_EC_IT IT Defines
<>	156:95d6b41a828b	1506	* @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
<>	156:95d6b41a828b	1507	* @{
<>	156:95d6b41a828b	1508	*/
<>	156:95d6b41a828b	1509	#define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /!< Rx buffer not empty interrupt enable /
<>	156:95d6b41a828b	1510	#define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /!< Tx buffer empty interrupt enable /
<>	156:95d6b41a828b	1511	#define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /!< Error interrupt enable /
<>	156:95d6b41a828b	1512	/**
<>	156:95d6b41a828b	1513	* @}
<>	156:95d6b41a828b	1514	*/
<>	156:95d6b41a828b	1515
<>	156:95d6b41a828b	1516	/** @defgroup I2S_LL_EC_DATA_FORMAT Data format
<>	156:95d6b41a828b	1517	* @{
<>	156:95d6b41a828b	1518	*/
Anna Bridge	180:96ed750bd169	1519	#define LL_I2S_DATAFORMAT_16B 0x00000000U /!< Data length 16 bits, Channel lenght 16bit /
<>	156:95d6b41a828b	1520	#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /!< Data length 16 bits, Channel lenght 32bit /
<>	156:95d6b41a828b	1521	#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATLEN_0) /!< Data length 24 bits, Channel lenght 32bit /
<>	156:95d6b41a828b	1522	#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATLEN_1) /!< Data length 16 bits, Channel lenght 32bit /
<>	156:95d6b41a828b	1523	/**
<>	156:95d6b41a828b	1524	* @}
<>	156:95d6b41a828b	1525	*/
<>	156:95d6b41a828b	1526
<>	156:95d6b41a828b	1527	/** @defgroup I2S_LL_EC_POLARITY Clock Polarity
<>	156:95d6b41a828b	1528	* @{
<>	156:95d6b41a828b	1529	*/
Anna Bridge	180:96ed750bd169	1530	#define LL_I2S_POLARITY_LOW 0x00000000U /!< Clock steady state is low level /
<>	156:95d6b41a828b	1531	#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /!< Clock steady state is high level /
<>	156:95d6b41a828b	1532	/**
<>	156:95d6b41a828b	1533	* @}
<>	156:95d6b41a828b	1534	*/
<>	156:95d6b41a828b	1535
<>	156:95d6b41a828b	1536	/** @defgroup I2S_LL_EC_STANDARD I2s Standard
<>	156:95d6b41a828b	1537	* @{
<>	156:95d6b41a828b	1538	*/
Anna Bridge	180:96ed750bd169	1539	#define LL_I2S_STANDARD_PHILIPS 0x00000000U /!< I2S standard philips /
<>	156:95d6b41a828b	1540	#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /!< MSB justified standard (left justified) /
<>	156:95d6b41a828b	1541	#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /!< LSB justified standard (right justified) /
<>	156:95d6b41a828b	1542	#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 \| SPI_I2SCFGR_I2SSTD_1) /!< PCM standard, short frame synchronization /
<>	156:95d6b41a828b	1543	#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 \| SPI_I2SCFGR_I2SSTD_1 \| SPI_I2SCFGR_PCMSYNC) /!< PCM standard, long frame synchronization /
<>	156:95d6b41a828b	1544	/**
<>	156:95d6b41a828b	1545	* @}
<>	156:95d6b41a828b	1546	*/
<>	156:95d6b41a828b	1547
<>	156:95d6b41a828b	1548	/** @defgroup I2S_LL_EC_MODE Operation Mode
<>	156:95d6b41a828b	1549	* @{
<>	156:95d6b41a828b	1550	*/
Anna Bridge	180:96ed750bd169	1551	#define LL_I2S_MODE_SLAVE_TX 0x00000000U /!< Slave Tx configuration /
<>	156:95d6b41a828b	1552	#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /!< Slave Rx configuration /
<>	156:95d6b41a828b	1553	#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /!< Master Tx configuration /
<>	156:95d6b41a828b	1554	#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 \| SPI_I2SCFGR_I2SCFG_1) /!< Master Rx configuration /
<>	156:95d6b41a828b	1555	/**
<>	156:95d6b41a828b	1556	* @}
<>	156:95d6b41a828b	1557	*/
<>	156:95d6b41a828b	1558
<>	156:95d6b41a828b	1559	/** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
<>	156:95d6b41a828b	1560	* @{
<>	156:95d6b41a828b	1561	*/
Anna Bridge	180:96ed750bd169	1562	#define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /!< Odd factor: Real divider value is = I2SDIV 2 */
<>	156:95d6b41a828b	1563	#define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /!< Odd factor: Real divider value is = (I2SDIV 2)+1 */
<>	156:95d6b41a828b	1564	/**
<>	156:95d6b41a828b	1565	* @}
<>	156:95d6b41a828b	1566	*/
<>	156:95d6b41a828b	1567
<>	156:95d6b41a828b	1568	#if defined(USE_FULL_LL_DRIVER)
<>	156:95d6b41a828b	1569
<>	156:95d6b41a828b	1570	/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
<>	156:95d6b41a828b	1571	* @{
<>	156:95d6b41a828b	1572	*/
Anna Bridge	180:96ed750bd169	1573	#define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /!< Master clock output is disabled /
<>	156:95d6b41a828b	1574	#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /!< Master clock output is enabled /
<>	156:95d6b41a828b	1575	/**
<>	156:95d6b41a828b	1576	* @}
<>	156:95d6b41a828b	1577	*/
<>	156:95d6b41a828b	1578
<>	156:95d6b41a828b	1579	/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
<>	156:95d6b41a828b	1580	* @{
<>	156:95d6b41a828b	1581	*/
<>	156:95d6b41a828b	1582
Anna Bridge	180:96ed750bd169	1583	#define LL_I2S_AUDIOFREQ_192K 192000U /!< Audio Frequency configuration 192000 Hz /
Anna Bridge	180:96ed750bd169	1584	#define LL_I2S_AUDIOFREQ_96K 96000U /!< Audio Frequency configuration 96000 Hz /
Anna Bridge	180:96ed750bd169	1585	#define LL_I2S_AUDIOFREQ_48K 48000U /!< Audio Frequency configuration 48000 Hz /
Anna Bridge	180:96ed750bd169	1586	#define LL_I2S_AUDIOFREQ_44K 44100U /!< Audio Frequency configuration 44100 Hz /
Anna Bridge	180:96ed750bd169	1587	#define LL_I2S_AUDIOFREQ_32K 32000U /!< Audio Frequency configuration 32000 Hz /
Anna Bridge	180:96ed750bd169	1588	#define LL_I2S_AUDIOFREQ_22K 22050U /!< Audio Frequency configuration 22050 Hz /
Anna Bridge	180:96ed750bd169	1589	#define LL_I2S_AUDIOFREQ_16K 16000U /!< Audio Frequency configuration 16000 Hz /
Anna Bridge	180:96ed750bd169	1590	#define LL_I2S_AUDIOFREQ_11K 11025U /!< Audio Frequency configuration 11025 Hz /
Anna Bridge	180:96ed750bd169	1591	#define LL_I2S_AUDIOFREQ_8K 8000U /!< Audio Frequency configuration 8000 Hz /
Anna Bridge	180:96ed750bd169	1592	#define LL_I2S_AUDIOFREQ_DEFAULT 2U /!< Audio Freq not specified. Register I2SDIV = 2 /
<>	156:95d6b41a828b	1593	/**
<>	156:95d6b41a828b	1594	* @}
<>	156:95d6b41a828b	1595	*/
<>	156:95d6b41a828b	1596	#endif /* USE_FULL_LL_DRIVER */
<>	156:95d6b41a828b	1597
<>	156:95d6b41a828b	1598	/**
<>	156:95d6b41a828b	1599	* @}
<>	156:95d6b41a828b	1600	*/
<>	156:95d6b41a828b	1601
<>	156:95d6b41a828b	1602	/* Exported macro ------------------------------------------------------------*/
<>	156:95d6b41a828b	1603	/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
<>	156:95d6b41a828b	1604	* @{
<>	156:95d6b41a828b	1605	*/
<>	156:95d6b41a828b	1606
<>	156:95d6b41a828b	1607	/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
<>	156:95d6b41a828b	1608	* @{
<>	156:95d6b41a828b	1609	*/
<>	156:95d6b41a828b	1610
<>	156:95d6b41a828b	1611	/**
<>	156:95d6b41a828b	1612	* @brief Write a value in I2S register
<>	156:95d6b41a828b	1613	* @param __INSTANCE__ I2S Instance
<>	156:95d6b41a828b	1614	* @param __REG__ Register to be written
<>	156:95d6b41a828b	1615	* @param __VALUE__ Value to be written in the register
<>	156:95d6b41a828b	1616	* @retval None
<>	156:95d6b41a828b	1617	*/
<>	156:95d6b41a828b	1618	#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<>	156:95d6b41a828b	1619
<>	156:95d6b41a828b	1620	/**
<>	156:95d6b41a828b	1621	* @brief Read a value in I2S register
<>	156:95d6b41a828b	1622	* @param __INSTANCE__ I2S Instance
<>	156:95d6b41a828b	1623	* @param __REG__ Register to be read
<>	156:95d6b41a828b	1624	* @retval Register value
<>	156:95d6b41a828b	1625	*/
<>	156:95d6b41a828b	1626	#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<>	156:95d6b41a828b	1627	/**
<>	156:95d6b41a828b	1628	* @}
<>	156:95d6b41a828b	1629	*/
<>	156:95d6b41a828b	1630
<>	156:95d6b41a828b	1631	/**
<>	156:95d6b41a828b	1632	* @}
<>	156:95d6b41a828b	1633	*/
<>	156:95d6b41a828b	1634
<>	156:95d6b41a828b	1635
<>	156:95d6b41a828b	1636	/* Exported functions --------------------------------------------------------*/
<>	156:95d6b41a828b	1637
<>	156:95d6b41a828b	1638	/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
<>	156:95d6b41a828b	1639	* @{
<>	156:95d6b41a828b	1640	*/
<>	156:95d6b41a828b	1641
<>	156:95d6b41a828b	1642	/** @defgroup I2S_LL_EF_Configuration Configuration
<>	156:95d6b41a828b	1643	* @{
<>	156:95d6b41a828b	1644	*/
<>	156:95d6b41a828b	1645
<>	156:95d6b41a828b	1646	/**
<>	156:95d6b41a828b	1647	* @brief Select I2S mode and Enable I2S peripheral
<>	156:95d6b41a828b	1648	* @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
<>	156:95d6b41a828b	1649	* I2SCFGR I2SE LL_I2S_Enable
<>	156:95d6b41a828b	1650	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1651	* @retval None
<>	156:95d6b41a828b	1652	*/
<>	156:95d6b41a828b	1653	__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	1654	{
<>	156:95d6b41a828b	1655	SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD \| SPI_I2SCFGR_I2SE);
<>	156:95d6b41a828b	1656	}
<>	156:95d6b41a828b	1657
<>	156:95d6b41a828b	1658	/**
<>	156:95d6b41a828b	1659	* @brief Disable I2S peripheral
<>	156:95d6b41a828b	1660	* @rmtoll I2SCFGR I2SE LL_I2S_Disable
<>	156:95d6b41a828b	1661	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1662	* @retval None
<>	156:95d6b41a828b	1663	*/
<>	156:95d6b41a828b	1664	__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	1665	{
<>	156:95d6b41a828b	1666	CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD \| SPI_I2SCFGR_I2SE);
<>	156:95d6b41a828b	1667	}
<>	156:95d6b41a828b	1668
<>	156:95d6b41a828b	1669	/**
<>	156:95d6b41a828b	1670	* @brief Check if I2S peripheral is enabled
<>	156:95d6b41a828b	1671	* @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled
<>	156:95d6b41a828b	1672	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1673	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1674	*/
<>	156:95d6b41a828b	1675	__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	1676	{
<>	156:95d6b41a828b	1677	return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE));
<>	156:95d6b41a828b	1678	}
<>	156:95d6b41a828b	1679
<>	156:95d6b41a828b	1680	/**
<>	156:95d6b41a828b	1681	* @brief Set I2S data frame length
<>	156:95d6b41a828b	1682	* @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
<>	156:95d6b41a828b	1683	* I2SCFGR CHLEN LL_I2S_SetDataFormat
<>	156:95d6b41a828b	1684	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1685	* @param DataFormat This parameter can be one of the following values:
<>	156:95d6b41a828b	1686	* @arg @ref LL_I2S_DATAFORMAT_16B
<>	156:95d6b41a828b	1687	* @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
<>	156:95d6b41a828b	1688	* @arg @ref LL_I2S_DATAFORMAT_24B
<>	156:95d6b41a828b	1689	* @arg @ref LL_I2S_DATAFORMAT_32B
<>	156:95d6b41a828b	1690	* @retval None
<>	156:95d6b41a828b	1691	*/
<>	156:95d6b41a828b	1692	__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
<>	156:95d6b41a828b	1693	{
<>	156:95d6b41a828b	1694	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN, DataFormat);
<>	156:95d6b41a828b	1695	}
<>	156:95d6b41a828b	1696
<>	156:95d6b41a828b	1697	/**
<>	156:95d6b41a828b	1698	* @brief Get I2S data frame length
<>	156:95d6b41a828b	1699	* @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
<>	156:95d6b41a828b	1700	* I2SCFGR CHLEN LL_I2S_GetDataFormat
<>	156:95d6b41a828b	1701	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1702	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	1703	* @arg @ref LL_I2S_DATAFORMAT_16B
<>	156:95d6b41a828b	1704	* @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
<>	156:95d6b41a828b	1705	* @arg @ref LL_I2S_DATAFORMAT_24B
<>	156:95d6b41a828b	1706	* @arg @ref LL_I2S_DATAFORMAT_32B
<>	156:95d6b41a828b	1707	*/
<>	156:95d6b41a828b	1708	__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	1709	{
<>	156:95d6b41a828b	1710	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN));
<>	156:95d6b41a828b	1711	}
<>	156:95d6b41a828b	1712
<>	156:95d6b41a828b	1713	/**
<>	156:95d6b41a828b	1714	* @brief Set I2S clock polarity
<>	156:95d6b41a828b	1715	* @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
<>	156:95d6b41a828b	1716	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1717	* @param ClockPolarity This parameter can be one of the following values:
<>	156:95d6b41a828b	1718	* @arg @ref LL_I2S_POLARITY_LOW
<>	156:95d6b41a828b	1719	* @arg @ref LL_I2S_POLARITY_HIGH
<>	156:95d6b41a828b	1720	* @retval None
<>	156:95d6b41a828b	1721	*/
<>	156:95d6b41a828b	1722	__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
<>	156:95d6b41a828b	1723	{
<>	156:95d6b41a828b	1724	SET_BIT(SPIx->I2SCFGR, ClockPolarity);
<>	156:95d6b41a828b	1725	}
<>	156:95d6b41a828b	1726
<>	156:95d6b41a828b	1727	/**
<>	156:95d6b41a828b	1728	* @brief Get I2S clock polarity
<>	156:95d6b41a828b	1729	* @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
<>	156:95d6b41a828b	1730	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1731	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	1732	* @arg @ref LL_I2S_POLARITY_LOW
<>	156:95d6b41a828b	1733	* @arg @ref LL_I2S_POLARITY_HIGH
<>	156:95d6b41a828b	1734	*/
<>	156:95d6b41a828b	1735	__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	1736	{
<>	156:95d6b41a828b	1737	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
<>	156:95d6b41a828b	1738	}
<>	156:95d6b41a828b	1739
<>	156:95d6b41a828b	1740	/**
<>	156:95d6b41a828b	1741	* @brief Set I2S standard protocol
<>	156:95d6b41a828b	1742	* @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
<>	156:95d6b41a828b	1743	* I2SCFGR PCMSYNC LL_I2S_SetStandard
<>	156:95d6b41a828b	1744	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1745	* @param Standard This parameter can be one of the following values:
<>	156:95d6b41a828b	1746	* @arg @ref LL_I2S_STANDARD_PHILIPS
<>	156:95d6b41a828b	1747	* @arg @ref LL_I2S_STANDARD_MSB
<>	156:95d6b41a828b	1748	* @arg @ref LL_I2S_STANDARD_LSB
<>	156:95d6b41a828b	1749	* @arg @ref LL_I2S_STANDARD_PCM_SHORT
<>	156:95d6b41a828b	1750	* @arg @ref LL_I2S_STANDARD_PCM_LONG
<>	156:95d6b41a828b	1751	* @retval None
<>	156:95d6b41a828b	1752	*/
<>	156:95d6b41a828b	1753	__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
<>	156:95d6b41a828b	1754	{
<>	156:95d6b41a828b	1755	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD \| SPI_I2SCFGR_PCMSYNC, Standard);
<>	156:95d6b41a828b	1756	}
<>	156:95d6b41a828b	1757
<>	156:95d6b41a828b	1758	/**
<>	156:95d6b41a828b	1759	* @brief Get I2S standard protocol
<>	156:95d6b41a828b	1760	* @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
<>	156:95d6b41a828b	1761	* I2SCFGR PCMSYNC LL_I2S_GetStandard
<>	156:95d6b41a828b	1762	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1763	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	1764	* @arg @ref LL_I2S_STANDARD_PHILIPS
<>	156:95d6b41a828b	1765	* @arg @ref LL_I2S_STANDARD_MSB
<>	156:95d6b41a828b	1766	* @arg @ref LL_I2S_STANDARD_LSB
<>	156:95d6b41a828b	1767	* @arg @ref LL_I2S_STANDARD_PCM_SHORT
<>	156:95d6b41a828b	1768	* @arg @ref LL_I2S_STANDARD_PCM_LONG
<>	156:95d6b41a828b	1769	*/
<>	156:95d6b41a828b	1770	__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	1771	{
<>	156:95d6b41a828b	1772	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD \| SPI_I2SCFGR_PCMSYNC));
<>	156:95d6b41a828b	1773	}
<>	156:95d6b41a828b	1774
<>	156:95d6b41a828b	1775	/**
<>	156:95d6b41a828b	1776	* @brief Set I2S transfer mode
<>	156:95d6b41a828b	1777	* @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
<>	156:95d6b41a828b	1778	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1779	* @param Mode This parameter can be one of the following values:
<>	156:95d6b41a828b	1780	* @arg @ref LL_I2S_MODE_SLAVE_TX
<>	156:95d6b41a828b	1781	* @arg @ref LL_I2S_MODE_SLAVE_RX
<>	156:95d6b41a828b	1782	* @arg @ref LL_I2S_MODE_MASTER_TX
<>	156:95d6b41a828b	1783	* @arg @ref LL_I2S_MODE_MASTER_RX
<>	156:95d6b41a828b	1784	* @retval None
<>	156:95d6b41a828b	1785	*/
<>	156:95d6b41a828b	1786	__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
<>	156:95d6b41a828b	1787	{
<>	156:95d6b41a828b	1788	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
<>	156:95d6b41a828b	1789	}
<>	156:95d6b41a828b	1790
<>	156:95d6b41a828b	1791	/**
<>	156:95d6b41a828b	1792	* @brief Get I2S transfer mode
<>	156:95d6b41a828b	1793	* @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
<>	156:95d6b41a828b	1794	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1795	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	1796	* @arg @ref LL_I2S_MODE_SLAVE_TX
<>	156:95d6b41a828b	1797	* @arg @ref LL_I2S_MODE_SLAVE_RX
<>	156:95d6b41a828b	1798	* @arg @ref LL_I2S_MODE_MASTER_TX
<>	156:95d6b41a828b	1799	* @arg @ref LL_I2S_MODE_MASTER_RX
<>	156:95d6b41a828b	1800	*/
<>	156:95d6b41a828b	1801	__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	1802	{
<>	156:95d6b41a828b	1803	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
<>	156:95d6b41a828b	1804	}
<>	156:95d6b41a828b	1805
<>	156:95d6b41a828b	1806	/**
<>	156:95d6b41a828b	1807	* @brief Set I2S linear prescaler
<>	156:95d6b41a828b	1808	* @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear
<>	156:95d6b41a828b	1809	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1810	* @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
<>	156:95d6b41a828b	1811	* @retval None
<>	156:95d6b41a828b	1812	*/
<>	156:95d6b41a828b	1813	__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
<>	156:95d6b41a828b	1814	{
<>	156:95d6b41a828b	1815	MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
<>	156:95d6b41a828b	1816	}
<>	156:95d6b41a828b	1817
<>	156:95d6b41a828b	1818	/**
<>	156:95d6b41a828b	1819	* @brief Get I2S linear prescaler
<>	156:95d6b41a828b	1820	* @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear
<>	156:95d6b41a828b	1821	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1822	* @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
<>	156:95d6b41a828b	1823	*/
<>	156:95d6b41a828b	1824	__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	1825	{
<>	156:95d6b41a828b	1826	return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
<>	156:95d6b41a828b	1827	}
<>	156:95d6b41a828b	1828
<>	156:95d6b41a828b	1829	/**
<>	156:95d6b41a828b	1830	* @brief Set I2S parity prescaler
<>	156:95d6b41a828b	1831	* @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity
<>	156:95d6b41a828b	1832	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1833	* @param PrescalerParity This parameter can be one of the following values:
<>	156:95d6b41a828b	1834	* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
<>	156:95d6b41a828b	1835	* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
<>	156:95d6b41a828b	1836	* @retval None
<>	156:95d6b41a828b	1837	*/
<>	156:95d6b41a828b	1838	__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
<>	156:95d6b41a828b	1839	{
<>	156:95d6b41a828b	1840	MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
<>	156:95d6b41a828b	1841	}
<>	156:95d6b41a828b	1842
<>	156:95d6b41a828b	1843	/**
<>	156:95d6b41a828b	1844	* @brief Get I2S parity prescaler
<>	156:95d6b41a828b	1845	* @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity
<>	156:95d6b41a828b	1846	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1847	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	1848	* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
<>	156:95d6b41a828b	1849	* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
<>	156:95d6b41a828b	1850	*/
<>	156:95d6b41a828b	1851	__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	1852	{
<>	156:95d6b41a828b	1853	return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
<>	156:95d6b41a828b	1854	}
<>	156:95d6b41a828b	1855
<>	156:95d6b41a828b	1856	/**
<>	156:95d6b41a828b	1857	* @brief Enable the master clock ouput (Pin MCK)
<>	156:95d6b41a828b	1858	* @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
<>	156:95d6b41a828b	1859	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1860	* @retval None
<>	156:95d6b41a828b	1861	*/
<>	156:95d6b41a828b	1862	__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	1863	{
<>	156:95d6b41a828b	1864	SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
<>	156:95d6b41a828b	1865	}
<>	156:95d6b41a828b	1866
<>	156:95d6b41a828b	1867	/**
<>	156:95d6b41a828b	1868	* @brief Disable the master clock ouput (Pin MCK)
<>	156:95d6b41a828b	1869	* @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
<>	156:95d6b41a828b	1870	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1871	* @retval None
<>	156:95d6b41a828b	1872	*/
<>	156:95d6b41a828b	1873	__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	1874	{
<>	156:95d6b41a828b	1875	CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
<>	156:95d6b41a828b	1876	}
<>	156:95d6b41a828b	1877
<>	156:95d6b41a828b	1878	/**
<>	156:95d6b41a828b	1879	* @brief Check if the master clock ouput (Pin MCK) is enabled
<>	156:95d6b41a828b	1880	* @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
<>	156:95d6b41a828b	1881	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1882	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1883	*/
<>	156:95d6b41a828b	1884	__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	1885	{
<>	156:95d6b41a828b	1886	return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE));
<>	156:95d6b41a828b	1887	}
<>	156:95d6b41a828b	1888
<>	156:95d6b41a828b	1889	#if defined(SPI_I2SCFGR_ASTRTEN)
<>	156:95d6b41a828b	1890	/**
<>	156:95d6b41a828b	1891	* @brief Enable asynchronous start
<>	156:95d6b41a828b	1892	* @rmtoll I2SCFGR ASTRTEN LL_I2S_EnableAsyncStart
<>	156:95d6b41a828b	1893	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1894	* @retval None
<>	156:95d6b41a828b	1895	*/
<>	156:95d6b41a828b	1896	__STATIC_INLINE void LL_I2S_EnableAsyncStart(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	1897	{
<>	156:95d6b41a828b	1898	SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
<>	156:95d6b41a828b	1899	}
<>	156:95d6b41a828b	1900
<>	156:95d6b41a828b	1901	/**
<>	156:95d6b41a828b	1902	* @brief Disable asynchronous start
<>	156:95d6b41a828b	1903	* @rmtoll I2SCFGR ASTRTEN LL_I2S_DisableAsyncStart
<>	156:95d6b41a828b	1904	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1905	* @retval None
<>	156:95d6b41a828b	1906	*/
<>	156:95d6b41a828b	1907	__STATIC_INLINE void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	1908	{
<>	156:95d6b41a828b	1909	CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
<>	156:95d6b41a828b	1910	}
<>	156:95d6b41a828b	1911
<>	156:95d6b41a828b	1912	/**
<>	156:95d6b41a828b	1913	* @brief Check if asynchronous start is enabled
<>	156:95d6b41a828b	1914	* @rmtoll I2SCFGR ASTRTEN LL_I2S_IsEnabledAsyncStart
<>	156:95d6b41a828b	1915	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1916	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1917	*/
<>	156:95d6b41a828b	1918	__STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	1919	{
<>	156:95d6b41a828b	1920	return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN));
<>	156:95d6b41a828b	1921	}
<>	156:95d6b41a828b	1922	#endif /* SPI_I2SCFGR_ASTRTEN */
<>	156:95d6b41a828b	1923
<>	156:95d6b41a828b	1924	/**
<>	156:95d6b41a828b	1925	* @}
<>	156:95d6b41a828b	1926	*/
<>	156:95d6b41a828b	1927
<>	156:95d6b41a828b	1928	/** @defgroup I2S_LL_EF_FLAG FLAG Management
<>	156:95d6b41a828b	1929	* @{
<>	156:95d6b41a828b	1930	*/
<>	156:95d6b41a828b	1931
<>	156:95d6b41a828b	1932	/**
<>	156:95d6b41a828b	1933	* @brief Check if Rx buffer is not empty
<>	156:95d6b41a828b	1934	* @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE
<>	156:95d6b41a828b	1935	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1936	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1937	*/
<>	156:95d6b41a828b	1938	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	1939	{
<>	156:95d6b41a828b	1940	return LL_SPI_IsActiveFlag_RXNE(SPIx);
<>	156:95d6b41a828b	1941	}
<>	156:95d6b41a828b	1942
<>	156:95d6b41a828b	1943	/**
<>	156:95d6b41a828b	1944	* @brief Check if Tx buffer is empty
<>	156:95d6b41a828b	1945	* @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE
<>	156:95d6b41a828b	1946	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1947	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1948	*/
<>	156:95d6b41a828b	1949	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	1950	{
<>	156:95d6b41a828b	1951	return LL_SPI_IsActiveFlag_TXE(SPIx);
<>	156:95d6b41a828b	1952	}
<>	156:95d6b41a828b	1953
<>	156:95d6b41a828b	1954	/**
<>	156:95d6b41a828b	1955	* @brief Get busy flag
<>	156:95d6b41a828b	1956	* @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY
<>	156:95d6b41a828b	1957	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1958	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1959	*/
<>	156:95d6b41a828b	1960	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	1961	{
<>	156:95d6b41a828b	1962	return LL_SPI_IsActiveFlag_BSY(SPIx);
<>	156:95d6b41a828b	1963	}
<>	156:95d6b41a828b	1964
<>	156:95d6b41a828b	1965	/**
<>	156:95d6b41a828b	1966	* @brief Get overrun error flag
<>	156:95d6b41a828b	1967	* @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
<>	156:95d6b41a828b	1968	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1969	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1970	*/
<>	156:95d6b41a828b	1971	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	1972	{
<>	156:95d6b41a828b	1973	return LL_SPI_IsActiveFlag_OVR(SPIx);
<>	156:95d6b41a828b	1974	}
<>	156:95d6b41a828b	1975
<>	156:95d6b41a828b	1976	/**
<>	156:95d6b41a828b	1977	* @brief Get underrun error flag
<>	156:95d6b41a828b	1978	* @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
<>	156:95d6b41a828b	1979	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1980	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1981	*/
<>	156:95d6b41a828b	1982	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	1983	{
<>	156:95d6b41a828b	1984	return (READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR));
<>	156:95d6b41a828b	1985	}
<>	156:95d6b41a828b	1986
<>	156:95d6b41a828b	1987	/**
<>	156:95d6b41a828b	1988	* @brief Get frame format error flag
<>	156:95d6b41a828b	1989	* @rmtoll SR FRE LL_I2S_IsActiveFlag_FRE
<>	156:95d6b41a828b	1990	* @param SPIx SPI Instance
<>	156:95d6b41a828b	1991	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1992	*/
<>	156:95d6b41a828b	1993	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	1994	{
<>	156:95d6b41a828b	1995	return LL_SPI_IsActiveFlag_FRE(SPIx);
<>	156:95d6b41a828b	1996	}
<>	156:95d6b41a828b	1997
<>	156:95d6b41a828b	1998	/**
<>	156:95d6b41a828b	1999	* @brief Get channel side flag.
<>	156:95d6b41a828b	2000	* @note 0: Channel Left has to be transmitted or has been received\n
<>	156:95d6b41a828b	2001	* 1: Channel Right has to be transmitted or has been received\n
<>	156:95d6b41a828b	2002	* It has no significance in PCM mode.
<>	156:95d6b41a828b	2003	* @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE
<>	156:95d6b41a828b	2004	* @param SPIx SPI Instance
<>	156:95d6b41a828b	2005	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	2006	*/
<>	156:95d6b41a828b	2007	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	2008	{
<>	156:95d6b41a828b	2009	return (READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE));
<>	156:95d6b41a828b	2010	}
<>	156:95d6b41a828b	2011
<>	156:95d6b41a828b	2012	/**
<>	156:95d6b41a828b	2013	* @brief Clear overrun error flag
<>	156:95d6b41a828b	2014	* @rmtoll SR OVR LL_I2S_ClearFlag_OVR
<>	156:95d6b41a828b	2015	* @param SPIx SPI Instance
<>	156:95d6b41a828b	2016	* @retval None
<>	156:95d6b41a828b	2017	*/
<>	156:95d6b41a828b	2018	__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	2019	{
<>	156:95d6b41a828b	2020	LL_SPI_ClearFlag_OVR(SPIx);
<>	156:95d6b41a828b	2021	}
<>	156:95d6b41a828b	2022
<>	156:95d6b41a828b	2023	/**
<>	156:95d6b41a828b	2024	* @brief Clear underrun error flag
<>	156:95d6b41a828b	2025	* @rmtoll SR UDR LL_I2S_ClearFlag_UDR
<>	156:95d6b41a828b	2026	* @param SPIx SPI Instance
<>	156:95d6b41a828b	2027	* @retval None
<>	156:95d6b41a828b	2028	*/
<>	156:95d6b41a828b	2029	__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	2030	{
<>	156:95d6b41a828b	2031	__IO uint32_t tmpreg;
<>	156:95d6b41a828b	2032	tmpreg = SPIx->SR;
<>	156:95d6b41a828b	2033	(void)tmpreg;
<>	156:95d6b41a828b	2034	}
<>	156:95d6b41a828b	2035
<>	156:95d6b41a828b	2036	/**
<>	156:95d6b41a828b	2037	* @brief Clear frame format error flag
<>	156:95d6b41a828b	2038	* @rmtoll SR FRE LL_I2S_ClearFlag_FRE
<>	156:95d6b41a828b	2039	* @param SPIx SPI Instance
<>	156:95d6b41a828b	2040	* @retval None
<>	156:95d6b41a828b	2041	*/
<>	156:95d6b41a828b	2042	__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	2043	{
<>	156:95d6b41a828b	2044	LL_SPI_ClearFlag_FRE(SPIx);
<>	156:95d6b41a828b	2045	}
<>	156:95d6b41a828b	2046
<>	156:95d6b41a828b	2047	/**
<>	156:95d6b41a828b	2048	* @}
<>	156:95d6b41a828b	2049	*/
<>	156:95d6b41a828b	2050
<>	156:95d6b41a828b	2051	/** @defgroup I2S_LL_EF_IT Interrupt Management
<>	156:95d6b41a828b	2052	* @{
<>	156:95d6b41a828b	2053	*/
<>	156:95d6b41a828b	2054
<>	156:95d6b41a828b	2055	/**
<>	156:95d6b41a828b	2056	* @brief Enable error IT
<>	156:95d6b41a828b	2057	* @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
<>	156:95d6b41a828b	2058	* @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR
<>	156:95d6b41a828b	2059	* @param SPIx SPI Instance
<>	156:95d6b41a828b	2060	* @retval None
<>	156:95d6b41a828b	2061	*/
<>	156:95d6b41a828b	2062	__STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	2063	{
<>	156:95d6b41a828b	2064	LL_SPI_EnableIT_ERR(SPIx);
<>	156:95d6b41a828b	2065	}
<>	156:95d6b41a828b	2066
<>	156:95d6b41a828b	2067	/**
<>	156:95d6b41a828b	2068	* @brief Enable Rx buffer not empty IT
<>	156:95d6b41a828b	2069	* @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE
<>	156:95d6b41a828b	2070	* @param SPIx SPI Instance
<>	156:95d6b41a828b	2071	* @retval None
<>	156:95d6b41a828b	2072	*/
<>	156:95d6b41a828b	2073	__STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	2074	{
<>	156:95d6b41a828b	2075	LL_SPI_EnableIT_RXNE(SPIx);
<>	156:95d6b41a828b	2076	}
<>	156:95d6b41a828b	2077
<>	156:95d6b41a828b	2078	/**
<>	156:95d6b41a828b	2079	* @brief Enable Tx buffer empty IT
<>	156:95d6b41a828b	2080	* @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE
<>	156:95d6b41a828b	2081	* @param SPIx SPI Instance
<>	156:95d6b41a828b	2082	* @retval None
<>	156:95d6b41a828b	2083	*/
<>	156:95d6b41a828b	2084	__STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	2085	{
<>	156:95d6b41a828b	2086	LL_SPI_EnableIT_TXE(SPIx);
<>	156:95d6b41a828b	2087	}
<>	156:95d6b41a828b	2088
<>	156:95d6b41a828b	2089	/**
<>	156:95d6b41a828b	2090	* @brief Disable error IT
<>	156:95d6b41a828b	2091	* @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
<>	156:95d6b41a828b	2092	* @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR
<>	156:95d6b41a828b	2093	* @param SPIx SPI Instance
<>	156:95d6b41a828b	2094	* @retval None
<>	156:95d6b41a828b	2095	*/
<>	156:95d6b41a828b	2096	__STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	2097	{
<>	156:95d6b41a828b	2098	LL_SPI_DisableIT_ERR(SPIx);
<>	156:95d6b41a828b	2099	}
<>	156:95d6b41a828b	2100
<>	156:95d6b41a828b	2101	/**
<>	156:95d6b41a828b	2102	* @brief Disable Rx buffer not empty IT
<>	156:95d6b41a828b	2103	* @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE
<>	156:95d6b41a828b	2104	* @param SPIx SPI Instance
<>	156:95d6b41a828b	2105	* @retval None
<>	156:95d6b41a828b	2106	*/
<>	156:95d6b41a828b	2107	__STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	2108	{
<>	156:95d6b41a828b	2109	LL_SPI_DisableIT_RXNE(SPIx);
<>	156:95d6b41a828b	2110	}
<>	156:95d6b41a828b	2111
<>	156:95d6b41a828b	2112	/**
<>	156:95d6b41a828b	2113	* @brief Disable Tx buffer empty IT
<>	156:95d6b41a828b	2114	* @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE
<>	156:95d6b41a828b	2115	* @param SPIx SPI Instance
<>	156:95d6b41a828b	2116	* @retval None
<>	156:95d6b41a828b	2117	*/
<>	156:95d6b41a828b	2118	__STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	2119	{
<>	156:95d6b41a828b	2120	LL_SPI_DisableIT_TXE(SPIx);
<>	156:95d6b41a828b	2121	}
<>	156:95d6b41a828b	2122
<>	156:95d6b41a828b	2123	/**
<>	156:95d6b41a828b	2124	* @brief Check if ERR IT is enabled
<>	156:95d6b41a828b	2125	* @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR
<>	156:95d6b41a828b	2126	* @param SPIx SPI Instance
<>	156:95d6b41a828b	2127	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	2128	*/
<>	156:95d6b41a828b	2129	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	2130	{
<>	156:95d6b41a828b	2131	return LL_SPI_IsEnabledIT_ERR(SPIx);
<>	156:95d6b41a828b	2132	}
<>	156:95d6b41a828b	2133
<>	156:95d6b41a828b	2134	/**
<>	156:95d6b41a828b	2135	* @brief Check if RXNE IT is enabled
<>	156:95d6b41a828b	2136	* @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE
<>	156:95d6b41a828b	2137	* @param SPIx SPI Instance
<>	156:95d6b41a828b	2138	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	2139	*/
<>	156:95d6b41a828b	2140	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	2141	{
<>	156:95d6b41a828b	2142	return LL_SPI_IsEnabledIT_RXNE(SPIx);
<>	156:95d6b41a828b	2143	}
<>	156:95d6b41a828b	2144
<>	156:95d6b41a828b	2145	/**
<>	156:95d6b41a828b	2146	* @brief Check if TXE IT is enabled
<>	156:95d6b41a828b	2147	* @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE
<>	156:95d6b41a828b	2148	* @param SPIx SPI Instance
<>	156:95d6b41a828b	2149	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	2150	*/
<>	156:95d6b41a828b	2151	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	2152	{
<>	156:95d6b41a828b	2153	return LL_SPI_IsEnabledIT_TXE(SPIx);
<>	156:95d6b41a828b	2154	}
<>	156:95d6b41a828b	2155
<>	156:95d6b41a828b	2156	/**
<>	156:95d6b41a828b	2157	* @}
<>	156:95d6b41a828b	2158	*/
<>	156:95d6b41a828b	2159
<>	156:95d6b41a828b	2160	/** @defgroup I2S_LL_EF_DMA DMA Management
<>	156:95d6b41a828b	2161	* @{
<>	156:95d6b41a828b	2162	*/
<>	156:95d6b41a828b	2163
<>	156:95d6b41a828b	2164	/**
<>	156:95d6b41a828b	2165	* @brief Enable DMA Rx
<>	156:95d6b41a828b	2166	* @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX
<>	156:95d6b41a828b	2167	* @param SPIx SPI Instance
<>	156:95d6b41a828b	2168	* @retval None
<>	156:95d6b41a828b	2169	*/
<>	156:95d6b41a828b	2170	__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	2171	{
<>	156:95d6b41a828b	2172	LL_SPI_EnableDMAReq_RX(SPIx);
<>	156:95d6b41a828b	2173	}
<>	156:95d6b41a828b	2174
<>	156:95d6b41a828b	2175	/**
<>	156:95d6b41a828b	2176	* @brief Disable DMA Rx
<>	156:95d6b41a828b	2177	* @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX
<>	156:95d6b41a828b	2178	* @param SPIx SPI Instance
<>	156:95d6b41a828b	2179	* @retval None
<>	156:95d6b41a828b	2180	*/
<>	156:95d6b41a828b	2181	__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	2182	{
<>	156:95d6b41a828b	2183	LL_SPI_DisableDMAReq_RX(SPIx);
<>	156:95d6b41a828b	2184	}
<>	156:95d6b41a828b	2185
<>	156:95d6b41a828b	2186	/**
<>	156:95d6b41a828b	2187	* @brief Check if DMA Rx is enabled
<>	156:95d6b41a828b	2188	* @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
<>	156:95d6b41a828b	2189	* @param SPIx SPI Instance
<>	156:95d6b41a828b	2190	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	2191	*/
<>	156:95d6b41a828b	2192	__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	2193	{
<>	156:95d6b41a828b	2194	return LL_SPI_IsEnabledDMAReq_RX(SPIx);
<>	156:95d6b41a828b	2195	}
<>	156:95d6b41a828b	2196
<>	156:95d6b41a828b	2197	/**
<>	156:95d6b41a828b	2198	* @brief Enable DMA Tx
<>	156:95d6b41a828b	2199	* @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX
<>	156:95d6b41a828b	2200	* @param SPIx SPI Instance
<>	156:95d6b41a828b	2201	* @retval None
<>	156:95d6b41a828b	2202	*/
<>	156:95d6b41a828b	2203	__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	2204	{
<>	156:95d6b41a828b	2205	LL_SPI_EnableDMAReq_TX(SPIx);
<>	156:95d6b41a828b	2206	}
<>	156:95d6b41a828b	2207
<>	156:95d6b41a828b	2208	/**
<>	156:95d6b41a828b	2209	* @brief Disable DMA Tx
<>	156:95d6b41a828b	2210	* @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX
<>	156:95d6b41a828b	2211	* @param SPIx SPI Instance
<>	156:95d6b41a828b	2212	* @retval None
<>	156:95d6b41a828b	2213	*/
<>	156:95d6b41a828b	2214	__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	2215	{
<>	156:95d6b41a828b	2216	LL_SPI_DisableDMAReq_TX(SPIx);
<>	156:95d6b41a828b	2217	}
<>	156:95d6b41a828b	2218
<>	156:95d6b41a828b	2219	/**
<>	156:95d6b41a828b	2220	* @brief Check if DMA Tx is enabled
<>	156:95d6b41a828b	2221	* @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
<>	156:95d6b41a828b	2222	* @param SPIx SPI Instance
<>	156:95d6b41a828b	2223	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	2224	*/
<>	156:95d6b41a828b	2225	__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	2226	{
<>	156:95d6b41a828b	2227	return LL_SPI_IsEnabledDMAReq_TX(SPIx);
<>	156:95d6b41a828b	2228	}
<>	156:95d6b41a828b	2229
<>	156:95d6b41a828b	2230	/**
<>	156:95d6b41a828b	2231	* @}
<>	156:95d6b41a828b	2232	*/
<>	156:95d6b41a828b	2233
<>	156:95d6b41a828b	2234	/** @defgroup I2S_LL_EF_DATA DATA Management
<>	156:95d6b41a828b	2235	* @{
<>	156:95d6b41a828b	2236	*/
<>	156:95d6b41a828b	2237
<>	156:95d6b41a828b	2238	/**
<>	156:95d6b41a828b	2239	* @brief Read 16-Bits in data register
<>	156:95d6b41a828b	2240	* @rmtoll DR DR LL_I2S_ReceiveData16
<>	156:95d6b41a828b	2241	* @param SPIx SPI Instance
<>	156:95d6b41a828b	2242	* @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
<>	156:95d6b41a828b	2243	*/
<>	156:95d6b41a828b	2244	__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
<>	156:95d6b41a828b	2245	{
<>	156:95d6b41a828b	2246	return LL_SPI_ReceiveData16(SPIx);
<>	156:95d6b41a828b	2247	}
<>	156:95d6b41a828b	2248
<>	156:95d6b41a828b	2249	/**
<>	156:95d6b41a828b	2250	* @brief Write 16-Bits in data register
<>	156:95d6b41a828b	2251	* @rmtoll DR DR LL_I2S_TransmitData16
<>	156:95d6b41a828b	2252	* @param SPIx SPI Instance
<>	156:95d6b41a828b	2253	* @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
<>	156:95d6b41a828b	2254	* @retval None
<>	156:95d6b41a828b	2255	*/
<>	156:95d6b41a828b	2256	__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
<>	156:95d6b41a828b	2257	{
<>	156:95d6b41a828b	2258	LL_SPI_TransmitData16(SPIx, TxData);
<>	156:95d6b41a828b	2259	}
<>	156:95d6b41a828b	2260
<>	156:95d6b41a828b	2261	/**
<>	156:95d6b41a828b	2262	* @}
<>	156:95d6b41a828b	2263	*/
<>	156:95d6b41a828b	2264
<>	156:95d6b41a828b	2265	#if defined(USE_FULL_LL_DRIVER)
<>	156:95d6b41a828b	2266	/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
<>	156:95d6b41a828b	2267	* @{
<>	156:95d6b41a828b	2268	*/
<>	156:95d6b41a828b	2269
<>	156:95d6b41a828b	2270	ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
<>	156:95d6b41a828b	2271	ErrorStatus LL_I2S_Init(SPI_TypeDef SPIx, LL_I2S_InitTypeDef I2S_InitStruct);
<>	156:95d6b41a828b	2272	void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
<>	156:95d6b41a828b	2273	void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
<>	156:95d6b41a828b	2274
<>	156:95d6b41a828b	2275	/**
<>	156:95d6b41a828b	2276	* @}
<>	156:95d6b41a828b	2277	*/
<>	156:95d6b41a828b	2278	#endif /* USE_FULL_LL_DRIVER */
<>	156:95d6b41a828b	2279
<>	156:95d6b41a828b	2280	/**
<>	156:95d6b41a828b	2281	* @}
<>	156:95d6b41a828b	2282	*/
<>	156:95d6b41a828b	2283
<>	156:95d6b41a828b	2284	/**
<>	156:95d6b41a828b	2285	* @}
<>	156:95d6b41a828b	2286	*/
<>	156:95d6b41a828b	2287	#endif /* SPI_I2S_SUPPORT */
<>	156:95d6b41a828b	2288
<>	156:95d6b41a828b	2289	#endif /* defined (SPI1) \|\| defined (SPI2) */
<>	156:95d6b41a828b	2290
<>	156:95d6b41a828b	2291	/**
<>	156:95d6b41a828b	2292	* @}
<>	156:95d6b41a828b	2293	*/
<>	156:95d6b41a828b	2294
<>	156:95d6b41a828b	2295	#ifdef __cplusplus
<>	156:95d6b41a828b	2296	}
<>	156:95d6b41a828b	2297	#endif
<>	156:95d6b41a828b	2298
<>	156:95d6b41a828b	2299	#endif /* __STM32F0xx_LL_SPI_H */
<>	156:95d6b41a828b	2300
<>	156:95d6b41a828b	2301	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/