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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_cortex.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
180:96ed750bd169 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 156:95d6b41a828b 1 /**
<> 156:95d6b41a828b 2 ******************************************************************************
<> 156:95d6b41a828b 3 * @file stm32f0xx_ll_cortex.h
<> 156:95d6b41a828b 4 * @author MCD Application Team
<> 156:95d6b41a828b 5 * @brief Header file of CORTEX LL module.
<> 156:95d6b41a828b 6 @verbatim
<> 156:95d6b41a828b 7 ==============================================================================
<> 156:95d6b41a828b 8 ##### How to use this driver #####
<> 156:95d6b41a828b 9 ==============================================================================
<> 156:95d6b41a828b 10 [..]
<> 156:95d6b41a828b 11 The LL CORTEX driver contains a set of generic APIs that can be
<> 156:95d6b41a828b 12 used by user:
<> 156:95d6b41a828b 13 (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
<> 156:95d6b41a828b 14 functions
<> 156:95d6b41a828b 15 (+) Low power mode configuration (SCB register of Cortex-MCU)
<> 156:95d6b41a828b 16 (+) API to access to MCU info (CPUID register)
<> 156:95d6b41a828b 17
<> 156:95d6b41a828b 18 @endverbatim
<> 156:95d6b41a828b 19 ******************************************************************************
<> 156:95d6b41a828b 20 * @attention
<> 156:95d6b41a828b 21 *
<> 156:95d6b41a828b 22 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 156:95d6b41a828b 23 *
<> 156:95d6b41a828b 24 * Redistribution and use in source and binary forms, with or without modification,
<> 156:95d6b41a828b 25 * are permitted provided that the following conditions are met:
<> 156:95d6b41a828b 26 * 1. Redistributions of source code must retain the above copyright notice,
<> 156:95d6b41a828b 27 * this list of conditions and the following disclaimer.
<> 156:95d6b41a828b 28 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 156:95d6b41a828b 29 * this list of conditions and the following disclaimer in the documentation
<> 156:95d6b41a828b 30 * and/or other materials provided with the distribution.
<> 156:95d6b41a828b 31 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 156:95d6b41a828b 32 * may be used to endorse or promote products derived from this software
<> 156:95d6b41a828b 33 * without specific prior written permission.
<> 156:95d6b41a828b 34 *
<> 156:95d6b41a828b 35 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 156:95d6b41a828b 36 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 156:95d6b41a828b 37 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 156:95d6b41a828b 38 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 156:95d6b41a828b 39 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 156:95d6b41a828b 40 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 156:95d6b41a828b 41 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 156:95d6b41a828b 42 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 156:95d6b41a828b 43 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 156:95d6b41a828b 44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 156:95d6b41a828b 45 *
<> 156:95d6b41a828b 46 ******************************************************************************
<> 156:95d6b41a828b 47 */
<> 156:95d6b41a828b 48
<> 156:95d6b41a828b 49 /* Define to prevent recursive inclusion -------------------------------------*/
<> 156:95d6b41a828b 50 #ifndef __STM32F0xx_LL_CORTEX_H
<> 156:95d6b41a828b 51 #define __STM32F0xx_LL_CORTEX_H
<> 156:95d6b41a828b 52
<> 156:95d6b41a828b 53 #ifdef __cplusplus
<> 156:95d6b41a828b 54 extern "C" {
<> 156:95d6b41a828b 55 #endif
<> 156:95d6b41a828b 56
<> 156:95d6b41a828b 57 /* Includes ------------------------------------------------------------------*/
<> 156:95d6b41a828b 58 #include "stm32f0xx.h"
<> 156:95d6b41a828b 59
<> 156:95d6b41a828b 60 /** @addtogroup STM32F0xx_LL_Driver
<> 156:95d6b41a828b 61 * @{
<> 156:95d6b41a828b 62 */
<> 156:95d6b41a828b 63
<> 156:95d6b41a828b 64 /** @defgroup CORTEX_LL CORTEX
<> 156:95d6b41a828b 65 * @{
<> 156:95d6b41a828b 66 */
<> 156:95d6b41a828b 67
<> 156:95d6b41a828b 68 /* Private types -------------------------------------------------------------*/
<> 156:95d6b41a828b 69 /* Private variables ---------------------------------------------------------*/
<> 156:95d6b41a828b 70
<> 156:95d6b41a828b 71 /* Private constants ---------------------------------------------------------*/
<> 156:95d6b41a828b 72
<> 156:95d6b41a828b 73 /* Private macros ------------------------------------------------------------*/
<> 156:95d6b41a828b 74
<> 156:95d6b41a828b 75 /* Exported types ------------------------------------------------------------*/
<> 156:95d6b41a828b 76 /* Exported constants --------------------------------------------------------*/
<> 156:95d6b41a828b 77 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
<> 156:95d6b41a828b 78 * @{
<> 156:95d6b41a828b 79 */
<> 156:95d6b41a828b 80
<> 156:95d6b41a828b 81 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
<> 156:95d6b41a828b 82 * @{
<> 156:95d6b41a828b 83 */
Anna Bridge 180:96ed750bd169 84 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/
Anna Bridge 180:96ed750bd169 85 #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
<> 156:95d6b41a828b 86 /**
<> 156:95d6b41a828b 87 * @}
<> 156:95d6b41a828b 88 */
<> 156:95d6b41a828b 89
<> 156:95d6b41a828b 90 /**
<> 156:95d6b41a828b 91 * @}
<> 156:95d6b41a828b 92 */
<> 156:95d6b41a828b 93
<> 156:95d6b41a828b 94 /* Exported macro ------------------------------------------------------------*/
<> 156:95d6b41a828b 95
<> 156:95d6b41a828b 96 /* Exported functions --------------------------------------------------------*/
<> 156:95d6b41a828b 97 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
<> 156:95d6b41a828b 98 * @{
<> 156:95d6b41a828b 99 */
<> 156:95d6b41a828b 100
<> 156:95d6b41a828b 101 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
<> 156:95d6b41a828b 102 * @{
<> 156:95d6b41a828b 103 */
<> 156:95d6b41a828b 104
<> 156:95d6b41a828b 105 /**
<> 156:95d6b41a828b 106 * @brief This function checks if the Systick counter flag is active or not.
<> 156:95d6b41a828b 107 * @note It can be used in timeout function on application side.
<> 156:95d6b41a828b 108 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
<> 156:95d6b41a828b 109 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 110 */
<> 156:95d6b41a828b 111 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
<> 156:95d6b41a828b 112 {
<> 156:95d6b41a828b 113 return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
<> 156:95d6b41a828b 114 }
<> 156:95d6b41a828b 115
<> 156:95d6b41a828b 116 /**
<> 156:95d6b41a828b 117 * @brief Configures the SysTick clock source
<> 156:95d6b41a828b 118 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
<> 156:95d6b41a828b 119 * @param Source This parameter can be one of the following values:
<> 156:95d6b41a828b 120 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
<> 156:95d6b41a828b 121 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
<> 156:95d6b41a828b 122 * @retval None
<> 156:95d6b41a828b 123 */
<> 156:95d6b41a828b 124 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
<> 156:95d6b41a828b 125 {
<> 156:95d6b41a828b 126 if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
<> 156:95d6b41a828b 127 {
<> 156:95d6b41a828b 128 SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
<> 156:95d6b41a828b 129 }
<> 156:95d6b41a828b 130 else
<> 156:95d6b41a828b 131 {
<> 156:95d6b41a828b 132 CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
<> 156:95d6b41a828b 133 }
<> 156:95d6b41a828b 134 }
<> 156:95d6b41a828b 135
<> 156:95d6b41a828b 136 /**
<> 156:95d6b41a828b 137 * @brief Get the SysTick clock source
<> 156:95d6b41a828b 138 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
<> 156:95d6b41a828b 139 * @retval Returned value can be one of the following values:
<> 156:95d6b41a828b 140 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
<> 156:95d6b41a828b 141 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
<> 156:95d6b41a828b 142 */
<> 156:95d6b41a828b 143 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
<> 156:95d6b41a828b 144 {
<> 156:95d6b41a828b 145 return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
<> 156:95d6b41a828b 146 }
<> 156:95d6b41a828b 147
<> 156:95d6b41a828b 148 /**
<> 156:95d6b41a828b 149 * @brief Enable SysTick exception request
<> 156:95d6b41a828b 150 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
<> 156:95d6b41a828b 151 * @retval None
<> 156:95d6b41a828b 152 */
<> 156:95d6b41a828b 153 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
<> 156:95d6b41a828b 154 {
<> 156:95d6b41a828b 155 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
<> 156:95d6b41a828b 156 }
<> 156:95d6b41a828b 157
<> 156:95d6b41a828b 158 /**
<> 156:95d6b41a828b 159 * @brief Disable SysTick exception request
<> 156:95d6b41a828b 160 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
<> 156:95d6b41a828b 161 * @retval None
<> 156:95d6b41a828b 162 */
<> 156:95d6b41a828b 163 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
<> 156:95d6b41a828b 164 {
<> 156:95d6b41a828b 165 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
<> 156:95d6b41a828b 166 }
<> 156:95d6b41a828b 167
<> 156:95d6b41a828b 168 /**
<> 156:95d6b41a828b 169 * @brief Checks if the SYSTICK interrupt is enabled or disabled.
<> 156:95d6b41a828b 170 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
<> 156:95d6b41a828b 171 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 172 */
<> 156:95d6b41a828b 173 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
<> 156:95d6b41a828b 174 {
<> 156:95d6b41a828b 175 return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
<> 156:95d6b41a828b 176 }
<> 156:95d6b41a828b 177
<> 156:95d6b41a828b 178 /**
<> 156:95d6b41a828b 179 * @}
<> 156:95d6b41a828b 180 */
<> 156:95d6b41a828b 181
<> 156:95d6b41a828b 182 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
<> 156:95d6b41a828b 183 * @{
<> 156:95d6b41a828b 184 */
<> 156:95d6b41a828b 185
<> 156:95d6b41a828b 186 /**
<> 156:95d6b41a828b 187 * @brief Processor uses sleep as its low power mode
<> 156:95d6b41a828b 188 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
<> 156:95d6b41a828b 189 * @retval None
<> 156:95d6b41a828b 190 */
<> 156:95d6b41a828b 191 __STATIC_INLINE void LL_LPM_EnableSleep(void)
<> 156:95d6b41a828b 192 {
<> 156:95d6b41a828b 193 /* Clear SLEEPDEEP bit of Cortex System Control Register */
<> 156:95d6b41a828b 194 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
<> 156:95d6b41a828b 195 }
<> 156:95d6b41a828b 196
<> 156:95d6b41a828b 197 /**
<> 156:95d6b41a828b 198 * @brief Processor uses deep sleep as its low power mode
<> 156:95d6b41a828b 199 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
<> 156:95d6b41a828b 200 * @retval None
<> 156:95d6b41a828b 201 */
<> 156:95d6b41a828b 202 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
<> 156:95d6b41a828b 203 {
<> 156:95d6b41a828b 204 /* Set SLEEPDEEP bit of Cortex System Control Register */
<> 156:95d6b41a828b 205 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
<> 156:95d6b41a828b 206 }
<> 156:95d6b41a828b 207
<> 156:95d6b41a828b 208 /**
<> 156:95d6b41a828b 209 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
<> 156:95d6b41a828b 210 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
<> 156:95d6b41a828b 211 * empty main application.
<> 156:95d6b41a828b 212 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
<> 156:95d6b41a828b 213 * @retval None
<> 156:95d6b41a828b 214 */
<> 156:95d6b41a828b 215 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
<> 156:95d6b41a828b 216 {
<> 156:95d6b41a828b 217 /* Set SLEEPONEXIT bit of Cortex System Control Register */
<> 156:95d6b41a828b 218 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
<> 156:95d6b41a828b 219 }
<> 156:95d6b41a828b 220
<> 156:95d6b41a828b 221 /**
<> 156:95d6b41a828b 222 * @brief Do not sleep when returning to Thread mode.
<> 156:95d6b41a828b 223 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
<> 156:95d6b41a828b 224 * @retval None
<> 156:95d6b41a828b 225 */
<> 156:95d6b41a828b 226 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
<> 156:95d6b41a828b 227 {
<> 156:95d6b41a828b 228 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
<> 156:95d6b41a828b 229 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
<> 156:95d6b41a828b 230 }
<> 156:95d6b41a828b 231
<> 156:95d6b41a828b 232 /**
<> 156:95d6b41a828b 233 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
<> 156:95d6b41a828b 234 * processor.
<> 156:95d6b41a828b 235 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
<> 156:95d6b41a828b 236 * @retval None
<> 156:95d6b41a828b 237 */
<> 156:95d6b41a828b 238 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
<> 156:95d6b41a828b 239 {
<> 156:95d6b41a828b 240 /* Set SEVEONPEND bit of Cortex System Control Register */
<> 156:95d6b41a828b 241 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
<> 156:95d6b41a828b 242 }
<> 156:95d6b41a828b 243
<> 156:95d6b41a828b 244 /**
<> 156:95d6b41a828b 245 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
<> 156:95d6b41a828b 246 * excluded
<> 156:95d6b41a828b 247 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
<> 156:95d6b41a828b 248 * @retval None
<> 156:95d6b41a828b 249 */
<> 156:95d6b41a828b 250 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
<> 156:95d6b41a828b 251 {
<> 156:95d6b41a828b 252 /* Clear SEVEONPEND bit of Cortex System Control Register */
<> 156:95d6b41a828b 253 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
<> 156:95d6b41a828b 254 }
<> 156:95d6b41a828b 255
<> 156:95d6b41a828b 256 /**
<> 156:95d6b41a828b 257 * @}
<> 156:95d6b41a828b 258 */
<> 156:95d6b41a828b 259
<> 156:95d6b41a828b 260 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
<> 156:95d6b41a828b 261 * @{
<> 156:95d6b41a828b 262 */
<> 156:95d6b41a828b 263
<> 156:95d6b41a828b 264 /**
<> 156:95d6b41a828b 265 * @brief Get Implementer code
<> 156:95d6b41a828b 266 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
<> 156:95d6b41a828b 267 * @retval Value should be equal to 0x41 for ARM
<> 156:95d6b41a828b 268 */
<> 156:95d6b41a828b 269 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
<> 156:95d6b41a828b 270 {
<> 156:95d6b41a828b 271 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
<> 156:95d6b41a828b 272 }
<> 156:95d6b41a828b 273
<> 156:95d6b41a828b 274 /**
<> 156:95d6b41a828b 275 * @brief Get Variant number (The r value in the rnpn product revision identifier)
<> 156:95d6b41a828b 276 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
<> 156:95d6b41a828b 277 * @retval Value between 0 and 255 (0x0: revision 0)
<> 156:95d6b41a828b 278 */
<> 156:95d6b41a828b 279 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
<> 156:95d6b41a828b 280 {
<> 156:95d6b41a828b 281 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
<> 156:95d6b41a828b 282 }
<> 156:95d6b41a828b 283
<> 156:95d6b41a828b 284 /**
<> 156:95d6b41a828b 285 * @brief Get Architecture number
<> 156:95d6b41a828b 286 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture
<> 156:95d6b41a828b 287 * @retval Value should be equal to 0xC for Cortex-M0 devices
<> 156:95d6b41a828b 288 */
<> 156:95d6b41a828b 289 __STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void)
<> 156:95d6b41a828b 290 {
<> 156:95d6b41a828b 291 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
<> 156:95d6b41a828b 292 }
<> 156:95d6b41a828b 293
<> 156:95d6b41a828b 294 /**
<> 156:95d6b41a828b 295 * @brief Get Part number
<> 156:95d6b41a828b 296 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
<> 156:95d6b41a828b 297 * @retval Value should be equal to 0xC20 for Cortex-M0
<> 156:95d6b41a828b 298 */
<> 156:95d6b41a828b 299 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
<> 156:95d6b41a828b 300 {
<> 156:95d6b41a828b 301 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
<> 156:95d6b41a828b 302 }
<> 156:95d6b41a828b 303
<> 156:95d6b41a828b 304 /**
<> 156:95d6b41a828b 305 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
<> 156:95d6b41a828b 306 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
<> 156:95d6b41a828b 307 * @retval Value between 0 and 255 (0x1: patch 1)
<> 156:95d6b41a828b 308 */
<> 156:95d6b41a828b 309 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
<> 156:95d6b41a828b 310 {
<> 156:95d6b41a828b 311 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
<> 156:95d6b41a828b 312 }
<> 156:95d6b41a828b 313
<> 156:95d6b41a828b 314 /**
<> 156:95d6b41a828b 315 * @}
<> 156:95d6b41a828b 316 */
<> 156:95d6b41a828b 317
<> 156:95d6b41a828b 318 /**
<> 156:95d6b41a828b 319 * @}
<> 156:95d6b41a828b 320 */
<> 156:95d6b41a828b 321
<> 156:95d6b41a828b 322 /**
<> 156:95d6b41a828b 323 * @}
<> 156:95d6b41a828b 324 */
<> 156:95d6b41a828b 325
<> 156:95d6b41a828b 326 /**
<> 156:95d6b41a828b 327 * @}
<> 156:95d6b41a828b 328 */
<> 156:95d6b41a828b 329
<> 156:95d6b41a828b 330 #ifdef __cplusplus
<> 156:95d6b41a828b 331 }
<> 156:95d6b41a828b 332 #endif
<> 156:95d6b41a828b 333
<> 156:95d6b41a828b 334 #endif /* __STM32F0xx_LL_CORTEX_H */
<> 156:95d6b41a828b 335
<> 156:95d6b41a828b 336 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/