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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_irda_ex.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
180:96ed750bd169 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_irda_ex.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 156:95d6b41a828b 5 * @brief Header file of IRDA HAL Extended module.
<> 144:ef7eb2e8f9f7 6 ******************************************************************************
<> 144:ef7eb2e8f9f7 7 * @attention
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 12 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 14 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 17 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 19 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 20 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 32 *
<> 144:ef7eb2e8f9f7 33 ******************************************************************************
<> 144:ef7eb2e8f9f7 34 */
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 37 #ifndef __STM32F0xx_HAL_IRDA_EX_H
<> 144:ef7eb2e8f9f7 38 #define __STM32F0xx_HAL_IRDA_EX_H
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 41 extern "C" {
<> 144:ef7eb2e8f9f7 42 #endif
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32f0xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 156:95d6b41a828b 53 /** @addtogroup IRDAEx
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 59 /** @defgroup IRDAEx_Exported_Constants IRDAEx Exported Constants
<> 144:ef7eb2e8f9f7 60 * @{
<> 144:ef7eb2e8f9f7 61 */
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /** @defgroup IRDAEx_Word_Length IRDA Word Length
<> 144:ef7eb2e8f9f7 64 * @{
<> 144:ef7eb2e8f9f7 65 */
<> 144:ef7eb2e8f9f7 66 #if defined (STM32F042x6) || defined (STM32F048xx) || \
<> 144:ef7eb2e8f9f7 67 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
<> 144:ef7eb2e8f9f7 68 defined (STM32F091xC) || defined (STM32F098xx)
<> 144:ef7eb2e8f9f7 69 #define IRDA_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long frame */
<> 156:95d6b41a828b 70 #define IRDA_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long frame */
<> 144:ef7eb2e8f9f7 71 #define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long frame */
<> 144:ef7eb2e8f9f7 72 #else
<> 156:95d6b41a828b 73 #define IRDA_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long frame */
<> 144:ef7eb2e8f9f7 74 #define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M) /*!< 9-bit long frame */
<> 144:ef7eb2e8f9f7 75 #endif /* defined (STM32F042x6) || defined (STM32F048xx) || \
<> 144:ef7eb2e8f9f7 76 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
<> 144:ef7eb2e8f9f7 77 defined (STM32F091xC) || defined (STM32F098xx)*/
<> 144:ef7eb2e8f9f7 78 /**
<> 144:ef7eb2e8f9f7 79 * @}
<> 144:ef7eb2e8f9f7 80 */
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 /**
<> 144:ef7eb2e8f9f7 83 * @}
<> 144:ef7eb2e8f9f7 84 */
<> 156:95d6b41a828b 85
<> 144:ef7eb2e8f9f7 86 /* Exported macros -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 87 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 /** @defgroup IRDAEx_Private_Macros IRDAEx Private Macros
<> 144:ef7eb2e8f9f7 92 * @{
<> 144:ef7eb2e8f9f7 93 */
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 /** @brief Report the IRDA clock source.
Anna Bridge 180:96ed750bd169 96 * @param __HANDLE__ specifies the IRDA Handle.
Anna Bridge 180:96ed750bd169 97 * @param __CLOCKSOURCE__ output variable.
<> 144:ef7eb2e8f9f7 98 * @retval IRDA clocking source, written in __CLOCKSOURCE__.
<> 144:ef7eb2e8f9f7 99 */
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 #if defined(STM32F031x6) || defined(STM32F038xx)
<> 156:95d6b41a828b 102 #define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
<> 144:ef7eb2e8f9f7 103 do { \
<> 144:ef7eb2e8f9f7 104 switch(__HAL_RCC_GET_USART1_SOURCE()) \
<> 144:ef7eb2e8f9f7 105 { \
<> 144:ef7eb2e8f9f7 106 case RCC_USART1CLKSOURCE_PCLK1: \
<> 144:ef7eb2e8f9f7 107 (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 108 break; \
<> 144:ef7eb2e8f9f7 109 case RCC_USART1CLKSOURCE_HSI: \
<> 144:ef7eb2e8f9f7 110 (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
<> 144:ef7eb2e8f9f7 111 break; \
<> 144:ef7eb2e8f9f7 112 case RCC_USART1CLKSOURCE_SYSCLK: \
<> 144:ef7eb2e8f9f7 113 (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
<> 144:ef7eb2e8f9f7 114 break; \
<> 144:ef7eb2e8f9f7 115 case RCC_USART1CLKSOURCE_LSE: \
<> 144:ef7eb2e8f9f7 116 (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
<> 144:ef7eb2e8f9f7 117 break; \
<> 144:ef7eb2e8f9f7 118 default: \
<> 144:ef7eb2e8f9f7 119 (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 120 break; \
<> 144:ef7eb2e8f9f7 121 } \
<> 156:95d6b41a828b 122 } while(0)
<> 144:ef7eb2e8f9f7 123 #elif defined (STM32F042x6) || defined (STM32F048xx) || \
<> 144:ef7eb2e8f9f7 124 defined (STM32F051x8) || defined (STM32F058xx)
<> 156:95d6b41a828b 125 #define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
<> 144:ef7eb2e8f9f7 126 do { \
<> 144:ef7eb2e8f9f7 127 if((__HANDLE__)->Instance == USART1) \
<> 144:ef7eb2e8f9f7 128 { \
<> 144:ef7eb2e8f9f7 129 switch(__HAL_RCC_GET_USART1_SOURCE()) \
<> 144:ef7eb2e8f9f7 130 { \
<> 144:ef7eb2e8f9f7 131 case RCC_USART1CLKSOURCE_PCLK1: \
<> 144:ef7eb2e8f9f7 132 (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 133 break; \
<> 144:ef7eb2e8f9f7 134 case RCC_USART1CLKSOURCE_HSI: \
<> 144:ef7eb2e8f9f7 135 (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
<> 144:ef7eb2e8f9f7 136 break; \
<> 144:ef7eb2e8f9f7 137 case RCC_USART1CLKSOURCE_SYSCLK: \
<> 144:ef7eb2e8f9f7 138 (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
<> 144:ef7eb2e8f9f7 139 break; \
<> 144:ef7eb2e8f9f7 140 case RCC_USART1CLKSOURCE_LSE: \
<> 144:ef7eb2e8f9f7 141 (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
<> 144:ef7eb2e8f9f7 142 break; \
<> 144:ef7eb2e8f9f7 143 default: \
<> 144:ef7eb2e8f9f7 144 (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 145 break; \
<> 144:ef7eb2e8f9f7 146 } \
<> 144:ef7eb2e8f9f7 147 } \
<> 144:ef7eb2e8f9f7 148 else if((__HANDLE__)->Instance == USART2) \
<> 144:ef7eb2e8f9f7 149 { \
<> 144:ef7eb2e8f9f7 150 (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 151 } \
<> 144:ef7eb2e8f9f7 152 else \
<> 144:ef7eb2e8f9f7 153 { \
<> 144:ef7eb2e8f9f7 154 (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 155 } \
<> 156:95d6b41a828b 156 } while(0)
<> 144:ef7eb2e8f9f7 157 #elif defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
<> 156:95d6b41a828b 158 #define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
<> 144:ef7eb2e8f9f7 159 do { \
<> 144:ef7eb2e8f9f7 160 if((__HANDLE__)->Instance == USART1) \
<> 144:ef7eb2e8f9f7 161 { \
<> 144:ef7eb2e8f9f7 162 switch(__HAL_RCC_GET_USART1_SOURCE()) \
<> 144:ef7eb2e8f9f7 163 { \
<> 144:ef7eb2e8f9f7 164 case RCC_USART1CLKSOURCE_PCLK1: \
<> 144:ef7eb2e8f9f7 165 (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 166 break; \
<> 144:ef7eb2e8f9f7 167 case RCC_USART1CLKSOURCE_HSI: \
<> 144:ef7eb2e8f9f7 168 (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
<> 144:ef7eb2e8f9f7 169 break; \
<> 144:ef7eb2e8f9f7 170 case RCC_USART1CLKSOURCE_SYSCLK: \
<> 144:ef7eb2e8f9f7 171 (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
<> 144:ef7eb2e8f9f7 172 break; \
<> 144:ef7eb2e8f9f7 173 case RCC_USART1CLKSOURCE_LSE: \
<> 144:ef7eb2e8f9f7 174 (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
<> 144:ef7eb2e8f9f7 175 break; \
<> 144:ef7eb2e8f9f7 176 default: \
<> 144:ef7eb2e8f9f7 177 (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 178 break; \
<> 144:ef7eb2e8f9f7 179 } \
<> 144:ef7eb2e8f9f7 180 } \
<> 144:ef7eb2e8f9f7 181 else if((__HANDLE__)->Instance == USART2) \
<> 144:ef7eb2e8f9f7 182 { \
<> 144:ef7eb2e8f9f7 183 switch(__HAL_RCC_GET_USART2_SOURCE()) \
<> 144:ef7eb2e8f9f7 184 { \
<> 144:ef7eb2e8f9f7 185 case RCC_USART2CLKSOURCE_PCLK1: \
<> 144:ef7eb2e8f9f7 186 (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 187 break; \
<> 144:ef7eb2e8f9f7 188 case RCC_USART2CLKSOURCE_HSI: \
<> 144:ef7eb2e8f9f7 189 (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
<> 144:ef7eb2e8f9f7 190 break; \
<> 144:ef7eb2e8f9f7 191 case RCC_USART2CLKSOURCE_SYSCLK: \
<> 144:ef7eb2e8f9f7 192 (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
<> 144:ef7eb2e8f9f7 193 break; \
<> 144:ef7eb2e8f9f7 194 case RCC_USART2CLKSOURCE_LSE: \
<> 144:ef7eb2e8f9f7 195 (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
<> 144:ef7eb2e8f9f7 196 break; \
<> 144:ef7eb2e8f9f7 197 default: \
<> 144:ef7eb2e8f9f7 198 (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 199 break; \
<> 144:ef7eb2e8f9f7 200 } \
<> 144:ef7eb2e8f9f7 201 } \
<> 144:ef7eb2e8f9f7 202 else if((__HANDLE__)->Instance == USART3) \
<> 144:ef7eb2e8f9f7 203 { \
<> 144:ef7eb2e8f9f7 204 (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 205 } \
<> 144:ef7eb2e8f9f7 206 else if((__HANDLE__)->Instance == USART4) \
<> 144:ef7eb2e8f9f7 207 { \
<> 144:ef7eb2e8f9f7 208 (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 209 } \
<> 144:ef7eb2e8f9f7 210 else \
<> 144:ef7eb2e8f9f7 211 { \
<> 144:ef7eb2e8f9f7 212 (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 213 } \
<> 156:95d6b41a828b 214 } while(0)
<> 144:ef7eb2e8f9f7 215 #elif defined(STM32F091xC) || defined(STM32F098xx)
<> 156:95d6b41a828b 216 #define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
<> 144:ef7eb2e8f9f7 217 do { \
<> 144:ef7eb2e8f9f7 218 if((__HANDLE__)->Instance == USART1) \
<> 144:ef7eb2e8f9f7 219 { \
<> 144:ef7eb2e8f9f7 220 switch(__HAL_RCC_GET_USART1_SOURCE()) \
<> 144:ef7eb2e8f9f7 221 { \
<> 144:ef7eb2e8f9f7 222 case RCC_USART1CLKSOURCE_PCLK1: \
<> 144:ef7eb2e8f9f7 223 (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 224 break; \
<> 144:ef7eb2e8f9f7 225 case RCC_USART1CLKSOURCE_HSI: \
<> 144:ef7eb2e8f9f7 226 (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
<> 144:ef7eb2e8f9f7 227 break; \
<> 144:ef7eb2e8f9f7 228 case RCC_USART1CLKSOURCE_SYSCLK: \
<> 144:ef7eb2e8f9f7 229 (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
<> 144:ef7eb2e8f9f7 230 break; \
<> 144:ef7eb2e8f9f7 231 case RCC_USART1CLKSOURCE_LSE: \
<> 144:ef7eb2e8f9f7 232 (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
<> 144:ef7eb2e8f9f7 233 break; \
<> 144:ef7eb2e8f9f7 234 default: \
<> 144:ef7eb2e8f9f7 235 (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 236 break; \
<> 144:ef7eb2e8f9f7 237 } \
<> 144:ef7eb2e8f9f7 238 } \
<> 144:ef7eb2e8f9f7 239 else if((__HANDLE__)->Instance == USART2) \
<> 144:ef7eb2e8f9f7 240 { \
<> 144:ef7eb2e8f9f7 241 switch(__HAL_RCC_GET_USART2_SOURCE()) \
<> 144:ef7eb2e8f9f7 242 { \
<> 144:ef7eb2e8f9f7 243 case RCC_USART2CLKSOURCE_PCLK1: \
<> 144:ef7eb2e8f9f7 244 (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 245 break; \
<> 144:ef7eb2e8f9f7 246 case RCC_USART2CLKSOURCE_HSI: \
<> 144:ef7eb2e8f9f7 247 (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
<> 144:ef7eb2e8f9f7 248 break; \
<> 144:ef7eb2e8f9f7 249 case RCC_USART2CLKSOURCE_SYSCLK: \
<> 144:ef7eb2e8f9f7 250 (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
<> 144:ef7eb2e8f9f7 251 break; \
<> 144:ef7eb2e8f9f7 252 case RCC_USART2CLKSOURCE_LSE: \
<> 144:ef7eb2e8f9f7 253 (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
<> 144:ef7eb2e8f9f7 254 break; \
<> 144:ef7eb2e8f9f7 255 default: \
<> 144:ef7eb2e8f9f7 256 (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 257 break; \
<> 144:ef7eb2e8f9f7 258 } \
<> 144:ef7eb2e8f9f7 259 } \
<> 144:ef7eb2e8f9f7 260 else if((__HANDLE__)->Instance == USART3) \
<> 144:ef7eb2e8f9f7 261 { \
<> 144:ef7eb2e8f9f7 262 switch(__HAL_RCC_GET_USART3_SOURCE()) \
<> 144:ef7eb2e8f9f7 263 { \
<> 144:ef7eb2e8f9f7 264 case RCC_USART3CLKSOURCE_PCLK1: \
<> 144:ef7eb2e8f9f7 265 (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 266 break; \
<> 144:ef7eb2e8f9f7 267 case RCC_USART3CLKSOURCE_HSI: \
<> 144:ef7eb2e8f9f7 268 (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
<> 144:ef7eb2e8f9f7 269 break; \
<> 144:ef7eb2e8f9f7 270 case RCC_USART3CLKSOURCE_SYSCLK: \
<> 144:ef7eb2e8f9f7 271 (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
<> 144:ef7eb2e8f9f7 272 break; \
<> 144:ef7eb2e8f9f7 273 case RCC_USART3CLKSOURCE_LSE: \
<> 144:ef7eb2e8f9f7 274 (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
<> 144:ef7eb2e8f9f7 275 break; \
<> 144:ef7eb2e8f9f7 276 default: \
<> 144:ef7eb2e8f9f7 277 (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 278 break; \
<> 144:ef7eb2e8f9f7 279 } \
<> 144:ef7eb2e8f9f7 280 } \
<> 144:ef7eb2e8f9f7 281 else if((__HANDLE__)->Instance == USART4) \
<> 144:ef7eb2e8f9f7 282 { \
<> 144:ef7eb2e8f9f7 283 (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 284 } \
<> 144:ef7eb2e8f9f7 285 else if((__HANDLE__)->Instance == USART5) \
<> 144:ef7eb2e8f9f7 286 { \
<> 144:ef7eb2e8f9f7 287 (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 288 } \
<> 144:ef7eb2e8f9f7 289 else if((__HANDLE__)->Instance == USART6) \
<> 144:ef7eb2e8f9f7 290 { \
<> 144:ef7eb2e8f9f7 291 (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 292 } \
<> 144:ef7eb2e8f9f7 293 else if((__HANDLE__)->Instance == USART7) \
<> 144:ef7eb2e8f9f7 294 { \
<> 144:ef7eb2e8f9f7 295 (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 296 } \
<> 144:ef7eb2e8f9f7 297 else if((__HANDLE__)->Instance == USART8) \
<> 144:ef7eb2e8f9f7 298 { \
<> 144:ef7eb2e8f9f7 299 (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 300 } \
<> 144:ef7eb2e8f9f7 301 else \
<> 144:ef7eb2e8f9f7 302 { \
<> 144:ef7eb2e8f9f7 303 (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 304 } \
<> 144:ef7eb2e8f9f7 305 } while(0)
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 #endif /* defined(STM32F031x6) || defined(STM32F038xx) */
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 /** @brief Compute the mask to apply to retrieve the received data
<> 144:ef7eb2e8f9f7 311 * according to the word length and to the parity bits activation.
<> 144:ef7eb2e8f9f7 312 * @note If PCE = 1, the parity bit is not included in the data extracted
<> 144:ef7eb2e8f9f7 313 * by the reception API().
<> 144:ef7eb2e8f9f7 314 * This masking operation is not carried out in the case of
<> 144:ef7eb2e8f9f7 315 * DMA transfers.
Anna Bridge 180:96ed750bd169 316 * @param __HANDLE__ specifies the IRDA Handle.
<> 156:95d6b41a828b 317 * @retval None, the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field.
<> 156:95d6b41a828b 318 */
<> 144:ef7eb2e8f9f7 319 #if defined (STM32F042x6) || defined (STM32F048xx) || \
<> 144:ef7eb2e8f9f7 320 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
<> 144:ef7eb2e8f9f7 321 defined (STM32F091xC) || defined (STM32F098xx)
<> 156:95d6b41a828b 322 #define IRDA_MASK_COMPUTATION(__HANDLE__) \
<> 144:ef7eb2e8f9f7 323 do { \
<> 144:ef7eb2e8f9f7 324 if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \
<> 144:ef7eb2e8f9f7 325 { \
<> 144:ef7eb2e8f9f7 326 if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
<> 144:ef7eb2e8f9f7 327 { \
<> 156:95d6b41a828b 328 (__HANDLE__)->Mask = 0x01FFU ; \
<> 144:ef7eb2e8f9f7 329 } \
<> 144:ef7eb2e8f9f7 330 else \
<> 144:ef7eb2e8f9f7 331 { \
<> 156:95d6b41a828b 332 (__HANDLE__)->Mask = 0x00FFU ; \
<> 144:ef7eb2e8f9f7 333 } \
<> 144:ef7eb2e8f9f7 334 } \
<> 144:ef7eb2e8f9f7 335 else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \
<> 144:ef7eb2e8f9f7 336 { \
<> 144:ef7eb2e8f9f7 337 if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
<> 144:ef7eb2e8f9f7 338 { \
<> 156:95d6b41a828b 339 (__HANDLE__)->Mask = 0x00FFU ; \
<> 144:ef7eb2e8f9f7 340 } \
<> 144:ef7eb2e8f9f7 341 else \
<> 144:ef7eb2e8f9f7 342 { \
<> 156:95d6b41a828b 343 (__HANDLE__)->Mask = 0x007FU ; \
<> 144:ef7eb2e8f9f7 344 } \
<> 144:ef7eb2e8f9f7 345 } \
<> 144:ef7eb2e8f9f7 346 else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) \
<> 144:ef7eb2e8f9f7 347 { \
<> 144:ef7eb2e8f9f7 348 if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
<> 144:ef7eb2e8f9f7 349 { \
<> 156:95d6b41a828b 350 (__HANDLE__)->Mask = 0x007FU ; \
<> 144:ef7eb2e8f9f7 351 } \
<> 144:ef7eb2e8f9f7 352 else \
<> 144:ef7eb2e8f9f7 353 { \
<> 156:95d6b41a828b 354 (__HANDLE__)->Mask = 0x003FU ; \
<> 144:ef7eb2e8f9f7 355 } \
<> 144:ef7eb2e8f9f7 356 } \
<> 156:95d6b41a828b 357 } while(0)
<> 144:ef7eb2e8f9f7 358 #else
<> 156:95d6b41a828b 359 #define IRDA_MASK_COMPUTATION(__HANDLE__) \
<> 144:ef7eb2e8f9f7 360 do { \
<> 144:ef7eb2e8f9f7 361 if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \
<> 144:ef7eb2e8f9f7 362 { \
<> 144:ef7eb2e8f9f7 363 if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
<> 144:ef7eb2e8f9f7 364 { \
<> 156:95d6b41a828b 365 (__HANDLE__)->Mask = 0x01FFU ; \
<> 144:ef7eb2e8f9f7 366 } \
<> 144:ef7eb2e8f9f7 367 else \
<> 144:ef7eb2e8f9f7 368 { \
<> 156:95d6b41a828b 369 (__HANDLE__)->Mask = 0x00FFU ; \
<> 144:ef7eb2e8f9f7 370 } \
<> 144:ef7eb2e8f9f7 371 } \
<> 144:ef7eb2e8f9f7 372 else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \
<> 144:ef7eb2e8f9f7 373 { \
<> 144:ef7eb2e8f9f7 374 if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
<> 144:ef7eb2e8f9f7 375 { \
<> 156:95d6b41a828b 376 (__HANDLE__)->Mask = 0x00FFU ; \
<> 144:ef7eb2e8f9f7 377 } \
<> 144:ef7eb2e8f9f7 378 else \
<> 144:ef7eb2e8f9f7 379 { \
<> 156:95d6b41a828b 380 (__HANDLE__)->Mask = 0x007FU ; \
<> 144:ef7eb2e8f9f7 381 } \
<> 144:ef7eb2e8f9f7 382 } \
<> 156:95d6b41a828b 383 } while(0)
<> 144:ef7eb2e8f9f7 384 #endif /* defined (STM32F042x6) || defined (STM32F048xx) || \
<> 144:ef7eb2e8f9f7 385 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
<> 144:ef7eb2e8f9f7 386 defined (STM32F091xC) || defined(STM32F098xx) */
<> 144:ef7eb2e8f9f7 387
<> 144:ef7eb2e8f9f7 388 /**
<> 144:ef7eb2e8f9f7 389 * @brief Ensure that IRDA frame length is valid.
Anna Bridge 180:96ed750bd169 390 * @param __LENGTH__ IRDA frame length.
<> 144:ef7eb2e8f9f7 391 * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
<> 144:ef7eb2e8f9f7 392 */
<> 144:ef7eb2e8f9f7 393 #if defined (STM32F042x6) || defined (STM32F048xx) || \
<> 144:ef7eb2e8f9f7 394 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
<> 144:ef7eb2e8f9f7 395 defined (STM32F091xC) || defined (STM32F098xx)
<> 144:ef7eb2e8f9f7 396 #define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_7B) || \
<> 144:ef7eb2e8f9f7 397 ((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
<> 144:ef7eb2e8f9f7 398 ((__LENGTH__) == IRDA_WORDLENGTH_9B))
<> 144:ef7eb2e8f9f7 399 #else
<> 144:ef7eb2e8f9f7 400 #define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
<> 144:ef7eb2e8f9f7 401 ((__LENGTH__) == IRDA_WORDLENGTH_9B))
<> 144:ef7eb2e8f9f7 402 #endif /* defined (STM32F042x6) || defined (STM32F048xx) || \
<> 144:ef7eb2e8f9f7 403 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
<> 144:ef7eb2e8f9f7 404 defined (STM32F091xC) || defined (STM32F098xx)*/
<> 144:ef7eb2e8f9f7 405
<> 144:ef7eb2e8f9f7 406 /**
<> 144:ef7eb2e8f9f7 407 * @}
<> 144:ef7eb2e8f9f7 408 */
<> 144:ef7eb2e8f9f7 409
<> 144:ef7eb2e8f9f7 410 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 411
<> 144:ef7eb2e8f9f7 412 /**
<> 144:ef7eb2e8f9f7 413 * @}
<> 144:ef7eb2e8f9f7 414 */
<> 144:ef7eb2e8f9f7 415
<> 144:ef7eb2e8f9f7 416 /**
<> 144:ef7eb2e8f9f7 417 * @}
<> 144:ef7eb2e8f9f7 418 */
<> 144:ef7eb2e8f9f7 419
<> 144:ef7eb2e8f9f7 420 #endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 423 }
<> 144:ef7eb2e8f9f7 424 #endif
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426 #endif /* __STM32F0xx_HAL_IRDA_EX_H */
<> 144:ef7eb2e8f9f7 427
<> 144:ef7eb2e8f9f7 428 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 429