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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_cortex.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
180:96ed750bd169 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_cortex.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief CORTEX HAL module driver.
<> 144:ef7eb2e8f9f7 6 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 7 * functionalities of the CORTEX:
<> 144:ef7eb2e8f9f7 8 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 9 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * @verbatim
<> 144:ef7eb2e8f9f7 12 ==============================================================================
<> 144:ef7eb2e8f9f7 13 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 14 ==============================================================================
<> 144:ef7eb2e8f9f7 15
<> 144:ef7eb2e8f9f7 16 [..]
<> 144:ef7eb2e8f9f7 17 *** How to configure Interrupts using CORTEX HAL driver ***
<> 144:ef7eb2e8f9f7 18 ===========================================================
<> 144:ef7eb2e8f9f7 19 [..]
<> 144:ef7eb2e8f9f7 20 This section provides functions allowing to configure the NVIC interrupts (IRQ).
<> 144:ef7eb2e8f9f7 21 The Cortex-M0 exceptions are managed by CMSIS functions.
<> 144:ef7eb2e8f9f7 22 (#) Enable and Configure the priority of the selected IRQ Channels.
<> 144:ef7eb2e8f9f7 23 The priority can be 0..3.
<> 144:ef7eb2e8f9f7 24
<> 144:ef7eb2e8f9f7 25 -@- Lower priority values gives higher priority.
<> 144:ef7eb2e8f9f7 26 -@- Priority Order:
<> 144:ef7eb2e8f9f7 27 (#@) Lowest priority.
<> 144:ef7eb2e8f9f7 28 (#@) Lowest hardware priority (IRQn position).
<> 144:ef7eb2e8f9f7 29
<> 144:ef7eb2e8f9f7 30 (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()
<> 144:ef7eb2e8f9f7 31
<> 144:ef7eb2e8f9f7 32 (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 -@- Negative value of IRQn_Type are not allowed.
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 [..]
<> 144:ef7eb2e8f9f7 38 *** How to configure Systick using CORTEX HAL driver ***
<> 144:ef7eb2e8f9f7 39 ========================================================
<> 144:ef7eb2e8f9f7 40 [..]
<> 144:ef7eb2e8f9f7 41 Setup SysTick Timer for time base.
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
<> 144:ef7eb2e8f9f7 44 is a CMSIS function that:
<> 144:ef7eb2e8f9f7 45 (++) Configures the SysTick Reload register with value passed as function parameter.
<> 144:ef7eb2e8f9f7 46 (++) Configures the SysTick IRQ priority to the lowest value (0x03).
<> 144:ef7eb2e8f9f7 47 (++) Resets the SysTick Counter register.
<> 144:ef7eb2e8f9f7 48 (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
<> 144:ef7eb2e8f9f7 49 (++) Enables the SysTick Interrupt.
<> 144:ef7eb2e8f9f7 50 (++) Starts the SysTick Counter.
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
<> 144:ef7eb2e8f9f7 53 HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
<> 144:ef7eb2e8f9f7 54 HAL_SYSTICK_Config() function call. The HAL_SYSTICK_CLKSourceConfig() macro is defined
<> 144:ef7eb2e8f9f7 55 inside the stm32f0xx_hal_cortex.h file.
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 (+) You can change the SysTick IRQ priority by calling the
<> 144:ef7eb2e8f9f7 58 HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
<> 144:ef7eb2e8f9f7 59 call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 (+) To adjust the SysTick time base, use the following formula:
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
<> 144:ef7eb2e8f9f7 64 (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
<> 144:ef7eb2e8f9f7 65 (++) Reload Value should not exceed 0xFFFFFF
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 @endverbatim
<> 144:ef7eb2e8f9f7 68 ******************************************************************************
<> 144:ef7eb2e8f9f7 69 * @attention
<> 144:ef7eb2e8f9f7 70 *
<> 144:ef7eb2e8f9f7 71 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 72 *
<> 144:ef7eb2e8f9f7 73 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 74 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 75 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 76 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 77 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 78 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 79 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 80 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 81 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 82 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 83 *
<> 144:ef7eb2e8f9f7 84 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 85 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 86 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 87 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 88 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 89 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 90 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 91 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 92 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 93 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 94 *
<> 144:ef7eb2e8f9f7 95 ******************************************************************************
<> 144:ef7eb2e8f9f7 96 */
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 99 #include "stm32f0xx_hal.h"
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 102 * @{
<> 144:ef7eb2e8f9f7 103 */
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 /** @defgroup CORTEX CORTEX
<> 144:ef7eb2e8f9f7 106 * @brief CORTEX CORTEX HAL module driver
<> 144:ef7eb2e8f9f7 107 * @{
<> 144:ef7eb2e8f9f7 108 */
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 #ifdef HAL_CORTEX_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 113 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 114 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 115 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 116 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 117 /* Exported functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
<> 144:ef7eb2e8f9f7 120 * @{
<> 144:ef7eb2e8f9f7 121 */
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 125 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 126 *
<> 144:ef7eb2e8f9f7 127 @verbatim
<> 144:ef7eb2e8f9f7 128 ==============================================================================
<> 144:ef7eb2e8f9f7 129 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 130 ==============================================================================
<> 144:ef7eb2e8f9f7 131 [..]
<> 144:ef7eb2e8f9f7 132 This section provides the CORTEX HAL driver functions allowing to configure Interrupts
<> 144:ef7eb2e8f9f7 133 Systick functionalities
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 @endverbatim
<> 144:ef7eb2e8f9f7 136 * @{
<> 144:ef7eb2e8f9f7 137 */
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 /**
<> 144:ef7eb2e8f9f7 140 * @brief Sets the priority of an interrupt.
Anna Bridge 180:96ed750bd169 141 * @param IRQn External interrupt number .
<> 144:ef7eb2e8f9f7 142 * This parameter can be an enumerator of IRQn_Type enumeration
Anna Bridge 180:96ed750bd169 143 * (For the complete STM32 Devices IRQ Channels list, please refer to stm32f0xx.h file)
Anna Bridge 180:96ed750bd169 144 * @param PreemptPriority The preemption priority for the IRQn channel.
<> 144:ef7eb2e8f9f7 145 * This parameter can be a value between 0 and 3.
<> 144:ef7eb2e8f9f7 146 * A lower priority value indicates a higher priority
Anna Bridge 180:96ed750bd169 147 * @param SubPriority the subpriority level for the IRQ channel.
<> 144:ef7eb2e8f9f7 148 * with stm32f0xx devices, this parameter is a dummy value and it is ignored, because
<> 144:ef7eb2e8f9f7 149 * no subpriority supported in Cortex M0 based products.
<> 144:ef7eb2e8f9f7 150 * @retval None
<> 144:ef7eb2e8f9f7 151 */
<> 144:ef7eb2e8f9f7 152 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
<> 144:ef7eb2e8f9f7 153 {
<> 144:ef7eb2e8f9f7 154 /* Check the parameters */
<> 144:ef7eb2e8f9f7 155 assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
<> 144:ef7eb2e8f9f7 156 NVIC_SetPriority(IRQn,PreemptPriority);
<> 144:ef7eb2e8f9f7 157 }
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 /**
<> 144:ef7eb2e8f9f7 160 * @brief Enables a device specific interrupt in the NVIC interrupt controller.
<> 144:ef7eb2e8f9f7 161 * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
<> 144:ef7eb2e8f9f7 162 * function should be called before.
<> 144:ef7eb2e8f9f7 163 * @param IRQn External interrupt number.
<> 144:ef7eb2e8f9f7 164 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 165 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h))
<> 144:ef7eb2e8f9f7 166 * @retval None
<> 144:ef7eb2e8f9f7 167 */
<> 144:ef7eb2e8f9f7 168 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 169 {
<> 144:ef7eb2e8f9f7 170 /* Check the parameters */
<> 144:ef7eb2e8f9f7 171 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 /* Enable interrupt */
<> 144:ef7eb2e8f9f7 174 NVIC_EnableIRQ(IRQn);
<> 144:ef7eb2e8f9f7 175 }
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 /**
<> 144:ef7eb2e8f9f7 178 * @brief Disables a device specific interrupt in the NVIC interrupt controller.
<> 144:ef7eb2e8f9f7 179 * @param IRQn External interrupt number.
<> 144:ef7eb2e8f9f7 180 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 181 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h))
<> 144:ef7eb2e8f9f7 182 * @retval None
<> 144:ef7eb2e8f9f7 183 */
<> 144:ef7eb2e8f9f7 184 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 185 {
<> 144:ef7eb2e8f9f7 186 /* Check the parameters */
<> 144:ef7eb2e8f9f7 187 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 /* Disable interrupt */
<> 144:ef7eb2e8f9f7 190 NVIC_DisableIRQ(IRQn);
<> 144:ef7eb2e8f9f7 191 }
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 /**
<> 144:ef7eb2e8f9f7 194 * @brief Initiates a system reset request to reset the MCU.
<> 144:ef7eb2e8f9f7 195 * @retval None
<> 144:ef7eb2e8f9f7 196 */
<> 144:ef7eb2e8f9f7 197 void HAL_NVIC_SystemReset(void)
<> 144:ef7eb2e8f9f7 198 {
<> 144:ef7eb2e8f9f7 199 /* System Reset */
<> 144:ef7eb2e8f9f7 200 NVIC_SystemReset();
<> 144:ef7eb2e8f9f7 201 }
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 /**
<> 144:ef7eb2e8f9f7 204 * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
<> 144:ef7eb2e8f9f7 205 * Counter is in free running mode to generate periodic interrupts.
Anna Bridge 180:96ed750bd169 206 * @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
<> 144:ef7eb2e8f9f7 207 * @retval status: - 0 Function succeeded.
<> 144:ef7eb2e8f9f7 208 * - 1 Function failed.
<> 144:ef7eb2e8f9f7 209 */
<> 144:ef7eb2e8f9f7 210 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
<> 144:ef7eb2e8f9f7 211 {
<> 144:ef7eb2e8f9f7 212 return SysTick_Config(TicksNumb);
<> 144:ef7eb2e8f9f7 213 }
<> 144:ef7eb2e8f9f7 214 /**
<> 144:ef7eb2e8f9f7 215 * @}
<> 144:ef7eb2e8f9f7 216 */
<> 144:ef7eb2e8f9f7 217
<> 144:ef7eb2e8f9f7 218 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
<> 144:ef7eb2e8f9f7 219 * @brief Cortex control functions
<> 144:ef7eb2e8f9f7 220 *
<> 144:ef7eb2e8f9f7 221 @verbatim
<> 144:ef7eb2e8f9f7 222 ==============================================================================
<> 144:ef7eb2e8f9f7 223 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 224 ==============================================================================
<> 144:ef7eb2e8f9f7 225 [..]
<> 144:ef7eb2e8f9f7 226 This subsection provides a set of functions allowing to control the CORTEX
<> 144:ef7eb2e8f9f7 227 (NVIC, SYSTICK) functionalities.
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 @endverbatim
<> 144:ef7eb2e8f9f7 231 * @{
<> 144:ef7eb2e8f9f7 232 */
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 /**
<> 144:ef7eb2e8f9f7 236 * @brief Gets the priority of an interrupt.
Anna Bridge 180:96ed750bd169 237 * @param IRQn External interrupt number.
<> 144:ef7eb2e8f9f7 238 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 239 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h))
<> 144:ef7eb2e8f9f7 240 * @retval None
<> 144:ef7eb2e8f9f7 241 */
<> 144:ef7eb2e8f9f7 242 uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 243 {
<> 144:ef7eb2e8f9f7 244 /* Get priority for Cortex-M system or device specific interrupts */
<> 144:ef7eb2e8f9f7 245 return NVIC_GetPriority(IRQn);
<> 144:ef7eb2e8f9f7 246 }
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 /**
<> 144:ef7eb2e8f9f7 249 * @brief Sets Pending bit of an external interrupt.
<> 144:ef7eb2e8f9f7 250 * @param IRQn External interrupt number
<> 144:ef7eb2e8f9f7 251 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 252 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h))
<> 144:ef7eb2e8f9f7 253 * @retval None
<> 144:ef7eb2e8f9f7 254 */
<> 144:ef7eb2e8f9f7 255 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 256 {
<> 144:ef7eb2e8f9f7 257 /* Check the parameters */
<> 144:ef7eb2e8f9f7 258 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 /* Set interrupt pending */
<> 144:ef7eb2e8f9f7 261 NVIC_SetPendingIRQ(IRQn);
<> 144:ef7eb2e8f9f7 262 }
<> 144:ef7eb2e8f9f7 263
<> 144:ef7eb2e8f9f7 264 /**
<> 144:ef7eb2e8f9f7 265 * @brief Gets Pending Interrupt (reads the pending register in the NVIC
<> 144:ef7eb2e8f9f7 266 * and returns the pending bit for the specified interrupt).
<> 144:ef7eb2e8f9f7 267 * @param IRQn External interrupt number.
<> 144:ef7eb2e8f9f7 268 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 269 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h))
<> 144:ef7eb2e8f9f7 270 * @retval status: - 0 Interrupt status is not pending.
<> 144:ef7eb2e8f9f7 271 * - 1 Interrupt status is pending.
<> 144:ef7eb2e8f9f7 272 */
<> 144:ef7eb2e8f9f7 273 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 274 {
<> 144:ef7eb2e8f9f7 275 /* Check the parameters */
<> 144:ef7eb2e8f9f7 276 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 /* Return 1 if pending else 0 */
<> 144:ef7eb2e8f9f7 279 return NVIC_GetPendingIRQ(IRQn);
<> 144:ef7eb2e8f9f7 280 }
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282 /**
<> 144:ef7eb2e8f9f7 283 * @brief Clears the pending bit of an external interrupt.
<> 144:ef7eb2e8f9f7 284 * @param IRQn External interrupt number.
<> 144:ef7eb2e8f9f7 285 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 286 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h))
<> 144:ef7eb2e8f9f7 287 * @retval None
<> 144:ef7eb2e8f9f7 288 */
<> 144:ef7eb2e8f9f7 289 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 290 {
<> 144:ef7eb2e8f9f7 291 /* Check the parameters */
<> 144:ef7eb2e8f9f7 292 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
<> 144:ef7eb2e8f9f7 293
<> 144:ef7eb2e8f9f7 294 /* Clear pending interrupt */
<> 144:ef7eb2e8f9f7 295 NVIC_ClearPendingIRQ(IRQn);
<> 144:ef7eb2e8f9f7 296 }
<> 144:ef7eb2e8f9f7 297
<> 144:ef7eb2e8f9f7 298 /**
<> 144:ef7eb2e8f9f7 299 * @brief Configures the SysTick clock source.
Anna Bridge 180:96ed750bd169 300 * @param CLKSource specifies the SysTick clock source.
<> 144:ef7eb2e8f9f7 301 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 302 * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
<> 144:ef7eb2e8f9f7 303 * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
<> 144:ef7eb2e8f9f7 304 * @retval None
<> 144:ef7eb2e8f9f7 305 */
<> 144:ef7eb2e8f9f7 306 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
<> 144:ef7eb2e8f9f7 307 {
<> 144:ef7eb2e8f9f7 308 /* Check the parameters */
<> 144:ef7eb2e8f9f7 309 assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
<> 144:ef7eb2e8f9f7 310 if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
<> 144:ef7eb2e8f9f7 311 {
<> 144:ef7eb2e8f9f7 312 SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
<> 144:ef7eb2e8f9f7 313 }
<> 144:ef7eb2e8f9f7 314 else
<> 144:ef7eb2e8f9f7 315 {
<> 144:ef7eb2e8f9f7 316 SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
<> 144:ef7eb2e8f9f7 317 }
<> 144:ef7eb2e8f9f7 318 }
<> 144:ef7eb2e8f9f7 319
<> 144:ef7eb2e8f9f7 320 /**
<> 144:ef7eb2e8f9f7 321 * @brief This function handles SYSTICK interrupt request.
<> 144:ef7eb2e8f9f7 322 * @retval None
<> 144:ef7eb2e8f9f7 323 */
<> 144:ef7eb2e8f9f7 324 void HAL_SYSTICK_IRQHandler(void)
<> 144:ef7eb2e8f9f7 325 {
<> 144:ef7eb2e8f9f7 326 HAL_SYSTICK_Callback();
<> 144:ef7eb2e8f9f7 327 }
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 /**
<> 144:ef7eb2e8f9f7 330 * @brief SYSTICK callback.
<> 144:ef7eb2e8f9f7 331 * @retval None
<> 144:ef7eb2e8f9f7 332 */
<> 144:ef7eb2e8f9f7 333 __weak void HAL_SYSTICK_Callback(void)
<> 144:ef7eb2e8f9f7 334 {
<> 144:ef7eb2e8f9f7 335 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 336 the HAL_SYSTICK_Callback could be implemented in the user file
<> 144:ef7eb2e8f9f7 337 */
<> 144:ef7eb2e8f9f7 338 }
<> 144:ef7eb2e8f9f7 339
<> 144:ef7eb2e8f9f7 340 /**
<> 144:ef7eb2e8f9f7 341 * @}
<> 144:ef7eb2e8f9f7 342 */
<> 144:ef7eb2e8f9f7 343
<> 144:ef7eb2e8f9f7 344 /**
<> 144:ef7eb2e8f9f7 345 * @}
<> 144:ef7eb2e8f9f7 346 */
<> 144:ef7eb2e8f9f7 347
<> 144:ef7eb2e8f9f7 348 #endif /* HAL_CORTEX_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 349 /**
<> 144:ef7eb2e8f9f7 350 * @}
<> 144:ef7eb2e8f9f7 351 */
<> 144:ef7eb2e8f9f7 352
<> 144:ef7eb2e8f9f7 353 /**
<> 144:ef7eb2e8f9f7 354 * @}
<> 144:ef7eb2e8f9f7 355 */
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/