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mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_sys.h@173:e131a1973e81, 2017-09-15 (annotated)
- Committer:
- AnnaBridge
- Date:
- Fri Sep 15 14:59:18 2017 +0100
- Revision:
- 173:e131a1973e81
- Parent:
- 172:7d866c31b3c5
This updates the lib to the mbed lib v 151
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 172:7d866c31b3c5 | 1 | /**************************************************************************//** |
| AnnaBridge | 172:7d866c31b3c5 | 2 | * @file SYS.h |
| AnnaBridge | 172:7d866c31b3c5 | 3 | * @version V3.0 |
| AnnaBridge | 172:7d866c31b3c5 | 4 | * @brief M480 Series SYS Driver Header File |
| AnnaBridge | 172:7d866c31b3c5 | 5 | * |
| AnnaBridge | 172:7d866c31b3c5 | 6 | * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. |
| AnnaBridge | 172:7d866c31b3c5 | 7 | ******************************************************************************/ |
| AnnaBridge | 172:7d866c31b3c5 | 8 | |
| AnnaBridge | 172:7d866c31b3c5 | 9 | #ifndef __SYS_H__ |
| AnnaBridge | 172:7d866c31b3c5 | 10 | #define __SYS_H__ |
| AnnaBridge | 172:7d866c31b3c5 | 11 | |
| AnnaBridge | 172:7d866c31b3c5 | 12 | #ifdef __cplusplus |
| AnnaBridge | 172:7d866c31b3c5 | 13 | extern "C" |
| AnnaBridge | 172:7d866c31b3c5 | 14 | { |
| AnnaBridge | 172:7d866c31b3c5 | 15 | #endif |
| AnnaBridge | 172:7d866c31b3c5 | 16 | |
| AnnaBridge | 172:7d866c31b3c5 | 17 | |
| AnnaBridge | 172:7d866c31b3c5 | 18 | /** @addtogroup M480_Device_Driver M480 Device Driver |
| AnnaBridge | 172:7d866c31b3c5 | 19 | @{ |
| AnnaBridge | 172:7d866c31b3c5 | 20 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 21 | |
| AnnaBridge | 172:7d866c31b3c5 | 22 | /** @addtogroup M480_SYS_Driver SYS Driver |
| AnnaBridge | 172:7d866c31b3c5 | 23 | @{ |
| AnnaBridge | 172:7d866c31b3c5 | 24 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 25 | |
| AnnaBridge | 172:7d866c31b3c5 | 26 | /** @addtogroup M480_SYS_EXPORTED_CONSTANTS SYS Exported Constants |
| AnnaBridge | 172:7d866c31b3c5 | 27 | @{ |
| AnnaBridge | 172:7d866c31b3c5 | 28 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 29 | |
| AnnaBridge | 172:7d866c31b3c5 | 30 | |
| AnnaBridge | 172:7d866c31b3c5 | 31 | /*---------------------------------------------------------------------------------------------------------*/ |
| AnnaBridge | 172:7d866c31b3c5 | 32 | /* Module Reset Control Resister constant definitions. */ |
| AnnaBridge | 172:7d866c31b3c5 | 33 | /*---------------------------------------------------------------------------------------------------------*/ |
| AnnaBridge | 172:7d866c31b3c5 | 34 | #define PDMA_RST ((0UL<<24) | SYS_IPRST0_PDMARST_Pos) /*!< Reset PDMA \hideinitializer*/ |
| AnnaBridge | 172:7d866c31b3c5 | 35 | #define EBI_RST ((0UL<<24) | SYS_IPRST0_EBIRST_Pos) /*!< Reset EBI \hideinitializer*/ |
| AnnaBridge | 172:7d866c31b3c5 | 36 | #define EMAC_RST ((0UL<<24) | SYS_IPRST0_EMACRST_Pos) /*!< Reset EMAC \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 37 | #define SDH0_RST ((0UL<<24) | SYS_IPRST0_SDH0RST_Pos) /*!< Reset SDH0 \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 38 | #define CRC_RST ((0UL<<24) | SYS_IPRST0_CRCRST_Pos) /*!< Reset CRC \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 39 | #define HSUSBD_RST ((0UL<<24) | SYS_IPRST0_HSUSBDRST_Pos) /*!< Reset HSUSBD \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 40 | #define CRPT_RST ((0UL<<24) | SYS_IPRST0_CRPTRST_Pos) /*!< Reset CRPT \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 41 | #define SPIM_RST ((0UL<<24) | SYS_IPRST0_SPIMRST_Pos) /*!< Reset SPIM \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 42 | #define USBH_RST ((0UL<<24) | SYS_IPRST0_USBHRST_Pos) /*!< Reset USBH \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 43 | #define SDH1_RST ((0UL<<24) | SYS_IPRST0_SDH1RST_Pos) /*!< Reset SDH1 \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 44 | |
| AnnaBridge | 172:7d866c31b3c5 | 45 | #define GPIO_RST ((4UL<<24) | SYS_IPRST1_GPIORST_Pos) /*!< Reset GPIO \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 46 | #define TMR0_RST ((4UL<<24) | SYS_IPRST1_TMR0RST_Pos) /*!< Reset TMR0 \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 47 | #define TMR1_RST ((4UL<<24) | SYS_IPRST1_TMR1RST_Pos) /*!< Reset TMR1 \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 48 | #define TMR2_RST ((4UL<<24) | SYS_IPRST1_TMR2RST_Pos) /*!< Reset TMR2 \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 49 | #define TMR3_RST ((4UL<<24) | SYS_IPRST1_TMR3RST_Pos) /*!< Reset TMR3 \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 50 | #define ACMP01_RST ((4UL<<24) | SYS_IPRST1_ACMP01RST_Pos) /*!< Reset ACMP01 \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 51 | #define I2C0_RST ((4UL<<24) | SYS_IPRST1_I2C0RST_Pos) /*!< Reset I2C0 \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 52 | #define I2C1_RST ((4UL<<24) | SYS_IPRST1_I2C1RST_Pos) /*!< Reset I2C1 \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 53 | #define I2C2_RST ((4UL<<24) | SYS_IPRST1_I2C2RST_Pos) /*!< Reset I2C2 \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 54 | #define SPI0_RST ((4UL<<24) | SYS_IPRST1_SPI0RST_Pos) /*!< Reset SPI0 \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 55 | #define SPI1_RST ((4UL<<24) | SYS_IPRST1_SPI1RST_Pos) /*!< Reset SPI1 \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 56 | #define SPI2_RST ((4UL<<24) | SYS_IPRST1_SPI2RST_Pos) /*!< Reset SPI2 \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 57 | #define SPI3_RST ((4UL<<24) | SYS_IPRST1_SPI3RST_Pos) /*!< Reset SPI3 \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 58 | #define UART0_RST ((4UL<<24) | SYS_IPRST1_UART0RST_Pos) /*!< Reset UART0 \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 59 | #define UART1_RST ((4UL<<24) | SYS_IPRST1_UART1RST_Pos) /*!< Reset UART1 \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 60 | #define UART2_RST ((4UL<<24) | SYS_IPRST1_UART2RST_Pos) /*!< Reset UART2 \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 61 | #define UART3_RST ((4UL<<24) | SYS_IPRST1_UART3RST_Pos) /*!< Reset UART3 \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 62 | #define UART4_RST ((4UL<<24) | SYS_IPRST1_UART4RST_Pos) /*!< Reset UART4 \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 63 | #define UART5_RST ((4UL<<24) | SYS_IPRST1_UART5RST_Pos) /*!< Reset UART5 \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 64 | #define CAN0_RST ((4UL<<24) | SYS_IPRST1_CAN0RST_Pos) /*!< Reset CAN0 \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 65 | #define CAN1_RST ((4UL<<24) | SYS_IPRST1_CAN1RST_Pos) /*!< Reset CAN1 \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 66 | #define USBD_RST ((4UL<<24) | SYS_IPRST1_USBDRST_Pos) /*!< Reset USBD \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 67 | #define EADC_RST ((4UL<<24) | SYS_IPRST1_EADCRST_Pos) /*!< Reset EADC \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 68 | #define I2S0_RST ((4UL<<24) | SYS_IPRST1_I2S0RST_Pos) /*!< Reset I2S0 \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 69 | |
| AnnaBridge | 172:7d866c31b3c5 | 70 | #define SC0_RST ((8UL<<24) | SYS_IPRST2_SC0RST_Pos) /*!< Reset SC0 \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 71 | #define SC1_RST ((8UL<<24) | SYS_IPRST2_SC1RST_Pos) /*!< Reset SC1 \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 72 | #define SC2_RST ((8UL<<24) | SYS_IPRST2_SC2RST_Pos) /*!< Reset SC2 \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 73 | #define SPI4_RST ((8UL<<24) | SYS_IPRST2_SPI4RST_Pos) /*!< Reset SPI4 \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 74 | #define USCI0_RST ((8UL<<24) | SYS_IPRST2_USCI0RST_Pos) /*!< Reset USCI0 \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 75 | #define USCI1_RST ((8UL<<24) | SYS_IPRST2_USCI1RST_Pos) /*!< Reset USCI1 \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 76 | #define DAC_RST ((8UL<<24) | SYS_IPRST2_DACRST_Pos) /*!< Reset DAC \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 77 | #define EPWM0_RST ((8UL<<24) | SYS_IPRST2_EPWM0RST_Pos) /*!< Reset EPWM0 \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 78 | #define EPWM1_RST ((8UL<<24) | SYS_IPRST2_EPWM1RST_Pos) /*!< Reset EPWM1 \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 79 | #define BPWM0_RST ((8UL<<24) | SYS_IPRST2_BPWM0RST_Pos) /*!< Reset BPWM0 \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 80 | #define BPWM1_RST ((8UL<<24) | SYS_IPRST2_BPWM1RST_Pos) /*!< Reset BPWM1 \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 81 | #define QEI0_RST ((8UL<<24) | SYS_IPRST2_QEI0RST_Pos) /*!< Reset QEI0 \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 82 | #define QEI1_RST ((8UL<<24) | SYS_IPRST2_QEI1RST_Pos) /*!< Reset QEI1 \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 83 | #define ECAP0_RST ((8UL<<24) | SYS_IPRST2_ECAP0RST_Pos) /*!< Reset ECAP0 \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 84 | #define ECAP1_RST ((8UL<<24) | SYS_IPRST2_ECAP1RST_Pos) /*!< Reset ECAP1 \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 85 | #define OPA_RST ((8UL<<24) | SYS_IPRST2_OPARST_Pos) /*!< Reset OPA \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 86 | |
| AnnaBridge | 172:7d866c31b3c5 | 87 | /*---------------------------------------------------------------------------------------------------------*/ |
| AnnaBridge | 172:7d866c31b3c5 | 88 | /* Brown Out Detector Threshold Voltage Selection constant definitions. */ |
| AnnaBridge | 172:7d866c31b3c5 | 89 | /*---------------------------------------------------------------------------------------------------------*/ |
| AnnaBridge | 172:7d866c31b3c5 | 90 | #define SYS_BODCTL_BOD_RST_EN (1UL << SYS_BODCTL_BODRSTEN_Pos) /*!< Brown-out Reset Enable \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 91 | #define SYS_BODCTL_BOD_INTERRUPT_EN (0UL << SYS_BODCTL_BODRSTEN_Pos) /*!< Brown-out Interrupt Enable \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 92 | #define SYS_BODCTL_BODVL_3_0V (7UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 3.0V \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 93 | #define SYS_BODCTL_BODVL_2_8V (6UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.8V \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 94 | #define SYS_BODCTL_BODVL_2_6V (5UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.6V \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 95 | #define SYS_BODCTL_BODVL_2_4V (4UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.4V \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 96 | #define SYS_BODCTL_BODVL_2_2V (3UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.2V \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 97 | #define SYS_BODCTL_BODVL_2_0V (2UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.0V \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 98 | #define SYS_BODCTL_BODVL_1_8V (1UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 1.8V \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 99 | #define SYS_BODCTL_BODVL_1_6V (0UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 1.6V \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 100 | |
| AnnaBridge | 172:7d866c31b3c5 | 101 | |
| AnnaBridge | 172:7d866c31b3c5 | 102 | /*---------------------------------------------------------------------------------------------------------*/ |
| AnnaBridge | 172:7d866c31b3c5 | 103 | /* VREFCTL constant definitions. (Write-Protection Register) */ |
| AnnaBridge | 172:7d866c31b3c5 | 104 | /*---------------------------------------------------------------------------------------------------------*/ |
| AnnaBridge | 172:7d866c31b3c5 | 105 | #define SYS_VREFCTL_VREF_PIN (0x0UL << SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = Vref pin \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 106 | #define SYS_VREFCTL_VREF_1_6V (0x3UL << SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = 1.6V \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 107 | #define SYS_VREFCTL_VREF_2_0V (0x7UL << SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = 2.0V \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 108 | #define SYS_VREFCTL_VREF_2_5V (0xBUL << SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = 2.5V \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 109 | #define SYS_VREFCTL_VREF_3_0V (0xFUL << SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = 3.0V \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 110 | #define SYS_VREFCTL_VREF_AVDD (0x10UL << SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = AVDD \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 111 | |
| AnnaBridge | 172:7d866c31b3c5 | 112 | |
| AnnaBridge | 172:7d866c31b3c5 | 113 | /*---------------------------------------------------------------------------------------------------------*/ |
| AnnaBridge | 172:7d866c31b3c5 | 114 | /* USBPHY constant definitions. (Write-Protection Register) */ |
| AnnaBridge | 172:7d866c31b3c5 | 115 | /*---------------------------------------------------------------------------------------------------------*/ |
| AnnaBridge | 172:7d866c31b3c5 | 116 | #define SYS_USBPHY_USBROLE_STD_USBD (0x0UL << SYS_USBPHY_USBROLE_Pos) /*!< Standard USB device \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 117 | #define SYS_USBPHY_USBROLE_STD_USBH (0x1UL << SYS_USBPHY_USBROLE_Pos) /*!< Standard USB host \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 118 | #define SYS_USBPHY_USBROLE_ID_DEPH (0x2UL << SYS_USBPHY_USBROLE_Pos) /*!< ID dependent device \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 119 | #define SYS_USBPHY_USBROLE_ON_THE_GO (0x3UL << SYS_USBPHY_USBROLE_Pos) /*!< On-The-Go device \hideinitializer */ |
| AnnaBridge | 173:e131a1973e81 | 120 | #define SYS_USBPHY_HSUSBROLE_STD_USBD (0x0UL << SYS_USBPHY_HSUSBROLE_Pos) /*!< Standard USB device \hideinitializer */ |
| AnnaBridge | 173:e131a1973e81 | 121 | #define SYS_USBPHY_HSUSBROLE_STD_USBH (0x1UL << SYS_USBPHY_HSUSBROLE_Pos) /*!< Standard USB host \hideinitializer */ |
| AnnaBridge | 173:e131a1973e81 | 122 | #define SYS_USBPHY_HSUSBROLE_ID_DEPH (0x2UL << SYS_USBPHY_HSUSBROLE_Pos) /*!< ID dependent device \hideinitializer */ |
| AnnaBridge | 173:e131a1973e81 | 123 | #define SYS_USBPHY_HSUSBROLE_ON_THE_GO (0x3UL << SYS_USBPHY_HSUSBROLE_Pos) /*!< On-The-Go device \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 124 | |
| AnnaBridge | 172:7d866c31b3c5 | 125 | /*---------------------------------------------------------------------------------------------------------*/ |
| AnnaBridge | 172:7d866c31b3c5 | 126 | /* Multi-Function constant definitions. */ |
| AnnaBridge | 172:7d866c31b3c5 | 127 | /*---------------------------------------------------------------------------------------------------------*/ |
| AnnaBridge | 172:7d866c31b3c5 | 128 | /* How to use below #define? |
| AnnaBridge | 172:7d866c31b3c5 | 129 | Example 1: If user want to set PA.0 as SC0_CLK in initial function, |
| AnnaBridge | 172:7d866c31b3c5 | 130 | user can issue following command to achieve it. |
| AnnaBridge | 172:7d866c31b3c5 | 131 | |
| AnnaBridge | 172:7d866c31b3c5 | 132 | SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SYS_GPA_MFPL_PA0MFP_Msk) ) | SYS_GPA_MFPL_PA0_MFP_SC0_CLK ; |
| AnnaBridge | 172:7d866c31b3c5 | 133 | |
| AnnaBridge | 172:7d866c31b3c5 | 134 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 135 | /********************* Bit definition of GPA_MFPL register **********************/ |
| AnnaBridge | 172:7d866c31b3c5 | 136 | #define SYS_GPA_MFPL_PA0MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 137 | #define SYS_GPA_MFPL_PA0MFP_SPIM_MOSI (0x02UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< 1st SPIM MOSI (Master Out, Slave In) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 138 | #define SYS_GPA_MFPL_PA0MFP_SPI0_MOSI0 (0x03UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< 1st SPI0 MOSI (Master Out, Slave In) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 139 | #define SYS_GPA_MFPL_PA0MFP_SPI1_MOSI (0x04UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< 1st SPI1 MOSI (Master Out, Slave In) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 140 | #define SYS_GPA_MFPL_PA0MFP_SD1_DAT0 (0x05UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< SD/SDIO 1 data line bit 0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 141 | #define SYS_GPA_MFPL_PA0MFP_SC0_CLK (0x06UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< SmartCard0 clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 142 | #define SYS_GPA_MFPL_PA0MFP_UART0_RXD (0x07UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< Data receiver input pin for UART0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 143 | #define SYS_GPA_MFPL_PA0MFP_UART1_nRTS (0x08UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< Request to Send output pin for UART1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 144 | #define SYS_GPA_MFPL_PA0MFP_I2C2_SDA (0x09UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< I2C2 data input/output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 145 | #define SYS_GPA_MFPL_PA0MFP_BPWM0_CH0 (0x0CUL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< BPWM0 channel0 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 146 | #define SYS_GPA_MFPL_PA0MFP_EPWM0_CH5 (0x0DUL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< EPWM0 channel5 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 147 | #define SYS_GPA_MFPL_PA0MFP_DAC0_ST (0x0FUL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< DAC0 external trigger input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 148 | #define SYS_GPA_MFPL_PA1MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 149 | #define SYS_GPA_MFPL_PA1MFP_SPIM_MISO (0x02UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< 1st SPIM MISO (Master In, Slave Out) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 150 | #define SYS_GPA_MFPL_PA1MFP_SPI0_MISO0 (0x03UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< 1st SPI0 MISO (Master In, Slave Out) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 151 | #define SYS_GPA_MFPL_PA1MFP_SPI1_MISO (0x04UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< 1st SPI1 MISO (Master In, Slave Out) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 152 | #define SYS_GPA_MFPL_PA1MFP_SD1_DAT1 (0x05UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< SD/SDIO 1 data line bit 1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 153 | #define SYS_GPA_MFPL_PA1MFP_SC0_DAT (0x06UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< SmartCard0 data pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 154 | #define SYS_GPA_MFPL_PA1MFP_UART0_TXD (0x07UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< Data transmitter output pin for UART0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 155 | #define SYS_GPA_MFPL_PA1MFP_UART1_nCTS (0x08UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< Clear to Send input pin for UART1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 156 | #define SYS_GPA_MFPL_PA1MFP_I2C2_SCL (0x09UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< I2C2 clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 157 | #define SYS_GPA_MFPL_PA1MFP_BPWM0_CH1 (0x0CUL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< BPWM0 channel1 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 158 | #define SYS_GPA_MFPL_PA1MFP_EPWM0_CH4 (0x0DUL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< EPWM0 channel4 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 159 | #define SYS_GPA_MFPL_PA1MFP_DAC1_ST (0x0FUL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< DAC1 external trigger input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 160 | #define SYS_GPA_MFPL_PA2MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 161 | #define SYS_GPA_MFPL_PA2MFP_SPIM_CLK (0x02UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< SPIM serial clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 162 | #define SYS_GPA_MFPL_PA2MFP_SPI0_CLK (0x03UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< SPI0 serial clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 163 | #define SYS_GPA_MFPL_PA2MFP_SPI1_CLK (0x04UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< SPI1 serial clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 164 | #define SYS_GPA_MFPL_PA2MFP_SD1_DAT2 (0x05UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< SD/SDIO 1 data line bit 2. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 165 | #define SYS_GPA_MFPL_PA2MFP_SC0_RST (0x06UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< SmartCard0 reset pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 166 | #define SYS_GPA_MFPL_PA2MFP_UART4_RXD (0x07UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< Data receiver input pin for UART4. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 167 | #define SYS_GPA_MFPL_PA2MFP_UART1_RXD (0x08UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< Data receiver input pin for UART1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 168 | #define SYS_GPA_MFPL_PA2MFP_I2C1_SDA (0x09UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< I2C1 data input/output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 169 | #define SYS_GPA_MFPL_PA2MFP_BPWM0_CH2 (0x0CUL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< BPWM0 channel2 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 170 | #define SYS_GPA_MFPL_PA2MFP_EPWM0_CH3 (0x0DUL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< EPWM0 channel3 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 171 | #define SYS_GPA_MFPL_PA3MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 172 | #define SYS_GPA_MFPL_PA3MFP_SPIM_SS (0x02UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< 1st SPIM slave select pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 173 | #define SYS_GPA_MFPL_PA3MFP_SPI0_SS (0x03UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< 1st SPI0 slave select pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 174 | #define SYS_GPA_MFPL_PA3MFP_SPI1_SS (0x04UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< 1st SPI1 slave select pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 175 | #define SYS_GPA_MFPL_PA3MFP_SD1_DAT3 (0x05UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< SD/SDIO 1 data line bit 3. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 176 | #define SYS_GPA_MFPL_PA3MFP_SC0_PWR (0x06UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< SmartCard0 power pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 177 | #define SYS_GPA_MFPL_PA3MFP_UART4_TXD (0x07UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< Data transmitter output pin for UART4. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 178 | #define SYS_GPA_MFPL_PA3MFP_UART1_TXD (0x08UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< Data transmitter output pin for UART1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 179 | #define SYS_GPA_MFPL_PA3MFP_I2C1_SCL (0x09UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< I2C1 clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 180 | #define SYS_GPA_MFPL_PA3MFP_BPWM0_CH3 (0x0CUL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< BPWM0 channel3 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 181 | #define SYS_GPA_MFPL_PA3MFP_EPWM0_CH2 (0x0DUL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< EPWM0 channel2 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 182 | #define SYS_GPA_MFPL_PA3MFP_QEI0_B (0x0EUL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< Quadrature encoder phase B input of QEI Unit 0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 183 | #define SYS_GPA_MFPL_PA4MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 184 | #define SYS_GPA_MFPL_PA4MFP_SPIM_D3 (0x02UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< SPIM data 3 pin for Quad Mode I/O. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 185 | #define SYS_GPA_MFPL_PA4MFP_SPI0_MOSI1 (0x03UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< 2nd SPI0 MOSI (Master Out, Slave In) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 186 | #define SYS_GPA_MFPL_PA4MFP_SPI1_I2SMCLK (0x04UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< SPI1 I2S master clock output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 187 | #define SYS_GPA_MFPL_PA4MFP_SD1_CLK (0x05UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< SD/SDIO 1 clock. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 188 | #define SYS_GPA_MFPL_PA4MFP_SC0_nCD (0x06UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< SmartCard0 card detect pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 189 | #define SYS_GPA_MFPL_PA4MFP_UART0_nRTS (0x07UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< Request to Send output pin for UART0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 190 | #define SYS_GPA_MFPL_PA4MFP_UART5_RXD (0x08UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< Data receiver input pin for UART5. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 191 | #define SYS_GPA_MFPL_PA4MFP_I2C0_SDA (0x09UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< I2C0 data input/output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 192 | #define SYS_GPA_MFPL_PA4MFP_CAN0_RXD (0x0AUL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< CAN0 bus receiver input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 193 | #define SYS_GPA_MFPL_PA4MFP_BPWM0_CH4 (0x0CUL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< BPWM0 channel4 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 194 | #define SYS_GPA_MFPL_PA4MFP_EPWM0_CH1 (0x0DUL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< EPWM0 channel1 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 195 | #define SYS_GPA_MFPL_PA4MFP_QEI0_A (0x0EUL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< Quadrature encoder phase A input of QEI Unit 0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 196 | #define SYS_GPA_MFPL_PA5MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 197 | #define SYS_GPA_MFPL_PA5MFP_SPIM_D2 (0x02UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< SPIM data 2 pin for Quad Mode I/O. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 198 | #define SYS_GPA_MFPL_PA5MFP_SPI0_MISO1 (0x03UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< 2nd SPI0 MISO (Master In, Slave Out) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 199 | #define SYS_GPA_MFPL_PA5MFP_SPI2_I2SMCLK (0x04UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< SPI2 I2S master clock output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 200 | #define SYS_GPA_MFPL_PA5MFP_SD1_CMD (0x05UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< SD/SDIO 1 command/response. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 201 | #define SYS_GPA_MFPL_PA5MFP_SC2_nCD (0x06UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< SmartCard2 card detect pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 202 | #define SYS_GPA_MFPL_PA5MFP_UART0_nCTS (0x07UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< Clear to Send input pin for UART0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 203 | #define SYS_GPA_MFPL_PA5MFP_UART5_TXD (0x08UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< Data transmitter output pin for UART5. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 204 | #define SYS_GPA_MFPL_PA5MFP_I2C0_SCL (0x09UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< I2C0 clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 205 | #define SYS_GPA_MFPL_PA5MFP_CAN0_TXD (0x0AUL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< CAN0 bus transmitter output. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 206 | #define SYS_GPA_MFPL_PA5MFP_BPWM0_CH5 (0x0CUL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< BPWM0 channel5 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 207 | #define SYS_GPA_MFPL_PA5MFP_EPWM0_CH0 (0x0DUL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< EPWM0 channel0 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 208 | #define SYS_GPA_MFPL_PA5MFP_QEI0_INDEX (0x0EUL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< Quadrature encoder index input of QEI Unit 0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 209 | #define SYS_GPA_MFPL_PA6MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 210 | #define SYS_GPA_MFPL_PA6MFP_EBI_AD6 (0x02UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< EBI address/data bus bit6. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 211 | #define SYS_GPA_MFPL_PA6MFP_EMAC_RMII_RXERR (0x03UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< RMII Receive Data error. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 212 | #define SYS_GPA_MFPL_PA6MFP_SPI2_SS (0x04UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< 1st SPI2 slave select pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 213 | #define SYS_GPA_MFPL_PA6MFP_SD1_nCD (0x05UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< SD/SDIO 1 card detect \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 214 | #define SYS_GPA_MFPL_PA6MFP_SC2_CLK (0x06UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< SmartCard2 clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 215 | #define SYS_GPA_MFPL_PA6MFP_UART0_RXD (0x07UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< Data receiver input pin for UART0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 216 | #define SYS_GPA_MFPL_PA6MFP_I2C1_SDA (0x08UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< I2C1 data input/output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 217 | #define SYS_GPA_MFPL_PA6MFP_EPWM1_CH5 (0x0BUL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< EPWM1 channel5 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 218 | #define SYS_GPA_MFPL_PA6MFP_BPWM1_CH3 (0x0CUL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< BPWM1 channel3 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 219 | #define SYS_GPA_MFPL_PA6MFP_ACMP1_WLAT (0x0DUL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< Analog comparator1 window latch input pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 220 | #define SYS_GPA_MFPL_PA6MFP_TM3 (0x0EUL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< Timer3 event counter input / toggle output \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 221 | #define SYS_GPA_MFPL_PA6MFP_INT0 (0x0FUL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< External interrupt0 input pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 222 | #define SYS_GPA_MFPL_PA7MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 223 | #define SYS_GPA_MFPL_PA7MFP_EBI_AD7 (0x02UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< EBI address/data bus bit7. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 224 | #define SYS_GPA_MFPL_PA7MFP_EMAC_RMII_CRSDV (0x03UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< MII Receive Data Valid / RMII CRS_DV input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 225 | #define SYS_GPA_MFPL_PA7MFP_SPI2_CLK (0x04UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< SPI2 serial clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 226 | #define SYS_GPA_MFPL_PA7MFP_SC2_DAT (0x06UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< SmartCard2 data pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 227 | #define SYS_GPA_MFPL_PA7MFP_UART0_TXD (0x07UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< Data transmitter output pin for UART0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 228 | #define SYS_GPA_MFPL_PA7MFP_I2C1_SCL (0x08UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< I2C1 clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 229 | #define SYS_GPA_MFPL_PA7MFP_EPWM1_CH4 (0x0BUL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< EPWM1 channel4 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 230 | #define SYS_GPA_MFPL_PA7MFP_BPWM1_CH2 (0x0CUL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< BPWM1 channel2 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 231 | #define SYS_GPA_MFPL_PA7MFP_ACMP0_WLAT (0x0DUL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< Analog comparator0 window latch input pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 232 | #define SYS_GPA_MFPL_PA7MFP_TM2 (0x0EUL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< Timer2 event counter input / toggle output \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 233 | #define SYS_GPA_MFPL_PA7MFP_INT1 (0x0FUL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< External interrupt1 input pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 234 | /********************* Bit definition of GPA_MFPH register **********************/ |
| AnnaBridge | 172:7d866c31b3c5 | 235 | #define SYS_GPA_MFPH_PA8MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 236 | #define SYS_GPA_MFPH_PA8MFP_OPA1_P (0x01UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< Operational amplifier positive input pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 237 | #define SYS_GPA_MFPH_PA8MFP_EBI_ALE (0x02UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< EBI address latch enable output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 238 | #define SYS_GPA_MFPH_PA8MFP_SC2_CLK (0x03UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< SmartCard2 clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 239 | #define SYS_GPA_MFPH_PA8MFP_SPI3_MOSI (0x04UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< 1st SPI3 MOSI (Master Out, Slave In) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 240 | #define SYS_GPA_MFPH_PA8MFP_SD1_DAT0 (0x05UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< SD/SDIO 1 data line bit 0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 241 | #define SYS_GPA_MFPH_PA8MFP_USCI0_CTL1 (0x06UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< USCI0 control1 pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 242 | #define SYS_GPA_MFPH_PA8MFP_UART1_RXD (0x07UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< Data receiver input pin for UART1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 243 | #define SYS_GPA_MFPH_PA8MFP_BPWM0_CH3 (0x09UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< BPWM0 channel3 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 244 | #define SYS_GPA_MFPH_PA8MFP_QEI1_B (0x0AUL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< Quadrature encoder phase B input of QEI Unit 1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 245 | #define SYS_GPA_MFPH_PA8MFP_ECAP0_IC2 (0x0BUL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< Input 0 of enhanced capture unit 2. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 246 | #define SYS_GPA_MFPH_PA8MFP_TM3_EXT (0x0DUL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< Timer3 event counter input / toggle output \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 247 | #define SYS_GPA_MFPH_PA8MFP_INT4 (0x0FUL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< External interrupt4 input pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 248 | #define SYS_GPA_MFPH_PA9MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 249 | #define SYS_GPA_MFPH_PA9MFP_OPA1_N (0x01UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< Operational amplifier negative input pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 250 | #define SYS_GPA_MFPH_PA9MFP_EBI_MCLK (0x02UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< EBI external clock output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 251 | #define SYS_GPA_MFPH_PA9MFP_SC2_DAT (0x03UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< SmartCard2 data pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 252 | #define SYS_GPA_MFPH_PA9MFP_SPI3_MISO (0x04UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< 1st SPI3 MISO (Master In, Slave Out) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 253 | #define SYS_GPA_MFPH_PA9MFP_SD1_DAT1 (0x05UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< SD/SDIO 1 data line bit 1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 254 | #define SYS_GPA_MFPH_PA9MFP_USCI0_DAT1 (0x06UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< USCI0 data1 pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 255 | #define SYS_GPA_MFPH_PA9MFP_UART1_TXD (0x07UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< Data transmitter output pin for UART1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 256 | #define SYS_GPA_MFPH_PA9MFP_BPWM0_CH2 (0x09UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< BPWM0 channel2 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 257 | #define SYS_GPA_MFPH_PA9MFP_QEI1_A (0x0AUL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< Quadrature encoder phase A input of QEI Unit 1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 258 | #define SYS_GPA_MFPH_PA9MFP_ECAP0_IC1 (0x0BUL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< Input 1 of enhanced capture unit 0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 259 | #define SYS_GPA_MFPH_PA9MFP_TM2_EXT (0x0DUL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< Timer2 event counter input / toggle output \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 260 | #define SYS_GPA_MFPH_PA9MFP_SWDH_DAT (0x0FUL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< SWD Host interface input/output bus bit. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 261 | #define SYS_GPA_MFPH_PA10MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 262 | #define SYS_GPA_MFPH_PA10MFP_ACMP1_P0 (0x01UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< Analog comparator1 positive input pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 263 | #define SYS_GPA_MFPH_PA10MFP_OPA1_O (0x01UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< Operational amplifier output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 264 | #define SYS_GPA_MFPH_PA10MFP_EBI_nWR (0x02UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< EBI write enable output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 265 | #define SYS_GPA_MFPH_PA10MFP_SC2_RST (0x03UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< SmartCard2 reset pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 266 | #define SYS_GPA_MFPH_PA10MFP_SPI3_CLK (0x04UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< SPI3 serial clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 267 | #define SYS_GPA_MFPH_PA10MFP_SD1_DAT2 (0x05UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< SD/SDIO 1 data line bit 2. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 268 | #define SYS_GPA_MFPH_PA10MFP_USCI0_DAT0 (0x06UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< USCI0 data0 pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 269 | #define SYS_GPA_MFPH_PA10MFP_I2C2_SDA (0x07UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< I2C2 data input/output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 270 | #define SYS_GPA_MFPH_PA10MFP_BPWM0_CH1 (0x09UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< BPWM0 channel1 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 271 | #define SYS_GPA_MFPH_PA10MFP_QEI1_INDEX (0x0AUL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< Quadrature encoder index input of QEI Unit 1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 272 | #define SYS_GPA_MFPH_PA10MFP_ECAP0_IC0 (0x0BUL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< Input 0 of enhanced capture unit 0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 273 | #define SYS_GPA_MFPH_PA10MFP_TM1_EXT (0x0DUL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< Timer1 event counter input / toggle output \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 274 | #define SYS_GPA_MFPH_PA10MFP_DAC0_ST (0x0EUL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< DAC0 external trigger input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 275 | #define SYS_GPA_MFPH_PA10MFP_SWDH_CLK (0x0FUL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< SWD Host interface clock output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 276 | #define SYS_GPA_MFPH_PA11MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 277 | #define SYS_GPA_MFPH_PA11MFP_ACMP0_P0 (0x01UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< Analog comparator0 positive input pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 278 | #define SYS_GPA_MFPH_PA11MFP_EBI_nRD (0x02UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< EBI read enable output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 279 | #define SYS_GPA_MFPH_PA11MFP_SC2_PWR (0x03UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< SmartCard2 power pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 280 | #define SYS_GPA_MFPH_PA11MFP_SPI3_SS (0x04UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< 1st SPI3 slave select pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 281 | #define SYS_GPA_MFPH_PA11MFP_SD1_DAT3 (0x05UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< SD/SDIO 1 data line bit 3. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 282 | #define SYS_GPA_MFPH_PA11MFP_USCI0_CLK (0x06UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< USCI0 clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 283 | #define SYS_GPA_MFPH_PA11MFP_I2C2_SCL (0x07UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< I2C2 clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 284 | #define SYS_GPA_MFPH_PA11MFP_BPWM0_CH0 (0x09UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< BPWM0 channel0 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 285 | #define SYS_GPA_MFPH_PA11MFP_EPWM0_SYNC_OUT (0x0AUL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< EPWM0 counter synchronous trigger output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 286 | #define SYS_GPA_MFPH_PA11MFP_TM0_EXT (0x0DUL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< Timer0 event counter input / toggle output \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 287 | #define SYS_GPA_MFPH_PA11MFP_DAC1_ST (0x0EUL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< DAC1 external trigger input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 288 | #define SYS_GPA_MFPH_PA12MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 289 | #define SYS_GPA_MFPH_PA12MFP_I2S0_BCLK (0x02UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< I2S0 bit clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 290 | #define SYS_GPA_MFPH_PA12MFP_UART4_TXD (0x03UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< Data transmitter output pin for UART4. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 291 | #define SYS_GPA_MFPH_PA12MFP_I2C1_SCL (0x04UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< I2C1 clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 292 | #define SYS_GPA_MFPH_PA12MFP_SPI3_SS (0x05UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< 1st SPI3 slave select pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 293 | #define SYS_GPA_MFPH_PA12MFP_CAN0_TXD (0x06UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< CAN0 bus transmitter output. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 294 | #define SYS_GPA_MFPH_PA12MFP_SC2_PWR (0x07UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< SmartCard2 power pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 295 | #define SYS_GPA_MFPH_PA12MFP_BPWM1_CH2 (0x0BUL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< BPWM1 channel2 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 296 | #define SYS_GPA_MFPH_PA12MFP_QEI1_INDEX (0x0CUL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< Quadrature encoder index input of QEI Unit 1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 297 | #define SYS_GPA_MFPH_PA12MFP_USB_VBUS (0x0EUL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< Power supply from USB Full speed host or HUB. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 298 | #define SYS_GPA_MFPH_PA13MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 299 | #define SYS_GPA_MFPH_PA13MFP_I2S0_MCLK (0x02UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< I2S0 master clock output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 300 | #define SYS_GPA_MFPH_PA13MFP_UART4_RXD (0x03UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< Data receiver input pin for UART4. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 301 | #define SYS_GPA_MFPH_PA13MFP_I2C1_SDA (0x04UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< I2C1 data input/output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 302 | #define SYS_GPA_MFPH_PA13MFP_SPI3_CLK (0x05UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< SPI3 serial clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 303 | #define SYS_GPA_MFPH_PA13MFP_CAN0_RXD (0x06UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< CAN0 bus receiver input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 304 | #define SYS_GPA_MFPH_PA13MFP_SC2_RST (0x07UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< SmartCard2 reset pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 305 | #define SYS_GPA_MFPH_PA13MFP_BPWM1_CH3 (0x0BUL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< BPWM1 channel3 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 306 | #define SYS_GPA_MFPH_PA13MFP_QEI1_A (0x0CUL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< Quadrature encoder phase A input of QEI Unit 1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 307 | #define SYS_GPA_MFPH_PA13MFP_USB_D_N (0x0EUL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< USB Full speed differential signal D-. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 308 | #define SYS_GPA_MFPH_PA14MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 309 | #define SYS_GPA_MFPH_PA14MFP_I2S0_DI (0x02UL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< I2S0 data input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 310 | #define SYS_GPA_MFPH_PA14MFP_UART0_TXD (0x03UL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< Data transmitter output pin for UART0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 311 | #define SYS_GPA_MFPH_PA14MFP_SPI3_MISO (0x05UL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< 1st SPI3 MISO (Master In, Slave Out) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 312 | #define SYS_GPA_MFPH_PA14MFP_I2C2_SCL (0x06UL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< I2C2 clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 313 | #define SYS_GPA_MFPH_PA14MFP_SC2_DAT (0x07UL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< SmartCard2 data pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 314 | #define SYS_GPA_MFPH_PA14MFP_BPWM1_CH4 (0x0BUL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< BPWM1 channel4 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 315 | #define SYS_GPA_MFPH_PA14MFP_QEI1_B (0x0CUL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< Quadrature encoder phase B input of QEI Unit 1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 316 | #define SYS_GPA_MFPH_PA14MFP_USB_D_P (0x0EUL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< USB Full speed differential signal D+. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 317 | #define SYS_GPA_MFPH_PA15MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 318 | #define SYS_GPA_MFPH_PA15MFP_I2S0_DO (0x02UL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< I2S0 data output. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 319 | #define SYS_GPA_MFPH_PA15MFP_UART0_RXD (0x03UL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< Data receiver input pin for UART0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 320 | #define SYS_GPA_MFPH_PA15MFP_SPI3_MOSI (0x05UL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< 1st SPI3 MOSI (Master Out, Slave In) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 321 | #define SYS_GPA_MFPH_PA15MFP_I2C2_SDA (0x06UL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< I2C2 data input/output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 322 | #define SYS_GPA_MFPH_PA15MFP_SC2_CLK (0x07UL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< SmartCard2 clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 323 | #define SYS_GPA_MFPH_PA15MFP_BPWM1_CH5 (0x0BUL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< BPWM1 channel5 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 324 | #define SYS_GPA_MFPH_PA15MFP_EPWM0_SYNC_IN (0x0CUL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< EPWM0 counter synchronous trigger input pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 325 | #define SYS_GPA_MFPH_PA15MFP_USB_OTG_ID (0x0EUL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< USB Full speed identification. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 326 | /********************* Bit definition of GPB_MFPL register **********************/ |
| AnnaBridge | 172:7d866c31b3c5 | 327 | #define SYS_GPB_MFPL_PB0MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 328 | #define SYS_GPB_MFPL_PB0MFP_EADC0_CH0 (0x01UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< EADC0 channel0 analog input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 329 | #define SYS_GPB_MFPL_PB0MFP_OPA0_P (0x01UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< Operational amplifier positive input pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 330 | #define SYS_GPB_MFPL_PB0MFP_EBI_ADR9 (0x02UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 331 | #define SYS_GPB_MFPL_PB0MFP_SD0_CMD (0x03UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< SD/SDIO 0 command/response. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 332 | #define SYS_GPB_MFPL_PB0MFP_UART2_RXD (0x07UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< Data receiver input pin for UART2. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 333 | #define SYS_GPB_MFPL_PB0MFP_SPI1_I2SMCLK (0x08UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< SPI1 I2S master clock output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 334 | #define SYS_GPB_MFPL_PB0MFP_I2C1_SDA (0x09UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< I2C1 data input/output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 335 | #define SYS_GPB_MFPL_PB0MFP_EPWM0_CH5 (0x0BUL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< EPWM0 channel5 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 336 | #define SYS_GPB_MFPL_PB0MFP_EPWM1_CH5 (0x0CUL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< EPWM1 channel5 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 337 | #define SYS_GPB_MFPL_PB0MFP_EPWM0_BRAKE1 (0x0DUL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< Brake input pin 1 of EPWM0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 338 | #define SYS_GPB_MFPL_PB1MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 339 | #define SYS_GPB_MFPL_PB1MFP_EADC0_CH1 (0x01UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< EADC0 channel1 analog input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 340 | #define SYS_GPB_MFPL_PB1MFP_OPA0_N (0x01UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< Operational amplifier negative input pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 341 | #define SYS_GPB_MFPL_PB1MFP_EBI_ADR8 (0x02UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 342 | #define SYS_GPB_MFPL_PB1MFP_SD0_CLK (0x03UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< SD/SDIO 0 clock. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 343 | #define SYS_GPB_MFPL_PB1MFP_EMAC_RMII_RXERR (0x04UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< RMII Receive Data error. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 344 | #define SYS_GPB_MFPL_PB1MFP_SPI2_I2SMCLK (0x05UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< SPI2 I2S master clock output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 345 | #define SYS_GPB_MFPL_PB1MFP_SPI4_I2SMCLK (0x06UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< SPI4 I2S master clock output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 346 | #define SYS_GPB_MFPL_PB1MFP_UART2_TXD (0x07UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< Data transmitter output pin for UART2. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 347 | #define SYS_GPB_MFPL_PB1MFP_USCI1_CLK (0x08UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< USCI1 clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 348 | #define SYS_GPB_MFPL_PB1MFP_I2C1_SCL (0x09UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< I2C1 clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 349 | #define SYS_GPB_MFPL_PB1MFP_I2S0_LRCK (0x0AUL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< I2S0 left right channel clock. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 350 | #define SYS_GPB_MFPL_PB1MFP_EPWM0_CH4 (0x0BUL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< EPWM0 channel4 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 351 | #define SYS_GPB_MFPL_PB1MFP_EPWM1_CH4 (0x0CUL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< EPWM1 channel4 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 352 | #define SYS_GPB_MFPL_PB1MFP_EPWM0_BRAKE0 (0x0DUL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< Brake input pin 0 of EPWM0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 353 | #define SYS_GPB_MFPL_PB2MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 354 | #define SYS_GPB_MFPL_PB2MFP_ACMP0_P1 (0x01UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< Analog comparator0 positive input pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 355 | #define SYS_GPB_MFPL_PB2MFP_EADC0_CH2 (0x01UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< EADC0 channel2 analog input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 356 | #define SYS_GPB_MFPL_PB2MFP_OPA0_O (0x01UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< Operational amplifier output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 357 | #define SYS_GPB_MFPL_PB2MFP_EBI_ADR3 (0x02UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 358 | #define SYS_GPB_MFPL_PB2MFP_SD0_DAT0 (0x03UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< SD/SDIO 0 data line bit 0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 359 | #define SYS_GPB_MFPL_PB2MFP_EMAC_RMII_CRSDV (0x04UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< MII Receive Data Valid / RMII CRS_DV input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 360 | #define SYS_GPB_MFPL_PB2MFP_SPI2_SS (0x05UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< 1st SPI2 slave select pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 361 | #define SYS_GPB_MFPL_PB2MFP_UART1_RXD (0x06UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< Data receiver input pin for UART1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 362 | #define SYS_GPB_MFPL_PB2MFP_UART5_nCTS (0x07UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< Clear to Send input pin for UART5. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 363 | #define SYS_GPB_MFPL_PB2MFP_USCI1_DAT0 (0x08UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< USCI1 data0 pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 364 | #define SYS_GPB_MFPL_PB2MFP_SC0_PWR (0x09UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< SmartCard0 power pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 365 | #define SYS_GPB_MFPL_PB2MFP_I2S0_DO (0x0AUL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< I2S0 data output. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 366 | #define SYS_GPB_MFPL_PB2MFP_EPWM0_CH3 (0x0BUL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< EPWM0 channel3 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 367 | #define SYS_GPB_MFPL_PB2MFP_TM3 (0x0EUL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< Timer3 event counter input / toggle output \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 368 | #define SYS_GPB_MFPL_PB2MFP_INT3 (0x0FUL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< External interrupt3 input pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 369 | #define SYS_GPB_MFPL_PB3MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 370 | #define SYS_GPB_MFPL_PB3MFP_ACMP0_N (0x01UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< Analog comparator0 negative input pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 371 | #define SYS_GPB_MFPL_PB3MFP_EADC0_CH3 (0x01UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< EADC0 channel3 analog input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 372 | #define SYS_GPB_MFPL_PB3MFP_EBI_ADR2 (0x02UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 373 | #define SYS_GPB_MFPL_PB3MFP_SD0_DAT1 (0x03UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< SD/SDIO 0 data line bit 1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 374 | #define SYS_GPB_MFPL_PB3MFP_EMAC_RMII_RXD1 (0x04UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< RMII Receive Data bus bit 1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 375 | #define SYS_GPB_MFPL_PB3MFP_SPI2_CLK (0x05UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< SPI2 serial clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 376 | #define SYS_GPB_MFPL_PB3MFP_UART1_TXD (0x06UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< Data transmitter output pin for UART1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 377 | #define SYS_GPB_MFPL_PB3MFP_UART5_nRTS (0x07UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< Request to Send output pin for UART5. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 378 | #define SYS_GPB_MFPL_PB3MFP_USCI1_DAT1 (0x08UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< USCI1 data1 pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 379 | #define SYS_GPB_MFPL_PB3MFP_SC0_RST (0x09UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< SmartCard0 reset pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 380 | #define SYS_GPB_MFPL_PB3MFP_I2S0_DI (0x0AUL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< I2S0 data input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 381 | #define SYS_GPB_MFPL_PB3MFP_EPWM0_CH2 (0x0BUL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< EPWM0 channel2 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 382 | #define SYS_GPB_MFPL_PB3MFP_TM2 (0x0EUL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< Timer2 event counter input / toggle output \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 383 | #define SYS_GPB_MFPL_PB3MFP_INT2 (0x0FUL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< External interrupt2 input pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 384 | #define SYS_GPB_MFPL_PB4MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 385 | #define SYS_GPB_MFPL_PB4MFP_ACMP1_P1 (0x01UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< Analog comparator1 positive input pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 386 | #define SYS_GPB_MFPL_PB4MFP_EADC0_CH4 (0x01UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< EADC0 channel4 analog input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 387 | #define SYS_GPB_MFPL_PB4MFP_EBI_ADR1 (0x02UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 388 | #define SYS_GPB_MFPL_PB4MFP_SD0_DAT2 (0x03UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< SD/SDIO 0 data line bit 2. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 389 | #define SYS_GPB_MFPL_PB4MFP_EMAC_RMII_RXD0 (0x04UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< RMII Receive Data bus bit 0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 390 | #define SYS_GPB_MFPL_PB4MFP_SPI2_MOSI (0x05UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< 1st SPI2 MOSI (Master Out, Slave In) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 391 | #define SYS_GPB_MFPL_PB4MFP_I2C0_SDA (0x06UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< I2C0 data input/output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 392 | #define SYS_GPB_MFPL_PB4MFP_UART5_RXD (0x07UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< Data receiver input pin for UART5. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 393 | #define SYS_GPB_MFPL_PB4MFP_USCI1_CTL1 (0x08UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< USCI1 control1 pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 394 | #define SYS_GPB_MFPL_PB4MFP_SC0_DAT (0x09UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< SmartCard0 data pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 395 | #define SYS_GPB_MFPL_PB4MFP_I2S0_MCLK (0x0AUL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< I2S0 master clock output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 396 | #define SYS_GPB_MFPL_PB4MFP_EPWM0_CH1 (0x0BUL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< EPWM0 channel1 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 397 | #define SYS_GPB_MFPL_PB4MFP_TM1 (0x0EUL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< Timer1 event counter input / toggle output \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 398 | #define SYS_GPB_MFPL_PB4MFP_INT1 (0x0FUL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< External interrupt1 input pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 399 | #define SYS_GPB_MFPL_PB5MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 400 | #define SYS_GPB_MFPL_PB5MFP_ACMP1_N (0x01UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< Analog comparator1 negative input pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 401 | #define SYS_GPB_MFPL_PB5MFP_EADC0_CH5 (0x01UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< EADC0 channel5 analog input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 402 | #define SYS_GPB_MFPL_PB5MFP_EBI_ADR0 (0x02UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 403 | #define SYS_GPB_MFPL_PB5MFP_SD0_DAT3 (0x03UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< SD/SDIO 0 data line bit 3. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 404 | #define SYS_GPB_MFPL_PB5MFP_EMAC_RMII_REFCLK (0x04UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< EMAC mode clock input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 405 | #define SYS_GPB_MFPL_PB5MFP_SPI2_MISO (0x05UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< 1st SPI2 MISO (Master In, Slave Out) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 406 | #define SYS_GPB_MFPL_PB5MFP_I2C0_SCL (0x06UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< I2C0 clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 407 | #define SYS_GPB_MFPL_PB5MFP_UART5_TXD (0x07UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< Data transmitter output pin for UART5. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 408 | #define SYS_GPB_MFPL_PB5MFP_USCI1_CTL0 (0x08UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< USCI1 control0 pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 409 | #define SYS_GPB_MFPL_PB5MFP_SC0_CLK (0x09UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< SmartCard0 clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 410 | #define SYS_GPB_MFPL_PB5MFP_I2S0_BCLK (0x0AUL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< I2S0 bit clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 411 | #define SYS_GPB_MFPL_PB5MFP_EPWM0_CH0 (0x0BUL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< EPWM0 channel0 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 412 | #define SYS_GPB_MFPL_PB5MFP_TM0 (0x0EUL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< Timer0 event counter input / toggle output \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 413 | #define SYS_GPB_MFPL_PB5MFP_INT0 (0x0FUL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< External interrupt0 input pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 414 | #define SYS_GPB_MFPL_PB6MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 415 | #define SYS_GPB_MFPL_PB6MFP_EADC0_CH6 (0x01UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< EADC0 channel6 analog input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 416 | #define SYS_GPB_MFPL_PB6MFP_EBI_nWRH (0x02UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< EBI write enable output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 417 | #define SYS_GPB_MFPL_PB6MFP_EMAC_PPS (0x03UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< EMAC Pulse Per Second output \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 418 | #define SYS_GPB_MFPL_PB6MFP_USCI1_DAT1 (0x04UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< USCI1 data1 pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 419 | #define SYS_GPB_MFPL_PB6MFP_CAN1_RXD (0x05UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< CAN1 bus receiver input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 420 | #define SYS_GPB_MFPL_PB6MFP_UART1_RXD (0x06UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< Data receiver input pin for UART1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 421 | #define SYS_GPB_MFPL_PB6MFP_SD1_CLK (0x07UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< SD/SDIO 1 clock. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 422 | #define SYS_GPB_MFPL_PB6MFP_EBI_nCS1 (0x08UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< EBI chip select enable output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 423 | #define SYS_GPB_MFPL_PB6MFP_BPWM1_CH5 (0x0AUL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< BPWM1 channel5 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 424 | #define SYS_GPB_MFPL_PB6MFP_EPWM1_BRAKE1 (0x0BUL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< Brake input pin 1 of EPWM1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 425 | #define SYS_GPB_MFPL_PB6MFP_EPWM1_CH5 (0x0CUL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< EPWM1 channel5 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 426 | #define SYS_GPB_MFPL_PB6MFP_INT4 (0x0DUL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< External interrupt4 input pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 427 | #define SYS_GPB_MFPL_PB6MFP_USB_VBUS_EN (0x0EUL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< Power supply from USB Full speed host or HUB. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 428 | #define SYS_GPB_MFPL_PB6MFP_ACMP1_O (0x0FUL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< Analog comparator1 output. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 429 | #define SYS_GPB_MFPL_PB7MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 430 | #define SYS_GPB_MFPL_PB7MFP_EADC0_CH7 (0x01UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< EADC0 channel7 analog input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 431 | #define SYS_GPB_MFPL_PB7MFP_EBI_nWRL (0x02UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< EBI write enable output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 432 | #define SYS_GPB_MFPL_PB7MFP_EMAC_RMII_TXEN (0x03UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< RMII? Transmit Enable. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 433 | #define SYS_GPB_MFPL_PB7MFP_USCI1_DAT0 (0x04UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< USCI1 data0 pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 434 | #define SYS_GPB_MFPL_PB7MFP_CAN1_TXD (0x05UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< CAN1 bus transmitter output. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 435 | #define SYS_GPB_MFPL_PB7MFP_UART1_TXD (0x06UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< Data transmitter output pin for UART1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 436 | #define SYS_GPB_MFPL_PB7MFP_SD1_CMD (0x07UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< SD/SDIO 1 command/response. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 437 | #define SYS_GPB_MFPL_PB7MFP_EBI_nCS0 (0x08UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< EBI chip select enable output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 438 | #define SYS_GPB_MFPL_PB7MFP_BPWM1_CH4 (0x0AUL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< BPWM1 channel4 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 439 | #define SYS_GPB_MFPL_PB7MFP_EPWM1_BRAKE0 (0x0BUL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< Brake input pin 0 of EPWM1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 440 | #define SYS_GPB_MFPL_PB7MFP_EPWM1_CH4 (0x0CUL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< EPWM1 channel4 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 441 | #define SYS_GPB_MFPL_PB7MFP_INT5 (0x0DUL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< External interrupt5 input pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 442 | #define SYS_GPB_MFPL_PB7MFP_USB_VBUS_ST (0x0EUL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< Power supply from USB Full speed host or HUB. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 443 | #define SYS_GPB_MFPL_PB7MFP_ACMP0_O (0x0FUL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< Analog comparator0 output. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 444 | /********************* Bit definition of GPB_MFPH register **********************/ |
| AnnaBridge | 172:7d866c31b3c5 | 445 | #define SYS_GPB_MFPH_PB8MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 446 | #define SYS_GPB_MFPH_PB8MFP_EADC0_CH8 (0x01UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< EADC0 channel8 analog input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 447 | #define SYS_GPB_MFPH_PB8MFP_EBI_ADR19 (0x02UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 448 | #define SYS_GPB_MFPH_PB8MFP_EMAC_RMII_TXD1 (0x03UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< RMII Transmit Data bus bit 1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 449 | #define SYS_GPB_MFPH_PB8MFP_USCI1_CLK (0x04UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< USCI1 clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 450 | #define SYS_GPB_MFPH_PB8MFP_UART0_RXD (0x05UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< Data receiver input pin for UART0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 451 | #define SYS_GPB_MFPH_PB8MFP_UART1_nRTS (0x06UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< Request to Send output pin for UART1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 452 | #define SYS_GPB_MFPH_PB8MFP_I2C1_SMBSUS (0x07UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< I2C1 SMBus SMBSUS# pin (PMBus CONTROL pin) \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 453 | #define SYS_GPB_MFPH_PB8MFP_BPWM1_CH3 (0x0AUL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< BPWM1 channel3 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 454 | #define SYS_GPB_MFPH_PB8MFP_SPI4_MOSI (0x0BUL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< 1st SPI4 MOSI (Master Out, Slave In) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 455 | #define SYS_GPB_MFPH_PB8MFP_INT6 (0x0DUL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< External interrupt6 input pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 456 | #define SYS_GPB_MFPH_PB9MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 457 | #define SYS_GPB_MFPH_PB9MFP_EADC0_CH9 (0x01UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< EADC0 channel9 analog input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 458 | #define SYS_GPB_MFPH_PB9MFP_EBI_ADR18 (0x02UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 459 | #define SYS_GPB_MFPH_PB9MFP_EMAC_RMII_TXD0 (0x03UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< RMII Transmit Data bus bit 0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 460 | #define SYS_GPB_MFPH_PB9MFP_USCI1_CTL1 (0x04UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< USCI1 control1 pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 461 | #define SYS_GPB_MFPH_PB9MFP_UART0_TXD (0x05UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< Data transmitter output pin for UART0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 462 | #define SYS_GPB_MFPH_PB9MFP_UART1_nCTS (0x06UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< Clear to Send input pin for UART1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 463 | #define SYS_GPB_MFPH_PB9MFP_I2C1_SMBAL (0x07UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< I2C1 SMBus SMBALTER# pin \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 464 | #define SYS_GPB_MFPH_PB9MFP_BPWM1_CH2 (0x0AUL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< BPWM1 channel2 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 465 | #define SYS_GPB_MFPH_PB9MFP_SPI4_MISO (0x0BUL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< 1st SPI4 MISO (Master In, Slave Out) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 466 | #define SYS_GPB_MFPH_PB9MFP_INT7 (0x0DUL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< External interrupt7 input pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 467 | #define SYS_GPB_MFPH_PB10MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 468 | #define SYS_GPB_MFPH_PB10MFP_EADC0_CH10 (0x01UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< EADC0 channel1 analog input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 469 | #define SYS_GPB_MFPH_PB10MFP_EBI_ADR17 (0x02UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 470 | #define SYS_GPB_MFPH_PB10MFP_EMAC_RMII_MDIO (0x03UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< RMII Management Data I/O. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 471 | #define SYS_GPB_MFPH_PB10MFP_USCI1_CTL0 (0x04UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< USCI1 control0 pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 472 | #define SYS_GPB_MFPH_PB10MFP_UART0_nRTS (0x05UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< Request to Send output pin for UART0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 473 | #define SYS_GPB_MFPH_PB10MFP_UART4_RXD (0x06UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< Data receiver input pin for UART4. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 474 | #define SYS_GPB_MFPH_PB10MFP_I2C1_SDA (0x07UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< I2C1 data input/output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 475 | #define SYS_GPB_MFPH_PB10MFP_CAN0_RXD (0x08UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< CAN0 bus receiver input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 476 | #define SYS_GPB_MFPH_PB10MFP_BPWM1_CH1 (0x0AUL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< BPWM1 channel1 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 477 | #define SYS_GPB_MFPH_PB10MFP_SPI4_SS (0x0BUL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< 1st SPI4 slave select pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 478 | #define SYS_GPB_MFPH_PB10MFP_HSUSB_VBUS_EN (0x0EUL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< Power supply from USB High speed host or HUB. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 479 | #define SYS_GPB_MFPH_PB11MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 480 | #define SYS_GPB_MFPH_PB11MFP_EADC0_CH11 (0x01UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< EADC0 channel1 analog input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 481 | #define SYS_GPB_MFPH_PB11MFP_EBI_ADR16 (0x02UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 482 | #define SYS_GPB_MFPH_PB11MFP_EMAC_RMII_MDC (0x03UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< RMII Management Data Clock. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 483 | #define SYS_GPB_MFPH_PB11MFP_UART0_nCTS (0x05UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< Clear to Send input pin for UART0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 484 | #define SYS_GPB_MFPH_PB11MFP_UART4_TXD (0x06UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< Data transmitter output pin for UART4. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 485 | #define SYS_GPB_MFPH_PB11MFP_I2C1_SCL (0x07UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< I2C1 clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 486 | #define SYS_GPB_MFPH_PB11MFP_CAN0_TXD (0x08UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< CAN0 bus transmitter output. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 487 | #define SYS_GPB_MFPH_PB11MFP_SPI1_I2SMCLK (0x09UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< SPI1 I2S master clock output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 488 | #define SYS_GPB_MFPH_PB11MFP_BPWM1_CH0 (0x0AUL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< BPWM1 channel0 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 489 | #define SYS_GPB_MFPH_PB11MFP_SPI4_CLK (0x0BUL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< SPI4 serial clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 490 | #define SYS_GPB_MFPH_PB11MFP_HSUSB_VBUS_ST (0x0EUL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< Power supply from USB High speed host or HUB. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 491 | #define SYS_GPB_MFPH_PB12MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 492 | #define SYS_GPB_MFPH_PB12MFP_ACMP0_P2 (0x01UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< Analog comparator0 positive input pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 493 | #define SYS_GPB_MFPH_PB12MFP_ACMP1_P2 (0x01UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< Analog comparator1 positive input pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 494 | #define SYS_GPB_MFPH_PB12MFP_DAC0_OUT (0x01UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< DAC0 channel analog output. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 495 | #define SYS_GPB_MFPH_PB12MFP_EADC0_CH12 (0x01UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< EADC0 channel1 analog input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 496 | #define SYS_GPB_MFPH_PB12MFP_EBI_AD15 (0x02UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 497 | #define SYS_GPB_MFPH_PB12MFP_SC1_CLK (0x03UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< SmartCard1 clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 498 | #define SYS_GPB_MFPH_PB12MFP_SPI1_MOSI (0x04UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< 1st SPI1 MOSI (Master Out, Slave In) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 499 | #define SYS_GPB_MFPH_PB12MFP_USCI0_CLK (0x05UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< USCI0 clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 500 | #define SYS_GPB_MFPH_PB12MFP_UART0_RXD (0x06UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< Data receiver input pin for UART0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 501 | #define SYS_GPB_MFPH_PB12MFP_UART3_nCTS (0x07UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< Clear to Send input pin for UART3. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 502 | #define SYS_GPB_MFPH_PB12MFP_I2C2_SDA (0x08UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< I2C2 data input/output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 503 | #define SYS_GPB_MFPH_PB12MFP_SD0_nCD (0x09UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< SD/SDIO 0 card detect \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 504 | #define SYS_GPB_MFPH_PB12MFP_EPWM1_CH3 (0x0BUL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< EPWM1 channel3 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 505 | #define SYS_GPB_MFPH_PB12MFP_ETM_TRACE_DATA3 (0x0CUL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< ETM Rx input bus bit3. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 506 | #define SYS_GPB_MFPH_PB12MFP_TM3_EXT (0x0DUL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< Timer3 event counter input / toggle output \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 507 | #define SYS_GPB_MFPH_PB13MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 508 | #define SYS_GPB_MFPH_PB13MFP_ACMP0_P3 (0x01UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< Analog comparator0 positive input pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 509 | #define SYS_GPB_MFPH_PB13MFP_ACMP1_P3 (0x01UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< Analog comparator1 positive input pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 510 | #define SYS_GPB_MFPH_PB13MFP_DAC1_OUT (0x01UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< DAC1 channel analog output. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 511 | #define SYS_GPB_MFPH_PB13MFP_EADC0_CH13 (0x01UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< EADC0 channel1 analog input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 512 | #define SYS_GPB_MFPH_PB13MFP_EBI_AD14 (0x02UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 513 | #define SYS_GPB_MFPH_PB13MFP_SC1_DAT (0x03UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< SmartCard1 data pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 514 | #define SYS_GPB_MFPH_PB13MFP_SPI1_MISO (0x04UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< 1st SPI1 MISO (Master In, Slave Out) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 515 | #define SYS_GPB_MFPH_PB13MFP_USCI0_DAT0 (0x05UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< USCI0 data0 pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 516 | #define SYS_GPB_MFPH_PB13MFP_UART0_TXD (0x06UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< Data transmitter output pin for UART0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 517 | #define SYS_GPB_MFPH_PB13MFP_UART3_nRTS (0x07UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< Request to Send output pin for UART3. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 518 | #define SYS_GPB_MFPH_PB13MFP_I2C2_SCL (0x08UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< I2C2 clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 519 | #define SYS_GPB_MFPH_PB13MFP_EPWM1_CH2 (0x0BUL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< EPWM1 channel2 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 520 | #define SYS_GPB_MFPH_PB13MFP_ETM_TRACE_DATA2 (0x0CUL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< ETM Rx input bus bit2. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 521 | #define SYS_GPB_MFPH_PB13MFP_TM2_EXT (0x0DUL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< Timer2 event counter input / toggle output \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 522 | #define SYS_GPB_MFPH_PB14MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 523 | #define SYS_GPB_MFPH_PB14MFP_EADC0_CH14 (0x01UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< EADC0 channel1 analog input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 524 | #define SYS_GPB_MFPH_PB14MFP_EBI_AD13 (0x02UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 525 | #define SYS_GPB_MFPH_PB14MFP_SC1_RST (0x03UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< SmartCard1 reset pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 526 | #define SYS_GPB_MFPH_PB14MFP_SPI1_CLK (0x04UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< SPI1 serial clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 527 | #define SYS_GPB_MFPH_PB14MFP_USCI0_DAT1 (0x05UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< USCI0 data1 pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 528 | #define SYS_GPB_MFPH_PB14MFP_UART0_nRTS (0x06UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< Request to Send output pin for UART0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 529 | #define SYS_GPB_MFPH_PB14MFP_UART3_RXD (0x07UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< Data receiver input pin for UART3. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 530 | #define SYS_GPB_MFPH_PB14MFP_I2C2_SMBSUS (0x08UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< I2C2 SMBus SMBSUS# pin (PMBus CONTROL pin) \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 531 | #define SYS_GPB_MFPH_PB14MFP_EPWM1_CH1 (0x0BUL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< EPWM1 channel1 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 532 | #define SYS_GPB_MFPH_PB14MFP_ETM_TRACE_DATA1 (0x0CUL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< ETM Rx input bus bit1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 533 | #define SYS_GPB_MFPH_PB14MFP_TM1_EXT (0x0DUL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< Timer1 event counter input / toggle output \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 534 | #define SYS_GPB_MFPH_PB14MFP_CLKO (0x0EUL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< Clock Output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 535 | #define SYS_GPB_MFPH_PB15MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 536 | #define SYS_GPB_MFPH_PB15MFP_EADC0_CH15 (0x01UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< EADC0 channel1 analog input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 537 | #define SYS_GPB_MFPH_PB15MFP_EBI_AD12 (0x02UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 538 | #define SYS_GPB_MFPH_PB15MFP_SC1_PWR (0x03UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< SmartCard1 power pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 539 | #define SYS_GPB_MFPH_PB15MFP_SPI1_SS (0x04UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< 1st SPI1 slave select pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 540 | #define SYS_GPB_MFPH_PB15MFP_USCI0_CTL1 (0x05UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< USCI0 control1 pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 541 | #define SYS_GPB_MFPH_PB15MFP_UART0_nCTS (0x06UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< Clear to Send input pin for UART0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 542 | #define SYS_GPB_MFPH_PB15MFP_UART3_TXD (0x07UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< Data transmitter output pin for UART3. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 543 | #define SYS_GPB_MFPH_PB15MFP_I2C2_SMBAL (0x08UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< I2C2 SMBus SMBALTER# pin \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 544 | #define SYS_GPB_MFPH_PB15MFP_EPWM1_CH0 (0x0BUL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< EPWM1 channel0 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 545 | #define SYS_GPB_MFPH_PB15MFP_ETM_TRACE_DATA0 (0x0CUL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< ETM Rx input bus bit0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 546 | #define SYS_GPB_MFPH_PB15MFP_TM0_EXT (0x0DUL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< Timer0 event counter input / toggle output \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 547 | #define SYS_GPB_MFPH_PB15MFP_USB_VBUS_EN (0x0EUL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< Power supply from USB Full speed host or HUB. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 548 | #define SYS_GPB_MFPH_PB15MFP_HSUSB_VBUS_EN (0x0FUL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< Power supply from USB High speed host or HUB. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 549 | /********************* Bit definition of GPC_MFPL register **********************/ |
| AnnaBridge | 172:7d866c31b3c5 | 550 | #define SYS_GPC_MFPL_PC0MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 551 | #define SYS_GPC_MFPL_PC0MFP_EBI_AD0 (0x02UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< EBI address/data bus bit0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 552 | #define SYS_GPC_MFPL_PC0MFP_SPIM_MOSI (0x03UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< 1st SPIM MOSI (Master Out, Slave In) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 553 | #define SYS_GPC_MFPL_PC0MFP_SPI0_MOSI0 (0x04UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< 1st SPI0 MOSI (Master Out, Slave In) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 554 | #define SYS_GPC_MFPL_PC0MFP_SC1_CLK (0x05UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< SmartCard1 clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 555 | #define SYS_GPC_MFPL_PC0MFP_I2S0_LRCK (0x06UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< I2S0 left right channel clock. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 556 | #define SYS_GPC_MFPL_PC0MFP_SPI2_SS (0x07UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< 1st SPI2 slave select pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 557 | #define SYS_GPC_MFPL_PC0MFP_UART2_RXD (0x08UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< Data receiver input pin for UART2. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 558 | #define SYS_GPC_MFPL_PC0MFP_I2C0_SDA (0x09UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< I2C0 data input/output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 559 | #define SYS_GPC_MFPL_PC0MFP_EPWM1_CH5 (0x0CUL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< EPWM1 channel5 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 560 | #define SYS_GPC_MFPL_PC0MFP_ACMP1_O (0x0EUL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< Analog comparator1 output. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 561 | #define SYS_GPC_MFPL_PC1MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 562 | #define SYS_GPC_MFPL_PC1MFP_EBI_AD1 (0x02UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 563 | #define SYS_GPC_MFPL_PC1MFP_SPIM_MISO (0x03UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< 1st SPIM MISO (Master In, Slave Out) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 564 | #define SYS_GPC_MFPL_PC1MFP_SPI0_MISO0 (0x04UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< 1st SPI0 MISO (Master In, Slave Out) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 565 | #define SYS_GPC_MFPL_PC1MFP_SC1_DAT (0x05UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< SmartCard1 data pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 566 | #define SYS_GPC_MFPL_PC1MFP_I2S0_DO (0x06UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< I2S0 data output. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 567 | #define SYS_GPC_MFPL_PC1MFP_SPI2_CLK (0x07UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< SPI2 serial clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 568 | #define SYS_GPC_MFPL_PC1MFP_UART2_TXD (0x08UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< Data transmitter output pin for UART2. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 569 | #define SYS_GPC_MFPL_PC1MFP_I2C0_SCL (0x09UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< I2C0 clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 570 | #define SYS_GPC_MFPL_PC1MFP_EPWM1_CH4 (0x0CUL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< EPWM1 channel4 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 571 | #define SYS_GPC_MFPL_PC1MFP_ACMP0_O (0x0EUL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< Analog comparator0 output. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 572 | #define SYS_GPC_MFPL_PC2MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 573 | #define SYS_GPC_MFPL_PC2MFP_EBI_AD2 (0x02UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< EBI address/data bus bit2. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 574 | #define SYS_GPC_MFPL_PC2MFP_SPIM_CLK (0x03UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< SPIM serial clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 575 | #define SYS_GPC_MFPL_PC2MFP_SPI0_CLK (0x04UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< SPI0 serial clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 576 | #define SYS_GPC_MFPL_PC2MFP_SC1_RST (0x05UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< SmartCard1 reset pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 577 | #define SYS_GPC_MFPL_PC2MFP_I2S0_DI (0x06UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< I2S0 data input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 578 | #define SYS_GPC_MFPL_PC2MFP_SPI2_MOSI (0x07UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< 1st SPI2 MOSI (Master Out, Slave In) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 579 | #define SYS_GPC_MFPL_PC2MFP_UART2_nCTS (0x08UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< Clear to Send input pin for UART2. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 580 | #define SYS_GPC_MFPL_PC2MFP_I2C0_SMBSUS (0x09UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< I2C0 SMBus SMBSUS# pin (PMBus CONTROL pin) \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 581 | #define SYS_GPC_MFPL_PC2MFP_CAN1_RXD (0x0AUL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< CAN1 bus receiver input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 582 | #define SYS_GPC_MFPL_PC2MFP_UART3_RXD (0x0BUL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< Data receiver input pin for UART3. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 583 | #define SYS_GPC_MFPL_PC2MFP_EPWM1_CH3 (0x0CUL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< EPWM1 channel3 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 584 | #define SYS_GPC_MFPL_PC3MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 585 | #define SYS_GPC_MFPL_PC3MFP_EBI_AD3 (0x02UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< EBI address/data bus bit3. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 586 | #define SYS_GPC_MFPL_PC3MFP_SPIM_SS (0x03UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< 1st SPIM slave select pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 587 | #define SYS_GPC_MFPL_PC3MFP_SPI0_SS (0x04UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< 1st SPI0 slave select pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 588 | #define SYS_GPC_MFPL_PC3MFP_SC1_PWR (0x05UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< SmartCard1 power pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 589 | #define SYS_GPC_MFPL_PC3MFP_I2S0_MCLK (0x06UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< I2S0 master clock output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 590 | #define SYS_GPC_MFPL_PC3MFP_SPI2_MISO (0x07UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< 1st SPI2 MISO (Master In, Slave Out) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 591 | #define SYS_GPC_MFPL_PC3MFP_UART2_nRTS (0x08UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< Request to Send output pin for UART2. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 592 | #define SYS_GPC_MFPL_PC3MFP_I2C0_SMBAL (0x09UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< I2C0 SMBus SMBALTER# pin \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 593 | #define SYS_GPC_MFPL_PC3MFP_CAN1_TXD (0x0AUL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< CAN1 bus transmitter output. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 594 | #define SYS_GPC_MFPL_PC3MFP_UART3_TXD (0x0BUL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< Data transmitter output pin for UART3. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 595 | #define SYS_GPC_MFPL_PC3MFP_EPWM1_CH2 (0x0CUL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< EPWM1 channel2 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 596 | #define SYS_GPC_MFPL_PC4MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 597 | #define SYS_GPC_MFPL_PC4MFP_EBI_AD4 (0x02UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< EBI address/data bus bit4. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 598 | #define SYS_GPC_MFPL_PC4MFP_SPIM_D3 (0x03UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< SPIM data 3 pin for Quad Mode I/O. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 599 | #define SYS_GPC_MFPL_PC4MFP_SPI0_MOSI1 (0x04UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< 2nd SPI0 MOSI (Master Out, Slave In) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 600 | #define SYS_GPC_MFPL_PC4MFP_SC1_nCD (0x05UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< SmartCard1 card detect pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 601 | #define SYS_GPC_MFPL_PC4MFP_I2S0_BCLK (0x06UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< I2S0 bit clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 602 | #define SYS_GPC_MFPL_PC4MFP_SPI2_I2SMCLK (0x07UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< SPI2 I2S master clock output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 603 | #define SYS_GPC_MFPL_PC4MFP_UART2_RXD (0x08UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< Data receiver input pin for UART2. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 604 | #define SYS_GPC_MFPL_PC4MFP_I2C1_SDA (0x09UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< I2C1 data input/output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 605 | #define SYS_GPC_MFPL_PC4MFP_CAN0_RXD (0x0AUL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< CAN0 bus receiver input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 606 | #define SYS_GPC_MFPL_PC4MFP_UART4_RXD (0x0BUL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< Data receiver input pin for UART4. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 607 | #define SYS_GPC_MFPL_PC4MFP_EPWM1_CH1 (0x0CUL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< EPWM1 channel1 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 608 | #define SYS_GPC_MFPL_PC5MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 609 | #define SYS_GPC_MFPL_PC5MFP_EBI_AD5 (0x02UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< EBI address/data bus bit5. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 610 | #define SYS_GPC_MFPL_PC5MFP_SPIM_D2 (0x03UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< SPIM data 2 pin for Quad Mode I/O. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 611 | #define SYS_GPC_MFPL_PC5MFP_SPI0_MISO1 (0x04UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< 2nd SPI0 MISO (Master In, Slave Out) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 612 | #define SYS_GPC_MFPL_PC5MFP_UART2_TXD (0x08UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< Data transmitter output pin for UART2. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 613 | #define SYS_GPC_MFPL_PC5MFP_I2C1_SCL (0x09UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< I2C1 clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 614 | #define SYS_GPC_MFPL_PC5MFP_CAN0_TXD (0x0AUL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< CAN0 bus transmitter output. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 615 | #define SYS_GPC_MFPL_PC5MFP_UART4_TXD (0x0BUL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< Data transmitter output pin for UART4. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 616 | #define SYS_GPC_MFPL_PC5MFP_EPWM1_CH0 (0x0CUL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< EPWM1 channel0 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 617 | #define SYS_GPC_MFPL_PC6MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 618 | #define SYS_GPC_MFPL_PC6MFP_EBI_AD8 (0x02UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< EBI address/data bus bit8. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 619 | #define SYS_GPC_MFPL_PC6MFP_EMAC_RMII_RXD1 (0x03UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< RMII Receive Data bus bit 1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 620 | #define SYS_GPC_MFPL_PC6MFP_SPI2_MOSI (0x04UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< 1st SPI2 MOSI (Master Out, Slave In) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 621 | #define SYS_GPC_MFPL_PC6MFP_UART4_RXD (0x05UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< Data receiver input pin for UART4. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 622 | #define SYS_GPC_MFPL_PC6MFP_SC2_RST (0x06UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< SmartCard2 reset pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 623 | #define SYS_GPC_MFPL_PC6MFP_UART0_nRTS (0x07UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< Request to Send output pin for UART0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 624 | #define SYS_GPC_MFPL_PC6MFP_I2C1_SMBSUS (0x08UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< I2C1 SMBus SMBSUS# pin (PMBus CONTROL pin) \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 625 | #define SYS_GPC_MFPL_PC6MFP_EPWM1_CH3 (0x0BUL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< EPWM1 channel3 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 626 | #define SYS_GPC_MFPL_PC6MFP_BPWM1_CH1 (0x0CUL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< BPWM1 channel1 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 627 | #define SYS_GPC_MFPL_PC6MFP_TM1 (0x0EUL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< Timer1 event counter input / toggle output \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 628 | #define SYS_GPC_MFPL_PC6MFP_INT2 (0x0FUL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< External interrupt2 input pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 629 | #define SYS_GPC_MFPL_PC7MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 630 | #define SYS_GPC_MFPL_PC7MFP_EBI_AD9 (0x02UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< EBI address/data bus bit9. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 631 | #define SYS_GPC_MFPL_PC7MFP_EMAC_RMII_RXD0 (0x03UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< RMII Receive Data bus bit 0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 632 | #define SYS_GPC_MFPL_PC7MFP_SPI2_MISO (0x04UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< 1st SPI2 MISO (Master In, Slave Out) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 633 | #define SYS_GPC_MFPL_PC7MFP_UART4_TXD (0x05UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< Data transmitter output pin for UART4. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 634 | #define SYS_GPC_MFPL_PC7MFP_SC2_PWR (0x06UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< SmartCard2 power pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 635 | #define SYS_GPC_MFPL_PC7MFP_UART0_nCTS (0x07UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< Clear to Send input pin for UART0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 636 | #define SYS_GPC_MFPL_PC7MFP_I2C1_SMBAL (0x08UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< I2C1 SMBus SMBALTER# pin \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 637 | #define SYS_GPC_MFPL_PC7MFP_EPWM1_CH2 (0x0BUL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< EPWM1 channel2 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 638 | #define SYS_GPC_MFPL_PC7MFP_BPWM1_CH0 (0x0CUL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< BPWM1 channel0 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 639 | #define SYS_GPC_MFPL_PC7MFP_TM0 (0x0EUL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< Timer0 event counter input / toggle output \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 640 | #define SYS_GPC_MFPL_PC7MFP_INT3 (0x0FUL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< External interrupt3 input pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 641 | /********************* Bit definition of GPC_MFPH register **********************/ |
| AnnaBridge | 172:7d866c31b3c5 | 642 | #define SYS_GPC_MFPH_PC8MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 643 | #define SYS_GPC_MFPH_PC8MFP_EBI_ADR16 (0x02UL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 644 | #define SYS_GPC_MFPH_PC8MFP_EMAC_RMII_REFCLK (0x03UL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< EMAC mode clock input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 645 | #define SYS_GPC_MFPH_PC8MFP_I2C0_SDA (0x04UL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< I2C0 data input/output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 646 | #define SYS_GPC_MFPH_PC8MFP_UART4_nCTS (0x05UL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< Clear to Send input pin for UART4. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 647 | #define SYS_GPC_MFPH_PC8MFP_UART1_RXD (0x08UL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< Data receiver input pin for UART1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 648 | #define SYS_GPC_MFPH_PC8MFP_EPWM1_CH1 (0x0BUL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< EPWM1 channel1 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 649 | #define SYS_GPC_MFPH_PC8MFP_BPWM1_CH4 (0x0CUL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< BPWM1 channel4 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 650 | #define SYS_GPC_MFPH_PC9MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 651 | #define SYS_GPC_MFPH_PC9MFP_EBI_ADR7 (0x02UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 652 | #define SYS_GPC_MFPH_PC9MFP_SPI4_SS (0x06UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< 1st SPI4 slave select pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 653 | #define SYS_GPC_MFPH_PC9MFP_UART3_RXD (0x07UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< Data receiver input pin for UART3. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 654 | #define SYS_GPC_MFPH_PC9MFP_CAN1_RXD (0x09UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< CAN1 bus receiver input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 655 | #define SYS_GPC_MFPH_PC9MFP_EPWM1_CH3 (0x0CUL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< EPWM1 channel3 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 656 | #define SYS_GPC_MFPH_PC10MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 657 | #define SYS_GPC_MFPH_PC10MFP_EBI_ADR6 (0x02UL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 658 | #define SYS_GPC_MFPH_PC10MFP_SPI4_CLK (0x06UL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< SPI4 serial clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 659 | #define SYS_GPC_MFPH_PC10MFP_UART3_TXD (0x07UL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< Data transmitter output pin for UART3. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 660 | #define SYS_GPC_MFPH_PC10MFP_CAN1_TXD (0x09UL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< CAN1 bus transmitter output. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 661 | #define SYS_GPC_MFPH_PC10MFP_ECAP1_IC0 (0x0BUL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< Input 0 of enhanced capture unit 1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 662 | #define SYS_GPC_MFPH_PC10MFP_EPWM1_CH2 (0x0CUL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< EPWM1 channel2 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 663 | #define SYS_GPC_MFPH_PC11MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 664 | #define SYS_GPC_MFPH_PC11MFP_EBI_ADR5 (0x02UL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 665 | #define SYS_GPC_MFPH_PC11MFP_UART0_RXD (0x03UL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< Data receiver input pin for UART0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 666 | #define SYS_GPC_MFPH_PC11MFP_I2C0_SDA (0x04UL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< I2C0 data input/output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 667 | #define SYS_GPC_MFPH_PC11MFP_SPI4_MOSI (0x06UL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< 1st SPI4 MOSI (Master Out, Slave In) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 668 | #define SYS_GPC_MFPH_PC11MFP_ECAP1_IC1 (0x0BUL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< Input 1 of enhanced capture unit 1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 669 | #define SYS_GPC_MFPH_PC11MFP_EPWM1_CH1 (0x0CUL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< EPWM1 channel1 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 670 | #define SYS_GPC_MFPH_PC11MFP_ACMP1_O (0x0EUL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< Analog comparator1 output. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 671 | #define SYS_GPC_MFPH_PC12MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 672 | #define SYS_GPC_MFPH_PC12MFP_EBI_ADR4 (0x02UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 673 | #define SYS_GPC_MFPH_PC12MFP_UART0_TXD (0x03UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< Data transmitter output pin for UART0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 674 | #define SYS_GPC_MFPH_PC12MFP_I2C0_SCL (0x04UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< I2C0 clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 675 | #define SYS_GPC_MFPH_PC12MFP_SPI4_MISO (0x06UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< 1st SPI4 MISO (Master In, Slave Out) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 676 | #define SYS_GPC_MFPH_PC12MFP_SC0_nCD (0x09UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< SmartCard0 card detect pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 677 | #define SYS_GPC_MFPH_PC12MFP_ECAP1_IC2 (0x0BUL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< Input 1 of enhanced capture unit 2. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 678 | #define SYS_GPC_MFPH_PC12MFP_EPWM1_CH0 (0x0CUL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< EPWM1 channel0 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 679 | #define SYS_GPC_MFPH_PC12MFP_ACMP0_O (0x0EUL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< Analog comparator0 output. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 680 | #define SYS_GPC_MFPH_PC13MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 681 | #define SYS_GPC_MFPH_PC13MFP_EBI_ADR10 (0x02UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 682 | #define SYS_GPC_MFPH_PC13MFP_SC2_nCD (0x03UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< SmartCard2 card detect pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 683 | #define SYS_GPC_MFPH_PC13MFP_SPI3_I2SMCLK (0x04UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< SPI3 I2S master clock output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 684 | #define SYS_GPC_MFPH_PC13MFP_CAN1_TXD (0x05UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< CAN1 bus transmitter output. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 685 | #define SYS_GPC_MFPH_PC13MFP_USCI0_CTL0 (0x06UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< USCI0 control0 pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 686 | #define SYS_GPC_MFPH_PC13MFP_UART2_TXD (0x07UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< Data transmitter output pin for UART2. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 687 | #define SYS_GPC_MFPH_PC13MFP_BPWM0_CH4 (0x09UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< BPWM0 channel4 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 688 | #define SYS_GPC_MFPH_PC13MFP_CLKO (0x0DUL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< Clock Output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 689 | #define SYS_GPC_MFPH_PC13MFP_EADC0_ST (0x0EUL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< EADC external trigger input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 690 | #define SYS_GPC_MFPH_PC14MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 691 | #define SYS_GPC_MFPH_PC14MFP_EBI_AD11 (0x02UL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 692 | #define SYS_GPC_MFPH_PC14MFP_SC1_nCD (0x03UL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< SmartCard1 card detect pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 693 | #define SYS_GPC_MFPH_PC14MFP_SPI1_I2SMCLK (0x04UL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< SPI1 I2S master clock output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 694 | #define SYS_GPC_MFPH_PC14MFP_USCI0_CTL0 (0x05UL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< USCI0 control0 pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 695 | #define SYS_GPC_MFPH_PC14MFP_SPI0_CLK (0x06UL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< SPI0 serial clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 696 | #define SYS_GPC_MFPH_PC14MFP_EPWM0_SYNC_IN (0x0BUL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< EPWM0 counter synchronous trigger input pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 697 | #define SYS_GPC_MFPH_PC14MFP_ETM_TRACE_CLK (0x0CUL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< ETM Rx clock input pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 698 | #define SYS_GPC_MFPH_PC14MFP_TM1 (0x0DUL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< Timer1 event counter input / toggle output \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 699 | #define SYS_GPC_MFPH_PC14MFP_USB_VBUS_ST (0x0EUL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< Power supply from USB Full speed host or HUB. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 700 | #define SYS_GPC_MFPH_PC14MFP_HSUSB_VBUS_ST (0x0FUL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< Power supply from USB High speed host or HUB. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 701 | /********************* Bit definition of GPD_MFPL register **********************/ |
| AnnaBridge | 172:7d866c31b3c5 | 702 | #define SYS_GPD_MFPL_PD0MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 703 | #define SYS_GPD_MFPL_PD0MFP_EBI_AD13 (0x02UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 704 | #define SYS_GPD_MFPL_PD0MFP_USCI0_CLK (0x03UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< USCI0 clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 705 | #define SYS_GPD_MFPL_PD0MFP_SPI1_MOSI (0x04UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< 1st SPI1 MOSI (Master Out, Slave In) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 706 | #define SYS_GPD_MFPL_PD0MFP_UART3_RXD (0x05UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< Data receiver input pin for UART3. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 707 | #define SYS_GPD_MFPL_PD0MFP_I2C2_SDA (0x06UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< I2C2 data input/output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 708 | #define SYS_GPD_MFPL_PD0MFP_SC2_CLK (0x07UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< SmartCard2 clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 709 | #define SYS_GPD_MFPL_PD0MFP_TM2 (0x0EUL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< Timer2 event counter input / toggle output \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 710 | #define SYS_GPD_MFPL_PD1MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 711 | #define SYS_GPD_MFPL_PD1MFP_EBI_AD12 (0x02UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 712 | #define SYS_GPD_MFPL_PD1MFP_USCI0_DAT0 (0x03UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< USCI0 data0 pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 713 | #define SYS_GPD_MFPL_PD1MFP_SPI1_MISO (0x04UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< 1st SPI1 MISO (Master In, Slave Out) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 714 | #define SYS_GPD_MFPL_PD1MFP_UART3_TXD (0x05UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< Data transmitter output pin for UART3. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 715 | #define SYS_GPD_MFPL_PD1MFP_I2C2_SCL (0x06UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< I2C2 clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 716 | #define SYS_GPD_MFPL_PD1MFP_SC2_DAT (0x07UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< SmartCard2 data pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 717 | #define SYS_GPD_MFPL_PD2MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 718 | #define SYS_GPD_MFPL_PD2MFP_EBI_AD11 (0x02UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 719 | #define SYS_GPD_MFPL_PD2MFP_USCI0_DAT1 (0x03UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< USCI0 data1 pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 720 | #define SYS_GPD_MFPL_PD2MFP_SPI1_CLK (0x04UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< SPI1 serial clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 721 | #define SYS_GPD_MFPL_PD2MFP_UART3_nCTS (0x05UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< Clear to Send input pin for UART3. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 722 | #define SYS_GPD_MFPL_PD2MFP_SC2_RST (0x07UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< SmartCard2 reset pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 723 | #define SYS_GPD_MFPL_PD2MFP_UART0_RXD (0x09UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< Data receiver input pin for UART0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 724 | #define SYS_GPD_MFPL_PD3MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 725 | #define SYS_GPD_MFPL_PD3MFP_EBI_AD10 (0x02UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 726 | #define SYS_GPD_MFPL_PD3MFP_USCI0_CTL1 (0x03UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< USCI0 control1 pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 727 | #define SYS_GPD_MFPL_PD3MFP_SPI1_SS (0x04UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< 1st SPI1 slave select pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 728 | #define SYS_GPD_MFPL_PD3MFP_UART3_nRTS (0x05UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< Request to Send output pin for UART3. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 729 | #define SYS_GPD_MFPL_PD3MFP_USCI1_CTL0 (0x06UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< USCI1 control0 pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 730 | #define SYS_GPD_MFPL_PD3MFP_SC2_PWR (0x07UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< SmartCard2 power pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 731 | #define SYS_GPD_MFPL_PD3MFP_SC1_nCD (0x08UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< SmartCard1 card detect pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 732 | #define SYS_GPD_MFPL_PD3MFP_UART0_TXD (0x09UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< Data transmitter output pin for UART0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 733 | #define SYS_GPD_MFPL_PD4MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 734 | #define SYS_GPD_MFPL_PD4MFP_USCI0_CTL0 (0x03UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< USCI0 control0 pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 735 | #define SYS_GPD_MFPL_PD4MFP_I2C1_SDA (0x04UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< I2C1 data input/output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 736 | #define SYS_GPD_MFPL_PD4MFP_SPI2_SS (0x05UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< 1st SPI2 slave select pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 737 | #define SYS_GPD_MFPL_PD4MFP_USCI1_CTL1 (0x06UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< USCI1 control1 pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 738 | #define SYS_GPD_MFPL_PD4MFP_SC1_CLK (0x08UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< SmartCard1 clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 739 | #define SYS_GPD_MFPL_PD4MFP_USB_VBUS_ST (0x0EUL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< Power supply from USB Full speed host or HUB. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 740 | #define SYS_GPD_MFPL_PD5MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD5MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 741 | #define SYS_GPD_MFPL_PD5MFP_I2C1_SCL (0x04UL<<SYS_GPD_MFPL_PD5MFP_Pos) /*!< I2C1 clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 742 | #define SYS_GPD_MFPL_PD5MFP_SPI2_CLK (0x05UL<<SYS_GPD_MFPL_PD5MFP_Pos) /*!< SPI2 serial clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 743 | #define SYS_GPD_MFPL_PD5MFP_USCI1_DAT0 (0x06UL<<SYS_GPD_MFPL_PD5MFP_Pos) /*!< USCI1 data0 pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 744 | #define SYS_GPD_MFPL_PD5MFP_SC1_DAT (0x08UL<<SYS_GPD_MFPL_PD5MFP_Pos) /*!< SmartCard1 data pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 745 | #define SYS_GPD_MFPL_PD6MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 746 | #define SYS_GPD_MFPL_PD6MFP_UART1_RXD (0x03UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< Data receiver input pin for UART1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 747 | #define SYS_GPD_MFPL_PD6MFP_I2C0_SDA (0x04UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< I2C0 data input/output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 748 | #define SYS_GPD_MFPL_PD6MFP_SPI2_MOSI (0x05UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< 1st SPI2 MOSI (Master Out, Slave In) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 749 | #define SYS_GPD_MFPL_PD6MFP_USCI1_DAT1 (0x06UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< USCI1 data1 pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 750 | #define SYS_GPD_MFPL_PD6MFP_SC1_RST (0x08UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< SmartCard1 reset pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 751 | #define SYS_GPD_MFPL_PD7MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 752 | #define SYS_GPD_MFPL_PD7MFP_UART1_TXD (0x03UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< Data transmitter output pin for UART1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 753 | #define SYS_GPD_MFPL_PD7MFP_I2C0_SCL (0x04UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< I2C0 clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 754 | #define SYS_GPD_MFPL_PD7MFP_SPI2_MISO (0x05UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< 1st SPI2 MISO (Master In, Slave Out) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 755 | #define SYS_GPD_MFPL_PD7MFP_USCI1_CLK (0x06UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< USCI1 clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 756 | #define SYS_GPD_MFPL_PD7MFP_SC1_PWR (0x08UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< SmartCard1 power pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 757 | /********************* Bit definition of GPD_MFPH register **********************/ |
| AnnaBridge | 172:7d866c31b3c5 | 758 | #define SYS_GPD_MFPH_PD8MFP_GPIO (0x00UL<<SYS_GPD_MFPH_PD8MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 759 | #define SYS_GPD_MFPH_PD8MFP_EBI_AD6 (0x02UL<<SYS_GPD_MFPH_PD8MFP_Pos) /*!< EBI address/data bus bit6. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 760 | #define SYS_GPD_MFPH_PD8MFP_I2C2_SDA (0x03UL<<SYS_GPD_MFPH_PD8MFP_Pos) /*!< I2C2 data input/output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 761 | #define SYS_GPD_MFPH_PD8MFP_UART2_nRTS (0x04UL<<SYS_GPD_MFPH_PD8MFP_Pos) /*!< Request to Send output pin for UART2. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 762 | #define SYS_GPD_MFPH_PD9MFP_GPIO (0x00UL<<SYS_GPD_MFPH_PD9MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 763 | #define SYS_GPD_MFPH_PD9MFP_EBI_AD7 (0x02UL<<SYS_GPD_MFPH_PD9MFP_Pos) /*!< EBI address/data bus bit7. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 764 | #define SYS_GPD_MFPH_PD9MFP_I2C2_SCL (0x03UL<<SYS_GPD_MFPH_PD9MFP_Pos) /*!< I2C2 clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 765 | #define SYS_GPD_MFPH_PD9MFP_UART2_nCTS (0x04UL<<SYS_GPD_MFPH_PD9MFP_Pos) /*!< Clear to Send input pin for UART2. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 766 | #define SYS_GPD_MFPH_PD10MFP_GPIO (0x00UL<<SYS_GPD_MFPH_PD10MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 767 | #define SYS_GPD_MFPH_PD10MFP_OPA2_P (0x01UL<<SYS_GPD_MFPH_PD10MFP_Pos) /*!< Operational amplifier positive input pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 768 | #define SYS_GPD_MFPH_PD10MFP_EBI_nCS2 (0x02UL<<SYS_GPD_MFPH_PD10MFP_Pos) /*!< EBI chip select enable output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 769 | #define SYS_GPD_MFPH_PD10MFP_UART1_RXD (0x03UL<<SYS_GPD_MFPH_PD10MFP_Pos) /*!< Data receiver input pin for UART1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 770 | #define SYS_GPD_MFPH_PD10MFP_CAN0_RXD (0x04UL<<SYS_GPD_MFPH_PD10MFP_Pos) /*!< CAN0 bus receiver input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 771 | #define SYS_GPD_MFPH_PD10MFP_QEI0_B (0x0AUL<<SYS_GPD_MFPH_PD10MFP_Pos) /*!< Quadrature encoder phase B input of QEI Unit 0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 772 | #define SYS_GPD_MFPH_PD10MFP_INT7 (0x0FUL<<SYS_GPD_MFPH_PD10MFP_Pos) /*!< External interrupt7 input pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 773 | #define SYS_GPD_MFPH_PD11MFP_GPIO (0x00UL<<SYS_GPD_MFPH_PD11MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 774 | #define SYS_GPD_MFPH_PD11MFP_OPA2_N (0x01UL<<SYS_GPD_MFPH_PD11MFP_Pos) /*!< Operational amplifier negative input pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 775 | #define SYS_GPD_MFPH_PD11MFP_EBI_nCS1 (0x02UL<<SYS_GPD_MFPH_PD11MFP_Pos) /*!< EBI chip select enable output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 776 | #define SYS_GPD_MFPH_PD11MFP_UART1_TXD (0x03UL<<SYS_GPD_MFPH_PD11MFP_Pos) /*!< Data transmitter output pin for UART1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 777 | #define SYS_GPD_MFPH_PD11MFP_CAN0_TXD (0x04UL<<SYS_GPD_MFPH_PD11MFP_Pos) /*!< CAN0 bus transmitter output. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 778 | #define SYS_GPD_MFPH_PD11MFP_QEI0_A (0x0AUL<<SYS_GPD_MFPH_PD11MFP_Pos) /*!< Quadrature encoder phase A input of QEI Unit 0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 779 | #define SYS_GPD_MFPH_PD11MFP_INT6 (0x0FUL<<SYS_GPD_MFPH_PD11MFP_Pos) /*!< External interrupt6 input pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 780 | #define SYS_GPD_MFPH_PD12MFP_GPIO (0x00UL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 781 | #define SYS_GPD_MFPH_PD12MFP_OPA2_O (0x01UL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< Operational amplifier output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 782 | #define SYS_GPD_MFPH_PD12MFP_EBI_nCS0 (0x02UL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< EBI chip select enable output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 783 | #define SYS_GPD_MFPH_PD12MFP_CAN1_RXD (0x05UL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< CAN1 bus receiver input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 784 | #define SYS_GPD_MFPH_PD12MFP_UART2_RXD (0x07UL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< Data receiver input pin for UART2. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 785 | #define SYS_GPD_MFPH_PD12MFP_BPWM0_CH5 (0x09UL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< BPWM0 channel5 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 786 | #define SYS_GPD_MFPH_PD12MFP_QEI0_INDEX (0x0AUL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< Quadrature encoder index input of QEI Unit 0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 787 | #define SYS_GPD_MFPH_PD12MFP_CLKO (0x0DUL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< Clock Output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 788 | #define SYS_GPD_MFPH_PD12MFP_EADC0_ST (0x0EUL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< EADC external trigger input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 789 | #define SYS_GPD_MFPH_PD12MFP_INT5 (0x0FUL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< External interrupt5 input pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 790 | #define SYS_GPD_MFPH_PD13MFP_GPIO (0x00UL<<SYS_GPD_MFPH_PD13MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 791 | #define SYS_GPD_MFPH_PD13MFP_EBI_AD10 (0x02UL<<SYS_GPD_MFPH_PD13MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 792 | #define SYS_GPD_MFPH_PD13MFP_SD0_nCD (0x03UL<<SYS_GPD_MFPH_PD13MFP_Pos) /*!< SD/SDIO 0 card detect \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 793 | #define SYS_GPD_MFPH_PD13MFP_SPI1_I2SMCLK (0x04UL<<SYS_GPD_MFPH_PD13MFP_Pos) /*!< SPI1 I2S master clock output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 794 | #define SYS_GPD_MFPH_PD13MFP_SPI2_I2SMCLK (0x05UL<<SYS_GPD_MFPH_PD13MFP_Pos) /*!< SPI2 I2S master clock output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 795 | #define SYS_GPD_MFPH_PD13MFP_SC2_nCD (0x07UL<<SYS_GPD_MFPH_PD13MFP_Pos) /*!< SmartCard2 card detect pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 796 | #define SYS_GPD_MFPH_PD14MFP_GPIO (0x00UL<<SYS_GPD_MFPH_PD14MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 797 | #define SYS_GPD_MFPH_PD14MFP_EBI_nCS0 (0x02UL<<SYS_GPD_MFPH_PD14MFP_Pos) /*!< EBI chip select enable output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 798 | #define SYS_GPD_MFPH_PD14MFP_SPI4_I2SMCLK (0x03UL<<SYS_GPD_MFPH_PD14MFP_Pos) /*!< SPI4 I2S master clock output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 799 | #define SYS_GPD_MFPH_PD14MFP_SC1_nCD (0x04UL<<SYS_GPD_MFPH_PD14MFP_Pos) /*!< SmartCard1 card detect pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 800 | #define SYS_GPD_MFPH_PD14MFP_EPWM0_CH4 (0x0BUL<<SYS_GPD_MFPH_PD14MFP_Pos) /*!< EPWM0 channel4 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 801 | /********************* Bit definition of GPE_MFPL register **********************/ |
| AnnaBridge | 172:7d866c31b3c5 | 802 | #define SYS_GPE_MFPL_PE0MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 803 | #define SYS_GPE_MFPL_PE0MFP_EBI_AD11 (0x02UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 804 | #define SYS_GPE_MFPL_PE0MFP_SPI0_MOSI0 (0x03UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< 1st SPI0 MOSI (Master Out, Slave In) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 805 | #define SYS_GPE_MFPL_PE0MFP_SC2_CLK (0x04UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< SmartCard2 clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 806 | #define SYS_GPE_MFPL_PE0MFP_I2S0_MCLK (0x05UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< I2S0 master clock output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 807 | #define SYS_GPE_MFPL_PE0MFP_SPI2_MOSI (0x06UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< 1st SPI2 MOSI (Master Out, Slave In) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 808 | #define SYS_GPE_MFPL_PE0MFP_UART3_RXD (0x07UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< Data receiver input pin for UART3. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 809 | #define SYS_GPE_MFPL_PE0MFP_I2C1_SDA (0x08UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< I2C1 data input/output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 810 | #define SYS_GPE_MFPL_PE0MFP_UART4_nRTS (0x09UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< Request to Send output pin for UART4. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 811 | #define SYS_GPE_MFPL_PE1MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 812 | #define SYS_GPE_MFPL_PE1MFP_EBI_AD10 (0x02UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 813 | #define SYS_GPE_MFPL_PE1MFP_SPI0_MISO0 (0x03UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< 1st SPI0 MISO (Master In, Slave Out) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 814 | #define SYS_GPE_MFPL_PE1MFP_SC2_DAT (0x04UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< SmartCard2 data pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 815 | #define SYS_GPE_MFPL_PE1MFP_I2S0_BCLK (0x05UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< I2S0 bit clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 816 | #define SYS_GPE_MFPL_PE1MFP_SPI2_MISO (0x06UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< 1st SPI2 MISO (Master In, Slave Out) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 817 | #define SYS_GPE_MFPL_PE1MFP_UART3_TXD (0x07UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< Data transmitter output pin for UART3. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 818 | #define SYS_GPE_MFPL_PE1MFP_I2C1_SCL (0x08UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< I2C1 clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 819 | #define SYS_GPE_MFPL_PE1MFP_UART4_nCTS (0x09UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< Clear to Send input pin for UART4. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 820 | #define SYS_GPE_MFPL_PE2MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 821 | #define SYS_GPE_MFPL_PE2MFP_EBI_ALE (0x02UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< EBI address latch enable output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 822 | #define SYS_GPE_MFPL_PE2MFP_SD0_DAT0 (0x03UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< SD/SDIO 0 data line bit 0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 823 | #define SYS_GPE_MFPL_PE2MFP_SPIM_MOSI (0x04UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< 1st SPIM MOSI (Master Out, Slave In) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 824 | #define SYS_GPE_MFPL_PE2MFP_SPI4_MOSI (0x05UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< 1st SPI4 MOSI (Master Out, Slave In) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 825 | #define SYS_GPE_MFPL_PE2MFP_SC0_CLK (0x06UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< SmartCard0 clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 826 | #define SYS_GPE_MFPL_PE2MFP_USCI0_CLK (0x07UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< USCI0 clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 827 | #define SYS_GPE_MFPL_PE2MFP_QEI0_B (0x0BUL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< Quadrature encoder phase B input of QEI Unit 0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 828 | #define SYS_GPE_MFPL_PE2MFP_EPWM0_CH5 (0x0CUL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< EPWM0 channel5 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 829 | #define SYS_GPE_MFPL_PE2MFP_BPWM0_CH0 (0x0DUL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< BPWM0 channel0 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 830 | #define SYS_GPE_MFPL_PE3MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 831 | #define SYS_GPE_MFPL_PE3MFP_EBI_MCLK (0x02UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< EBI external clock output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 832 | #define SYS_GPE_MFPL_PE3MFP_SD0_DAT1 (0x03UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< SD/SDIO 0 data line bit 1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 833 | #define SYS_GPE_MFPL_PE3MFP_SPIM_MISO (0x04UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< 1st SPIM MISO (Master In, Slave Out) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 834 | #define SYS_GPE_MFPL_PE3MFP_SPI4_MISO (0x05UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< 1st SPI4 MISO (Master In, Slave Out) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 835 | #define SYS_GPE_MFPL_PE3MFP_SC0_DAT (0x06UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< SmartCard0 data pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 836 | #define SYS_GPE_MFPL_PE3MFP_USCI0_DAT0 (0x07UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< USCI0 data0 pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 837 | #define SYS_GPE_MFPL_PE3MFP_QEI0_A (0x0BUL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< Quadrature encoder phase A input of QEI Unit 0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 838 | #define SYS_GPE_MFPL_PE3MFP_EPWM0_CH4 (0x0CUL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< EPWM0 channel4 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 839 | #define SYS_GPE_MFPL_PE3MFP_BPWM0_CH1 (0x0DUL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< BPWM0 channel1 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 840 | #define SYS_GPE_MFPL_PE4MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 841 | #define SYS_GPE_MFPL_PE4MFP_EBI_nWR (0x02UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< EBI write enable output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 842 | #define SYS_GPE_MFPL_PE4MFP_SD0_DAT2 (0x03UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< SD/SDIO 0 data line bit 2. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 843 | #define SYS_GPE_MFPL_PE4MFP_SPIM_CLK (0x04UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< SPIM serial clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 844 | #define SYS_GPE_MFPL_PE4MFP_SPI4_CLK (0x05UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< SPI4 serial clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 845 | #define SYS_GPE_MFPL_PE4MFP_SC0_RST (0x06UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< SmartCard0 reset pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 846 | #define SYS_GPE_MFPL_PE4MFP_USCI0_DAT1 (0x07UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< USCI0 data1 pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 847 | #define SYS_GPE_MFPL_PE4MFP_QEI0_INDEX (0x0BUL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< Quadrature encoder index input of QEI Unit 0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 848 | #define SYS_GPE_MFPL_PE4MFP_EPWM0_CH3 (0x0CUL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< EPWM0 channel3 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 849 | #define SYS_GPE_MFPL_PE4MFP_BPWM0_CH2 (0x0DUL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< BPWM0 channel2 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 850 | #define SYS_GPE_MFPL_PE5MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 851 | #define SYS_GPE_MFPL_PE5MFP_EBI_nRD (0x02UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< EBI read enable output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 852 | #define SYS_GPE_MFPL_PE5MFP_SD0_DAT3 (0x03UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< SD/SDIO 0 data line bit 3. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 853 | #define SYS_GPE_MFPL_PE5MFP_SPIM_SS (0x04UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< 1st SPIM slave select pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 854 | #define SYS_GPE_MFPL_PE5MFP_SPI4_SS (0x05UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< 1st SPI4 slave select pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 855 | #define SYS_GPE_MFPL_PE5MFP_SC0_PWR (0x06UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< SmartCard0 power pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 856 | #define SYS_GPE_MFPL_PE5MFP_USCI0_CTL1 (0x07UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< USCI0 control1 pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 857 | #define SYS_GPE_MFPL_PE5MFP_QEI1_B (0x0BUL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< Quadrature encoder phase B input of QEI Unit 1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 858 | #define SYS_GPE_MFPL_PE5MFP_EPWM0_CH2 (0x0CUL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< EPWM0 channel2 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 859 | #define SYS_GPE_MFPL_PE5MFP_BPWM0_CH3 (0x0DUL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< BPWM0 channel3 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 860 | #define SYS_GPE_MFPL_PE6MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 861 | #define SYS_GPE_MFPL_PE6MFP_SD0_CLK (0x03UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< SD/SDIO 0 clock. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 862 | #define SYS_GPE_MFPL_PE6MFP_SPIM_D3 (0x04UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< SPIM data 3 pin for Quad Mode I/O. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 863 | #define SYS_GPE_MFPL_PE6MFP_SPI4_I2SMCLK (0x05UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< SPI4 I2S master clock output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 864 | #define SYS_GPE_MFPL_PE6MFP_SC0_nCD (0x06UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< SmartCard0 card detect pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 865 | #define SYS_GPE_MFPL_PE6MFP_USCI0_CTL0 (0x07UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< USCI0 control0 pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 866 | #define SYS_GPE_MFPL_PE6MFP_UART5_RXD (0x08UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< Data receiver input pin for UART5. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 867 | #define SYS_GPE_MFPL_PE6MFP_CAN1_RXD (0x09UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< CAN1 bus receiver input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 868 | #define SYS_GPE_MFPL_PE6MFP_QEI1_A (0x0BUL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< Quadrature encoder phase A input of QEI Unit 1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 869 | #define SYS_GPE_MFPL_PE6MFP_EPWM0_CH1 (0x0CUL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< EPWM0 channel1 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 870 | #define SYS_GPE_MFPL_PE6MFP_BPWM0_CH4 (0x0DUL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< BPWM0 channel4 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 871 | #define SYS_GPE_MFPL_PE7MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 872 | #define SYS_GPE_MFPL_PE7MFP_SD0_CMD (0x03UL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< SD/SDIO 0 command/response. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 873 | #define SYS_GPE_MFPL_PE7MFP_SPIM_D2 (0x04UL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< SPIM data 2 pin for Quad Mode I/O. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 874 | #define SYS_GPE_MFPL_PE7MFP_UART5_TXD (0x08UL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< Data transmitter output pin for UART5. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 875 | #define SYS_GPE_MFPL_PE7MFP_CAN1_TXD (0x09UL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< CAN1 bus transmitter output. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 876 | #define SYS_GPE_MFPL_PE7MFP_QEI1_INDEX (0x0BUL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< Quadrature encoder index input of QEI Unit 1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 877 | #define SYS_GPE_MFPL_PE7MFP_EPWM0_CH0 (0x0CUL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< EPWM0 channel0 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 878 | #define SYS_GPE_MFPL_PE7MFP_BPWM0_CH5 (0x0DUL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< BPWM0 channel5 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 879 | /********************* Bit definition of GPE_MFPH register **********************/ |
| AnnaBridge | 172:7d866c31b3c5 | 880 | #define SYS_GPE_MFPH_PE8MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 881 | #define SYS_GPE_MFPH_PE8MFP_EBI_ADR10 (0x02UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 882 | #define SYS_GPE_MFPH_PE8MFP_EMAC_RMII_MDC (0x03UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< RMII Management Data Clock. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 883 | #define SYS_GPE_MFPH_PE8MFP_I2S0_BCLK (0x04UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< I2S0 bit clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 884 | #define SYS_GPE_MFPH_PE8MFP_SPI3_CLK (0x05UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< SPI3 serial clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 885 | #define SYS_GPE_MFPH_PE8MFP_USCI1_CTL1 (0x06UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< USCI1 control1 pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 886 | #define SYS_GPE_MFPH_PE8MFP_UART2_TXD (0x07UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< Data transmitter output pin for UART2. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 887 | #define SYS_GPE_MFPH_PE8MFP_EPWM0_CH0 (0x0AUL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< EPWM0 channel0 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 888 | #define SYS_GPE_MFPH_PE8MFP_EPWM0_BRAKE0 (0x0BUL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< Brake input pin 0 of EPWM0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 889 | #define SYS_GPE_MFPH_PE8MFP_ECAP0_IC0 (0x0CUL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< Input 0 of enhanced capture unit 0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 890 | #define SYS_GPE_MFPH_PE8MFP_TRACE_CLK (0x0EUL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< ETM Rx clock input pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 891 | #define SYS_GPE_MFPH_PE9MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 892 | #define SYS_GPE_MFPH_PE9MFP_EBI_ADR11 (0x02UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 893 | #define SYS_GPE_MFPH_PE9MFP_EMAC_RMII_MDIO (0x03UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< RMII Management Data I/O. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 894 | #define SYS_GPE_MFPH_PE9MFP_I2S0_MCLK (0x04UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< I2S0 master clock output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 895 | #define SYS_GPE_MFPH_PE9MFP_SPI3_MISO (0x05UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< 1st SPI3 MISO (Master In, Slave Out) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 896 | #define SYS_GPE_MFPH_PE9MFP_USCI1_CTL0 (0x06UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< USCI1 control0 pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 897 | #define SYS_GPE_MFPH_PE9MFP_UART2_RXD (0x07UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< Data receiver input pin for UART2. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 898 | #define SYS_GPE_MFPH_PE9MFP_EPWM0_CH1 (0x0AUL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< EPWM0 channel1 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 899 | #define SYS_GPE_MFPH_PE9MFP_EPWM0_BRAKE1 (0x0BUL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< Brake input pin 1 of EPWM0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 900 | #define SYS_GPE_MFPH_PE9MFP_ECAP0_IC1 (0x0CUL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< Input 1 of enhanced capture unit 0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 901 | #define SYS_GPE_MFPH_PE9MFP_TRACE_DATA0 (0x0EUL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< ETM Rx input bus bit0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 902 | #define SYS_GPE_MFPH_PE10MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 903 | #define SYS_GPE_MFPH_PE10MFP_EBI_ADR12 (0x02UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 904 | #define SYS_GPE_MFPH_PE10MFP_EMAC_RMII_TXD0 (0x03UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< RMII Transmit Data bus bit 0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 905 | #define SYS_GPE_MFPH_PE10MFP_I2S0_DI (0x04UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< I2S0 data input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 906 | #define SYS_GPE_MFPH_PE10MFP_SPI3_MOSI (0x05UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< 1st SPI3 MOSI (Master Out, Slave In) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 907 | #define SYS_GPE_MFPH_PE10MFP_USCI1_DAT0 (0x06UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< USCI1 data0 pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 908 | #define SYS_GPE_MFPH_PE10MFP_UART3_TXD (0x07UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< Data transmitter output pin for UART3. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 909 | #define SYS_GPE_MFPH_PE10MFP_EPWM0_CH2 (0x0AUL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< EPWM0 channel2 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 910 | #define SYS_GPE_MFPH_PE10MFP_EPWM1_BRAKE0 (0x0BUL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< Brake input pin 0 of EPWM1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 911 | #define SYS_GPE_MFPH_PE10MFP_ECAP0_IC2 (0x0CUL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< Input 0 of enhanced capture unit 2. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 912 | #define SYS_GPE_MFPH_PE10MFP_TRACE_DATA1 (0x0EUL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< ETM Rx input bus bit1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 913 | #define SYS_GPE_MFPH_PE11MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 914 | #define SYS_GPE_MFPH_PE11MFP_EBI_ADR13 (0x02UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 915 | #define SYS_GPE_MFPH_PE11MFP_EMAC_RMII_TXD1 (0x03UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< RMII Transmit Data bus bit 1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 916 | #define SYS_GPE_MFPH_PE11MFP_I2S0_DO (0x04UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< I2S0 data output. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 917 | #define SYS_GPE_MFPH_PE11MFP_SPI3_SS (0x05UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< 1st SPI3 slave select pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 918 | #define SYS_GPE_MFPH_PE11MFP_USCI1_DAT1 (0x06UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< USCI1 data1 pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 919 | #define SYS_GPE_MFPH_PE11MFP_UART3_RXD (0x07UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< Data receiver input pin for UART3. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 920 | #define SYS_GPE_MFPH_PE11MFP_UART1_nCTS (0x08UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< Clear to Send input pin for UART1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 921 | #define SYS_GPE_MFPH_PE11MFP_EPWM0_CH3 (0x0AUL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< EPWM0 channel3 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 922 | #define SYS_GPE_MFPH_PE11MFP_EPWM1_BRAKE1 (0x0BUL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< Brake input pin 1 of EPWM1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 923 | #define SYS_GPE_MFPH_PE11MFP_ECAP1_IC2 (0x0DUL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< Input 1 of enhanced capture unit 2. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 924 | #define SYS_GPE_MFPH_PE11MFP_TRACE_DATA2 (0x0EUL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< ETM Rx input bus bit2. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 925 | #define SYS_GPE_MFPH_PE12MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 926 | #define SYS_GPE_MFPH_PE12MFP_EBI_ADR14 (0x02UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 927 | #define SYS_GPE_MFPH_PE12MFP_EMAC_RMII_TXEN (0x03UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< RMII? Transmit Enable. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 928 | #define SYS_GPE_MFPH_PE12MFP_I2S0_LRCK (0x04UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< I2S0 left right channel clock. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 929 | #define SYS_GPE_MFPH_PE12MFP_SPI3_I2SMCLK (0x05UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< SPI3 I2S master clock output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 930 | #define SYS_GPE_MFPH_PE12MFP_USCI1_CLK (0x06UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< USCI1 clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 931 | #define SYS_GPE_MFPH_PE12MFP_UART1_nRTS (0x08UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< Request to Send output pin for UART1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 932 | #define SYS_GPE_MFPH_PE12MFP_EPWM0_CH4 (0x0AUL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< EPWM0 channel4 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 933 | #define SYS_GPE_MFPH_PE12MFP_ECAP1_IC1 (0x0DUL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< Input 1 of enhanced capture unit 1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 934 | #define SYS_GPE_MFPH_PE12MFP_TRACE_DATA3 (0x0EUL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< ETM Rx input bus bit3. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 935 | #define SYS_GPE_MFPH_PE13MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 936 | #define SYS_GPE_MFPH_PE13MFP_EBI_ADR15 (0x02UL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 937 | #define SYS_GPE_MFPH_PE13MFP_EMAC_PPS (0x03UL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< EMAC Pulse Per Second output \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 938 | #define SYS_GPE_MFPH_PE13MFP_I2C0_SCL (0x04UL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< I2C0 clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 939 | #define SYS_GPE_MFPH_PE13MFP_UART4_nRTS (0x05UL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< Request to Send output pin for UART4. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 940 | #define SYS_GPE_MFPH_PE13MFP_UART1_TXD (0x08UL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< Data transmitter output pin for UART1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 941 | #define SYS_GPE_MFPH_PE13MFP_EPWM0_CH5 (0x0AUL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< EPWM0 channel5 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 942 | #define SYS_GPE_MFPH_PE13MFP_EPWM1_CH0 (0x0BUL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< EPWM1 channel0 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 943 | #define SYS_GPE_MFPH_PE13MFP_BPWM1_CH5 (0x0CUL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< BPWM1 channel5 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 944 | #define SYS_GPE_MFPH_PE13MFP_ECAP1_IC0 (0x0DUL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< Input 0 of enhanced capture unit 1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 945 | #define SYS_GPE_MFPH_PE14MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE14MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 946 | #define SYS_GPE_MFPH_PE14MFP_EBI_AD8 (0x02UL<<SYS_GPE_MFPH_PE14MFP_Pos) /*!< EBI address/data bus bit8. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 947 | #define SYS_GPE_MFPH_PE14MFP_UART2_TXD (0x03UL<<SYS_GPE_MFPH_PE14MFP_Pos) /*!< Data transmitter output pin for UART2. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 948 | #define SYS_GPE_MFPH_PE14MFP_CAN0_TXD (0x04UL<<SYS_GPE_MFPH_PE14MFP_Pos) /*!< CAN0 bus transmitter output. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 949 | #define SYS_GPE_MFPH_PE14MFP_SD1_nCD (0x05UL<<SYS_GPE_MFPH_PE14MFP_Pos) /*!< SD/SDIO 1 card detect \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 950 | #define SYS_GPE_MFPH_PE15MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE15MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 951 | #define SYS_GPE_MFPH_PE15MFP_EBI_AD9 (0x02UL<<SYS_GPE_MFPH_PE15MFP_Pos) /*!< EBI address/data bus bit9. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 952 | #define SYS_GPE_MFPH_PE15MFP_UART2_RXD (0x03UL<<SYS_GPE_MFPH_PE15MFP_Pos) /*!< Data receiver input pin for UART2. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 953 | #define SYS_GPE_MFPH_PE15MFP_CAN0_RXD (0x04UL<<SYS_GPE_MFPH_PE15MFP_Pos) /*!< CAN0 bus receiver input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 954 | /********************* Bit definition of GPF_MFPL register **********************/ |
| AnnaBridge | 172:7d866c31b3c5 | 955 | #define SYS_GPF_MFPL_PF0MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF0MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 956 | #define SYS_GPF_MFPL_PF0MFP_UART1_TXD (0x02UL<<SYS_GPF_MFPL_PF0MFP_Pos) /*!< Data transmitter output pin for UART1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 957 | #define SYS_GPF_MFPL_PF0MFP_I2C1_SCL (0x03UL<<SYS_GPF_MFPL_PF0MFP_Pos) /*!< I2C1 clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 958 | #define SYS_GPF_MFPL_PF0MFP_BPWM1_CH0 (0x0CUL<<SYS_GPF_MFPL_PF0MFP_Pos) /*!< BPWM1 channel0 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 959 | #define SYS_GPF_MFPL_PF0MFP_ICE_DAT (0x0EUL<<SYS_GPF_MFPL_PF0MFP_Pos) /*!< Serial wired debugger data pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 960 | #define SYS_GPF_MFPL_PF1MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF1MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 961 | #define SYS_GPF_MFPL_PF1MFP_UART1_RXD (0x02UL<<SYS_GPF_MFPL_PF1MFP_Pos) /*!< Data receiver input pin for UART1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 962 | #define SYS_GPF_MFPL_PF1MFP_I2C1_SDA (0x03UL<<SYS_GPF_MFPL_PF1MFP_Pos) /*!< I2C1 data input/output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 963 | #define SYS_GPF_MFPL_PF1MFP_BPWM1_CH1 (0x0CUL<<SYS_GPF_MFPL_PF1MFP_Pos) /*!< BPWM1 channel1 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 964 | #define SYS_GPF_MFPL_PF1MFP_ICE_CLK (0x0EUL<<SYS_GPF_MFPL_PF1MFP_Pos) /*!< Serial wired debugger clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 965 | #define SYS_GPF_MFPL_PF2MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 966 | #define SYS_GPF_MFPL_PF2MFP_EBI_nCS1 (0x02UL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< EBI chip select enable output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 967 | #define SYS_GPF_MFPL_PF2MFP_UART0_RXD (0x03UL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< Data receiver input pin for UART0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 968 | #define SYS_GPF_MFPL_PF2MFP_I2C0_SDA (0x04UL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< I2C0 data input/output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 969 | #define SYS_GPF_MFPL_PF2MFP_SPI0_CLK (0x05UL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< SPI0 serial clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 970 | #define SYS_GPF_MFPL_PF2MFP_XT1_OUT (0x0AUL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< External 4~24 MHz (high speed) crystal output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 971 | #define SYS_GPF_MFPL_PF2MFP_BPWM1_CH1 (0x0BUL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< BPWM1 channel1 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 972 | #define SYS_GPF_MFPL_PF3MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 973 | #define SYS_GPF_MFPL_PF3MFP_EBI_nCS0 (0x02UL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< EBI chip select enable output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 974 | #define SYS_GPF_MFPL_PF3MFP_UART0_TXD (0x03UL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< Data transmitter output pin for UART0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 975 | #define SYS_GPF_MFPL_PF3MFP_I2C0_SCL (0x04UL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< I2C0 clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 976 | #define SYS_GPF_MFPL_PF3MFP_XT1_IN (0x0AUL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< External 4~24 MHz (high speed) crystal input pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 977 | #define SYS_GPF_MFPL_PF3MFP_BPWM1_CH0 (0x0BUL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< BPWM1 channel0 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 978 | #define SYS_GPF_MFPL_PF4MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF4MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 979 | #define SYS_GPF_MFPL_PF4MFP_UART2_TXD (0x02UL<<SYS_GPF_MFPL_PF4MFP_Pos) /*!< Data transmitter output pin for UART2. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 980 | #define SYS_GPF_MFPL_PF4MFP_UART2_nRTS (0x04UL<<SYS_GPF_MFPL_PF4MFP_Pos) /*!< Request to Send output pin for UART2. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 981 | #define SYS_GPF_MFPL_PF4MFP_BPWM0_CH5 (0x08UL<<SYS_GPF_MFPL_PF4MFP_Pos) /*!< BPWM0 channel5 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 982 | #define SYS_GPF_MFPL_PF4MFP_X32_OUT (0x0AUL<<SYS_GPF_MFPL_PF4MFP_Pos) /*!< External 32.768 kHz (low speed) crystal output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 983 | #define SYS_GPF_MFPL_PF5MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 984 | #define SYS_GPF_MFPL_PF5MFP_UART2_RXD (0x02UL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< Data receiver input pin for UART2. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 985 | #define SYS_GPF_MFPL_PF5MFP_UART2_nCTS (0x04UL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< Clear to Send input pin for UART2. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 986 | #define SYS_GPF_MFPL_PF5MFP_BPWM0_CH4 (0x08UL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< BPWM0 channel4 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 987 | #define SYS_GPF_MFPL_PF5MFP_EPWM0_SYNC_OUT (0x09UL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< EPWM0 counter synchronous trigger output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 988 | #define SYS_GPF_MFPL_PF5MFP_X32_IN (0x0AUL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< External 32.768 kHz (low speed) crystal input pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 989 | #define SYS_GPF_MFPL_PF5MFP_EADC0_ST (0x0BUL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< EADC external trigger input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 990 | #define SYS_GPF_MFPL_PF6MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 991 | #define SYS_GPF_MFPL_PF6MFP_EBI_ADR19 (0x02UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 992 | #define SYS_GPF_MFPL_PF6MFP_SC0_CLK (0x03UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< SmartCard0 clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 993 | #define SYS_GPF_MFPL_PF6MFP_I2S0_LRCK (0x04UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< I2S0 left right channel clock. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 994 | #define SYS_GPF_MFPL_PF6MFP_SPI1_MOSI (0x05UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< 1st SPI1 MOSI (Master Out, Slave In) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 995 | #define SYS_GPF_MFPL_PF6MFP_UART4_RXD (0x06UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< Data receiver input pin for UART4. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 996 | #define SYS_GPF_MFPL_PF6MFP_EBI_nCS0 (0x07UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< EBI chip select enable output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 997 | #define SYS_GPF_MFPL_PF6MFP_TAMPER0 (0x0AUL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< TAMPER detector loop pin0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 998 | #define SYS_GPF_MFPL_PF7MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 999 | #define SYS_GPF_MFPL_PF7MFP_EBI_ADR18 (0x02UL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1000 | #define SYS_GPF_MFPL_PF7MFP_SC0_DAT (0x03UL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< SmartCard0 data pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1001 | #define SYS_GPF_MFPL_PF7MFP_I2S0_DO (0x04UL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< I2S0 data output. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1002 | #define SYS_GPF_MFPL_PF7MFP_SPI1_MISO (0x05UL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< 1st SPI1 MISO (Master In, Slave Out) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1003 | #define SYS_GPF_MFPL_PF7MFP_UART4_TXD (0x06UL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< Data transmitter output pin for UART4. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1004 | #define SYS_GPF_MFPL_PF7MFP_TAMPER1 (0x0AUL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< TAMPER detector loop pin1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1005 | /********************* Bit definition of GPF_MFPH register **********************/ |
| AnnaBridge | 172:7d866c31b3c5 | 1006 | #define SYS_GPF_MFPH_PF8MFP_GPIO (0x00UL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1007 | #define SYS_GPF_MFPH_PF8MFP_EBI_ADR17 (0x02UL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1008 | #define SYS_GPF_MFPH_PF8MFP_SC0_RST (0x03UL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< SmartCard0 reset pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1009 | #define SYS_GPF_MFPH_PF8MFP_I2S0_DI (0x04UL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< I2S0 data input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1010 | #define SYS_GPF_MFPH_PF8MFP_SPI1_CLK (0x05UL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< SPI1 serial clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1011 | #define SYS_GPF_MFPH_PF8MFP_TAMPER2 (0x0AUL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< TAMPER detector loop pin2. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1012 | #define SYS_GPF_MFPH_PF9MFP_GPIO (0x00UL<<SYS_GPF_MFPH_PF9MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1013 | #define SYS_GPF_MFPH_PF9MFP_EBI_ADR16 (0x02UL<<SYS_GPF_MFPH_PF9MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1014 | #define SYS_GPF_MFPH_PF9MFP_SC0_PWR (0x03UL<<SYS_GPF_MFPH_PF9MFP_Pos) /*!< SmartCard0 power pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1015 | #define SYS_GPF_MFPH_PF9MFP_I2S0_MCLK (0x04UL<<SYS_GPF_MFPH_PF9MFP_Pos) /*!< I2S0 master clock output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1016 | #define SYS_GPF_MFPH_PF9MFP_SPI1_SS (0x05UL<<SYS_GPF_MFPH_PF9MFP_Pos) /*!< 1st SPI1 slave select pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1017 | #define SYS_GPF_MFPH_PF9MFP_TAMPER3 (0x0AUL<<SYS_GPF_MFPH_PF9MFP_Pos) /*!< TAMPER detector loop pin3. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1018 | #define SYS_GPF_MFPH_PF10MFP_GPIO (0x00UL<<SYS_GPF_MFPH_PF10MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1019 | #define SYS_GPF_MFPH_PF10MFP_EBI_ADR15 (0x02UL<<SYS_GPF_MFPH_PF10MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1020 | #define SYS_GPF_MFPH_PF10MFP_SC0_nCD (0x03UL<<SYS_GPF_MFPH_PF10MFP_Pos) /*!< SmartCard0 card detect pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1021 | #define SYS_GPF_MFPH_PF10MFP_I2S0_BCLK (0x04UL<<SYS_GPF_MFPH_PF10MFP_Pos) /*!< I2S0 bit clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1022 | #define SYS_GPF_MFPH_PF10MFP_SPI1_I2SMCLK (0x05UL<<SYS_GPF_MFPH_PF10MFP_Pos) /*!< SPI1 I2S master clock output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1023 | #define SYS_GPF_MFPH_PF10MFP_TAMPER4 (0x0AUL<<SYS_GPF_MFPH_PF10MFP_Pos) /*!< TAMPER detector loop pin4. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1024 | #define SYS_GPF_MFPH_PF11MFP_GPIO (0x00UL<<SYS_GPF_MFPH_PF11MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1025 | #define SYS_GPF_MFPH_PF11MFP_EBI_ADR14 (0x02UL<<SYS_GPF_MFPH_PF11MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1026 | #define SYS_GPF_MFPH_PF11MFP_SPI3_MOSI (0x03UL<<SYS_GPF_MFPH_PF11MFP_Pos) /*!< 1st SPI3 MOSI (Master Out, Slave In) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1027 | #define SYS_GPF_MFPH_PF11MFP_TAMPER5 (0x0AUL<<SYS_GPF_MFPH_PF11MFP_Pos) /*!< TAMPER detector loop pin5. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1028 | #define SYS_GPF_MFPH_PF11MFP_TM3 (0x0DUL<<SYS_GPF_MFPH_PF11MFP_Pos) /*!< Timer3 event counter input / toggle output \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1029 | /********************* Bit definition of GPG_MFPL register **********************/ |
| AnnaBridge | 172:7d866c31b3c5 | 1030 | #define SYS_GPG_MFPL_PG0MFP_GPIO (0x00UL<<SYS_GPG_MFPL_PG0MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1031 | #define SYS_GPG_MFPL_PG0MFP_EBI_ADR8 (0x02UL<<SYS_GPG_MFPL_PG0MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1032 | #define SYS_GPG_MFPL_PG0MFP_I2C0_SCL (0x04UL<<SYS_GPG_MFPL_PG0MFP_Pos) /*!< I2C0 clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1033 | #define SYS_GPG_MFPL_PG0MFP_I2C1_SMBAL (0x05UL<<SYS_GPG_MFPL_PG0MFP_Pos) /*!< I2C1 SMBus SMBALTER# pin \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1034 | #define SYS_GPG_MFPL_PG0MFP_UART2_RXD (0x06UL<<SYS_GPG_MFPL_PG0MFP_Pos) /*!< Data receiver input pin for UART2. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1035 | #define SYS_GPG_MFPL_PG0MFP_CAN1_TXD (0x07UL<<SYS_GPG_MFPL_PG0MFP_Pos) /*!< CAN1 bus transmitter output. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1036 | #define SYS_GPG_MFPL_PG0MFP_UART1_TXD (0x08UL<<SYS_GPG_MFPL_PG0MFP_Pos) /*!< Data transmitter output pin for UART1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1037 | #define SYS_GPG_MFPL_PG1MFP_GPIO (0x00UL<<SYS_GPG_MFPL_PG1MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1038 | #define SYS_GPG_MFPL_PG1MFP_EBI_ADR9 (0x02UL<<SYS_GPG_MFPL_PG1MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1039 | #define SYS_GPG_MFPL_PG1MFP_SPI3_I2SMCLK (0x03UL<<SYS_GPG_MFPL_PG1MFP_Pos) /*!< SPI3 I2S master clock output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1040 | #define SYS_GPG_MFPL_PG1MFP_I2C0_SDA (0x04UL<<SYS_GPG_MFPL_PG1MFP_Pos) /*!< I2C0 data input/output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1041 | #define SYS_GPG_MFPL_PG1MFP_I2C1_SMBSUS (0x05UL<<SYS_GPG_MFPL_PG1MFP_Pos) /*!< I2C1 SMBus SMBSUS# pin (PMBus CONTROL pin) \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1042 | #define SYS_GPG_MFPL_PG1MFP_UART2_TXD (0x06UL<<SYS_GPG_MFPL_PG1MFP_Pos) /*!< Data transmitter output pin for UART2. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1043 | #define SYS_GPG_MFPL_PG1MFP_CAN1_RXD (0x07UL<<SYS_GPG_MFPL_PG1MFP_Pos) /*!< CAN1 bus receiver input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1044 | #define SYS_GPG_MFPL_PG1MFP_UART1_RXD (0x08UL<<SYS_GPG_MFPL_PG1MFP_Pos) /*!< Data receiver input pin for UART1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1045 | #define SYS_GPG_MFPL_PG2MFP_GPIO (0x00UL<<SYS_GPG_MFPL_PG2MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1046 | #define SYS_GPG_MFPL_PG2MFP_EBI_ADR11 (0x02UL<<SYS_GPG_MFPL_PG2MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1047 | #define SYS_GPG_MFPL_PG2MFP_SPI3_SS (0x03UL<<SYS_GPG_MFPL_PG2MFP_Pos) /*!< 1st SPI3 slave select pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1048 | #define SYS_GPG_MFPL_PG2MFP_I2C0_SMBAL (0x04UL<<SYS_GPG_MFPL_PG2MFP_Pos) /*!< I2C0 SMBus SMBALTER# pin \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1049 | #define SYS_GPG_MFPL_PG2MFP_I2C1_SCL (0x05UL<<SYS_GPG_MFPL_PG2MFP_Pos) /*!< I2C1 clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1050 | #define SYS_GPG_MFPL_PG2MFP_TM0 (0x0DUL<<SYS_GPG_MFPL_PG2MFP_Pos) /*!< Timer0 event counter input / toggle output \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1051 | #define SYS_GPG_MFPL_PG3MFP_GPIO (0x00UL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1052 | #define SYS_GPG_MFPL_PG3MFP_EBI_ADR12 (0x02UL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1053 | #define SYS_GPG_MFPL_PG3MFP_SPI3_CLK (0x03UL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< SPI3 serial clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1054 | #define SYS_GPG_MFPL_PG3MFP_I2C0_SMBSUS (0x04UL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< I2C0 SMBus SMBSUS# pin (PMBus CONTROL pin) \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1055 | #define SYS_GPG_MFPL_PG3MFP_I2C1_SDA (0x05UL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< I2C1 data input/output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1056 | #define SYS_GPG_MFPL_PG3MFP_TM1 (0x0DUL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< Timer1 event counter input / toggle output \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1057 | #define SYS_GPG_MFPL_PG4MFP_GPIO (0x00UL<<SYS_GPG_MFPL_PG4MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1058 | #define SYS_GPG_MFPL_PG4MFP_EBI_ADR13 (0x02UL<<SYS_GPG_MFPL_PG4MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1059 | #define SYS_GPG_MFPL_PG4MFP_SPI3_MISO (0x03UL<<SYS_GPG_MFPL_PG4MFP_Pos) /*!< 1st SPI3 MISO (Master In, Slave Out) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1060 | #define SYS_GPG_MFPL_PG4MFP_TM2 (0x0DUL<<SYS_GPG_MFPL_PG4MFP_Pos) /*!< Timer2 event counter input / toggle output \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1061 | #define SYS_GPG_MFPL_PG5MFP_GPIO (0x00UL<<SYS_GPG_MFPL_PG5MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1062 | #define SYS_GPG_MFPL_PG5MFP_EBI_nCS1 (0x02UL<<SYS_GPG_MFPL_PG5MFP_Pos) /*!< EBI chip select enable output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1063 | #define SYS_GPG_MFPL_PG5MFP_SPI4_SS (0x03UL<<SYS_GPG_MFPL_PG5MFP_Pos) /*!< 1st SPI4 slave select pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1064 | #define SYS_GPG_MFPL_PG5MFP_SC1_PWR (0x04UL<<SYS_GPG_MFPL_PG5MFP_Pos) /*!< SmartCard1 power pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1065 | #define SYS_GPG_MFPL_PG5MFP_EPWM0_CH3 (0x0BUL<<SYS_GPG_MFPL_PG5MFP_Pos) /*!< EPWM0 channel3 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1066 | #define SYS_GPG_MFPL_PG6MFP_GPIO (0x00UL<<SYS_GPG_MFPL_PG6MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1067 | #define SYS_GPG_MFPL_PG6MFP_EBI_nCS2 (0x02UL<<SYS_GPG_MFPL_PG6MFP_Pos) /*!< EBI chip select enable output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1068 | #define SYS_GPG_MFPL_PG6MFP_SPI4_CLK (0x03UL<<SYS_GPG_MFPL_PG6MFP_Pos) /*!< SPI4 serial clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1069 | #define SYS_GPG_MFPL_PG6MFP_SC1_RST (0x04UL<<SYS_GPG_MFPL_PG6MFP_Pos) /*!< SmartCard1 reset pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1070 | #define SYS_GPG_MFPL_PG6MFP_EPWM0_CH2 (0x0BUL<<SYS_GPG_MFPL_PG6MFP_Pos) /*!< EPWM0 channel2 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1071 | #define SYS_GPG_MFPL_PG7MFP_GPIO (0x00UL<<SYS_GPG_MFPL_PG7MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1072 | #define SYS_GPG_MFPL_PG7MFP_EBI_nWRL (0x02UL<<SYS_GPG_MFPL_PG7MFP_Pos) /*!< EBI write enable output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1073 | #define SYS_GPG_MFPL_PG7MFP_SPI4_MISO (0x03UL<<SYS_GPG_MFPL_PG7MFP_Pos) /*!< 1st SPI4 MISO (Master In, Slave Out) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1074 | #define SYS_GPG_MFPL_PG7MFP_SC1_DAT (0x04UL<<SYS_GPG_MFPL_PG7MFP_Pos) /*!< SmartCard1 data pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1075 | #define SYS_GPG_MFPL_PG7MFP_EPWM0_CH1 (0x0BUL<<SYS_GPG_MFPL_PG7MFP_Pos) /*!< EPWM0 channel1 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1076 | /********************* Bit definition of GPG_MFPH register **********************/ |
| AnnaBridge | 172:7d866c31b3c5 | 1077 | #define SYS_GPG_MFPH_PG8MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG8MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1078 | #define SYS_GPG_MFPH_PG8MFP_EBI_nWRH (0x02UL<<SYS_GPG_MFPH_PG8MFP_Pos) /*!< EBI write enable output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1079 | #define SYS_GPG_MFPH_PG8MFP_SPI4_MOSI (0x03UL<<SYS_GPG_MFPH_PG8MFP_Pos) /*!< 1st SPI4 MOSI (Master Out, Slave In) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1080 | #define SYS_GPG_MFPH_PG8MFP_SC1_CLK (0x04UL<<SYS_GPG_MFPH_PG8MFP_Pos) /*!< SmartCard1 clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1081 | #define SYS_GPG_MFPH_PG8MFP_EPWM0_CH0 (0x0BUL<<SYS_GPG_MFPH_PG8MFP_Pos) /*!< EPWM0 channel0 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1082 | #define SYS_GPG_MFPH_PG9MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG9MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1083 | #define SYS_GPG_MFPH_PG9MFP_EBI_AD0 (0x02UL<<SYS_GPG_MFPH_PG9MFP_Pos) /*!< EBI address/data bus bit0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1084 | #define SYS_GPG_MFPH_PG9MFP_SD1_DAT3 (0x03UL<<SYS_GPG_MFPH_PG9MFP_Pos) /*!< SD/SDIO 1 data line bit 3. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1085 | #define SYS_GPG_MFPH_PG9MFP_SPIM_D2 (0x04UL<<SYS_GPG_MFPH_PG9MFP_Pos) /*!< SPIM data 2 pin for Quad Mode I/O. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1086 | #define SYS_GPG_MFPH_PG9MFP_BPWM0_CH5 (0x0CUL<<SYS_GPG_MFPH_PG9MFP_Pos) /*!< BPWM0 channel5 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1087 | #define SYS_GPG_MFPH_PG10MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG10MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1088 | #define SYS_GPG_MFPH_PG10MFP_EBI_AD1 (0x02UL<<SYS_GPG_MFPH_PG10MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1089 | #define SYS_GPG_MFPH_PG10MFP_SD1_DAT2 (0x03UL<<SYS_GPG_MFPH_PG10MFP_Pos) /*!< SD/SDIO 1 data line bit 2. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1090 | #define SYS_GPG_MFPH_PG10MFP_SPIM_D3 (0x04UL<<SYS_GPG_MFPH_PG10MFP_Pos) /*!< SPIM data 3 pin for Quad Mode I/O. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1091 | #define SYS_GPG_MFPH_PG10MFP_BPWM0_CH4 (0x0CUL<<SYS_GPG_MFPH_PG10MFP_Pos) /*!< BPWM0 channel4 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1092 | #define SYS_GPG_MFPH_PG11MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG11MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1093 | #define SYS_GPG_MFPH_PG11MFP_EBI_AD2 (0x02UL<<SYS_GPG_MFPH_PG11MFP_Pos) /*!< EBI address/data bus bit2. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1094 | #define SYS_GPG_MFPH_PG11MFP_SD1_DAT1 (0x03UL<<SYS_GPG_MFPH_PG11MFP_Pos) /*!< SD/SDIO 1 data line bit 1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1095 | #define SYS_GPG_MFPH_PG11MFP_SPIM_SS (0x04UL<<SYS_GPG_MFPH_PG11MFP_Pos) /*!< 1st SPIM slave select pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1096 | #define SYS_GPG_MFPH_PG11MFP_BPWM0_CH3 (0x0CUL<<SYS_GPG_MFPH_PG11MFP_Pos) /*!< BPWM0 channel3 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1097 | #define SYS_GPG_MFPH_PG12MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG12MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1098 | #define SYS_GPG_MFPH_PG12MFP_EBI_AD3 (0x02UL<<SYS_GPG_MFPH_PG12MFP_Pos) /*!< EBI address/data bus bit3. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1099 | #define SYS_GPG_MFPH_PG12MFP_SD1_DAT0 (0x03UL<<SYS_GPG_MFPH_PG12MFP_Pos) /*!< SD/SDIO 1 data line bit 0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1100 | #define SYS_GPG_MFPH_PG12MFP_SPIM_CLK (0x04UL<<SYS_GPG_MFPH_PG12MFP_Pos) /*!< SPIM serial clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1101 | #define SYS_GPG_MFPH_PG12MFP_BPWM0_CH2 (0x0CUL<<SYS_GPG_MFPH_PG12MFP_Pos) /*!< BPWM0 channel2 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1102 | #define SYS_GPG_MFPH_PG13MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG13MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1103 | #define SYS_GPG_MFPH_PG13MFP_EBI_AD4 (0x02UL<<SYS_GPG_MFPH_PG13MFP_Pos) /*!< EBI address/data bus bit4. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1104 | #define SYS_GPG_MFPH_PG13MFP_SD1_CMD (0x03UL<<SYS_GPG_MFPH_PG13MFP_Pos) /*!< SD/SDIO 1 command/response. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1105 | #define SYS_GPG_MFPH_PG13MFP_SPIM_MISO (0x04UL<<SYS_GPG_MFPH_PG13MFP_Pos) /*!< 1st SPIM MISO (Master In, Slave Out) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1106 | #define SYS_GPG_MFPH_PG13MFP_BPWM0_CH1 (0x0CUL<<SYS_GPG_MFPH_PG13MFP_Pos) /*!< BPWM0 channel1 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1107 | #define SYS_GPG_MFPH_PG14MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG14MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1108 | #define SYS_GPG_MFPH_PG14MFP_EBI_AD5 (0x02UL<<SYS_GPG_MFPH_PG14MFP_Pos) /*!< EBI address/data bus bit5. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1109 | #define SYS_GPG_MFPH_PG14MFP_SD1_CLK (0x03UL<<SYS_GPG_MFPH_PG14MFP_Pos) /*!< SD/SDIO 1 clock. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1110 | #define SYS_GPG_MFPH_PG14MFP_SPIM_MOSI (0x04UL<<SYS_GPG_MFPH_PG14MFP_Pos) /*!< 1st SPIM MOSI (Master Out, Slave In) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1111 | #define SYS_GPG_MFPH_PG14MFP_BPWM0_CH0 (0x0CUL<<SYS_GPG_MFPH_PG14MFP_Pos) /*!< BPWM0 channel0 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1112 | #define SYS_GPG_MFPH_PG15MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG15MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1113 | #define SYS_GPG_MFPH_PG15MFP_SD1_nCD (0x03UL<<SYS_GPG_MFPH_PG15MFP_Pos) /*!< SD/SDIO 1 card detect \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1114 | #define SYS_GPG_MFPH_PG15MFP_CLKO (0x0EUL<<SYS_GPG_MFPH_PG15MFP_Pos) /*!< Clock Output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1115 | #define SYS_GPG_MFPH_PG15MFP_EADC0_ST (0x0FUL<<SYS_GPG_MFPH_PG15MFP_Pos) /*!< EADC external trigger input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1116 | /********************* Bit definition of GPH_MFPL register **********************/ |
| AnnaBridge | 172:7d866c31b3c5 | 1117 | #define SYS_GPH_MFPL_PH0MFP_GPIO (0x00UL<<SYS_GPH_MFPL_PH0MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1118 | #define SYS_GPH_MFPL_PH0MFP_EBI_ADR7 (0x02UL<<SYS_GPH_MFPL_PH0MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1119 | #define SYS_GPH_MFPL_PH0MFP_UART5_TXD (0x04UL<<SYS_GPH_MFPL_PH0MFP_Pos) /*!< Data transmitter output pin for UART5. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1120 | #define SYS_GPH_MFPL_PH0MFP_TM0_EXT (0x0DUL<<SYS_GPH_MFPL_PH0MFP_Pos) /*!< Timer0 event counter input / toggle output \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1121 | #define SYS_GPH_MFPL_PH1MFP_GPIO (0x00UL<<SYS_GPH_MFPL_PH1MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1122 | #define SYS_GPH_MFPL_PH1MFP_EBI_ADR6 (0x02UL<<SYS_GPH_MFPL_PH1MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1123 | #define SYS_GPH_MFPL_PH1MFP_UART5_RXD (0x04UL<<SYS_GPH_MFPL_PH1MFP_Pos) /*!< Data receiver input pin for UART5. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1124 | #define SYS_GPH_MFPL_PH1MFP_TM1_EXT (0x0DUL<<SYS_GPH_MFPL_PH1MFP_Pos) /*!< Timer1 event counter input / toggle output \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1125 | #define SYS_GPH_MFPL_PH2MFP_GPIO (0x00UL<<SYS_GPH_MFPL_PH2MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1126 | #define SYS_GPH_MFPL_PH2MFP_EBI_ADR5 (0x02UL<<SYS_GPH_MFPL_PH2MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1127 | #define SYS_GPH_MFPL_PH2MFP_UART5_nRTS (0x04UL<<SYS_GPH_MFPL_PH2MFP_Pos) /*!< Request to Send output pin for UART5. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1128 | #define SYS_GPH_MFPL_PH2MFP_UART4_TXD (0x05UL<<SYS_GPH_MFPL_PH2MFP_Pos) /*!< Data transmitter output pin for UART4. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1129 | #define SYS_GPH_MFPL_PH2MFP_I2C0_SCL (0x06UL<<SYS_GPH_MFPL_PH2MFP_Pos) /*!< I2C0 clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1130 | #define SYS_GPH_MFPL_PH2MFP_TM2_EXT (0x0DUL<<SYS_GPH_MFPL_PH2MFP_Pos) /*!< Timer2 event counter input / toggle output \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1131 | #define SYS_GPH_MFPL_PH3MFP_GPIO (0x00UL<<SYS_GPH_MFPL_PH3MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1132 | #define SYS_GPH_MFPL_PH3MFP_EBI_ADR4 (0x02UL<<SYS_GPH_MFPL_PH3MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1133 | #define SYS_GPH_MFPL_PH3MFP_SPI2_I2SMCLK (0x03UL<<SYS_GPH_MFPL_PH3MFP_Pos) /*!< SPI2 I2S master clock output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1134 | #define SYS_GPH_MFPL_PH3MFP_UART5_nCTS (0x04UL<<SYS_GPH_MFPL_PH3MFP_Pos) /*!< Clear to Send input pin for UART5. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1135 | #define SYS_GPH_MFPL_PH3MFP_UART4_RXD (0x05UL<<SYS_GPH_MFPL_PH3MFP_Pos) /*!< Data receiver input pin for UART4. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1136 | #define SYS_GPH_MFPL_PH3MFP_I2C0_SDA (0x06UL<<SYS_GPH_MFPL_PH3MFP_Pos) /*!< I2C0 data input/output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1137 | #define SYS_GPH_MFPL_PH3MFP_TM3_EXT (0x0DUL<<SYS_GPH_MFPL_PH3MFP_Pos) /*!< Timer3 event counter input / toggle output \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1138 | #define SYS_GPH_MFPL_PH4MFP_GPIO (0x00UL<<SYS_GPH_MFPL_PH4MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1139 | #define SYS_GPH_MFPL_PH4MFP_EBI_ADR3 (0x02UL<<SYS_GPH_MFPL_PH4MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1140 | #define SYS_GPH_MFPL_PH4MFP_SPI2_MISO (0x03UL<<SYS_GPH_MFPL_PH4MFP_Pos) /*!< 1st SPI2 MISO (Master In, Slave Out) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1141 | #define SYS_GPH_MFPL_PH5MFP_GPIO (0x00UL<<SYS_GPH_MFPL_PH5MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1142 | #define SYS_GPH_MFPL_PH5MFP_EBI_ADR2 (0x02UL<<SYS_GPH_MFPL_PH5MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1143 | #define SYS_GPH_MFPL_PH5MFP_SPI2_MOSI (0x03UL<<SYS_GPH_MFPL_PH5MFP_Pos) /*!< 1st SPI2 MOSI (Master Out, Slave In) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1144 | #define SYS_GPH_MFPL_PH6MFP_GPIO (0x00UL<<SYS_GPH_MFPL_PH6MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1145 | #define SYS_GPH_MFPL_PH6MFP_EBI_ADR1 (0x02UL<<SYS_GPH_MFPL_PH6MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1146 | #define SYS_GPH_MFPL_PH6MFP_SPI2_CLK (0x03UL<<SYS_GPH_MFPL_PH6MFP_Pos) /*!< SPI2 serial clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1147 | #define SYS_GPH_MFPL_PH7MFP_GPIO (0x00UL<<SYS_GPH_MFPL_PH7MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1148 | #define SYS_GPH_MFPL_PH7MFP_EBI_ADR0 (0x02UL<<SYS_GPH_MFPL_PH7MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1149 | #define SYS_GPH_MFPL_PH7MFP_SPI2_SS (0x03UL<<SYS_GPH_MFPL_PH7MFP_Pos) /*!< 1st SPI2 slave select pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1150 | /********************* Bit definition of GPH_MFPH register **********************/ |
| AnnaBridge | 172:7d866c31b3c5 | 1151 | #define SYS_GPH_MFPH_PH8MFP_GPIO (0x00UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1152 | #define SYS_GPH_MFPH_PH8MFP_EBI_AD12 (0x02UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1153 | #define SYS_GPH_MFPH_PH8MFP_SPI0_CLK (0x03UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< SPI0 serial clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1154 | #define SYS_GPH_MFPH_PH8MFP_SC2_PWR (0x04UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< SmartCard2 power pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1155 | #define SYS_GPH_MFPH_PH8MFP_I2S0_DI (0x05UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< I2S0 data input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1156 | #define SYS_GPH_MFPH_PH8MFP_SPI2_CLK (0x06UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< SPI2 serial clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1157 | #define SYS_GPH_MFPH_PH8MFP_UART3_nRTS (0x07UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< Request to Send output pin for UART3. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1158 | #define SYS_GPH_MFPH_PH8MFP_I2C1_SMBAL (0x08UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< I2C1 SMBus SMBALTER# pin \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1159 | #define SYS_GPH_MFPH_PH8MFP_I2C2_SCL (0x09UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< I2C2 clock pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1160 | #define SYS_GPH_MFPH_PH8MFP_UART1_TXD (0x0AUL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< Data transmitter output pin for UART1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1161 | #define SYS_GPH_MFPH_PH9MFP_GPIO (0x00UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1162 | #define SYS_GPH_MFPH_PH9MFP_EBI_AD13 (0x02UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1163 | #define SYS_GPH_MFPH_PH9MFP_SPI0_SS (0x03UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< 1st SPI0 slave select pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1164 | #define SYS_GPH_MFPH_PH9MFP_SC2_RST (0x04UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< SmartCard2 reset pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1165 | #define SYS_GPH_MFPH_PH9MFP_I2S0_DO (0x05UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< I2S0 data output. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1166 | #define SYS_GPH_MFPH_PH9MFP_SPI2_SS (0x06UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< 1st SPI2 slave select pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1167 | #define SYS_GPH_MFPH_PH9MFP_UART3_nCTS (0x07UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< Clear to Send input pin for UART3. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1168 | #define SYS_GPH_MFPH_PH9MFP_I2C1_SMBSUS (0x08UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< I2C1 SMBus SMBSUS# pin (PMBus CONTROL pin) \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1169 | #define SYS_GPH_MFPH_PH9MFP_I2C2_SDA (0x09UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< I2C2 data input/output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1170 | #define SYS_GPH_MFPH_PH9MFP_UART1_RXD (0x0AUL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< Data receiver input pin for UART1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1171 | #define SYS_GPH_MFPH_PH10MFP_GPIO (0x00UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1172 | #define SYS_GPH_MFPH_PH10MFP_EBI_AD14 (0x02UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1173 | #define SYS_GPH_MFPH_PH10MFP_SPI0_MISO1 (0x03UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< 2nd SPI0 MISO (Master In, Slave Out) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1174 | #define SYS_GPH_MFPH_PH10MFP_SC2_nCD (0x04UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< SmartCard2 card detect pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1175 | #define SYS_GPH_MFPH_PH10MFP_I2S0_LRCK (0x05UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< I2S0 left right channel clock. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1176 | #define SYS_GPH_MFPH_PH10MFP_SPI2_I2SMCLK (0x06UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< SPI2 I2S master clock output pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1177 | #define SYS_GPH_MFPH_PH10MFP_UART4_TXD (0x07UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< Data transmitter output pin for UART4. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1178 | #define SYS_GPH_MFPH_PH10MFP_UART0_TXD (0x08UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< Data transmitter output pin for UART0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1179 | #define SYS_GPH_MFPH_PH11MFP_GPIO (0x00UL<<SYS_GPH_MFPH_PH11MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1180 | #define SYS_GPH_MFPH_PH11MFP_EBI_AD15 (0x02UL<<SYS_GPH_MFPH_PH11MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1181 | #define SYS_GPH_MFPH_PH11MFP_SPI0_MOSI1 (0x03UL<<SYS_GPH_MFPH_PH11MFP_Pos) /*!< 2nd SPI0 MOSI (Master Out, Slave In) pin. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1182 | #define SYS_GPH_MFPH_PH11MFP_UART4_RXD (0x07UL<<SYS_GPH_MFPH_PH11MFP_Pos) /*!< Data receiver input pin for UART4. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1183 | #define SYS_GPH_MFPH_PH11MFP_UART0_RXD (0x08UL<<SYS_GPH_MFPH_PH11MFP_Pos) /*!< Data receiver input pin for UART0. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1184 | #define SYS_GPH_MFPH_PH11MFP_EPWM0_CH5 (0x0BUL<<SYS_GPH_MFPH_PH11MFP_Pos) /*!< EPWM0 channel5 output/capture input. \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 1185 | |
| AnnaBridge | 172:7d866c31b3c5 | 1186 | /*@}*/ /* end of group M480_SYS_EXPORTED_CONSTANTS */ |
| AnnaBridge | 172:7d866c31b3c5 | 1187 | |
| AnnaBridge | 172:7d866c31b3c5 | 1188 | |
| AnnaBridge | 172:7d866c31b3c5 | 1189 | /** @addtogroup M480_SYS_EXPORTED_FUNCTIONS SYS Exported Functions |
| AnnaBridge | 172:7d866c31b3c5 | 1190 | @{ |
| AnnaBridge | 172:7d866c31b3c5 | 1191 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 1192 | |
| AnnaBridge | 172:7d866c31b3c5 | 1193 | |
| AnnaBridge | 172:7d866c31b3c5 | 1194 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 1195 | * @brief Clear Brown-out detector interrupt flag |
| AnnaBridge | 172:7d866c31b3c5 | 1196 | * @param None |
| AnnaBridge | 172:7d866c31b3c5 | 1197 | * @return None |
| AnnaBridge | 172:7d866c31b3c5 | 1198 | * @details This macro clear Brown-out detector interrupt flag. |
| AnnaBridge | 172:7d866c31b3c5 | 1199 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 1200 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 1201 | #define SYS_CLEAR_BOD_INT_FLAG() (SYS->BODCTL |= SYS_BODCTL_BODIF_Msk) |
| AnnaBridge | 172:7d866c31b3c5 | 1202 | |
| AnnaBridge | 172:7d866c31b3c5 | 1203 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 1204 | * @brief Set Brown-out detector function to normal mode |
| AnnaBridge | 172:7d866c31b3c5 | 1205 | * @param None |
| AnnaBridge | 172:7d866c31b3c5 | 1206 | * @return None |
| AnnaBridge | 172:7d866c31b3c5 | 1207 | * @details This macro set Brown-out detector to normal mode. |
| AnnaBridge | 172:7d866c31b3c5 | 1208 | * The register write-protection function should be disabled before using this macro. |
| AnnaBridge | 172:7d866c31b3c5 | 1209 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 1210 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 1211 | #define SYS_CLEAR_BOD_LPM() (SYS->BODCTL &= ~SYS_BODCTL_BODLPM_Msk) |
| AnnaBridge | 172:7d866c31b3c5 | 1212 | |
| AnnaBridge | 172:7d866c31b3c5 | 1213 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 1214 | * @brief Disable Brown-out detector function |
| AnnaBridge | 172:7d866c31b3c5 | 1215 | * @param None |
| AnnaBridge | 172:7d866c31b3c5 | 1216 | * @return None |
| AnnaBridge | 172:7d866c31b3c5 | 1217 | * @details This macro disable Brown-out detector function. |
| AnnaBridge | 172:7d866c31b3c5 | 1218 | * The register write-protection function should be disabled before using this macro. |
| AnnaBridge | 172:7d866c31b3c5 | 1219 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 1220 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 1221 | #define SYS_DISABLE_BOD() (SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk) |
| AnnaBridge | 172:7d866c31b3c5 | 1222 | |
| AnnaBridge | 172:7d866c31b3c5 | 1223 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 1224 | * @brief Enable Brown-out detector function |
| AnnaBridge | 172:7d866c31b3c5 | 1225 | * @param None |
| AnnaBridge | 172:7d866c31b3c5 | 1226 | * @return None |
| AnnaBridge | 172:7d866c31b3c5 | 1227 | * @details This macro enable Brown-out detector function. |
| AnnaBridge | 172:7d866c31b3c5 | 1228 | * The register write-protection function should be disabled before using this macro. |
| AnnaBridge | 172:7d866c31b3c5 | 1229 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 1230 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 1231 | #define SYS_ENABLE_BOD() (SYS->BODCTL |= SYS_BODCTL_BODEN_Msk) |
| AnnaBridge | 172:7d866c31b3c5 | 1232 | |
| AnnaBridge | 172:7d866c31b3c5 | 1233 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 1234 | * @brief Get Brown-out detector interrupt flag |
| AnnaBridge | 172:7d866c31b3c5 | 1235 | * @param None |
| AnnaBridge | 172:7d866c31b3c5 | 1236 | * @retval 0 Brown-out detect interrupt flag is not set. |
| AnnaBridge | 172:7d866c31b3c5 | 1237 | * @retval >=1 Brown-out detect interrupt flag is set. |
| AnnaBridge | 172:7d866c31b3c5 | 1238 | * @details This macro get Brown-out detector interrupt flag. |
| AnnaBridge | 172:7d866c31b3c5 | 1239 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 1240 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 1241 | #define SYS_GET_BOD_INT_FLAG() (SYS->BODCTL & SYS_BODCTL_BODIF_Msk) |
| AnnaBridge | 172:7d866c31b3c5 | 1242 | |
| AnnaBridge | 172:7d866c31b3c5 | 1243 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 1244 | * @brief Get Brown-out detector status |
| AnnaBridge | 172:7d866c31b3c5 | 1245 | * @param None |
| AnnaBridge | 172:7d866c31b3c5 | 1246 | * @retval 0 System voltage is higher than BOD threshold voltage setting or BOD function is disabled. |
| AnnaBridge | 172:7d866c31b3c5 | 1247 | * @retval >=1 System voltage is lower than BOD threshold voltage setting. |
| AnnaBridge | 172:7d866c31b3c5 | 1248 | * @details This macro get Brown-out detector output status. |
| AnnaBridge | 172:7d866c31b3c5 | 1249 | * If the BOD function is disabled, this function always return 0. |
| AnnaBridge | 172:7d866c31b3c5 | 1250 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 1251 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 1252 | #define SYS_GET_BOD_OUTPUT() (SYS->BODCTL & SYS_BODCTL_BODOUT_Msk) |
| AnnaBridge | 172:7d866c31b3c5 | 1253 | |
| AnnaBridge | 172:7d866c31b3c5 | 1254 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 1255 | * @brief Enable Brown-out detector interrupt function |
| AnnaBridge | 172:7d866c31b3c5 | 1256 | * @param None |
| AnnaBridge | 172:7d866c31b3c5 | 1257 | * @return None |
| AnnaBridge | 172:7d866c31b3c5 | 1258 | * @details This macro enable Brown-out detector interrupt function. |
| AnnaBridge | 172:7d866c31b3c5 | 1259 | * The register write-protection function should be disabled before using this macro. |
| AnnaBridge | 172:7d866c31b3c5 | 1260 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 1261 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 1262 | #define SYS_DISABLE_BOD_RST() (SYS->BODCTL &= ~SYS_BODCTL_BODRSTEN_Msk) |
| AnnaBridge | 172:7d866c31b3c5 | 1263 | |
| AnnaBridge | 172:7d866c31b3c5 | 1264 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 1265 | * @brief Enable Brown-out detector reset function |
| AnnaBridge | 172:7d866c31b3c5 | 1266 | * @param None |
| AnnaBridge | 172:7d866c31b3c5 | 1267 | * @return None |
| AnnaBridge | 172:7d866c31b3c5 | 1268 | * @details This macro enable Brown-out detect reset function. |
| AnnaBridge | 172:7d866c31b3c5 | 1269 | * The register write-protection function should be disabled before using this macro. |
| AnnaBridge | 172:7d866c31b3c5 | 1270 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 1271 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 1272 | #define SYS_ENABLE_BOD_RST() (SYS->BODCTL |= SYS_BODCTL_BODRSTEN_Msk) |
| AnnaBridge | 172:7d866c31b3c5 | 1273 | |
| AnnaBridge | 172:7d866c31b3c5 | 1274 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 1275 | * @brief Set Brown-out detector function low power mode |
| AnnaBridge | 172:7d866c31b3c5 | 1276 | * @param None |
| AnnaBridge | 172:7d866c31b3c5 | 1277 | * @return None |
| AnnaBridge | 172:7d866c31b3c5 | 1278 | * @details This macro set Brown-out detector to low power mode. |
| AnnaBridge | 172:7d866c31b3c5 | 1279 | * The register write-protection function should be disabled before using this macro. |
| AnnaBridge | 172:7d866c31b3c5 | 1280 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 1281 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 1282 | #define SYS_SET_BOD_LPM() (SYS->BODCTL |= SYS_BODCTL_BODLPM_Msk) |
| AnnaBridge | 172:7d866c31b3c5 | 1283 | |
| AnnaBridge | 172:7d866c31b3c5 | 1284 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 1285 | * @brief Set Brown-out detector voltage level |
| AnnaBridge | 172:7d866c31b3c5 | 1286 | * @param[in] u32Level is Brown-out voltage level. Including : |
| AnnaBridge | 172:7d866c31b3c5 | 1287 | * - \ref SYS_BODCTL_BODVL_3_0V |
| AnnaBridge | 172:7d866c31b3c5 | 1288 | * - \ref SYS_BODCTL_BODVL_2_8V |
| AnnaBridge | 172:7d866c31b3c5 | 1289 | * - \ref SYS_BODCTL_BODVL_2_6V |
| AnnaBridge | 172:7d866c31b3c5 | 1290 | * - \ref SYS_BODCTL_BODVL_2_4V |
| AnnaBridge | 172:7d866c31b3c5 | 1291 | * - \ref SYS_BODCTL_BODVL_2_2V |
| AnnaBridge | 172:7d866c31b3c5 | 1292 | * - \ref SYS_BODCTL_BODVL_2_0V |
| AnnaBridge | 172:7d866c31b3c5 | 1293 | * - \ref SYS_BODCTL_BODVL_1_8V |
| AnnaBridge | 172:7d866c31b3c5 | 1294 | * - \ref SYS_BODCTL_BODVL_1_6V |
| AnnaBridge | 172:7d866c31b3c5 | 1295 | * @return None |
| AnnaBridge | 172:7d866c31b3c5 | 1296 | * @details This macro set Brown-out detector voltage level. |
| AnnaBridge | 172:7d866c31b3c5 | 1297 | * The write-protection function should be disabled before using this macro. |
| AnnaBridge | 172:7d866c31b3c5 | 1298 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 1299 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 1300 | #define SYS_SET_BOD_LEVEL(u32Level) (SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODVL_Msk) | (u32Level)) |
| AnnaBridge | 172:7d866c31b3c5 | 1301 | |
| AnnaBridge | 172:7d866c31b3c5 | 1302 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 1303 | * @brief Get reset source is from Brown-out detector reset |
| AnnaBridge | 172:7d866c31b3c5 | 1304 | * @param None |
| AnnaBridge | 172:7d866c31b3c5 | 1305 | * @retval 0 Previous reset source is not from Brown-out detector reset |
| AnnaBridge | 172:7d866c31b3c5 | 1306 | * @retval >=1 Previous reset source is from Brown-out detector reset |
| AnnaBridge | 172:7d866c31b3c5 | 1307 | * @details This macro get previous reset source is from Brown-out detect reset or not. |
| AnnaBridge | 172:7d866c31b3c5 | 1308 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 1309 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 1310 | #define SYS_IS_BOD_RST() (SYS->RSTSTS & SYS_RSTSTS_BODRF_Msk) |
| AnnaBridge | 172:7d866c31b3c5 | 1311 | |
| AnnaBridge | 172:7d866c31b3c5 | 1312 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 1313 | * @brief Get reset source is from CPU reset |
| AnnaBridge | 172:7d866c31b3c5 | 1314 | * @param None |
| AnnaBridge | 172:7d866c31b3c5 | 1315 | * @retval 0 Previous reset source is not from CPU reset |
| AnnaBridge | 172:7d866c31b3c5 | 1316 | * @retval >=1 Previous reset source is from CPU reset |
| AnnaBridge | 172:7d866c31b3c5 | 1317 | * @details This macro get previous reset source is from CPU reset. |
| AnnaBridge | 172:7d866c31b3c5 | 1318 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 1319 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 1320 | #define SYS_IS_CPU_RST() (SYS->RSTSTS & SYS_RSTSTS_CPURF_Msk) |
| AnnaBridge | 172:7d866c31b3c5 | 1321 | |
| AnnaBridge | 172:7d866c31b3c5 | 1322 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 1323 | * @brief Get reset source is from LVR Reset |
| AnnaBridge | 172:7d866c31b3c5 | 1324 | * @param None |
| AnnaBridge | 172:7d866c31b3c5 | 1325 | * @retval 0 Previous reset source is not from Low-Voltage-Reset |
| AnnaBridge | 172:7d866c31b3c5 | 1326 | * @retval >=1 Previous reset source is from Low-Voltage-Reset |
| AnnaBridge | 172:7d866c31b3c5 | 1327 | * @details This macro get previous reset source is from Low-Voltage-Reset. |
| AnnaBridge | 172:7d866c31b3c5 | 1328 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 1329 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 1330 | #define SYS_IS_LVR_RST() (SYS->RSTSTS & SYS_RSTSTS_LVRF_Msk) |
| AnnaBridge | 172:7d866c31b3c5 | 1331 | |
| AnnaBridge | 172:7d866c31b3c5 | 1332 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 1333 | * @brief Get reset source is from Power-on Reset |
| AnnaBridge | 172:7d866c31b3c5 | 1334 | * @param None |
| AnnaBridge | 172:7d866c31b3c5 | 1335 | * @retval 0 Previous reset source is not from Power-on Reset |
| AnnaBridge | 172:7d866c31b3c5 | 1336 | * @retval >=1 Previous reset source is from Power-on Reset |
| AnnaBridge | 172:7d866c31b3c5 | 1337 | * @details This macro get previous reset source is from Power-on Reset. |
| AnnaBridge | 172:7d866c31b3c5 | 1338 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 1339 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 1340 | #define SYS_IS_POR_RST() (SYS->RSTSTS & SYS_RSTSTS_PORF_Msk) |
| AnnaBridge | 172:7d866c31b3c5 | 1341 | |
| AnnaBridge | 172:7d866c31b3c5 | 1342 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 1343 | * @brief Get reset source is from reset pin reset |
| AnnaBridge | 172:7d866c31b3c5 | 1344 | * @param None |
| AnnaBridge | 172:7d866c31b3c5 | 1345 | * @retval 0 Previous reset source is not from reset pin reset |
| AnnaBridge | 172:7d866c31b3c5 | 1346 | * @retval >=1 Previous reset source is from reset pin reset |
| AnnaBridge | 172:7d866c31b3c5 | 1347 | * @details This macro get previous reset source is from reset pin reset. |
| AnnaBridge | 172:7d866c31b3c5 | 1348 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 1349 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 1350 | #define SYS_IS_RSTPIN_RST() (SYS->RSTSTS & SYS_RSTSTS_PINRF_Msk) |
| AnnaBridge | 172:7d866c31b3c5 | 1351 | |
| AnnaBridge | 172:7d866c31b3c5 | 1352 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 1353 | * @brief Get reset source is from system reset |
| AnnaBridge | 172:7d866c31b3c5 | 1354 | * @param None |
| AnnaBridge | 172:7d866c31b3c5 | 1355 | * @retval 0 Previous reset source is not from system reset |
| AnnaBridge | 172:7d866c31b3c5 | 1356 | * @retval >=1 Previous reset source is from system reset |
| AnnaBridge | 172:7d866c31b3c5 | 1357 | * @details This macro get previous reset source is from system reset. |
| AnnaBridge | 172:7d866c31b3c5 | 1358 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 1359 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 1360 | #define SYS_IS_SYSTEM_RST() (SYS->RSTSTS & SYS_RSTSTS_SYSRF_Msk) |
| AnnaBridge | 172:7d866c31b3c5 | 1361 | |
| AnnaBridge | 172:7d866c31b3c5 | 1362 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 1363 | * @brief Get reset source is from window watch dog reset |
| AnnaBridge | 172:7d866c31b3c5 | 1364 | * @param None |
| AnnaBridge | 172:7d866c31b3c5 | 1365 | * @retval 0 Previous reset source is not from window watch dog reset |
| AnnaBridge | 172:7d866c31b3c5 | 1366 | * @retval >=1 Previous reset source is from window watch dog reset |
| AnnaBridge | 172:7d866c31b3c5 | 1367 | * @details This macro get previous reset source is from window watch dog reset. |
| AnnaBridge | 172:7d866c31b3c5 | 1368 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 1369 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 1370 | #define SYS_IS_WDT_RST() (SYS->RSTSTS & SYS_RSTSTS_WDTRF_Msk) |
| AnnaBridge | 172:7d866c31b3c5 | 1371 | |
| AnnaBridge | 172:7d866c31b3c5 | 1372 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 1373 | * @brief Disable Low-Voltage-Reset function |
| AnnaBridge | 172:7d866c31b3c5 | 1374 | * @param None |
| AnnaBridge | 172:7d866c31b3c5 | 1375 | * @return None |
| AnnaBridge | 172:7d866c31b3c5 | 1376 | * @details This macro disable Low-Voltage-Reset function. |
| AnnaBridge | 172:7d866c31b3c5 | 1377 | * The register write-protection function should be disabled before using this macro. |
| AnnaBridge | 172:7d866c31b3c5 | 1378 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 1379 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 1380 | #define SYS_DISABLE_LVR() (SYS->BODCTL &= ~SYS_BODCTL_LVREN_Msk) |
| AnnaBridge | 172:7d866c31b3c5 | 1381 | |
| AnnaBridge | 172:7d866c31b3c5 | 1382 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 1383 | * @brief Enable Low-Voltage-Reset function |
| AnnaBridge | 172:7d866c31b3c5 | 1384 | * @param None |
| AnnaBridge | 172:7d866c31b3c5 | 1385 | * @return None |
| AnnaBridge | 172:7d866c31b3c5 | 1386 | * @details This macro enable Low-Voltage-Reset function. |
| AnnaBridge | 172:7d866c31b3c5 | 1387 | * The register write-protection function should be disabled before using this macro. |
| AnnaBridge | 172:7d866c31b3c5 | 1388 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 1389 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 1390 | #define SYS_ENABLE_LVR() (SYS->BODCTL |= SYS_BODCTL_LVREN_Msk) |
| AnnaBridge | 172:7d866c31b3c5 | 1391 | |
| AnnaBridge | 172:7d866c31b3c5 | 1392 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 1393 | * @brief Disable Power-on Reset function |
| AnnaBridge | 172:7d866c31b3c5 | 1394 | * @param None |
| AnnaBridge | 172:7d866c31b3c5 | 1395 | * @return None |
| AnnaBridge | 172:7d866c31b3c5 | 1396 | * @details This macro disable Power-on Reset function. |
| AnnaBridge | 172:7d866c31b3c5 | 1397 | * The register write-protection function should be disabled before using this macro. |
| AnnaBridge | 172:7d866c31b3c5 | 1398 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 1399 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 1400 | #define SYS_DISABLE_POR() (SYS->PORCTL = 0x5AA5) |
| AnnaBridge | 172:7d866c31b3c5 | 1401 | |
| AnnaBridge | 172:7d866c31b3c5 | 1402 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 1403 | * @brief Enable Power-on Reset function |
| AnnaBridge | 172:7d866c31b3c5 | 1404 | * @param None |
| AnnaBridge | 172:7d866c31b3c5 | 1405 | * @return None |
| AnnaBridge | 172:7d866c31b3c5 | 1406 | * @details This macro enable Power-on Reset function. |
| AnnaBridge | 172:7d866c31b3c5 | 1407 | * The register write-protection function should be disabled before using this macro. |
| AnnaBridge | 172:7d866c31b3c5 | 1408 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 1409 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 1410 | #define SYS_ENABLE_POR() (SYS->PORCTL = 0) |
| AnnaBridge | 172:7d866c31b3c5 | 1411 | |
| AnnaBridge | 172:7d866c31b3c5 | 1412 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 1413 | * @brief Clear reset source flag |
| AnnaBridge | 172:7d866c31b3c5 | 1414 | * @param[in] u32RstSrc is reset source. Including : |
| AnnaBridge | 172:7d866c31b3c5 | 1415 | * - \ref SYS_RSTSTS_PORF_Msk |
| AnnaBridge | 172:7d866c31b3c5 | 1416 | * - \ref SYS_RSTSTS_PINRF_Msk |
| AnnaBridge | 172:7d866c31b3c5 | 1417 | * - \ref SYS_RSTSTS_WDTRF_Msk |
| AnnaBridge | 172:7d866c31b3c5 | 1418 | * - \ref SYS_RSTSTS_LVRF_Msk |
| AnnaBridge | 172:7d866c31b3c5 | 1419 | * - \ref SYS_RSTSTS_BODRF_Msk |
| AnnaBridge | 172:7d866c31b3c5 | 1420 | * - \ref SYS_RSTSTS_SYSRF_Msk |
| AnnaBridge | 172:7d866c31b3c5 | 1421 | * - \ref SYS_RSTSTS_CPURF_Msk |
| AnnaBridge | 172:7d866c31b3c5 | 1422 | * - \ref SYS_RSTSTS_CPULKRF_Msk |
| AnnaBridge | 172:7d866c31b3c5 | 1423 | * @return None |
| AnnaBridge | 172:7d866c31b3c5 | 1424 | * @details This macro clear reset source flag. |
| AnnaBridge | 172:7d866c31b3c5 | 1425 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 1426 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 1427 | #define SYS_CLEAR_RST_SOURCE(u32RstSrc) ((SYS->RSTSTS) = (u32RstSrc) ) |
| AnnaBridge | 172:7d866c31b3c5 | 1428 | |
| AnnaBridge | 172:7d866c31b3c5 | 1429 | |
| AnnaBridge | 172:7d866c31b3c5 | 1430 | /*---------------------------------------------------------------------------------------------------------*/ |
| AnnaBridge | 172:7d866c31b3c5 | 1431 | /* static inline functions */ |
| AnnaBridge | 172:7d866c31b3c5 | 1432 | /*---------------------------------------------------------------------------------------------------------*/ |
| AnnaBridge | 172:7d866c31b3c5 | 1433 | /* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ |
| AnnaBridge | 172:7d866c31b3c5 | 1434 | static __INLINE void SYS_UnlockReg(void); |
| AnnaBridge | 172:7d866c31b3c5 | 1435 | static __INLINE void SYS_LockReg(void); |
| AnnaBridge | 172:7d866c31b3c5 | 1436 | |
| AnnaBridge | 172:7d866c31b3c5 | 1437 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 1438 | * @brief Disable register write-protection function |
| AnnaBridge | 172:7d866c31b3c5 | 1439 | * @param None |
| AnnaBridge | 172:7d866c31b3c5 | 1440 | * @return None |
| AnnaBridge | 172:7d866c31b3c5 | 1441 | * @details This function disable register write-protection function. |
| AnnaBridge | 172:7d866c31b3c5 | 1442 | * To unlock the protected register to allow write access. |
| AnnaBridge | 172:7d866c31b3c5 | 1443 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 1444 | __STATIC_INLINE void SYS_UnlockReg(void) |
| AnnaBridge | 172:7d866c31b3c5 | 1445 | { |
| AnnaBridge | 172:7d866c31b3c5 | 1446 | do { |
| AnnaBridge | 172:7d866c31b3c5 | 1447 | SYS->REGLCTL = 0x59UL; |
| AnnaBridge | 172:7d866c31b3c5 | 1448 | SYS->REGLCTL = 0x16UL; |
| AnnaBridge | 172:7d866c31b3c5 | 1449 | SYS->REGLCTL = 0x88UL; |
| AnnaBridge | 172:7d866c31b3c5 | 1450 | } while(SYS->REGLCTL == 0UL); |
| AnnaBridge | 172:7d866c31b3c5 | 1451 | } |
| AnnaBridge | 172:7d866c31b3c5 | 1452 | |
| AnnaBridge | 172:7d866c31b3c5 | 1453 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 1454 | * @brief Enable register write-protection function |
| AnnaBridge | 172:7d866c31b3c5 | 1455 | * @param None |
| AnnaBridge | 172:7d866c31b3c5 | 1456 | * @return None |
| AnnaBridge | 172:7d866c31b3c5 | 1457 | * @details This function is used to enable register write-protection function. |
| AnnaBridge | 172:7d866c31b3c5 | 1458 | * To lock the protected register to forbid write access. |
| AnnaBridge | 172:7d866c31b3c5 | 1459 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 1460 | __STATIC_INLINE void SYS_LockReg(void) |
| AnnaBridge | 172:7d866c31b3c5 | 1461 | { |
| AnnaBridge | 172:7d866c31b3c5 | 1462 | SYS->REGLCTL = 0UL; |
| AnnaBridge | 172:7d866c31b3c5 | 1463 | } |
| AnnaBridge | 172:7d866c31b3c5 | 1464 | |
| AnnaBridge | 172:7d866c31b3c5 | 1465 | |
| AnnaBridge | 172:7d866c31b3c5 | 1466 | void SYS_ClearResetSrc(uint32_t u32Src); |
| AnnaBridge | 172:7d866c31b3c5 | 1467 | uint32_t SYS_GetBODStatus(void); |
| AnnaBridge | 172:7d866c31b3c5 | 1468 | uint32_t SYS_GetResetSrc(void); |
| AnnaBridge | 172:7d866c31b3c5 | 1469 | uint32_t SYS_IsRegLocked(void); |
| AnnaBridge | 172:7d866c31b3c5 | 1470 | uint32_t SYS_ReadPDID(void); |
| AnnaBridge | 172:7d866c31b3c5 | 1471 | void SYS_ResetChip(void); |
| AnnaBridge | 172:7d866c31b3c5 | 1472 | void SYS_ResetCPU(void); |
| AnnaBridge | 172:7d866c31b3c5 | 1473 | void SYS_ResetModule(uint32_t u32ModuleIndex); |
| AnnaBridge | 172:7d866c31b3c5 | 1474 | void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel); |
| AnnaBridge | 172:7d866c31b3c5 | 1475 | void SYS_DisableBOD(void); |
| AnnaBridge | 172:7d866c31b3c5 | 1476 | |
| AnnaBridge | 172:7d866c31b3c5 | 1477 | |
| AnnaBridge | 172:7d866c31b3c5 | 1478 | /*@}*/ /* end of group M480_SYS_EXPORTED_FUNCTIONS */ |
| AnnaBridge | 172:7d866c31b3c5 | 1479 | |
| AnnaBridge | 172:7d866c31b3c5 | 1480 | /*@}*/ /* end of group M480_SYS_Driver */ |
| AnnaBridge | 172:7d866c31b3c5 | 1481 | |
| AnnaBridge | 172:7d866c31b3c5 | 1482 | /*@}*/ /* end of group M480_Device_Driver */ |
| AnnaBridge | 172:7d866c31b3c5 | 1483 | |
| AnnaBridge | 172:7d866c31b3c5 | 1484 | |
| AnnaBridge | 172:7d866c31b3c5 | 1485 | #ifdef __cplusplus |
| AnnaBridge | 172:7d866c31b3c5 | 1486 | } |
| AnnaBridge | 172:7d866c31b3c5 | 1487 | #endif |
| AnnaBridge | 172:7d866c31b3c5 | 1488 | |
| AnnaBridge | 172:7d866c31b3c5 | 1489 | #endif /* __SYS_H__ */ |
| AnnaBridge | 172:7d866c31b3c5 | 1490 | |
| AnnaBridge | 172:7d866c31b3c5 | 1491 | /*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ |
