Revision 6:e380af098d52, committed 2017-09-07

Comitter:

coreyharris

Date:

Thu Sep 07 18:26:48 2017 +0000

Parent:

5:202ed7222217

Commit message:

Added RtoR support

Changed in this revision

diff -r 202ed7222217 -r e380af098d52 main.cpp
--- a/main.cpp	Tue Aug 29 20:23:45 2017 +0000
+++ b/main.cpp	Thu Sep 07 18:26:48 2017 +0000
@@ -41,10 +41,10 @@
 void ecg_config(MAX30003 &ecgAFE);
 
 /* ECG FIFO nearly full callback */
-volatile bool ecgFIFOIntFlag = 0; 
+volatile bool ecgIntFlag = 0; 
 void ecgFIFO_callback()  {
     
-    ecgFIFOIntFlag = 1;
+    ecgIntFlag = 1;
 
 }  
 
@@ -52,11 +52,14 @@
 {   
     
     // Constants
-    const int EINT_STATUS_MASK =  1 << 23;
-    const int FIFO_OVF_MASK =  0x7;
-    const int FIFO_VALID_SAMPLE_MASK =  0x0;
-    const int FIFO_FAST_SAMPLE_MASK =  0x1;
-    const int ETAG_BITS_MASK = 0x7;
+    const int EINT_STATUS =  1 << 23;
+    const int RTOR_STATUS =  1 << 10;
+    const int RTOR_REG_OFFSET = 10;
+    const float RTOR_LSB_RES = 0.008f;
+    const int FIFO_OVF =  0x7;
+    const int FIFO_VALID_SAMPLE =  0x0;
+    const int FIFO_FAST_SAMPLE =  0x1;
+    const int ETAG_BITS = 0x7;
     
     // Ports and serial connections
     Serial pc(USBTX, USBRX);            // Use USB debug probe for serial link
@@ -78,21 +81,40 @@
     
     ecgAFE.writeRegister( MAX30003::SYNCH , 0);
     
-    uint32_t ecgFIFO, readECGSamples, idx, ETAG[32], status;
+    uint32_t ecgFIFO, RtoR, readECGSamples, idx, ETAG[32], status;
     int16_t ecgSample[32];
+    float BPM;
     
     while(1) {
         
         /* Read back ECG samples from the FIFO */
-        if( ecgFIFOIntFlag ) {
+        if( ecgIntFlag ) {
             
-            ecgFIFOIntFlag = 0;
+            ecgIntFlag = 0;
             pc.printf("Interrupt received....\r\n");
             status = ecgAFE.readRegister( MAX30003::STATUS );      // Read the STATUS register
-            pc.printf("Status : 0x%x\r\n\r\n", status);
+            pc.printf("Status : 0x%x\r\n"
+                      "Current BPM is %3.2f\r\n\r\n", status, BPM);
+             
+             
+            // Check if R-to-R interrupt asserted
+            if( ( status & RTOR_STATUS ) == RTOR_STATUS ){           
+            
+                pc.printf("R-to-R Interrupt \r\n");
+                
+                // Read RtoR register
+                RtoR = ecgAFE.readRegister( MAX30003::RTOR ) >>  RTOR_REG_OFFSET;   
+                
+                // Convert to BPM
+                BPM = 1.0f / ( RtoR * RTOR_LSB_RES / 60.0f );   
+                
+                // Print RtoR              
+                pc.printf("RtoR : %d\r\n\r\n", RtoR);                   
+                
+            }  
              
             // Check if EINT interrupt asserted
-            if ( ( status & EINT_STATUS_MASK ) == EINT_STATUS_MASK ) {     
+            if ( ( status & EINT_STATUS ) == EINT_STATUS ) {     
             
                 pc.printf("FIFO Interrupt \r\n");
                 readECGSamples = 0;                        // Reset sample counter
@@ -100,17 +122,17 @@
                 do {
                     ecgFIFO = ecgAFE.readRegister( MAX30003::ECG_FIFO );       // Read FIFO
                     ecgSample[readECGSamples] = ecgFIFO >> 8;                  // Isolate voltage data
-                    ETAG[readECGSamples] = ( ecgFIFO >> 3 ) & ETAG_BITS_MASK;  // Isolate ETAG
+                    ETAG[readECGSamples] = ( ecgFIFO >> 3 ) & ETAG_BITS;  // Isolate ETAG
                     readECGSamples++;                                          // Increment sample counter
                 
                 // Check that sample is not last sample in FIFO                                              
-                } while ( ETAG[readECGSamples-1] == FIFO_VALID_SAMPLE_MASK || 
-                          ETAG[readECGSamples-1] == FIFO_FAST_SAMPLE_MASK ); 
+                } while ( ETAG[readECGSamples-1] == FIFO_VALID_SAMPLE || 
+                          ETAG[readECGSamples-1] == FIFO_FAST_SAMPLE ); 
             
                 pc.printf("%d samples read from FIFO \r\n", readECGSamples);
                 
                 // Check if FIFO has overflowed
-                if( ETAG[readECGSamples - 1] == FIFO_OVF_MASK ){                  
+                if( ETAG[readECGSamples - 1] == FIFO_OVF ){                  
                     ecgAFE.writeRegister( MAX30003::FIFO_RST , 0); // Reset FIFO
                 }
                 
@@ -139,24 +161,27 @@
     CNFG_GEN_r.bits.rbiasn = 1;     // Enable resistive bias on negative input
     CNFG_GEN_r.bits.rbiasp = 1;     // Enable resistive bias on positive input
     CNFG_GEN_r.bits.en_rbias = 1;   // Enable resistive bias
+    CNFG_GEN_r.bits.imag = 2;       // Current magnitude = 10nA
     CNFG_GEN_r.bits.en_dcloff = 1;  // Enable DC lead-off detection   
-    CNFG_GEN_r.bits.imag = 0b010;   // Current magnitude = 10nA
-    CNFG_GEN_r.bits.rbiasv = 0b00;  // Resistive bias = 50MOhm
     ecgAFE.writeRegister( MAX30003::CNFG_GEN , CNFG_GEN_r.all);
         
     
     // ECG Config register setting
     MAX30003::ECGConfiguration_u CNFG_ECG_r;
-    CNFG_ECG_r.bits.dlpf = 0b01;       // Digital LPF cutoff = 40Hz
-    CNFG_ECG_r.bits.dhpf = 1;          // Digital HPF cutoff = 0.5Hz
-    CNFG_ECG_r.bits.gain = 0b11;       // ECG gain = 160V/V
-    CNFG_ECG_r.bits.rate = 0b10;       // Sample rate = 128 sps
+    CNFG_ECG_r.bits.dlpf = 1;       // Digital LPF cutoff = 40Hz
+    CNFG_ECG_r.bits.dhpf = 1;       // Digital HPF cutoff = 0.5Hz
+    CNFG_ECG_r.bits.gain = 3;       // ECG gain = 160V/V
+    CNFG_ECG_r.bits.rate = 2;       // Sample rate = 128 sps
     ecgAFE.writeRegister( MAX30003::CNFG_ECG , CNFG_ECG_r.all);
       
     
     //R-to-R configuration
     MAX30003::RtoR1Configuration_u CNFG_RTOR_r;
-    CNFG_RTOR_r.bits.en_rtor = 0;           // Disable R-to-R detection
+    CNFG_RTOR_r.bits.wndw = 0b0011;         // WNDW = 96ms
+    CNFG_RTOR_r.bits.rgain = 0b1111;        // Auto-scale gain
+    CNFG_RTOR_r.bits.pavg = 0b11;           // 16-average
+    CNFG_RTOR_r.bits.ptsf = 0b0011;         // PTSF = 4/16
+    CNFG_RTOR_r.bits.en_rtor = 1;           // Enable R-to-R detection
     ecgAFE.writeRegister( MAX30003::CNFG_RTOR1 , CNFG_RTOR_r.all);
        
         
@@ -170,8 +195,8 @@
     //Enable interrupts register setting
     MAX30003::EnableInterrupts_u EN_INT_r;
     EN_INT_r.bits.en_eint = 1;              // Enable EINT interrupt
-    EN_INT_r.bits.en_rrint = 0;             // Disable R-to-R interrupt
-    EN_INT_r.bits.intb_type = 0b11;         // Open-drain NMOS with internal pullup
+    EN_INT_r.bits.en_rrint = 1;             // Enable R-to-R interrupt
+    EN_INT_r.bits.intb_type = 3;            // Open-drain NMOS with internal pullup
     ecgAFE.writeRegister( MAX30003::EN_INT , EN_INT_r.all);
        
        
@@ -185,8 +210,6 @@
     CNFG_MUX_r.bits.openn = 0;          // Connect ECGN to AFE channel
     CNFG_MUX_r.bits.openp = 0;          // Connect ECGP to AFE channel
     ecgAFE.writeRegister( MAX30003::CNFG_EMUX , CNFG_MUX_r.all);
-       
-       
     
     return;
 }