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enc28j60.h
00001 /***************************************************************************** 00002 * 00003 * Title : Microchip ENC28J60 Ethernet Interface Driver 00004 * Author : Pascal Stang (c)2005 00005 * Modified by Norbert Truchsess 00006 * Copyright: GPL V2 00007 * 00008 *This driver provides initialization and transmit/receive 00009 *functions for the Microchip ENC28J60 10Mb Ethernet Controller and PHY. 00010 *This chip is novel in that it is a full MAC+PHY interface all in a 28-pin 00011 *chip, using an SPI interface to the host processor. 00012 * 00013 * 00014 *****************************************************************************/ 00015 00016 #ifndef ENC28J60_H 00017 #define ENC28J60_H 00018 #include <inttypes.h> 00019 00020 // ENC28J60 Control Registers 00021 // Control register definitions are a combination of address, 00022 // bank number, and Ethernet/MAC/PHY indicator bits. 00023 // - Register address (bits 0-4) 00024 // - Bank number (bits 5-6) 00025 // - MAC/PHY indicator (bit 7) 00026 #define ADDR_MASK 0x1F 00027 #define BANK_MASK 0x60 00028 #define SPRD_MASK 0x80 00029 // All-bank registers 00030 #define EIE 0x1B 00031 #define EIR 0x1C 00032 #define ESTAT 0x1D 00033 #define ECON2 0x1E 00034 #define ECON1 0x1F 00035 // Bank 0 registers 00036 #define ERDPTL (0x00|0x00) 00037 #define ERDPTH (0x01|0x00) 00038 #define EWRPTL (0x02|0x00) 00039 #define EWRPTH (0x03|0x00) 00040 #define ETXSTL (0x04|0x00) 00041 #define ETXSTH (0x05|0x00) 00042 #define ETXNDL (0x06|0x00) 00043 #define ETXNDH (0x07|0x00) 00044 #define ERXSTL (0x08|0x00) 00045 #define ERXSTH (0x09|0x00) 00046 #define ERXNDL (0x0A|0x00) 00047 #define ERXNDH (0x0B|0x00) 00048 #define ERXRDPTL (0x0C|0x00) 00049 #define ERXRDPTH (0x0D|0x00) 00050 #define ERXWRPTL (0x0E|0x00) 00051 #define ERXWRPTH (0x0F|0x00) 00052 #define EDMASTL (0x10|0x00) 00053 #define EDMASTH (0x11|0x00) 00054 #define EDMANDL (0x12|0x00) 00055 #define EDMANDH (0x13|0x00) 00056 #define EDMADSTL (0x14|0x00) 00057 #define EDMADSTH (0x15|0x00) 00058 #define EDMACSL (0x16|0x00) 00059 #define EDMACSH (0x17|0x00) 00060 // Bank 1 registers 00061 #define EHT0 (0x00|0x20) 00062 #define EHT1 (0x01|0x20) 00063 #define EHT2 (0x02|0x20) 00064 #define EHT3 (0x03|0x20) 00065 #define EHT4 (0x04|0x20) 00066 #define EHT5 (0x05|0x20) 00067 #define EHT6 (0x06|0x20) 00068 #define EHT7 (0x07|0x20) 00069 #define EPMM0 (0x08|0x20) 00070 #define EPMM1 (0x09|0x20) 00071 #define EPMM2 (0x0A|0x20) 00072 #define EPMM3 (0x0B|0x20) 00073 #define EPMM4 (0x0C|0x20) 00074 #define EPMM5 (0x0D|0x20) 00075 #define EPMM6 (0x0E|0x20) 00076 #define EPMM7 (0x0F|0x20) 00077 #define EPMCSL (0x10|0x20) 00078 #define EPMCSH (0x11|0x20) 00079 #define EPMOL (0x14|0x20) 00080 #define EPMOH (0x15|0x20) 00081 #define EWOLIE (0x16|0x20) 00082 #define EWOLIR (0x17|0x20) 00083 #define ERXFCON (0x18|0x20) 00084 #define EPKTCNT (0x19|0x20) 00085 // Bank 2 registers 00086 #define MACON1 (0x00|0x40|0x80) 00087 #define MACON2 (0x01|0x40|0x80) 00088 #define MACON3 (0x02|0x40|0x80) 00089 #define MACON4 (0x03|0x40|0x80) 00090 #define MABBIPG (0x04|0x40|0x80) 00091 #define MAIPGL (0x06|0x40|0x80) 00092 #define MAIPGH (0x07|0x40|0x80) 00093 #define MACLCON1 (0x08|0x40|0x80) 00094 #define MACLCON2 (0x09|0x40|0x80) 00095 #define MAMXFLL (0x0A|0x40|0x80) 00096 #define MAMXFLH (0x0B|0x40|0x80) 00097 #define MAPHSUP (0x0D|0x40|0x80) 00098 #define MICON (0x11|0x40|0x80) 00099 #define MICMD (0x12|0x40|0x80) 00100 #define MIREGADR (0x14|0x40|0x80) 00101 #define MIWRL (0x16|0x40|0x80) 00102 #define MIWRH (0x17|0x40|0x80) 00103 #define MIRDL (0x18|0x40|0x80) 00104 #define MIRDH (0x19|0x40|0x80) 00105 // Bank 3 registers 00106 #define MAADR1 (0x00|0x60|0x80) 00107 #define MAADR0 (0x01|0x60|0x80) 00108 #define MAADR3 (0x02|0x60|0x80) 00109 #define MAADR2 (0x03|0x60|0x80) 00110 #define MAADR5 (0x04|0x60|0x80) 00111 #define MAADR4 (0x05|0x60|0x80) 00112 #define EBSTSD (0x06|0x60) 00113 #define EBSTCON (0x07|0x60) 00114 #define EBSTCSL (0x08|0x60) 00115 #define EBSTCSH (0x09|0x60) 00116 #define MISTAT (0x0A|0x60|0x80) 00117 #define EREVID (0x12|0x60) 00118 #define ECOCON (0x15|0x60) 00119 #define EFLOCON (0x17|0x60) 00120 #define EPAUSL (0x18|0x60) 00121 #define EPAUSH (0x19|0x60) 00122 // PHY registers 00123 #define PHCON1 0x00 00124 #define PHSTAT1 0x01 00125 #define PHHID1 0x02 00126 #define PHHID2 0x03 00127 #define PHCON2 0x10 00128 #define PHSTAT2 0x11 00129 #define PHIE 0x12 00130 #define PHIR 0x13 00131 #define PHLCON 0x14 00132 00133 // ENC28J60 ERXFCON Register Bit Definitions 00134 #define ERXFCON_UCEN 0x80 00135 #define ERXFCON_ANDOR 0x40 00136 #define ERXFCON_CRCEN 0x20 00137 #define ERXFCON_PMEN 0x10 00138 #define ERXFCON_MPEN 0x08 00139 #define ERXFCON_HTEN 0x04 00140 #define ERXFCON_MCEN 0x02 00141 #define ERXFCON_BCEN 0x01 00142 // ENC28J60 EIE Register Bit Definitions 00143 #define EIE_INTIE 0x80 00144 #define EIE_PKTIE 0x40 00145 #define EIE_DMAIE 0x20 00146 #define EIE_LINKIE 0x10 00147 #define EIE_TXIE 0x08 00148 #define EIE_WOLIE 0x04 00149 #define EIE_TXERIE 0x02 00150 #define EIE_RXERIE 0x01 00151 // ENC28J60 EIR Register Bit Definitions 00152 #define EIR_PKTIF 0x40 00153 #define EIR_DMAIF 0x20 00154 #define EIR_LINKIF 0x10 00155 #define EIR_TXIF 0x08 00156 #define EIR_WOLIF 0x04 00157 #define EIR_TXERIF 0x02 00158 #define EIR_RXERIF 0x01 00159 // ENC28J60 ESTAT Register Bit Definitions 00160 #define ESTAT_INT 0x80 00161 #define ESTAT_LATECOL 0x10 00162 #define ESTAT_RXBUSY 0x04 00163 #define ESTAT_TXABRT 0x02 00164 #define ESTAT_CLKRDY 0x01 00165 // ENC28J60 ECON2 Register Bit Definitions 00166 #define ECON2_AUTOINC 0x80 00167 #define ECON2_PKTDEC 0x40 00168 #define ECON2_PWRSV 0x20 00169 #define ECON2_VRPS 0x08 00170 // ENC28J60 ECON1 Register Bit Definitions 00171 #define ECON1_TXRST 0x80 00172 #define ECON1_RXRST 0x40 00173 #define ECON1_DMAST 0x20 00174 #define ECON1_CSUMEN 0x10 00175 #define ECON1_TXRTS 0x08 00176 #define ECON1_RXEN 0x04 00177 #define ECON1_BSEL1 0x02 00178 #define ECON1_BSEL0 0x01 00179 // ENC28J60 MACON1 Register Bit Definitions 00180 #define MACON1_LOOPBK 0x10 00181 #define MACON1_TXPAUS 0x08 00182 #define MACON1_RXPAUS 0x04 00183 #define MACON1_PASSALL 0x02 00184 #define MACON1_MARXEN 0x01 00185 // ENC28J60 MACON2 Register Bit Definitions 00186 #define MACON2_MARST 0x80 00187 #define MACON2_RNDRST 0x40 00188 #define MACON2_MARXRST 0x08 00189 #define MACON2_RFUNRST 0x04 00190 #define MACON2_MATXRST 0x02 00191 #define MACON2_TFUNRST 0x01 00192 // ENC28J60 MACON3 Register Bit Definitions 00193 #define MACON3_PADCFG2 0x80 00194 #define MACON3_PADCFG1 0x40 00195 #define MACON3_PADCFG0 0x20 00196 #define MACON3_TXCRCEN 0x10 00197 #define MACON3_PHDRLEN 0x08 00198 #define MACON3_HFRMLEN 0x04 00199 #define MACON3_FRMLNEN 0x02 00200 #define MACON3_FULDPX 0x01 00201 // ENC28J60 MICMD Register Bit Definitions 00202 #define MICMD_MIISCAN 0x02 00203 #define MICMD_MIIRD 0x01 00204 // ENC28J60 MISTAT Register Bit Definitions 00205 #define MISTAT_NVALID 0x04 00206 #define MISTAT_SCAN 0x02 00207 #define MISTAT_BUSY 0x01 00208 // ENC28J60 PHY PHCON1 Register Bit Definitions 00209 #define PHCON1_PRST 0x8000 00210 #define PHCON1_PLOOPBK 0x4000 00211 #define PHCON1_PPWRSV 0x0800 00212 #define PHCON1_PDPXMD 0x0100 00213 // ENC28J60 PHY PHSTAT1 Register Bit Definitions 00214 #define PHSTAT1_PFDPX 0x1000 00215 #define PHSTAT1_PHDPX 0x0800 00216 #define PHSTAT1_LLSTAT 0x0004 00217 #define PHSTAT1_JBSTAT 0x0002 00218 // ENC28J60 PHY PHCON2 Register Bit Definitions 00219 #define PHCON2_FRCLINK 0x4000 00220 #define PHCON2_TXDIS 0x2000 00221 #define PHCON2_JABBER 0x0400 00222 #define PHCON2_HDLDIS 0x0100 00223 00224 // ENC28J60 Packet Control Byte Bit Definitions 00225 #define PKTCTRL_PHUGEEN 0x08 00226 #define PKTCTRL_PPADEN 0x04 00227 #define PKTCTRL_PCRCEN 0x02 00228 #define PKTCTRL_POVERRIDE 0x01 00229 00230 // SPI operation codes 00231 #define ENC28J60_READ_CTRL_REG 0x00 00232 #define ENC28J60_READ_BUF_MEM 0x3A 00233 #define ENC28J60_WRITE_CTRL_REG 0x40 00234 #define ENC28J60_WRITE_BUF_MEM 0x7A 00235 #define ENC28J60_BIT_FIELD_SET 0x80 00236 #define ENC28J60_BIT_FIELD_CLR 0xA0 00237 #define ENC28J60_SOFT_RESET 0xFF 00238 00239 00240 // The RXSTART_INIT should be zero. See Silicon Errata: 00241 // Sometimes, when ERXST or ERXND is written to, the exact value, 0000h, is stored in the Internal 00242 // Receive Write Pointer instead of the ERXST address. 00243 // Work around: 00244 // Use the lower segment of the buffer memory for the receive buffer, starting at address 0000h. 00245 // For example, use the range (0000h to n) for the receive buffer, and ((n + 1) to 8191) for the transmit buffer. 00246 #define RXSTART_INIT 0x0 00247 // Receive buffer end. Make sure this is an odd value (See Rev. B1,B4,B5,B7 Silicon Errata 'Memory (Ethernet Buffer)') 00248 #define RXEND_INIT (0x1FFF - 0x1800) // 0x1800 = 512 * 12 00249 // Start TX buffer RXEND_INIT + 1 00250 #define TXSTART_INIT (RXEND_INIT + 1) 00251 // end TX buffer at end of mem 00252 #define TXEND_INIT 0x1FFF 00253 // 00254 // Max frame length which the conroller will accept: 00255 #define MAX_FRAMELEN 1518 // (note: maximum ethernet frame length is 1518) 00256 00257 #endif
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