sx127x_lora.h

00001 #include "sx12xx.h"
00002 
00003 // LoRa registers
00004 #define REG_LR_FIFOADDRPTR                          0x0d
00005 #define REG_LR_FIFOTXBASEADDR                       0x0e
00006 #define REG_LR_FIFORXBASEADDR                       0x0f
00007 #define REG_LR_FIFORXCURRENTADDR /*REG_LR_RXDATAADDR*/  0x10
00008 #define REG_LR_IRQFLAGSMASK                         0x11
00009 #define REG_LR_IRQFLAGS                             0x12
00010 #define REG_LR_RXNBBYTES                            0x13
00011 #define REG_LR_RXHEADERCNTVALUE_MSB                 0x14
00012 #define REG_LR_RXHEADERCNTVALUE_LSB                 0x15
00013 #define REG_LR_RXPACKETCNTVALUE_MSB                 0x16
00014 #define REG_LR_RXPACKETCNTVALUE_LSB                 0x17
00015 #define REG_LR_MODEMSTAT                            0x18
00016 #define REG_LR_PKTSNRVALUE                          0x19
00017 #define REG_LR_PKTRSSIVALUE                         0x1a
00018 #define REG_LR_RSSIVALUE                            0x1b
00019 #define REG_LR_HOPCHANNEL                           0x1c
00020 #define REG_LR_MODEMCONFIG                          0x1d
00021 #define REG_LR_MODEMCONFIG2                         0x1e
00022 #define REG_LR_SYMBTIMEOUTLSB                       0x1f
00023 #define REG_LR_PREAMBLEMSB                          0x20
00024 #define REG_LR_PREAMBLELSB                          0x21
00025 #define REG_LR_PAYLOADLENGTH                        0x22 // and RX length for implicit
00026 #define REG_LR_RX_MAX_PAYLOADLENGTH                 0x23 // length limit for explicit mode
00027 #define REG_LR_HOPPERIOD                            0x24
00028 #define REG_LR_RXBYTEADDR /*REG_LR_RXDATAADDR*/     0x25
00029 #define REG_LR_MODEMCONFIG3                         0x26    // sx1272 REG_LR_PPM_CORRECTION_MSB
00030 #define REG_LR_PPM_CORRECTION_LSB                   0x27
00031 #define REG_LR_TEST28                               0x28  // est_freq_error
00032 #define REG_LR_TEST29                               0x29    // est_freq_error
00033 #define REG_LR_TEST2A                               0x2a    // est_freq_error
00034 #define REG_LR_TEST2B                               0x2b    // 
00035 #define REG_LR_WIDEBAND_RSSI                        0x2c 
00036 #define REG_LR_AGCH_TH                              0x2d    // agc_upper_th
00037 #define REG_LR_AGCL_TH                              0x2e    // agc_lower_th
00038 #define REG_LR_IFFRQH                               0x2f    // if_freq(12:8)
00039 #define REG_LR_IFFRQL                               0x30    // if_freq(7:0)
00040 #define REG_LR_TEST31                               0x31    // if_freq_auto, ...
00041 #define REG_LR_TEST32                               0x32    // 
00042 #define REG_LR_TEST33                               0x33    // invert IQ
00043 #define REG_LR_CAD_PEAK_TO_NOISE_RATIO              0x34
00044 #define REG_LR_CAD_MIN_PEAK                         0x35
00045 #define REG_LR_SX1276_AUTO_DRIFT                    0x36
00046 #define REG_LR_DETECTION_THRESHOLD                  0x37
00047 #define REG_LR_SYNC_BYTE                            0x39    // default 0x12 (value of 0x21 will isolate network)
00048 #define REG_LR_GAIN_DRIFT                           0x3a
00049 #define REG_LR_DRIFT_INVERT                         0x3b  
00050 
00051 typedef union {
00052     struct {    // sx127x register 0x12
00053         uint8_t CadDetected         : 1;    // 0
00054         uint8_t FhssChangeChannel   : 1;    // 1
00055         uint8_t CadDone             : 1;    // 2
00056         uint8_t TxDone              : 1;    // 3
00057         uint8_t ValidHeader         : 1;    // 4
00058         uint8_t PayloadCrcError     : 1;    // 5
00059         uint8_t RxDone              : 1;    // 6
00060         uint8_t RxTimeout           : 1;    // 7
00061     } bits;
00062     uint8_t octet;
00063 } RegIrqFlags_t;
00064 
00065 typedef union {
00066     struct {    // sx127x register 0x18
00067         uint8_t detect          : 1;    // 0
00068         uint8_t sync            : 1;    // 1
00069         uint8_t rx_ongoing      : 1;    // 2
00070         uint8_t header_valid    : 1;    // 3
00071         uint8_t clear           : 1;    // 4
00072         uint8_t RxCodingRate    : 3;    // 5,6,7
00073     } bits;
00074     uint8_t octet;
00075 } RegModemStatus_t;
00076 
00077 typedef union {
00078     struct {    // sx127x register 0x1c
00079         uint8_t FhssPresentChannel  : 6;    // 0,1,2,3,4,5
00080         uint8_t RxPayloadCrcOn      : 1;    // 6
00081         uint8_t PllTimeout          : 1;    // 7
00082     } bits;
00083     uint8_t octet;
00084 } RegHopChannel_t;
00085 
00086 typedef union {
00087     struct {    // sx1276 register 0x1d
00088         uint8_t ImplicitHeaderModeOn    : 1;    // 0
00089         uint8_t CodingRate              : 3;    // 1,2,3
00090         uint8_t Bw                      : 4;    // 4,5,6,7
00091     } sx1276bits;
00092     struct {    // sx1272 register 0x1d
00093         uint8_t LowDataRateOptimize     : 1;    // 0  ppm_offset: number of cyclic shifts possible to encode to symbol
00094         uint8_t RxPayloadCrcOn          : 1;    // 1
00095         uint8_t ImplicitHeaderModeOn    : 1;    // 2
00096         uint8_t CodingRate              : 3;    // 3,4,5
00097         uint8_t Bw                      : 2;    // 6,7
00098     } sx1272bits;
00099     uint8_t octet;
00100 } RegModemConfig_t;
00101 
00102 typedef union {
00103     struct {    // sx1276 register 0x1e
00104         uint8_t SymbTimeoutMsb          : 2;    // 0,1
00105         uint8_t RxPayloadCrcOn          : 1;    // 2
00106         uint8_t TxContinuousMode        : 1;    // 3
00107         uint8_t SpreadingFactor         : 4;    // 4,5,6,7
00108     } sx1276bits;
00109     struct {    // sx1272 register 0x1e
00110         uint8_t SymbTimeoutMsb          : 2;    // 0,1
00111         uint8_t AgcAutoOn               : 1;    // 2
00112         uint8_t TxContinuousMode        : 1;    // 3
00113         uint8_t SpreadingFactor         : 4;    // 4,5,6,7
00114     } sx1272bits;
00115     uint8_t octet;
00116 } RegModemConfig2_t;
00117 
00118 typedef union {
00119     struct {    // sx127x register 0x26
00120         uint8_t reserved    : 2;    // 0,1
00121         uint8_t AgcAutoOn   : 1;    // 2
00122         uint8_t LowDataRateOptimize  : 1;    // 3   ppm_offset, use when symbol duration exceeds 16ms
00123         uint8_t unused      : 4;    // 4,5,6,7 
00124     } sx1276bits;
00125     uint8_t octet;
00126     uint8_t sx1272_ppm_correction_msb;
00127 } RegModemConfig3_t;
00128 
00129 
00130 typedef union {
00131     struct {    // sx127x register 0x31
00132         uint8_t detect_trig_same_peaks_nb  : 3;    // 0,1,2
00133         uint8_t disable_pll_timeout        : 1;    // 3
00134         uint8_t tracking_intergral         : 2;    // 4,5
00135         uint8_t frame_sync_gain            : 1;    // 6
00136         uint8_t if_freq_auto               : 1;    // 7
00137     } bits;
00138     uint8_t octet;
00139 } RegTest31_t;
00140 
00141 typedef union {
00142     struct {    // sx127x register 0x33
00143         uint8_t chirp_invert_tx    : 1;    // 0  invert TX spreading sequence  (default=1)
00144         uint8_t chirp_invert_rx    : 1;    // 1  invert chip direction in RX mode  (default=1)
00145         uint8_t sync_detect_th     : 1;    // 2  require 6dB despread SNR during preamble
00146         uint8_t invert_coef_phase  : 1;    // 3  
00147         uint8_t invert_coef_amp    : 1;    // 4
00148         uint8_t quad_correction_en : 1;    // 5  enable IQ compensation
00149         uint8_t invert_i_q         : 1;    // 6  RX invert (default=0)
00150         uint8_t start_rambist      : 1;    // 7
00151     } bits;
00152     uint8_t octet;
00153 } RegTest33_t;
00154 
00155 typedef union {
00156     struct {    // sx1276 register 0x36
00157         uint8_t freq_to_time_drift_auto         : 1;    // 0  manual control of 0x3a register (1=auto)
00158         uint8_t sd_max_freq_deviation_auto      : 1;    // 1  manual control of 0x3b[3:1] (1=auto)
00159         uint8_t reserved                        : 6;    // 
00160     } bits;
00161     uint8_t octet;
00162 } RegAutoDrift_t;
00163 
00164 typedef union {
00165     struct {    // sx127x register 0x3a
00166         uint8_t freq_to_time_drift         : 6;    // 0,1,2,3,4,5  manual control of 0x3a register
00167         uint8_t preamble_timing_gain       : 1;    // 6,7
00168     } bits;
00169     uint8_t octet;
00170 } RegGainDrift_t;
00171 
00172 typedef union {
00173     struct {    // sx127x register 0x3b
00174         uint8_t coarse_sync                     : 1;    // 0  must be set to 1
00175         uint8_t fine_sync                       : 1;    // 1  must be clr to 0
00176         uint8_t invert_timing_error_per_symbol  : 1;    // 2  set to !invert_i_q
00177         uint8_t invert_freq_error               : 1;    // 3  
00178         uint8_t invert_delta_sampling           : 1;    // 4    must be set to 1
00179         uint8_t reserved                        : 1;    // 5    must be clr to 0
00180         uint8_t invert_fast_timing              : 1;    // 6 
00181         uint8_t invert_carry_in                 : 1;    // 7
00182     } bits;
00183     uint8_t octet;
00184 } RegDriftInvert_t;
00185 
00186 
00187 //class SX127x_lora : public SX127x
00188 class SX127x_lora {
00189     public:
00190         //SX127x_lora(PinName mosi, PinName miso, PinName sclk, PinName cs, PinName rst, PinName dio_0, PinName dio_1, PinName fem_ctx, PinName fem_cps);
00191         SX127x_lora(SX127x& r);
00192         
00193         ~SX127x_lora();
00194         
00195         /** changes from FSK mode to LoRa mdoe */
00196         void enable(void);
00197         
00198         /** fills radio FIFO with payload contents, prior to transmission
00199          * @param len count of bytes to put into FIFO
00200          * @note tx_buf[] should contain desired payload (to send) prior to calling
00201          */
00202         void write_fifo(uint8_t len);     
00203         
00204         /** transmit a packet
00205          * @param len size of packet
00206          * @note Limited to (lora fifo size 256)
00207          */
00208         void start_tx(uint8_t len);
00209         
00210         /** start continuous receive mode
00211          * @param mode RF_OPMODE_RECEIVER or RF_OPMODE_RECEIVER_SINGLE
00212          * @note the variable service_action needs to be monitored to indicate read_fifo() needs to be called to pull packet from FIFO.
00213          */
00214         void start_rx(chip_mode_e mode);
00215         
00216         /** Called by main program when indicated by service_action variable, to pull recevied packet from radio FIFO.
00217          * @returns count of bytes received
00218          * @note received packet in rx_buf[]
00219          */
00220         void read_fifo(uint8_t len);
00221         
00222         /** CodingRate: how much FEC to encoding onto packet */
00223         uint8_t getCodingRate(bool from_rx);    // false:transmitted, true:last recevied packet
00224         void setCodingRate(uint8_t cr);
00225         
00226         /** HeaderMode: explicit mode sents CodingRate and payload length, implicit mode requires assumption by receiver */
00227         bool getHeaderMode(void);
00228         void setHeaderMode(bool hm);
00229 
00230         /** bandwidth: SX1272 has three bandwidths. SX1276 adds more narrower bandwidths. */
00231         uint8_t getBw(void);
00232         void setBw(uint8_t bw);
00233         
00234         /** Set bandwidth in KHz *
00235          * @param khz lora bandwidth in KHz
00236          */        
00237         void setBw_KHz(int khz);
00238         
00239         /** spreading factor: trade-off between data rate and processing gain (link budget) */
00240         uint8_t getSf(void);
00241         void setSf(uint8_t sf);        
00242         
00243         /** enable CRC in transmitted packet */
00244         bool getRxPayloadCrcOn(void);
00245         void setRxPayloadCrcOn(bool);
00246         
00247         bool getAgcAutoOn(void);
00248         void setAgcAutoOn(bool);
00249         
00250         int get_pkt_rssi(void);
00251         int get_current_rssi(void);
00252         
00253         /** retrieve symbol duration from bandwidth and spreading factor
00254          * @returns symbol duration in milliseconds
00255          */        
00256         float get_symbol_period(void);
00257         
00258         service_action_e service(void); // (SLIH) ISR bottom half 
00259         
00260         bool poll_vh;
00261         
00262         void set_nb_trig_peaks(int);
00263         
00264         /** get receiver difference in RF frequency 
00265           * @returns hertz
00266           * @note if receiver is lower in frequency than transmitter, a negative Hz will be returned
00267           */
00268         int get_freq_error_Hz(void);
00269         
00270         
00271         /** invert transmitted spectrum */
00272         void invert_tx(bool);
00273         
00274         /** invert spectrum on receiver */
00275         void invert_rx(bool);
00276         
00277         RegIrqFlags_t       RegIrqFlags;            // 0x12
00278         uint8_t             RegRxNbBytes;           // 0x13
00279         RegModemStatus_t    RegModemStatus;         // 0x18
00280         int8_t              RegPktSnrValue;         // 0x19  signed, s/n can be negative
00281         uint8_t             RegPktRssiValue;        // 0x1a
00282         RegHopChannel_t     RegHopChannel;          // 0x1c
00283         RegModemConfig_t    RegModemConfig;         // 0x1d
00284         RegModemConfig2_t   RegModemConfig2;        // 0x1e
00285         uint16_t            RegPreamble;            // 0x20->0x21
00286         uint8_t             RegPayloadLength;       // 0x22
00287         uint8_t             RegRxMaxPayloadLength;  // 0x23
00288         uint8_t             RegHopPeriod;           // 0x24
00289         RegModemConfig3_t   RegModemConfig3;        // 0x26
00290         RegTest31_t         RegTest31;              // 0x31
00291         RegTest33_t         RegTest33;              // 0x33
00292         RegAutoDrift_t      RegAutoDrift;           // 0x36  sx1276 only
00293         RegGainDrift_t      RegGainDrift;           // 0x3a
00294         RegDriftInvert_t    RegDriftInvert;         // 0x3b
00295         
00296         
00297         SX127x& m_xcvr;
00298 
00299     private:
00300                                                                  
00301 };