Matt Lloyd
Example of UART-DMA transfers taken form the npx cmsis driver libary
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lpc17xx_uart.c
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00001 /***********************************************************************//** 00002 * @file lpc17xx_uart.c 00003 * @brief Contains all functions support for UART firmware library on LPC17xx 00004 * @version 3.0 00005 * @date 18. June. 2010 00006 * @author NXP MCU SW Application Team 00007 ************************************************************************** 00008 * Software that is described herein is for illustrative purposes only 00009 * which provides customers with programming information regarding the 00010 * products. This software is supplied "AS IS" without any warranties. 00011 * NXP Semiconductors assumes no responsibility or liability for the 00012 * use of the software, conveys no license or title under any patent, 00013 * copyright, or mask work right to the product. NXP Semiconductors 00014 * reserves the right to make changes in the software without 00015 * notification. NXP Semiconductors also make no representation or 00016 * warranty that such application will be suitable for the specified 00017 * use without further testing or modification. 00018 **********************************************************************/ 00019 00020 /* Peripheral group ----------------------------------------------------------- */ 00021 /** @addtogroup UART 00022 * @{ 00023 */ 00024 00025 /* Includes ------------------------------------------------------------------- */ 00026 #include "lpc17xx_uart.h" 00027 #include "lpc17xx_clkpwr.h" 00028 00029 /* If this source file built with example, the LPC17xx FW library configuration 00030 * file in each example directory ("lpc17xx_libcfg.h") must be included, 00031 * otherwise the default FW library configuration file must be included instead 00032 */ 00033 #ifdef __BUILD_WITH_EXAMPLE__ 00034 #include "lpc17xx_libcfg.h" 00035 #else 00036 #include "lpc17xx_libcfg_default.h" 00037 #endif /* __BUILD_WITH_EXAMPLE__ */ 00038 00039 00040 #ifdef _UART 00041 00042 /* Private Functions ---------------------------------------------------------- */ 00043 00044 static Status uart_set_divisors(LPC_UART_TypeDef *UARTx, uint32_t baudrate); 00045 00046 00047 /*********************************************************************//** 00048 * @brief Determines best dividers to get a target clock rate 00049 * @param[in] UARTx Pointer to selected UART peripheral, should be: 00050 * - LPC_UART0: UART0 peripheral 00051 * - LPC_UART1: UART1 peripheral 00052 * - LPC_UART2: UART2 peripheral 00053 * - LPC_UART3: UART3 peripheral 00054 * @param[in] baudrate Desired UART baud rate. 00055 * @return Error status, could be: 00056 * - SUCCESS 00057 * - ERROR 00058 **********************************************************************/ 00059 static Status uart_set_divisors(LPC_UART_TypeDef *UARTx, uint32_t baudrate) 00060 { 00061 Status errorStatus = ERROR; 00062 00063 uint32_t uClk = 0; 00064 uint32_t calcBaudrate = 0; 00065 uint32_t temp = 0; 00066 00067 uint32_t mulFracDiv, dividerAddFracDiv; 00068 uint32_t diviser = 0 ; 00069 uint32_t mulFracDivOptimal = 1; 00070 uint32_t dividerAddOptimal = 0; 00071 uint32_t diviserOptimal = 0; 00072 00073 uint32_t relativeError = 0; 00074 uint32_t relativeOptimalError = 100000; 00075 00076 /* get UART block clock */ 00077 if (UARTx == (LPC_UART_TypeDef *)LPC_UART0) 00078 { 00079 uClk = CLKPWR_GetPCLK (CLKPWR_PCLKSEL_UART0); 00080 } 00081 else if (UARTx == (LPC_UART_TypeDef *)LPC_UART1) 00082 { 00083 uClk = CLKPWR_GetPCLK (CLKPWR_PCLKSEL_UART1); 00084 } 00085 else if (UARTx == LPC_UART2) 00086 { 00087 uClk = CLKPWR_GetPCLK (CLKPWR_PCLKSEL_UART2); 00088 } 00089 else if (UARTx == LPC_UART3) 00090 { 00091 uClk = CLKPWR_GetPCLK (CLKPWR_PCLKSEL_UART3); 00092 } 00093 00094 00095 uClk = uClk >> 4; /* div by 16 */ 00096 /* In the Uart IP block, baud rate is calculated using FDR and DLL-DLM registers 00097 * The formula is : 00098 * BaudRate= uClk * (mulFracDiv/(mulFracDiv+dividerAddFracDiv) / (16 * (DLL) 00099 * It involves floating point calculations. That's the reason the formulae are adjusted with 00100 * Multiply and divide method.*/ 00101 /* The value of mulFracDiv and dividerAddFracDiv should comply to the following expressions: 00102 * 0 < mulFracDiv <= 15, 0 <= dividerAddFracDiv <= 15 */ 00103 for (mulFracDiv = 1 ; mulFracDiv <= 15 ;mulFracDiv++) 00104 { 00105 for (dividerAddFracDiv = 0 ; dividerAddFracDiv <= 15 ;dividerAddFracDiv++) 00106 { 00107 temp = (mulFracDiv * uClk) / ((mulFracDiv + dividerAddFracDiv)); 00108 00109 diviser = temp / baudrate; 00110 if ((temp % baudrate) > (baudrate / 2)) 00111 diviser++; 00112 00113 if (diviser > 2 && diviser < 65536) 00114 { 00115 calcBaudrate = temp / diviser; 00116 00117 if (calcBaudrate <= baudrate) 00118 relativeError = baudrate - calcBaudrate; 00119 else 00120 relativeError = calcBaudrate - baudrate; 00121 00122 if ((relativeError < relativeOptimalError)) 00123 { 00124 mulFracDivOptimal = mulFracDiv ; 00125 dividerAddOptimal = dividerAddFracDiv; 00126 diviserOptimal = diviser; 00127 relativeOptimalError = relativeError; 00128 if (relativeError == 0) 00129 break; 00130 } 00131 } /* End of if */ 00132 } /* end of inner for loop */ 00133 if (relativeError == 0) 00134 break; 00135 } /* end of outer for loop */ 00136 00137 if (relativeOptimalError < ((baudrate * UART_ACCEPTED_BAUDRATE_ERROR)/100)) 00138 { 00139 if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) 00140 { 00141 ((LPC_UART1_TypeDef *)UARTx)->LCR |= UART_LCR_DLAB_EN; 00142 ((LPC_UART1_TypeDef *)UARTx)->/*DLIER.*/DLM = UART_LOAD_DLM(diviserOptimal); 00143 ((LPC_UART1_TypeDef *)UARTx)->/*RBTHDLR.*/DLL = UART_LOAD_DLL(diviserOptimal); 00144 /* Then reset DLAB bit */ 00145 ((LPC_UART1_TypeDef *)UARTx)->LCR &= (~UART_LCR_DLAB_EN) & UART_LCR_BITMASK; 00146 ((LPC_UART1_TypeDef *)UARTx)->FDR = (UART_FDR_MULVAL(mulFracDivOptimal) \ 00147 | UART_FDR_DIVADDVAL(dividerAddOptimal)) & UART_FDR_BITMASK; 00148 } 00149 else 00150 { 00151 UARTx->LCR |= UART_LCR_DLAB_EN; 00152 UARTx->/*DLIER.*/DLM = UART_LOAD_DLM(diviserOptimal); 00153 UARTx->/*RBTHDLR.*/DLL = UART_LOAD_DLL(diviserOptimal); 00154 /* Then reset DLAB bit */ 00155 UARTx->LCR &= (~UART_LCR_DLAB_EN) & UART_LCR_BITMASK; 00156 UARTx->FDR = (UART_FDR_MULVAL(mulFracDivOptimal) \ 00157 | UART_FDR_DIVADDVAL(dividerAddOptimal)) & UART_FDR_BITMASK; 00158 } 00159 errorStatus = SUCCESS; 00160 } 00161 00162 return errorStatus; 00163 } 00164 00165 /* End of Private Functions ---------------------------------------------------- */ 00166 00167 00168 /* Public Functions ----------------------------------------------------------- */ 00169 /** @addtogroup UART_Public_Functions 00170 * @{ 00171 */ 00172 /* UART Init/DeInit functions -------------------------------------------------*/ 00173 /********************************************************************//** 00174 * @brief Initializes the UARTx peripheral according to the specified 00175 * parameters in the UART_ConfigStruct. 00176 * @param[in] UARTx UART peripheral selected, should be: 00177 * - LPC_UART0: UART0 peripheral 00178 * - LPC_UART1: UART1 peripheral 00179 * - LPC_UART2: UART2 peripheral 00180 * - LPC_UART3: UART3 peripheral 00181 * @param[in] UART_ConfigStruct Pointer to a UART_CFG_Type structure 00182 * that contains the configuration information for the 00183 * specified UART peripheral. 00184 * @return None 00185 *********************************************************************/ 00186 void UART_Init(LPC_UART_TypeDef *UARTx, UART_CFG_Type *UART_ConfigStruct) 00187 { 00188 uint32_t tmp; 00189 00190 // For debug mode 00191 CHECK_PARAM(PARAM_UARTx(UARTx)); 00192 CHECK_PARAM(PARAM_UART_DATABIT(UART_ConfigStruct->Databits)); 00193 CHECK_PARAM(PARAM_UART_STOPBIT(UART_ConfigStruct->Stopbits)); 00194 CHECK_PARAM(PARAM_UART_PARITY(UART_ConfigStruct->Parity)); 00195 00196 #ifdef _UART0 00197 if(UARTx == (LPC_UART_TypeDef *)LPC_UART0) 00198 { 00199 /* Set up clock and power for UART module */ 00200 CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART0, ENABLE); 00201 } 00202 #endif 00203 00204 #ifdef _UART1 00205 if(((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) 00206 { 00207 /* Set up clock and power for UART module */ 00208 CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART1, ENABLE); 00209 } 00210 #endif 00211 00212 #ifdef _UART2 00213 if(UARTx == LPC_UART2) 00214 { 00215 /* Set up clock and power for UART module */ 00216 CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART2, ENABLE); 00217 } 00218 #endif 00219 00220 #ifdef _UART3 00221 if(UARTx == LPC_UART3) 00222 { 00223 /* Set up clock and power for UART module */ 00224 CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART3, ENABLE); 00225 } 00226 #endif 00227 00228 if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) 00229 { 00230 /* FIFOs are empty */ 00231 ((LPC_UART1_TypeDef *)UARTx)->/*IIFCR.*/FCR = ( UART_FCR_FIFO_EN \ 00232 | UART_FCR_RX_RS | UART_FCR_TX_RS); 00233 // Disable FIFO 00234 ((LPC_UART1_TypeDef *)UARTx)->/*IIFCR.*/FCR = 0; 00235 00236 // Dummy reading 00237 while (((LPC_UART1_TypeDef *)UARTx)->LSR & UART_LSR_RDR) 00238 { 00239 tmp = ((LPC_UART1_TypeDef *)UARTx)->/*RBTHDLR.*/RBR; 00240 } 00241 00242 ((LPC_UART1_TypeDef *)UARTx)->TER = UART_TER_TXEN; 00243 // Wait for current transmit complete 00244 while (!(((LPC_UART1_TypeDef *)UARTx)->LSR & UART_LSR_THRE)); 00245 // Disable Tx 00246 ((LPC_UART1_TypeDef *)UARTx)->TER = 0; 00247 00248 // Disable interrupt 00249 ((LPC_UART1_TypeDef *)UARTx)->/*DLIER.*/IER = 0; 00250 // Set LCR to default state 00251 ((LPC_UART1_TypeDef *)UARTx)->LCR = 0; 00252 // Set ACR to default state 00253 ((LPC_UART1_TypeDef *)UARTx)->ACR = 0; 00254 // Set Modem Control to default state 00255 ((LPC_UART1_TypeDef *)UARTx)->MCR = 0; 00256 // Set RS485 control to default state 00257 ((LPC_UART1_TypeDef *)UARTx)->RS485CTRL = 0; 00258 // Set RS485 delay timer to default state 00259 ((LPC_UART1_TypeDef *)UARTx)->RS485DLY = 0; 00260 // Set RS485 addr match to default state 00261 ((LPC_UART1_TypeDef *)UARTx)->ADRMATCH = 0; 00262 //Dummy Reading to Clear Status 00263 tmp = ((LPC_UART1_TypeDef *)UARTx)->MSR; 00264 tmp = ((LPC_UART1_TypeDef *)UARTx)->LSR; 00265 } 00266 else 00267 { 00268 /* FIFOs are empty */ 00269 UARTx->/*IIFCR.*/FCR = ( UART_FCR_FIFO_EN | UART_FCR_RX_RS | UART_FCR_TX_RS); 00270 // Disable FIFO 00271 UARTx->/*IIFCR.*/FCR = 0; 00272 00273 // Dummy reading 00274 while (UARTx->LSR & UART_LSR_RDR) 00275 { 00276 tmp = UARTx->/*RBTHDLR.*/RBR; 00277 } 00278 00279 UARTx->TER = UART_TER_TXEN; 00280 // Wait for current transmit complete 00281 while (!(UARTx->LSR & UART_LSR_THRE)); 00282 // Disable Tx 00283 UARTx->TER = 0; 00284 00285 // Disable interrupt 00286 UARTx->/*DLIER.*/IER = 0; 00287 // Set LCR to default state 00288 UARTx->LCR = 0; 00289 // Set ACR to default state 00290 UARTx->ACR = 0; 00291 // Dummy reading 00292 tmp = UARTx->LSR; 00293 } 00294 00295 if (UARTx == LPC_UART3) 00296 { 00297 // Set IrDA to default state 00298 UARTx->ICR = 0; 00299 } 00300 00301 // Set Line Control register ---------------------------- 00302 00303 uart_set_divisors(UARTx, (UART_ConfigStruct->Baud_rate)); 00304 00305 if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) 00306 { 00307 tmp = (((LPC_UART1_TypeDef *)UARTx)->LCR & (UART_LCR_DLAB_EN | UART_LCR_BREAK_EN)) \ 00308 & UART_LCR_BITMASK; 00309 } 00310 else 00311 { 00312 tmp = (UARTx->LCR & (UART_LCR_DLAB_EN | UART_LCR_BREAK_EN)) & UART_LCR_BITMASK; 00313 } 00314 00315 switch (UART_ConfigStruct->Databits){ 00316 case UART_DATABIT_5 : 00317 tmp |= UART_LCR_WLEN5; 00318 break; 00319 case UART_DATABIT_6 : 00320 tmp |= UART_LCR_WLEN6; 00321 break; 00322 case UART_DATABIT_7 : 00323 tmp |= UART_LCR_WLEN7; 00324 break; 00325 case UART_DATABIT_8 : 00326 default: 00327 tmp |= UART_LCR_WLEN8; 00328 break; 00329 } 00330 00331 if (UART_ConfigStruct->Parity == UART_PARITY_NONE ) 00332 { 00333 // Do nothing... 00334 } 00335 else 00336 { 00337 tmp |= UART_LCR_PARITY_EN; 00338 switch (UART_ConfigStruct->Parity) 00339 { 00340 case UART_PARITY_ODD : 00341 tmp |= UART_LCR_PARITY_ODD; 00342 break; 00343 00344 case UART_PARITY_EVEN : 00345 tmp |= UART_LCR_PARITY_EVEN; 00346 break; 00347 00348 case UART_PARITY_SP_1 : 00349 tmp |= UART_LCR_PARITY_F_1; 00350 break; 00351 00352 case UART_PARITY_SP_0 : 00353 tmp |= UART_LCR_PARITY_F_0; 00354 break; 00355 default: 00356 break; 00357 } 00358 } 00359 00360 switch (UART_ConfigStruct->Stopbits){ 00361 case UART_STOPBIT_2 : 00362 tmp |= UART_LCR_STOPBIT_SEL; 00363 break; 00364 case UART_STOPBIT_1 : 00365 default: 00366 // Do no thing 00367 break; 00368 } 00369 00370 00371 // Write back to LCR, configure FIFO and Disable Tx 00372 if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) 00373 { 00374 ((LPC_UART1_TypeDef *)UARTx)->LCR = (uint8_t)(tmp & UART_LCR_BITMASK); 00375 } 00376 else 00377 { 00378 UARTx->LCR = (uint8_t)(tmp & UART_LCR_BITMASK); 00379 } 00380 } 00381 00382 /*********************************************************************//** 00383 * @brief De-initializes the UARTx peripheral registers to their 00384 * default reset values. 00385 * @param[in] UARTx UART peripheral selected, should be: 00386 * - LPC_UART0: UART0 peripheral 00387 * - LPC_UART1: UART1 peripheral 00388 * - LPC_UART2: UART2 peripheral 00389 * - LPC_UART3: UART3 peripheral 00390 * @return None 00391 **********************************************************************/ 00392 void UART_DeInit(LPC_UART_TypeDef* UARTx) 00393 { 00394 // For debug mode 00395 CHECK_PARAM(PARAM_UARTx(UARTx)); 00396 00397 UART_TxCmd(UARTx, DISABLE); 00398 00399 #ifdef _UART0 00400 if (UARTx == (LPC_UART_TypeDef *)LPC_UART0) 00401 { 00402 /* Set up clock and power for UART module */ 00403 CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART0, DISABLE); 00404 } 00405 #endif 00406 00407 #ifdef _UART1 00408 if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) 00409 { 00410 /* Set up clock and power for UART module */ 00411 CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART1, DISABLE); 00412 } 00413 #endif 00414 00415 #ifdef _UART2 00416 if (UARTx == LPC_UART2) 00417 { 00418 /* Set up clock and power for UART module */ 00419 CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART2, DISABLE); 00420 } 00421 #endif 00422 00423 #ifdef _UART3 00424 if (UARTx == LPC_UART3) 00425 { 00426 /* Set up clock and power for UART module */ 00427 CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART3, DISABLE); 00428 } 00429 #endif 00430 } 00431 00432 /*****************************************************************************//** 00433 * @brief Fills each UART_InitStruct member with its default value: 00434 * - 9600 bps 00435 * - 8-bit data 00436 * - 1 Stopbit 00437 * - None Parity 00438 * @param[in] UART_InitStruct Pointer to a UART_CFG_Type structure 00439 * which will be initialized. 00440 * @return None 00441 *******************************************************************************/ 00442 void UART_ConfigStructInit(UART_CFG_Type *UART_InitStruct) 00443 { 00444 UART_InitStruct->Baud_rate = 9600; 00445 UART_InitStruct->Databits = UART_DATABIT_8 ; 00446 UART_InitStruct->Parity = UART_PARITY_NONE ; 00447 UART_InitStruct->Stopbits = UART_STOPBIT_1 ; 00448 } 00449 00450 /* UART Send/Recieve functions -------------------------------------------------*/ 00451 /*********************************************************************//** 00452 * @brief Transmit a single data through UART peripheral 00453 * @param[in] UARTx UART peripheral selected, should be: 00454 * - LPC_UART0: UART0 peripheral 00455 * - LPC_UART1: UART1 peripheral 00456 * - LPC_UART2: UART2 peripheral 00457 * - LPC_UART3: UART3 peripheral 00458 * @param[in] Data Data to transmit (must be 8-bit long) 00459 * @return None 00460 **********************************************************************/ 00461 void UART_SendByte(LPC_UART_TypeDef* UARTx, uint8_t Data) 00462 { 00463 CHECK_PARAM(PARAM_UARTx(UARTx)); 00464 00465 if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) 00466 { 00467 ((LPC_UART1_TypeDef *)UARTx)->/*RBTHDLR.*/THR = Data & UART_THR_MASKBIT; 00468 } 00469 else 00470 { 00471 UARTx->/*RBTHDLR.*/THR = Data & UART_THR_MASKBIT; 00472 } 00473 00474 } 00475 00476 00477 /*********************************************************************//** 00478 * @brief Receive a single data from UART peripheral 00479 * @param[in] UARTx UART peripheral selected, should be: 00480 * - LPC_UART0: UART0 peripheral 00481 * - LPC_UART1: UART1 peripheral 00482 * - LPC_UART2: UART2 peripheral 00483 * - LPC_UART3: UART3 peripheral 00484 * @return Data received 00485 **********************************************************************/ 00486 uint8_t UART_ReceiveByte(LPC_UART_TypeDef* UARTx) 00487 { 00488 CHECK_PARAM(PARAM_UARTx(UARTx)); 00489 00490 if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) 00491 { 00492 return (((LPC_UART1_TypeDef *)UARTx)->/*RBTHDLR.*/RBR & UART_RBR_MASKBIT); 00493 } 00494 else 00495 { 00496 return (UARTx->/*RBTHDLR.*/RBR & UART_RBR_MASKBIT); 00497 } 00498 } 00499 00500 /*********************************************************************//** 00501 * @brief Send a block of data via UART peripheral 00502 * @param[in] UARTx Selected UART peripheral used to send data, should be: 00503 * - LPC_UART0: UART0 peripheral 00504 * - LPC_UART1: UART1 peripheral 00505 * - LPC_UART2: UART2 peripheral 00506 * - LPC_UART3: UART3 peripheral 00507 * @param[in] txbuf Pointer to Transmit buffer 00508 * @param[in] buflen Length of Transmit buffer 00509 * @param[in] flag Flag used in UART transfer, should be 00510 * NONE_BLOCKING or BLOCKING 00511 * @return Number of bytes sent. 00512 * 00513 * Note: when using UART in BLOCKING mode, a time-out condition is used 00514 * via defined symbol UART_BLOCKING_TIMEOUT. 00515 **********************************************************************/ 00516 uint32_t UART_Send(LPC_UART_TypeDef *UARTx, uint8_t *txbuf, 00517 uint32_t buflen, TRANSFER_BLOCK_Type flag) 00518 { 00519 uint32_t bToSend, bSent, timeOut, fifo_cnt; 00520 uint8_t *pChar = txbuf; 00521 00522 bToSend = buflen; 00523 00524 // blocking mode 00525 if (flag == BLOCKING) { 00526 bSent = 0; 00527 while (bToSend){ 00528 timeOut = UART_BLOCKING_TIMEOUT; 00529 // Wait for THR empty with timeout 00530 while (!(UARTx->LSR & UART_LSR_THRE)) { 00531 if (timeOut == 0) break; 00532 timeOut--; 00533 } 00534 // Time out! 00535 if(timeOut == 0) break; 00536 fifo_cnt = UART_TX_FIFO_SIZE; 00537 while (fifo_cnt && bToSend){ 00538 UART_SendByte(UARTx, (*pChar++)); 00539 fifo_cnt--; 00540 bToSend--; 00541 bSent++; 00542 } 00543 } 00544 } 00545 // None blocking mode 00546 else { 00547 bSent = 0; 00548 while (bToSend) { 00549 if (!(UARTx->LSR & UART_LSR_THRE)){ 00550 break; 00551 } 00552 fifo_cnt = UART_TX_FIFO_SIZE; 00553 while (fifo_cnt && bToSend) { 00554 UART_SendByte(UARTx, (*pChar++)); 00555 bToSend--; 00556 fifo_cnt--; 00557 bSent++; 00558 } 00559 } 00560 } 00561 return bSent; 00562 } 00563 00564 /*********************************************************************//** 00565 * @brief Receive a block of data via UART peripheral 00566 * @param[in] UARTx Selected UART peripheral used to send data, 00567 * should be: 00568 * - LPC_UART0: UART0 peripheral 00569 * - LPC_UART1: UART1 peripheral 00570 * - LPC_UART2: UART2 peripheral 00571 * - LPC_UART3: UART3 peripheral 00572 * @param[out] rxbuf Pointer to Received buffer 00573 * @param[in] buflen Length of Received buffer 00574 * @param[in] flag Flag mode, should be NONE_BLOCKING or BLOCKING 00575 00576 * @return Number of bytes received 00577 * 00578 * Note: when using UART in BLOCKING mode, a time-out condition is used 00579 * via defined symbol UART_BLOCKING_TIMEOUT. 00580 **********************************************************************/ 00581 uint32_t UART_Receive(LPC_UART_TypeDef *UARTx, uint8_t *rxbuf, \ 00582 uint32_t buflen, TRANSFER_BLOCK_Type flag) 00583 { 00584 uint32_t bToRecv, bRecv, timeOut; 00585 uint8_t *pChar = rxbuf; 00586 00587 bToRecv = buflen; 00588 00589 // Blocking mode 00590 if (flag == BLOCKING) { 00591 bRecv = 0; 00592 while (bToRecv){ 00593 timeOut = UART_BLOCKING_TIMEOUT; 00594 while (!(UARTx->LSR & UART_LSR_RDR)){ 00595 if (timeOut == 0) break; 00596 timeOut--; 00597 } 00598 // Time out! 00599 if(timeOut == 0) break; 00600 // Get data from the buffer 00601 (*pChar++) = UART_ReceiveByte(UARTx); 00602 bToRecv--; 00603 bRecv++; 00604 } 00605 } 00606 // None blocking mode 00607 else { 00608 bRecv = 0; 00609 while (bToRecv) { 00610 if (!(UARTx->LSR & UART_LSR_RDR)) { 00611 break; 00612 } else { 00613 (*pChar++) = UART_ReceiveByte(UARTx); 00614 bRecv++; 00615 bToRecv--; 00616 } 00617 } 00618 } 00619 return bRecv; 00620 } 00621 00622 /*********************************************************************//** 00623 * @brief Force BREAK character on UART line, output pin UARTx TXD is 00624 forced to logic 0. 00625 * @param[in] UARTx UART peripheral selected, should be: 00626 * - LPC_UART0: UART0 peripheral 00627 * - LPC_UART1: UART1 peripheral 00628 * - LPC_UART2: UART2 peripheral 00629 * - LPC_UART3: UART3 peripheral 00630 * @return None 00631 **********************************************************************/ 00632 void UART_ForceBreak(LPC_UART_TypeDef* UARTx) 00633 { 00634 CHECK_PARAM(PARAM_UARTx(UARTx)); 00635 00636 if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) 00637 { 00638 ((LPC_UART1_TypeDef *)UARTx)->LCR |= UART_LCR_BREAK_EN; 00639 } 00640 else 00641 { 00642 UARTx->LCR |= UART_LCR_BREAK_EN; 00643 } 00644 } 00645 00646 00647 /********************************************************************//** 00648 * @brief Enable or disable specified UART interrupt. 00649 * @param[in] UARTx UART peripheral selected, should be 00650 * - LPC_UART0: UART0 peripheral 00651 * - LPC_UART1: UART1 peripheral 00652 * - LPC_UART2: UART2 peripheral 00653 * - LPC_UART3: UART3 peripheral 00654 * @param[in] UARTIntCfg Specifies the interrupt flag, 00655 * should be one of the following: 00656 - UART_INTCFG_RBR : RBR Interrupt enable 00657 - UART_INTCFG_THRE : THR Interrupt enable 00658 - UART_INTCFG_RLS : RX line status interrupt enable 00659 - UART1_INTCFG_MS : Modem status interrupt enable (UART1 only) 00660 - UART1_INTCFG_CTS : CTS1 signal transition interrupt enable (UART1 only) 00661 - UART_INTCFG_ABEO : Enables the end of auto-baud interrupt 00662 - UART_INTCFG_ABTO : Enables the auto-baud time-out interrupt 00663 * @param[in] NewState New state of specified UART interrupt type, 00664 * should be: 00665 * - ENALBE: Enable this UART interrupt type. 00666 * - DISALBE: Disable this UART interrupt type. 00667 * @return None 00668 *********************************************************************/ 00669 void UART_IntConfig(LPC_UART_TypeDef *UARTx, UART_INT_Type UARTIntCfg, FunctionalState NewState) 00670 { 00671 uint32_t tmp = 0; 00672 00673 CHECK_PARAM(PARAM_UARTx(UARTx)); 00674 CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState)); 00675 00676 switch(UARTIntCfg){ 00677 case UART_INTCFG_RBR : 00678 tmp = UART_IER_RBRINT_EN; 00679 break; 00680 case UART_INTCFG_THRE : 00681 tmp = UART_IER_THREINT_EN; 00682 break; 00683 case UART_INTCFG_RLS : 00684 tmp = UART_IER_RLSINT_EN; 00685 break; 00686 case UART1_INTCFG_MS : 00687 tmp = UART1_IER_MSINT_EN; 00688 break; 00689 case UART1_INTCFG_CTS : 00690 tmp = UART1_IER_CTSINT_EN; 00691 break; 00692 case UART_INTCFG_ABEO : 00693 tmp = UART_IER_ABEOINT_EN; 00694 break; 00695 case UART_INTCFG_ABTO : 00696 tmp = UART_IER_ABTOINT_EN; 00697 break; 00698 } 00699 00700 if ((LPC_UART1_TypeDef *) UARTx == LPC_UART1) 00701 { 00702 CHECK_PARAM((PARAM_UART_INTCFG(UARTIntCfg)) || (PARAM_UART1_INTCFG(UARTIntCfg))); 00703 } 00704 else 00705 { 00706 CHECK_PARAM(PARAM_UART_INTCFG(UARTIntCfg)); 00707 } 00708 00709 if (NewState == ENABLE) 00710 { 00711 if ((LPC_UART1_TypeDef *) UARTx == LPC_UART1) 00712 { 00713 ((LPC_UART1_TypeDef *)UARTx)->/*DLIER.*/IER |= tmp; 00714 } 00715 else 00716 { 00717 UARTx->/*DLIER.*/IER |= tmp; 00718 } 00719 } 00720 else 00721 { 00722 if ((LPC_UART1_TypeDef *) UARTx == LPC_UART1) 00723 { 00724 ((LPC_UART1_TypeDef *)UARTx)->/*DLIER.*/IER &= (~tmp) & UART1_IER_BITMASK; 00725 } 00726 else 00727 { 00728 UARTx->/*DLIER.*/IER &= (~tmp) & UART_IER_BITMASK; 00729 } 00730 } 00731 } 00732 00733 00734 /********************************************************************//** 00735 * @brief Get current value of Line Status register in UART peripheral. 00736 * @param[in] UARTx UART peripheral selected, should be: 00737 * - LPC_UART0: UART0 peripheral 00738 * - LPC_UART1: UART1 peripheral 00739 * - LPC_UART2: UART2 peripheral 00740 * - LPC_UART3: UART3 peripheral 00741 * @return Current value of Line Status register in UART peripheral. 00742 * Note: The return value of this function must be ANDed with each member in 00743 * UART_LS_Type enumeration to determine current flag status 00744 * corresponding to each Line status type. Because some flags in 00745 * Line Status register will be cleared after reading, the next reading 00746 * Line Status register could not be correct. So this function used to 00747 * read Line status register in one time only, then the return value 00748 * used to check all flags. 00749 *********************************************************************/ 00750 uint8_t UART_GetLineStatus(LPC_UART_TypeDef* UARTx) 00751 { 00752 CHECK_PARAM(PARAM_UARTx(UARTx)); 00753 00754 if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) 00755 { 00756 return ((((LPC_UART1_TypeDef *)LPC_UART1)->LSR) & UART_LSR_BITMASK); 00757 } 00758 else 00759 { 00760 return ((UARTx->LSR) & UART_LSR_BITMASK); 00761 } 00762 } 00763 00764 /********************************************************************//** 00765 * @brief Get Interrupt Identification value 00766 * @param[in] UARTx UART peripheral selected, should be: 00767 * - LPC_UART0: UART0 peripheral 00768 * - LPC_UART1: UART1 peripheral 00769 * - LPC_UART2: UART2 peripheral 00770 * - LPC_UART3: UART3 peripheral 00771 * @return Current value of UART UIIR register in UART peripheral. 00772 *********************************************************************/ 00773 uint32_t UART_GetIntId(LPC_UART_TypeDef* UARTx) 00774 { 00775 CHECK_PARAM(PARAM_UARTx(UARTx)); 00776 return (UARTx->IIR & 0x03CF); 00777 } 00778 00779 /*********************************************************************//** 00780 * @brief Check whether if UART is busy or not 00781 * @param[in] UARTx UART peripheral selected, should be: 00782 * - LPC_UART0: UART0 peripheral 00783 * - LPC_UART1: UART1 peripheral 00784 * - LPC_UART2: UART2 peripheral 00785 * - LPC_UART3: UART3 peripheral 00786 * @return RESET if UART is not busy, otherwise return SET. 00787 **********************************************************************/ 00788 FlagStatus UART_CheckBusy(LPC_UART_TypeDef *UARTx) 00789 { 00790 if (UARTx->LSR & UART_LSR_TEMT){ 00791 return RESET; 00792 } else { 00793 return SET; 00794 } 00795 } 00796 00797 00798 /*********************************************************************//** 00799 * @brief Configure FIFO function on selected UART peripheral 00800 * @param[in] UARTx UART peripheral selected, should be: 00801 * - LPC_UART0: UART0 peripheral 00802 * - LPC_UART1: UART1 peripheral 00803 * - LPC_UART2: UART2 peripheral 00804 * - LPC_UART3: UART3 peripheral 00805 * @param[in] FIFOCfg Pointer to a UART_FIFO_CFG_Type Structure that 00806 * contains specified information about FIFO configuration 00807 * @return none 00808 **********************************************************************/ 00809 void UART_FIFOConfig(LPC_UART_TypeDef *UARTx, UART_FIFO_CFG_Type *FIFOCfg) 00810 { 00811 uint8_t tmp = 0; 00812 00813 CHECK_PARAM(PARAM_UARTx(UARTx)); 00814 CHECK_PARAM(PARAM_UART_FIFO_LEVEL(FIFOCfg->FIFO_Level)); 00815 CHECK_PARAM(PARAM_FUNCTIONALSTATE(FIFOCfg->FIFO_DMAMode)); 00816 CHECK_PARAM(PARAM_FUNCTIONALSTATE(FIFOCfg->FIFO_ResetRxBuf)); 00817 CHECK_PARAM(PARAM_FUNCTIONALSTATE(FIFOCfg->FIFO_ResetTxBuf)); 00818 00819 tmp |= UART_FCR_FIFO_EN; 00820 switch (FIFOCfg->FIFO_Level){ 00821 case UART_FIFO_TRGLEV0 : 00822 tmp |= UART_FCR_TRG_LEV0; 00823 break; 00824 case UART_FIFO_TRGLEV1 : 00825 tmp |= UART_FCR_TRG_LEV1; 00826 break; 00827 case UART_FIFO_TRGLEV2 : 00828 tmp |= UART_FCR_TRG_LEV2; 00829 break; 00830 case UART_FIFO_TRGLEV3 : 00831 default: 00832 tmp |= UART_FCR_TRG_LEV3; 00833 break; 00834 } 00835 00836 if (FIFOCfg->FIFO_ResetTxBuf == ENABLE) 00837 { 00838 tmp |= UART_FCR_TX_RS; 00839 } 00840 if (FIFOCfg->FIFO_ResetRxBuf == ENABLE) 00841 { 00842 tmp |= UART_FCR_RX_RS; 00843 } 00844 if (FIFOCfg->FIFO_DMAMode == ENABLE) 00845 { 00846 tmp |= UART_FCR_DMAMODE_SEL; 00847 } 00848 00849 00850 //write to FIFO control register 00851 if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) 00852 { 00853 ((LPC_UART1_TypeDef *)UARTx)->/*IIFCR.*/FCR = tmp & UART_FCR_BITMASK; 00854 } 00855 else 00856 { 00857 UARTx->/*IIFCR.*/FCR = tmp & UART_FCR_BITMASK; 00858 } 00859 } 00860 00861 /*****************************************************************************//** 00862 * @brief Fills each UART_FIFOInitStruct member with its default value: 00863 * - FIFO_DMAMode = DISABLE 00864 * - FIFO_Level = UART_FIFO_TRGLEV0 00865 * - FIFO_ResetRxBuf = ENABLE 00866 * - FIFO_ResetTxBuf = ENABLE 00867 * - FIFO_State = ENABLE 00868 00869 * @param[in] UART_FIFOInitStruct Pointer to a UART_FIFO_CFG_Type structure 00870 * which will be initialized. 00871 * @return None 00872 *******************************************************************************/ 00873 void UART_FIFOConfigStructInit(UART_FIFO_CFG_Type *UART_FIFOInitStruct) 00874 { 00875 UART_FIFOInitStruct->FIFO_DMAMode = DISABLE; 00876 UART_FIFOInitStruct->FIFO_Level = UART_FIFO_TRGLEV0 ; 00877 UART_FIFOInitStruct->FIFO_ResetRxBuf = ENABLE; 00878 UART_FIFOInitStruct->FIFO_ResetTxBuf = ENABLE; 00879 } 00880 00881 00882 /*********************************************************************//** 00883 * @brief Start/Stop Auto Baudrate activity 00884 * @param[in] UARTx UART peripheral selected, should be 00885 * - LPC_UART0: UART0 peripheral 00886 * - LPC_UART1: UART1 peripheral 00887 * - LPC_UART2: UART2 peripheral 00888 * - LPC_UART3: UART3 peripheral 00889 * @param[in] ABConfigStruct A pointer to UART_AB_CFG_Type structure that 00890 * contains specified information about UART 00891 * auto baudrate configuration 00892 * @param[in] NewState New State of Auto baudrate activity, should be: 00893 * - ENABLE: Start this activity 00894 * - DISABLE: Stop this activity 00895 * Note: Auto-baudrate mode enable bit will be cleared once this mode 00896 * completed. 00897 * @return none 00898 **********************************************************************/ 00899 void UART_ABCmd(LPC_UART_TypeDef *UARTx, UART_AB_CFG_Type *ABConfigStruct, \ 00900 FunctionalState NewState) 00901 { 00902 uint32_t tmp; 00903 00904 CHECK_PARAM(PARAM_UARTx(UARTx)); 00905 CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState)); 00906 00907 tmp = 0; 00908 if (NewState == ENABLE) { 00909 if (ABConfigStruct->ABMode == UART_AUTOBAUD_MODE1){ 00910 tmp |= UART_ACR_MODE; 00911 } 00912 if (ABConfigStruct->AutoRestart == ENABLE){ 00913 tmp |= UART_ACR_AUTO_RESTART; 00914 } 00915 } 00916 00917 if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) 00918 { 00919 if (NewState == ENABLE) 00920 { 00921 // Clear DLL and DLM value 00922 ((LPC_UART1_TypeDef *)UARTx)->LCR |= UART_LCR_DLAB_EN; 00923 ((LPC_UART1_TypeDef *)UARTx)->DLL = 0; 00924 ((LPC_UART1_TypeDef *)UARTx)->DLM = 0; 00925 ((LPC_UART1_TypeDef *)UARTx)->LCR &= ~UART_LCR_DLAB_EN; 00926 // FDR value must be reset to default value 00927 ((LPC_UART1_TypeDef *)UARTx)->FDR = 0x10; 00928 ((LPC_UART1_TypeDef *)UARTx)->ACR = UART_ACR_START | tmp; 00929 } 00930 else 00931 { 00932 ((LPC_UART1_TypeDef *)UARTx)->ACR = 0; 00933 } 00934 } 00935 else 00936 { 00937 if (NewState == ENABLE) 00938 { 00939 // Clear DLL and DLM value 00940 UARTx->LCR |= UART_LCR_DLAB_EN; 00941 UARTx->DLL = 0; 00942 UARTx->DLM = 0; 00943 UARTx->LCR &= ~UART_LCR_DLAB_EN; 00944 // FDR value must be reset to default value 00945 UARTx->FDR = 0x10; 00946 UARTx->ACR = UART_ACR_START | tmp; 00947 } 00948 else 00949 { 00950 UARTx->ACR = 0; 00951 } 00952 } 00953 } 00954 00955 /*********************************************************************//** 00956 * @brief Clear Autobaud Interrupt Pending 00957 * @param[in] UARTx UART peripheral selected, should be 00958 * - LPC_UART0: UART0 peripheral 00959 * - LPC_UART1: UART1 peripheral 00960 * - LPC_UART2: UART2 peripheral 00961 * - LPC_UART3: UART3 peripheral 00962 * @param[in] ABIntType type of auto-baud interrupt, should be: 00963 * - UART_AUTOBAUD_INTSTAT_ABEO: End of Auto-baud interrupt 00964 * - UART_AUTOBAUD_INTSTAT_ABTO: Auto-baud time out interrupt 00965 * @return none 00966 **********************************************************************/ 00967 void UART_ABClearIntPending(LPC_UART_TypeDef *UARTx, UART_ABEO_Type ABIntType) 00968 { 00969 CHECK_PARAM(PARAM_UARTx(UARTx)); 00970 if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) 00971 { 00972 UARTx->ACR |= ABIntType; 00973 } 00974 else 00975 UARTx->ACR |= ABIntType; 00976 } 00977 00978 /*********************************************************************//** 00979 * @brief Enable/Disable transmission on UART TxD pin 00980 * @param[in] UARTx UART peripheral selected, should be: 00981 * - LPC_UART0: UART0 peripheral 00982 * - LPC_UART1: UART1 peripheral 00983 * - LPC_UART2: UART2 peripheral 00984 * - LPC_UART3: UART3 peripheral 00985 * @param[in] NewState New State of Tx transmission function, should be: 00986 * - ENABLE: Enable this function 00987 - DISABLE: Disable this function 00988 * @return none 00989 **********************************************************************/ 00990 void UART_TxCmd(LPC_UART_TypeDef *UARTx, FunctionalState NewState) 00991 { 00992 CHECK_PARAM(PARAM_UARTx(UARTx)); 00993 CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState)); 00994 00995 if (NewState == ENABLE) 00996 { 00997 if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) 00998 { 00999 ((LPC_UART1_TypeDef *)UARTx)->TER |= UART_TER_TXEN; 01000 } 01001 else 01002 { 01003 UARTx->TER |= UART_TER_TXEN; 01004 } 01005 } 01006 else 01007 { 01008 if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) 01009 { 01010 ((LPC_UART1_TypeDef *)UARTx)->TER &= (~UART_TER_TXEN) & UART_TER_BITMASK; 01011 } 01012 else 01013 { 01014 UARTx->TER &= (~UART_TER_TXEN) & UART_TER_BITMASK; 01015 } 01016 } 01017 } 01018 01019 /* UART IrDA functions ---------------------------------------------------*/ 01020 01021 #ifdef _UART3 01022 01023 /*********************************************************************//** 01024 * @brief Enable or disable inverting serial input function of IrDA 01025 * on UART peripheral. 01026 * @param[in] UARTx UART peripheral selected, should be LPC_UART3 (only) 01027 * @param[in] NewState New state of inverting serial input, should be: 01028 * - ENABLE: Enable this function. 01029 * - DISABLE: Disable this function. 01030 * @return none 01031 **********************************************************************/ 01032 void UART_IrDAInvtInputCmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState) 01033 { 01034 CHECK_PARAM(PARAM_UART_IrDA(UARTx)); 01035 CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState)); 01036 01037 if (NewState == ENABLE) 01038 { 01039 UARTx->ICR |= UART_ICR_IRDAINV; 01040 } 01041 else if (NewState == DISABLE) 01042 { 01043 UARTx->ICR &= (~UART_ICR_IRDAINV) & UART_ICR_BITMASK; 01044 } 01045 } 01046 01047 01048 /*********************************************************************//** 01049 * @brief Enable or disable IrDA function on UART peripheral. 01050 * @param[in] UARTx UART peripheral selected, should be LPC_UART3 (only) 01051 * @param[in] NewState New state of IrDA function, should be: 01052 * - ENABLE: Enable this function. 01053 * - DISABLE: Disable this function. 01054 * @return none 01055 **********************************************************************/ 01056 void UART_IrDACmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState) 01057 { 01058 CHECK_PARAM(PARAM_UART_IrDA(UARTx)); 01059 CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState)); 01060 01061 if (NewState == ENABLE) 01062 { 01063 UARTx->ICR |= UART_ICR_IRDAEN; 01064 } 01065 else 01066 { 01067 UARTx->ICR &= (~UART_ICR_IRDAEN) & UART_ICR_BITMASK; 01068 } 01069 } 01070 01071 01072 /*********************************************************************//** 01073 * @brief Configure Pulse divider for IrDA function on UART peripheral. 01074 * @param[in] UARTx UART peripheral selected, should be LPC_UART3 (only) 01075 * @param[in] PulseDiv Pulse Divider value from Peripheral clock, 01076 * should be one of the following: 01077 - UART_IrDA_PULSEDIV2 : Pulse width = 2 * Tpclk 01078 - UART_IrDA_PULSEDIV4 : Pulse width = 4 * Tpclk 01079 - UART_IrDA_PULSEDIV8 : Pulse width = 8 * Tpclk 01080 - UART_IrDA_PULSEDIV16 : Pulse width = 16 * Tpclk 01081 - UART_IrDA_PULSEDIV32 : Pulse width = 32 * Tpclk 01082 - UART_IrDA_PULSEDIV64 : Pulse width = 64 * Tpclk 01083 - UART_IrDA_PULSEDIV128 : Pulse width = 128 * Tpclk 01084 - UART_IrDA_PULSEDIV256 : Pulse width = 256 * Tpclk 01085 01086 * @return none 01087 **********************************************************************/ 01088 void UART_IrDAPulseDivConfig(LPC_UART_TypeDef *UARTx, UART_IrDA_PULSE_Type PulseDiv) 01089 { 01090 uint32_t tmp, tmp1; 01091 CHECK_PARAM(PARAM_UART_IrDA(UARTx)); 01092 CHECK_PARAM(PARAM_UART_IrDA_PULSEDIV(PulseDiv)); 01093 01094 tmp1 = UART_ICR_PULSEDIV(PulseDiv); 01095 tmp = UARTx->ICR & (~UART_ICR_PULSEDIV(7)); 01096 tmp |= tmp1 | UART_ICR_FIXPULSE_EN; 01097 UARTx->ICR = tmp & UART_ICR_BITMASK; 01098 } 01099 01100 #endif 01101 01102 01103 /* UART1 FullModem function ---------------------------------------------*/ 01104 01105 #ifdef _UART1 01106 01107 /*********************************************************************//** 01108 * @brief Force pin DTR/RTS corresponding to given state (Full modem mode) 01109 * @param[in] UARTx LPC_UART1 (only) 01110 * @param[in] Pin Pin that NewState will be applied to, should be: 01111 * - UART1_MODEM_PIN_DTR: DTR pin. 01112 * - UART1_MODEM_PIN_RTS: RTS pin. 01113 * @param[in] NewState New State of DTR/RTS pin, should be: 01114 * - INACTIVE: Force the pin to inactive signal. 01115 - ACTIVE: Force the pin to active signal. 01116 * @return none 01117 **********************************************************************/ 01118 void UART_FullModemForcePinState(LPC_UART1_TypeDef *UARTx, UART_MODEM_PIN_Type Pin, \ 01119 UART1_SignalState NewState) 01120 { 01121 uint8_t tmp = 0; 01122 01123 CHECK_PARAM(PARAM_UART1_MODEM(UARTx)); 01124 CHECK_PARAM(PARAM_UART1_MODEM_PIN(Pin)); 01125 CHECK_PARAM(PARAM_UART1_SIGNALSTATE(NewState)); 01126 01127 switch (Pin){ 01128 case UART1_MODEM_PIN_DTR : 01129 tmp = UART1_MCR_DTR_CTRL; 01130 break; 01131 case UART1_MODEM_PIN_RTS : 01132 tmp = UART1_MCR_RTS_CTRL; 01133 break; 01134 default: 01135 break; 01136 } 01137 01138 if (NewState == ACTIVE){ 01139 UARTx->MCR |= tmp; 01140 } else { 01141 UARTx->MCR &= (~tmp) & UART1_MCR_BITMASK; 01142 } 01143 } 01144 01145 01146 /*********************************************************************//** 01147 * @brief Configure Full Modem mode for UART peripheral 01148 * @param[in] UARTx LPC_UART1 (only) 01149 * @param[in] Mode Full Modem mode, should be: 01150 * - UART1_MODEM_MODE_LOOPBACK: Loop back mode. 01151 * - UART1_MODEM_MODE_AUTO_RTS: Auto-RTS mode. 01152 * - UART1_MODEM_MODE_AUTO_CTS: Auto-CTS mode. 01153 * @param[in] NewState New State of this mode, should be: 01154 * - ENABLE: Enable this mode. 01155 - DISABLE: Disable this mode. 01156 * @return none 01157 **********************************************************************/ 01158 void UART_FullModemConfigMode(LPC_UART1_TypeDef *UARTx, UART_MODEM_MODE_Type Mode, \ 01159 FunctionalState NewState) 01160 { 01161 uint8_t tmp = 0; 01162 01163 CHECK_PARAM(PARAM_UART1_MODEM(UARTx)); 01164 CHECK_PARAM(PARAM_UART1_MODEM_MODE(Mode)); 01165 CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState)); 01166 01167 switch(Mode){ 01168 case UART1_MODEM_MODE_LOOPBACK : 01169 tmp = UART1_MCR_LOOPB_EN; 01170 break; 01171 case UART1_MODEM_MODE_AUTO_RTS : 01172 tmp = UART1_MCR_AUTO_RTS_EN; 01173 break; 01174 case UART1_MODEM_MODE_AUTO_CTS : 01175 tmp = UART1_MCR_AUTO_CTS_EN; 01176 break; 01177 default: 01178 break; 01179 } 01180 01181 if (NewState == ENABLE) 01182 { 01183 UARTx->MCR |= tmp; 01184 } 01185 else 01186 { 01187 UARTx->MCR &= (~tmp) & UART1_MCR_BITMASK; 01188 } 01189 } 01190 01191 01192 /*********************************************************************//** 01193 * @brief Get current status of modem status register 01194 * @param[in] UARTx LPC_UART1 (only) 01195 * @return Current value of modem status register 01196 * Note: The return value of this function must be ANDed with each member 01197 * UART_MODEM_STAT_type enumeration to determine current flag status 01198 * corresponding to each modem flag status. Because some flags in 01199 * modem status register will be cleared after reading, the next reading 01200 * modem register could not be correct. So this function used to 01201 * read modem status register in one time only, then the return value 01202 * used to check all flags. 01203 **********************************************************************/ 01204 uint8_t UART_FullModemGetStatus(LPC_UART1_TypeDef *UARTx) 01205 { 01206 CHECK_PARAM(PARAM_UART1_MODEM(UARTx)); 01207 return ((UARTx->MSR) & UART1_MSR_BITMASK); 01208 } 01209 01210 01211 /* UART RS485 functions --------------------------------------------------------------*/ 01212 01213 /*********************************************************************//** 01214 * @brief Configure UART peripheral in RS485 mode according to the specified 01215 * parameters in the RS485ConfigStruct. 01216 * @param[in] UARTx LPC_UART1 (only) 01217 * @param[in] RS485ConfigStruct Pointer to a UART1_RS485_CTRLCFG_Type structure 01218 * that contains the configuration information for specified UART 01219 * in RS485 mode. 01220 * @return None 01221 **********************************************************************/ 01222 void UART_RS485Config(LPC_UART1_TypeDef *UARTx, UART1_RS485_CTRLCFG_Type *RS485ConfigStruct) 01223 { 01224 uint32_t tmp; 01225 01226 CHECK_PARAM(PARAM_UART1_MODEM(UARTx)); 01227 CHECK_PARAM(PARAM_FUNCTIONALSTATE(RS485ConfigStruct->AutoAddrDetect_State )); 01228 CHECK_PARAM(PARAM_FUNCTIONALSTATE(RS485ConfigStruct->AutoDirCtrl_State )); 01229 CHECK_PARAM(PARAM_UART1_RS485_CFG_DELAYVALUE(RS485ConfigStruct->DelayValue )); 01230 CHECK_PARAM(PARAM_SETSTATE(RS485ConfigStruct->DirCtrlPol_Level )); 01231 CHECK_PARAM(PARAM_UART_RS485_DIRCTRL_PIN(RS485ConfigStruct->DirCtrlPin )); 01232 CHECK_PARAM(PARAM_UART1_RS485_CFG_MATCHADDRVALUE(RS485ConfigStruct->MatchAddrValue )); 01233 CHECK_PARAM(PARAM_FUNCTIONALSTATE(RS485ConfigStruct->NormalMultiDropMode_State )); 01234 CHECK_PARAM(PARAM_FUNCTIONALSTATE(RS485ConfigStruct->Rx_State )); 01235 01236 tmp = 0; 01237 // If Auto Direction Control is enabled - This function is used in Master mode 01238 if (RS485ConfigStruct->AutoDirCtrl_State == ENABLE) 01239 { 01240 tmp |= UART1_RS485CTRL_DCTRL_EN; 01241 01242 // Set polar 01243 if (RS485ConfigStruct->DirCtrlPol_Level == SET) 01244 { 01245 tmp |= UART1_RS485CTRL_OINV_1; 01246 } 01247 01248 // Set pin according to 01249 if (RS485ConfigStruct->DirCtrlPin == UART1_RS485_DIRCTRL_DTR) 01250 { 01251 tmp |= UART1_RS485CTRL_SEL_DTR; 01252 } 01253 01254 // Fill delay time 01255 UARTx->RS485DLY = RS485ConfigStruct->DelayValue & UART1_RS485DLY_BITMASK; 01256 } 01257 01258 // MultiDrop mode is enable 01259 if (RS485ConfigStruct->NormalMultiDropMode_State == ENABLE) 01260 { 01261 tmp |= UART1_RS485CTRL_NMM_EN; 01262 } 01263 01264 // Auto Address Detect function 01265 if (RS485ConfigStruct->AutoAddrDetect_State == ENABLE) 01266 { 01267 tmp |= UART1_RS485CTRL_AADEN; 01268 // Fill Match Address 01269 UARTx->ADRMATCH = RS485ConfigStruct->MatchAddrValue & UART1_RS485ADRMATCH_BITMASK; 01270 } 01271 01272 01273 // Receiver is disable 01274 if (RS485ConfigStruct->Rx_State == DISABLE) 01275 { 01276 tmp |= UART1_RS485CTRL_RX_DIS; 01277 } 01278 01279 // write back to RS485 control register 01280 UARTx->RS485CTRL = tmp & UART1_RS485CTRL_BITMASK; 01281 01282 // Enable Parity function and leave parity in stick '0' parity as default 01283 UARTx->LCR |= (UART_LCR_PARITY_F_0 | UART_LCR_PARITY_EN); 01284 } 01285 01286 /*********************************************************************//** 01287 * @brief Enable/Disable receiver in RS485 module in UART1 01288 * @param[in] UARTx LPC_UART1 (only) 01289 * @param[in] NewState New State of command, should be: 01290 * - ENABLE: Enable this function. 01291 * - DISABLE: Disable this function. 01292 * @return None 01293 **********************************************************************/ 01294 void UART_RS485ReceiverCmd(LPC_UART1_TypeDef *UARTx, FunctionalState NewState) 01295 { 01296 if (NewState == ENABLE){ 01297 UARTx->RS485CTRL &= ~UART1_RS485CTRL_RX_DIS; 01298 } else { 01299 UARTx->RS485CTRL |= UART1_RS485CTRL_RX_DIS; 01300 } 01301 } 01302 01303 /*********************************************************************//** 01304 * @brief Send data on RS485 bus with specified parity stick value (9-bit mode). 01305 * @param[in] UARTx LPC_UART1 (only) 01306 * @param[in] pDatFrm Pointer to data frame. 01307 * @param[in] size Size of data. 01308 * @param[in] ParityStick Parity Stick value, should be 0 or 1. 01309 * @return None 01310 **********************************************************************/ 01311 uint32_t UART_RS485Send(LPC_UART1_TypeDef *UARTx, uint8_t *pDatFrm, \ 01312 uint32_t size, uint8_t ParityStick) 01313 { 01314 uint8_t tmp, save; 01315 uint32_t cnt; 01316 01317 if (ParityStick){ 01318 save = tmp = UARTx->LCR & UART_LCR_BITMASK; 01319 tmp &= ~(UART_LCR_PARITY_EVEN); 01320 UARTx->LCR = tmp; 01321 cnt = UART_Send((LPC_UART_TypeDef *)UARTx, pDatFrm, size, BLOCKING); 01322 while (!(UARTx->LSR & UART_LSR_TEMT)); 01323 UARTx->LCR = save; 01324 } else { 01325 cnt = UART_Send((LPC_UART_TypeDef *)UARTx, pDatFrm, size, BLOCKING); 01326 while (!(UARTx->LSR & UART_LSR_TEMT)); 01327 } 01328 return cnt; 01329 } 01330 01331 /*********************************************************************//** 01332 * @brief Send Slave address frames on RS485 bus. 01333 * @param[in] UARTx LPC_UART1 (only) 01334 * @param[in] SlvAddr Slave Address. 01335 * @return None 01336 **********************************************************************/ 01337 void UART_RS485SendSlvAddr(LPC_UART1_TypeDef *UARTx, uint8_t SlvAddr) 01338 { 01339 UART_RS485Send(UARTx, &SlvAddr, 1, 1); 01340 } 01341 01342 /*********************************************************************//** 01343 * @brief Send Data frames on RS485 bus. 01344 * @param[in] UARTx LPC_UART1 (only) 01345 * @param[in] pData Pointer to data to be sent. 01346 * @param[in] size Size of data frame to be sent. 01347 * @return None 01348 **********************************************************************/ 01349 uint32_t UART_RS485SendData(LPC_UART1_TypeDef *UARTx, uint8_t *pData, uint32_t size) 01350 { 01351 return (UART_RS485Send(UARTx, pData, size, 0)); 01352 } 01353 01354 #endif /* _UART1 */ 01355 01356 #endif /* _UART */ 01357 01358 /** 01359 * @} 01360 */ 01361 01362 /** 01363 * @} 01364 */ 01365 /* --------------------------------- End Of File ------------------------------ */ 01366
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