Matt Lloyd
Example of UART-DMA transfers taken form the npx cmsis driver libary
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lpc17xx_gpdma.c
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00001 /***********************************************************************//** 00002 * @file lpc17xx_gpdma.c 00003 * @brief Contains all functions support for GPDMA firmware library on LPC17xx 00004 * @version 2.0 00005 * @date 21. May. 2010 00006 * @author NXP MCU SW Application Team 00007 ************************************************************************** 00008 * Software that is described herein is for illustrative purposes only 00009 * which provides customers with programming information regarding the 00010 * products. This software is supplied "AS IS" without any warranties. 00011 * NXP Semiconductors assumes no responsibility or liability for the 00012 * use of the software, conveys no license or title under any patent, 00013 * copyright, or mask work right to the product. NXP Semiconductors 00014 * reserves the right to make changes in the software without 00015 * notification. NXP Semiconductors also make no representation or 00016 * warranty that such application will be suitable for the specified 00017 * use without further testing or modification. 00018 **********************************************************************/ 00019 00020 /* Peripheral group ----------------------------------------------------------- */ 00021 /** @addtogroup GPDMA 00022 * @{ 00023 */ 00024 00025 /* Includes ------------------------------------------------------------------- */ 00026 #include "lpc17xx_gpdma.h" 00027 #include "lpc17xx_clkpwr.h" 00028 00029 /* If this source file built with example, the LPC17xx FW library configuration 00030 * file in each example directory ("lpc17xx_libcfg.h") must be included, 00031 * otherwise the default FW library configuration file must be included instead 00032 */ 00033 #ifdef __BUILD_WITH_EXAMPLE__ 00034 #include "lpc17xx_libcfg.h" 00035 #else 00036 #include "lpc17xx_libcfg_default.h" 00037 #endif /* __BUILD_WITH_EXAMPLE__ */ 00038 00039 #ifdef _GPDMA 00040 00041 00042 /* Private Variables ---------------------------------------------------------- */ 00043 /** @defgroup GPDMA_Private_Variables GPDMA Private Variables 00044 * @{ 00045 */ 00046 00047 /** 00048 * @brief Lookup Table of Connection Type matched with 00049 * Peripheral Data (FIFO) register base address 00050 */ 00051 #ifdef __IAR_SYSTEMS_ICC__ 00052 volatile const void *GPDMA_LUTPerAddr[] = { 00053 (&LPC_SSP0->DR), // SSP0 Tx 00054 (&LPC_SSP0->DR), // SSP0 Rx 00055 (&LPC_SSP1->DR), // SSP1 Tx 00056 (&LPC_SSP1->DR), // SSP1 Rx 00057 (&LPC_ADC->ADGDR), // ADC 00058 (&LPC_I2S->I2STXFIFO), // I2S Tx 00059 (&LPC_I2S->I2SRXFIFO), // I2S Rx 00060 (&LPC_DAC->DACR), // DAC 00061 (&LPC_UART0->/*RBTHDLR.*/THR), // UART0 Tx 00062 (&LPC_UART0->/*RBTHDLR.*/RBR), // UART0 Rx 00063 (&LPC_UART1->/*RBTHDLR.*/THR), // UART1 Tx 00064 (&LPC_UART1->/*RBTHDLR.*/RBR), // UART1 Rx 00065 (&LPC_UART2->/*RBTHDLR.*/THR), // UART2 Tx 00066 (&LPC_UART2->/*RBTHDLR.*/RBR), // UART2 Rx 00067 (&LPC_UART3->/*RBTHDLR.*/THR), // UART3 Tx 00068 (&LPC_UART3->/*RBTHDLR.*/RBR), // UART3 Rx 00069 (&LPC_TIM0->MR0), // MAT0.0 00070 (&LPC_TIM0->MR1), // MAT0.1 00071 (&LPC_TIM1->MR0), // MAT1.0 00072 (&LPC_TIM1->MR1), // MAT1.1 00073 (&LPC_TIM2->MR0), // MAT2.0 00074 (&LPC_TIM2->MR1), // MAT2.1 00075 (&LPC_TIM3->MR0), // MAT3.0 00076 (&LPC_TIM3->MR1), // MAT3.1 00077 }; 00078 #else 00079 const uint32_t GPDMA_LUTPerAddr[] = { 00080 ((uint32_t)&LPC_SSP0->DR), // SSP0 Tx 00081 ((uint32_t)&LPC_SSP0->DR), // SSP0 Rx 00082 ((uint32_t)&LPC_SSP1->DR), // SSP1 Tx 00083 ((uint32_t)&LPC_SSP1->DR), // SSP1 Rx 00084 ((uint32_t)&LPC_ADC->ADGDR), // ADC 00085 ((uint32_t)&LPC_I2S->I2STXFIFO), // I2S Tx 00086 ((uint32_t)&LPC_I2S->I2SRXFIFO), // I2S Rx 00087 ((uint32_t)&LPC_DAC->DACR), // DAC 00088 ((uint32_t)&LPC_UART0->/*RBTHDLR.*/THR), // UART0 Tx 00089 ((uint32_t)&LPC_UART0->/*RBTHDLR.*/RBR), // UART0 Rx 00090 ((uint32_t)&LPC_UART1->/*RBTHDLR.*/THR), // UART1 Tx 00091 ((uint32_t)&LPC_UART1->/*RBTHDLR.*/RBR), // UART1 Rx 00092 ((uint32_t)&LPC_UART2->/*RBTHDLR.*/THR), // UART2 Tx 00093 ((uint32_t)&LPC_UART2->/*RBTHDLR.*/RBR), // UART2 Rx 00094 ((uint32_t)&LPC_UART3->/*RBTHDLR.*/THR), // UART3 Tx 00095 ((uint32_t)&LPC_UART3->/*RBTHDLR.*/RBR), // UART3 Rx 00096 ((uint32_t)&LPC_TIM0->MR0), // MAT0.0 00097 ((uint32_t)&LPC_TIM0->MR1), // MAT0.1 00098 ((uint32_t)&LPC_TIM1->MR0), // MAT1.0 00099 ((uint32_t)&LPC_TIM1->MR1), // MAT1.1 00100 ((uint32_t)&LPC_TIM2->MR0), // MAT2.0 00101 ((uint32_t)&LPC_TIM2->MR1), // MAT2.1 00102 ((uint32_t)&LPC_TIM3->MR0), // MAT3.0 00103 ((uint32_t)&LPC_TIM3->MR1), // MAT3.1 00104 }; 00105 #endif 00106 /** 00107 * @brief Lookup Table of GPDMA Channel Number matched with 00108 * GPDMA channel pointer 00109 */ 00110 const LPC_GPDMACH_TypeDef *pGPDMACh[8] = { 00111 LPC_GPDMACH0, // GPDMA Channel 0 00112 LPC_GPDMACH1, // GPDMA Channel 1 00113 LPC_GPDMACH2, // GPDMA Channel 2 00114 LPC_GPDMACH3, // GPDMA Channel 3 00115 LPC_GPDMACH4, // GPDMA Channel 4 00116 LPC_GPDMACH5, // GPDMA Channel 5 00117 LPC_GPDMACH6, // GPDMA Channel 6 00118 LPC_GPDMACH7, // GPDMA Channel 7 00119 }; 00120 /** 00121 * @brief Optimized Peripheral Source and Destination burst size 00122 */ 00123 const uint8_t GPDMA_LUTPerBurst[] = { 00124 GPDMA_BSIZE_4, // SSP0 Tx 00125 GPDMA_BSIZE_4, // SSP0 Rx 00126 GPDMA_BSIZE_4, // SSP1 Tx 00127 GPDMA_BSIZE_4, // SSP1 Rx 00128 GPDMA_BSIZE_4, // ADC 00129 GPDMA_BSIZE_32, // I2S channel 0 00130 GPDMA_BSIZE_32, // I2S channel 1 00131 GPDMA_BSIZE_1, // DAC 00132 GPDMA_BSIZE_1, // UART0 Tx 00133 GPDMA_BSIZE_1, // UART0 Rx 00134 GPDMA_BSIZE_1, // UART1 Tx 00135 GPDMA_BSIZE_1, // UART1 Rx 00136 GPDMA_BSIZE_1, // UART2 Tx 00137 GPDMA_BSIZE_1, // UART2 Rx 00138 GPDMA_BSIZE_1, // UART3 Tx 00139 GPDMA_BSIZE_1, // UART3 Rx 00140 GPDMA_BSIZE_1, // MAT0.0 00141 GPDMA_BSIZE_1, // MAT0.1 00142 GPDMA_BSIZE_1, // MAT1.0 00143 GPDMA_BSIZE_1, // MAT1.1 00144 GPDMA_BSIZE_1, // MAT2.0 00145 GPDMA_BSIZE_1, // MAT2.1 00146 GPDMA_BSIZE_1, // MAT3.0 00147 GPDMA_BSIZE_1, // MAT3.1 00148 }; 00149 /** 00150 * @brief Optimized Peripheral Source and Destination transfer width 00151 */ 00152 const uint8_t GPDMA_LUTPerWid[] = { 00153 GPDMA_WIDTH_BYTE, // SSP0 Tx 00154 GPDMA_WIDTH_BYTE, // SSP0 Rx 00155 GPDMA_WIDTH_BYTE, // SSP1 Tx 00156 GPDMA_WIDTH_BYTE, // SSP1 Rx 00157 GPDMA_WIDTH_WORD, // ADC 00158 GPDMA_WIDTH_WORD, // I2S channel 0 00159 GPDMA_WIDTH_WORD, // I2S channel 1 00160 GPDMA_WIDTH_BYTE, // DAC 00161 GPDMA_WIDTH_BYTE, // UART0 Tx 00162 GPDMA_WIDTH_BYTE, // UART0 Rx 00163 GPDMA_WIDTH_BYTE, // UART1 Tx 00164 GPDMA_WIDTH_BYTE, // UART1 Rx 00165 GPDMA_WIDTH_BYTE, // UART2 Tx 00166 GPDMA_WIDTH_BYTE, // UART2 Rx 00167 GPDMA_WIDTH_BYTE, // UART3 Tx 00168 GPDMA_WIDTH_BYTE, // UART3 Rx 00169 GPDMA_WIDTH_WORD, // MAT0.0 00170 GPDMA_WIDTH_WORD, // MAT0.1 00171 GPDMA_WIDTH_WORD, // MAT1.0 00172 GPDMA_WIDTH_WORD, // MAT1.1 00173 GPDMA_WIDTH_WORD, // MAT2.0 00174 GPDMA_WIDTH_WORD, // MAT2.1 00175 GPDMA_WIDTH_WORD, // MAT3.0 00176 GPDMA_WIDTH_WORD, // MAT3.1 00177 }; 00178 00179 /** 00180 * @} 00181 */ 00182 00183 /* Public Functions ----------------------------------------------------------- */ 00184 /** @addtogroup GPDMA_Public_Functions 00185 * @{ 00186 */ 00187 00188 /********************************************************************//** 00189 * @brief Initialize GPDMA controller 00190 * @param None 00191 * @return None 00192 *********************************************************************/ 00193 void GPDMA_Init(void) 00194 { 00195 /* Enable GPDMA clock */ 00196 CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCGPDMA, ENABLE); 00197 00198 // Reset all channel configuration register 00199 LPC_GPDMACH0->DMACCConfig = 0; 00200 LPC_GPDMACH1->DMACCConfig = 0; 00201 LPC_GPDMACH2->DMACCConfig = 0; 00202 LPC_GPDMACH3->DMACCConfig = 0; 00203 LPC_GPDMACH4->DMACCConfig = 0; 00204 LPC_GPDMACH5->DMACCConfig = 0; 00205 LPC_GPDMACH6->DMACCConfig = 0; 00206 LPC_GPDMACH7->DMACCConfig = 0; 00207 00208 /* Clear all DMA interrupt and error flag */ 00209 LPC_GPDMA->DMACIntTCClear = 0xFF; 00210 LPC_GPDMA->DMACIntErrClr = 0xFF; 00211 } 00212 00213 /********************************************************************//** 00214 * @brief Setup GPDMA channel peripheral according to the specified 00215 * parameters in the GPDMAChannelConfig. 00216 * @param[in] GPDMAChannelConfig Pointer to a GPDMA_CH_CFG_Type 00217 * structure that contains the configuration 00218 * information for the specified GPDMA channel peripheral. 00219 * @return ERROR if selected channel is enabled before 00220 * or SUCCESS if channel is configured successfully 00221 *********************************************************************/ 00222 Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig) 00223 { 00224 LPC_GPDMACH_TypeDef *pDMAch; 00225 uint32_t tmp1, tmp2; 00226 00227 if (LPC_GPDMA->DMACEnbldChns & (GPDMA_DMACEnbldChns_Ch(GPDMAChannelConfig->ChannelNum))) { 00228 // This channel is enabled, return ERROR, need to release this channel first 00229 return ERROR; 00230 } 00231 00232 // Get Channel pointer 00233 pDMAch = (LPC_GPDMACH_TypeDef *) pGPDMACh[GPDMAChannelConfig->ChannelNum]; 00234 00235 // Reset the Interrupt status 00236 LPC_GPDMA->DMACIntTCClear = GPDMA_DMACIntTCClear_Ch(GPDMAChannelConfig->ChannelNum); 00237 LPC_GPDMA->DMACIntErrClr = GPDMA_DMACIntErrClr_Ch(GPDMAChannelConfig->ChannelNum); 00238 00239 // Clear DMA configure 00240 pDMAch->DMACCControl = 0x00; 00241 pDMAch->DMACCConfig = 0x00; 00242 00243 /* Assign Linker List Item value */ 00244 pDMAch->DMACCLLI = GPDMAChannelConfig->DMALLI; 00245 00246 /* Set value to Channel Control Registers */ 00247 switch (GPDMAChannelConfig->TransferType) 00248 { 00249 // Memory to memory 00250 case GPDMA_TRANSFERTYPE_M2M: 00251 // Assign physical source and destination address 00252 pDMAch->DMACCSrcAddr = GPDMAChannelConfig->SrcMemAddr; 00253 pDMAch->DMACCDestAddr = GPDMAChannelConfig->DstMemAddr; 00254 pDMAch->DMACCControl 00255 = GPDMA_DMACCxControl_TransferSize(GPDMAChannelConfig->TransferSize) \ 00256 | GPDMA_DMACCxControl_SBSize(GPDMA_BSIZE_32) \ 00257 | GPDMA_DMACCxControl_DBSize(GPDMA_BSIZE_32) \ 00258 | GPDMA_DMACCxControl_SWidth(GPDMAChannelConfig->TransferWidth) \ 00259 | GPDMA_DMACCxControl_DWidth(GPDMAChannelConfig->TransferWidth) \ 00260 | GPDMA_DMACCxControl_SI \ 00261 | GPDMA_DMACCxControl_DI \ 00262 | GPDMA_DMACCxControl_I; 00263 break; 00264 // Memory to peripheral 00265 case GPDMA_TRANSFERTYPE_M2P: 00266 // Assign physical source 00267 pDMAch->DMACCSrcAddr = GPDMAChannelConfig->SrcMemAddr; 00268 // Assign peripheral destination address 00269 pDMAch->DMACCDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn]; 00270 pDMAch->DMACCControl 00271 = GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \ 00272 | GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \ 00273 | GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \ 00274 | GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \ 00275 | GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \ 00276 | GPDMA_DMACCxControl_SI \ 00277 | GPDMA_DMACCxControl_I; 00278 break; 00279 // Peripheral to memory 00280 case GPDMA_TRANSFERTYPE_P2M: 00281 // Assign peripheral source address 00282 pDMAch->DMACCSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn]; 00283 // Assign memory destination address 00284 pDMAch->DMACCDestAddr = GPDMAChannelConfig->DstMemAddr; 00285 pDMAch->DMACCControl 00286 = GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \ 00287 | GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \ 00288 | GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \ 00289 | GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \ 00290 | GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \ 00291 | GPDMA_DMACCxControl_DI \ 00292 | GPDMA_DMACCxControl_I; 00293 break; 00294 // Peripheral to peripheral 00295 case GPDMA_TRANSFERTYPE_P2P: 00296 // Assign peripheral source address 00297 pDMAch->DMACCSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn]; 00298 // Assign peripheral destination address 00299 pDMAch->DMACCDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn]; 00300 pDMAch->DMACCControl 00301 = GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \ 00302 | GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \ 00303 | GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \ 00304 | GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \ 00305 | GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \ 00306 | GPDMA_DMACCxControl_I; 00307 break; 00308 // Do not support any more transfer type, return ERROR 00309 default: 00310 return ERROR; 00311 } 00312 00313 /* Re-Configure DMA Request Select for source peripheral */ 00314 if (GPDMAChannelConfig->SrcConn > 15) 00315 { 00316 LPC_SC->RESERVED9 |= (1<<(GPDMAChannelConfig->SrcConn - 16)); 00317 } else { 00318 LPC_SC->RESERVED9 &= ~(1<<(GPDMAChannelConfig->SrcConn - 8)); 00319 } 00320 00321 /* Re-Configure DMA Request Select for Destination peripheral */ 00322 if (GPDMAChannelConfig->DstConn > 15) 00323 { 00324 LPC_SC->RESERVED9 |= (1<<(GPDMAChannelConfig->DstConn - 16)); 00325 } else { 00326 LPC_SC->RESERVED9 &= ~(1<<(GPDMAChannelConfig->DstConn - 8)); 00327 } 00328 00329 /* Enable DMA channels, little endian */ 00330 LPC_GPDMA->DMACConfig = GPDMA_DMACConfig_E; 00331 while (!(LPC_GPDMA->DMACConfig & GPDMA_DMACConfig_E)); 00332 00333 // Calculate absolute value for Connection number 00334 tmp1 = GPDMAChannelConfig->SrcConn; 00335 tmp1 = ((tmp1 > 15) ? (tmp1 - 8) : tmp1); 00336 tmp2 = GPDMAChannelConfig->DstConn; 00337 tmp2 = ((tmp2 > 15) ? (tmp2 - 8) : tmp2); 00338 00339 // Configure DMA Channel, enable Error Counter and Terminate counter 00340 pDMAch->DMACCConfig = GPDMA_DMACCxConfig_IE | GPDMA_DMACCxConfig_ITC /*| GPDMA_DMACCxConfig_E*/ \ 00341 | GPDMA_DMACCxConfig_TransferType((uint32_t)GPDMAChannelConfig->TransferType) \ 00342 | GPDMA_DMACCxConfig_SrcPeripheral(tmp1) \ 00343 | GPDMA_DMACCxConfig_DestPeripheral(tmp2); 00344 00345 return SUCCESS; 00346 } 00347 00348 00349 /*********************************************************************//** 00350 * @brief Enable/Disable DMA channel 00351 * @param[in] channelNum GPDMA channel, should be in range from 0 to 7 00352 * @param[in] NewState New State of this command, should be: 00353 * - ENABLE. 00354 * - DISABLE. 00355 * @return None 00356 **********************************************************************/ 00357 void GPDMA_ChannelCmd(uint8_t channelNum, FunctionalState NewState) 00358 { 00359 LPC_GPDMACH_TypeDef *pDMAch; 00360 00361 // Get Channel pointer 00362 pDMAch = (LPC_GPDMACH_TypeDef *) pGPDMACh[channelNum]; 00363 00364 if (NewState == ENABLE) { 00365 pDMAch->DMACCConfig |= GPDMA_DMACCxConfig_E; 00366 } else { 00367 pDMAch->DMACCConfig &= ~GPDMA_DMACCxConfig_E; 00368 } 00369 } 00370 /*********************************************************************//** 00371 * @brief Check if corresponding channel does have an active interrupt 00372 * request or not 00373 * @param[in] type type of status, should be: 00374 * - GPDMA_STAT_INT: GPDMA Interrupt Status 00375 * - GPDMA_STAT_INTTC: GPDMA Interrupt Terminal Count Request Status 00376 * - GPDMA_STAT_INTERR: GPDMA Interrupt Error Status 00377 * - GPDMA_STAT_RAWINTTC: GPDMA Raw Interrupt Terminal Count Status 00378 * - GPDMA_STAT_RAWINTERR: GPDMA Raw Error Interrupt Status 00379 * - GPDMA_STAT_ENABLED_CH:GPDMA Enabled Channel Status 00380 * @param[in] channel GPDMA channel, should be in range from 0 to 7 00381 * @return IntStatus status of DMA channel interrupt after masking 00382 * Should be: 00383 * - SET: the corresponding channel has no active interrupt request 00384 * - RESET: the corresponding channel does have an active interrupt request 00385 **********************************************************************/ 00386 IntStatus GPDMA_IntGetStatus(GPDMA_Status_Type type, uint8_t channel) 00387 { 00388 CHECK_PARAM(PARAM_GPDMA_STAT(type)); 00389 CHECK_PARAM(PARAM_GPDMA_CHANNEL(channel)); 00390 00391 switch (type) 00392 { 00393 case GPDMA_STAT_INT: //check status of DMA channel interrupts 00394 if (LPC_GPDMA->DMACIntStat & (GPDMA_DMACIntStat_Ch(channel))) 00395 return SET; 00396 return RESET; 00397 case GPDMA_STAT_INTTC: // check terminal count interrupt request status for DMA 00398 if (LPC_GPDMA->DMACIntTCStat & GPDMA_DMACIntTCStat_Ch(channel)) 00399 return SET; 00400 return RESET; 00401 case GPDMA_STAT_INTERR: //check interrupt status for DMA channels 00402 if (LPC_GPDMA->DMACIntErrStat & GPDMA_DMACIntTCClear_Ch(channel)) 00403 return SET; 00404 return RESET; 00405 case GPDMA_STAT_RAWINTTC: //check status of the terminal count interrupt for DMA channels 00406 if (LPC_GPDMA->DMACRawIntErrStat & GPDMA_DMACRawIntTCStat_Ch(channel)) 00407 return SET; 00408 return RESET; 00409 case GPDMA_STAT_RAWINTERR: //check status of the error interrupt for DMA channels 00410 if (LPC_GPDMA->DMACRawIntTCStat & GPDMA_DMACRawIntErrStat_Ch(channel)) 00411 return SET; 00412 return RESET; 00413 default: //check enable status for DMA channels 00414 if (LPC_GPDMA->DMACEnbldChns & GPDMA_DMACEnbldChns_Ch(channel)) 00415 return SET; 00416 return RESET; 00417 } 00418 } 00419 00420 /*********************************************************************//** 00421 * @brief Clear one or more interrupt requests on DMA channels 00422 * @param[in] type type of interrupt request, should be: 00423 * - GPDMA_STATCLR_INTTC: GPDMA Interrupt Terminal Count Request Clear 00424 * - GPDMA_STATCLR_INTERR: GPDMA Interrupt Error Clear 00425 * @param[in] channel GPDMA channel, should be in range from 0 to 7 00426 * @return None 00427 **********************************************************************/ 00428 void GPDMA_ClearIntPending(GPDMA_StateClear_Type type, uint8_t channel) 00429 { 00430 CHECK_PARAM(PARAM_GPDMA_STATCLR(type)); 00431 CHECK_PARAM(PARAM_GPDMA_CHANNEL(channel)); 00432 00433 if (type == GPDMA_STATCLR_INTTC) // clears the terminal count interrupt request on DMA channel 00434 LPC_GPDMA->DMACIntTCClear = GPDMA_DMACIntTCClear_Ch(channel); 00435 else // clear the error interrupt request 00436 LPC_GPDMA->DMACIntErrClr = GPDMA_DMACIntErrClr_Ch(channel); 00437 } 00438 00439 /** 00440 * @} 00441 */ 00442 00443 #endif /* _GPDMA */ 00444 00445 /** 00446 * @} 00447 */ 00448 00449 /* --------------------------------- End Of File ------------------------------ */ 00450
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