David Prentice
Please run it on your NUCLEO-L152
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mcufriend_special.h
00001 // only define one "USE_XXX" macro at any time 00002 00003 //#define USE_MEGA_8BIT_PROTOSHIELD 00004 //#define USE_MEGA_8BIT_SHIELD // 4.7sec Mega2560 Shield 00005 //#define USE_MEGA_16BIT_SHIELD // 2.14sec Mega2560 Shield 00006 //#define USE_BLD_BST_MEGA32U4 00007 //#define USE_BLD_BST_MEGA2560 // 12.23sec Uno Shield (17.38s C) 00008 //#define USE_BLD_BST_MEGA4809 // 5.43sec XPRO-Adapter (7.09s C) 00009 //#define USE_DUE_8BIT_PROTOSHIELD 00010 //#define USE_DUE_16BIT_SHIELD //RD on PA15 (D24) 00011 //#define USE_BOBCACHELOT_TEENSY 00012 //#define USE_OPENSMART_SHIELD_PINOUT_UNO 00013 //#define USE_OPENSMART_SHIELD_PINOUT_MEGA 00014 //#define USE_OPENSMART_SHIELD_PINOUT_DUE //thanks Michel53 00015 //#define USE_ELECHOUSE_DUE_16BIT_SHIELD //Untested yet 00016 //#define USE_MY_BLUEPILL 00017 //#define USE_ADIGITALEU_TEENSY 00018 //#define USE_MIKROELEKTRONIKA 00019 //#define USE_XPRO_MEGA4809 00020 00021 /* 00022 HX8347A tWC =100ns tWRH = 35ns tRCFM = 450ns tRC = ? ns 00023 HX8347D tWC = 66ns tWRH = 15ns tRCFM = 450ns tRC = 160ns 00024 HX8347I tWC =100ns tWRH = 15ns tRCFM = 600ns tRC = 160ns 00025 HX8357C tWC = 50ns tWRH = 15ns tRCFM = 450ns tRC = 160ns 00026 ILI9320 tWC =100ns tWRH = 50ns tRCFM = 300ns tRC = 300ns 00027 ILI9341 tWC = 66ns tWRH = 15ns tRCFM = 450ns tRC = 160ns 00028 ILI9481 tWC =100ns tWRH = 30ns tRCFM = 450ns tRC = 450ns 00029 ILI9486 tWC = 66ns tWRH = 15ns tRCFM = 450ns tRC = 160ns (tWCFM= 286ns on mystery 9486_16) 00030 ILI9486L tWC = 50ns tWRH = 15ns tRCFM = 450ns tRC = 160ns 00031 ILI9488 tWC = 30ns tWRH = 15ns tRCFM = 450ns tRC = 160ns 00032 NT35310 tWC = 40ns tWRH = 19ns tRCFM = 400ns tRC = 160ns 00033 RM68140 tWC = 50ns tWRH = 15ns tRCFM = 450ns tRC = 160ns (tWCFM= 119ns) 00034 SPFD5408 tWC =125ns tWRH = 70ns tRCFM = 450ns tRC = 450ns 00035 SSD1289 tWC =100ns tWRH = 50ns tRCFM =1000ns tRC =1000ns (tWCFM= 238ns) 00036 SSD1963 tWC = 26ns tWRH = 13ns tRCFM = 110ns tRC = 72ns 00037 ST7789V tWC = 66ns tWRH = 15ns tRCFM = 450ns tRC = 160ns 00038 */ 00039 00040 #if 0 00041 00042 #elif defined(__AVR_ATxmega128A1__) // Xplained or MIKROE 00043 #if defined(USE_MIKROELEKTRONIKA) // HX8347-D 16.2ns@62MHz 20.9ns@48MHz 00044 #if F_CPU > 46000000 00045 #error MIKROELEKTRONIKA must be less than 48MHz 00046 #else 00047 #warning MIKROELEKTRONIKA DEV BOARD (48MHz max) 00048 #endif 00049 #define WRITE_DELAY { } 00050 #define READ_DELAY { RD_ACTIVE4; } 00051 #define VPMAP10 0x58 // VPORT0=J, 1=F, 2=K, 3=D 00052 #define VPMAP32 0x39 // VPORT0=J, 1=F, 2=K, 3=D 00053 #define RD_PORT VPORT0 //PJ2. 00054 #define RD_PIN 2 00055 #define WR_PORT VPORT0 00056 #define WR_PIN 3 00057 #define CD_PORT VPORT0 00058 #define CD_PIN 4 00059 #define CS_PORT VPORT0 00060 #define CS_PIN 5 00061 #define RESET_PORT VPORT0 //PJ1 00062 #define RESET_PIN 1 00063 #else 00064 #warning Home made shield with Xplained 00065 #define WRITE_DELAY { } 00066 #define READ_DELAY { RD_ACTIVE4; } 00067 #define VPMAP10 0x15 // VPORT0=F, 1=B, 2=C, 3=D 00068 #define VPMAP32 0x32 // VPORT0=F, 1=B, 2=C, 3=D 00069 #define RD_PORT VPORT0 //PF0. 00070 #define RD_PIN 0 00071 #define WR_PORT VPORT0 00072 #define WR_PIN 1 00073 #define CD_PORT VPORT0 00074 #define CD_PIN 2 00075 #define CS_PORT VPORT0 00076 #define CS_PIN 3 00077 #define RESET_PORT VPORT0 //PK4 00078 #define RESET_PIN 4 00079 #endif 00080 00081 // VPORTs are very fast. CBI, SBI are only one cycle. Hence all those RD_ACTIVEs 00082 // ILI9320 data sheet says tDDR=100ns. We need 218ns to read REGs correctly. 00083 #define write_8(x) { VPORT2.OUT = x; } 00084 #define read_8() ( VPORT2.IN ) 00085 #define setWriteDir() { PORTCFG.VPCTRLA=VPMAP10; PORTCFG.VPCTRLB=VPMAP32; VPORT2.DIR = 0xFF; } 00086 #define setReadDir() { VPORT2.DIR = 0x00; } 00087 #define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; } 00088 #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); } 00089 //#define READ_8(dst) { RD_STROBE; RD_ACTIVE2; RD_ACTIVE; dst = read_8(); RD_IDLE; } 00090 #define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE; } 00091 #define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); } 00092 00093 #define PIN_LOW(p, b) (p).OUT &= ~(1<<(b)) 00094 #define PIN_HIGH(p, b) (p).OUT |= (1<<(b)) 00095 #define PIN_OUTPUT(p, b) (p).DIR |= (1<<(b)) 00096 #elif defined(__AVR_ATxmega32A4U__) || defined(__AVR_ATxmega128A4U__) // Home made shield with Batsocks module 00097 #warning Home made shield with Batsocks module 00098 #define RD_PORT VPORT1 //PB0. VPORT0=A, 1=B, 2=C, 3=D 00099 #define RD_PIN 0 00100 #define WR_PORT VPORT1 00101 #define WR_PIN 1 00102 #define CD_PORT VPORT1 00103 #define CD_PIN 2 00104 #define CS_PORT VPORT1 00105 #define CS_PIN 3 00106 #define RESET_PORT PORTE 00107 #define RESET_PIN 0 00108 00109 // VPORTs are very fast. CBI, SBI are only one cycle. Hence all those RD_ACTIVEs 00110 // ILI9320 data sheet says tDDR=100ns. We need 218ns to read REGs correctly. 00111 // S6D0154 data sheet says tDDR=250ns. We need ~500ns to read REGs correctly. 00112 // ST7789 data sheet says tRC=450ns. We need ~167ns to read REGs correctly. (10 cycles @ 60MHz ) 00113 // ST7789 says tRC=160ns for ID and tRC=450ns for Frame Memory 00114 // ILI9341 says tRC=160ns for ID and tRC=450ns for Frame Memory. They are FASTER 00115 #define WRITE_DELAY { } 00116 #define READ_DELAY { RD_ACTIVE4; } 00117 #define write_8(x) { VPORT2.OUT = x; } 00118 #define read_8() ( VPORT2.IN ) 00119 #define setWriteDir() { PORTCFG.VPCTRLA=0x10; PORTCFG.VPCTRLB=0x32; VPORT2.DIR = 0xFF; } 00120 #define setReadDir() { VPORT2.DIR = 0x00; } 00121 #define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; } 00122 #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); } 00123 #define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE; } 00124 #define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); } 00125 00126 #define PIN_LOW(p, b) (p).OUT &= ~(1<<(b)) 00127 #define PIN_HIGH(p, b) (p).OUT |= (1<<(b)) 00128 #define PIN_OUTPUT(p, b) (p).DIR |= (1<<(b)) 00129 00130 //################################# XPRO-4809 with XPRO-Shield_Adapter ############################ 00131 #elif defined(__AVR_ATmega4809__) && !defined(USE_BLD_BST_MEGA4809) && defined(USE_XPRO_MEGA4809) // XPRO-4809 with XPRO-Shield_Adapter 00132 #warning XPRO-4809 with XPRO-Shield_Adapter using PORT.OUTSET 00133 #define RD_PORT PORTD // 00134 #define RD_PIN 2 00135 #define WR_PORT PORTD 00136 #define WR_PIN 3 00137 #define CD_PORT PORTD 00138 #define CD_PIN 4 00139 #define CS_PORT PORTD 00140 #define CS_PIN 5 00141 #define RESET_PORT PORTC 00142 #define RESET_PIN 2 00143 00144 // PORT.OUTSET is fast but still 2 cycles. Hence all those RD_ACTIVEs 00145 #define AMASK (3<<2) 00146 #define BMASK (3<<2) 00147 #define CMASK (3<<6) 00148 #define EMASK (1<<1) 00149 #define FMASK (1<<6) 00150 #define write_8(x) { \ 00151 PORTA.OUTCLR = AMASK; PORTA.OUTSET = (((x) & (3<<0)) << 2); \ 00152 PORTB.OUTCLR = BMASK; PORTB.OUTSET = (((x) & (1<<2))) | (((x) & (1<<6)) >> 3); \ 00153 PORTC.OUTCLR = CMASK; PORTC.OUTSET = (((x) & (3<<3)) << 3); \ 00154 PORTE.OUTCLR = EMASK; PORTE.OUTSET = (((x) & (1<<7)) >> 6); \ 00155 PORTF.OUTCLR = FMASK; PORTF.OUTSET = (((x) & (1<<5)) << 1); \ 00156 } 00157 #define read_8() ( ((PORTA.IN & AMASK) >> 2)\ 00158 | ((PORTB.IN & (1<<2)) >> 0)\ 00159 | ((PORTB.IN & (1<<3)) << 3)\ 00160 | ((PORTC.IN & CMASK) >> 3)\ 00161 | ((PORTE.IN & EMASK) << 6)\ 00162 | ((PORTF.IN & FMASK) >> 1)\ 00163 ) 00164 #define setWriteDir() { PORTA.DIRSET = AMASK; PORTB.DIRSET = BMASK; PORTC.DIRSET = CMASK; PORTE.DIRSET = EMASK; PORTF.DIRSET = FMASK; } 00165 #define setReadDir() { PORTA.DIRCLR = AMASK; PORTB.DIRCLR = BMASK; PORTC.DIRCLR = CMASK; PORTE.DIRCLR = EMASK; PORTF.DIRCLR = FMASK; } 00166 00167 #define WRITE_DELAY { WR_ACTIVE2; WR_ACTIVE; } //-Os=7.09s @20MHz (-O1=8.13s, -O3=6.03s) 00168 #define READ_DELAY { RD_ACTIVE2; } //ID=0x7789 00169 #define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; } 00170 #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); } 00171 #define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE; } 00172 #define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); } 00173 00174 #define PIN_LOW(p, b) (p).OUTCLR = (1<<(b)) 00175 #define PIN_HIGH(p, b) (p).OUTSET = (1<<(b)) 00176 #define PIN_OUTPUT(p, b) (p).DIRSET = (1<<(b)) 00177 00178 #elif defined(__AVR_ATmega4809__) && defined(USE_BLD_BST_MEGA4809) && defined(USE_XPRO_MEGA4809) // XPRO-4809 with XPRO-Shield_Adapter 00179 #warning XPRO-4809 with XPRO-Shield_Adapter using VPORT.OUT and BLD/BST 00180 #define RD_PORT VPORTD // 00181 #define RD_PIN 2 00182 #define WR_PORT VPORTD 00183 #define WR_PIN 3 00184 #define CD_PORT VPORTD 00185 #define CD_PIN 4 00186 #define CS_PORT VPORTD 00187 #define CS_PIN 5 00188 #define RESET_PORT VPORTC 00189 #define RESET_PIN 2 00190 00191 #define AMASK (3<<2) 00192 #define BMASK (3<<2) 00193 #define CMASK (3<<6) 00194 #define EMASK (1<<1) 00195 #define FMASK (1<<6) 00196 static __attribute((always_inline)) 00197 void write_8(uint8_t val) 00198 { 00199 asm volatile("in __tmp_reg__,0x01" "\n\t" //VPORTA.OUT 00200 "BST %0,0" "\n\t" "BLD __tmp_reg__,2" "\n\t" 00201 "BST %0,1" "\n\t" "BLD __tmp_reg__,3" "\n\t" 00202 "out 0x01,__tmp_reg__" : : "a" (val)); 00203 asm volatile("in __tmp_reg__,0x05" "\n\t" //VPORTB.OUT 00204 "BST %0,2" "\n\t" "BLD __tmp_reg__,2" "\n\t" 00205 "BST %0,6" "\n\t" "BLD __tmp_reg__,3" "\n\t" 00206 "out 0x05,__tmp_reg__" : : "a" (val)); 00207 asm volatile("in __tmp_reg__,0x09" "\n\t" //VPORTC.OUT 00208 "BST %0,3" "\n\t" "BLD __tmp_reg__,6" "\n\t" 00209 "BST %0,4" "\n\t" "BLD __tmp_reg__,7" "\n\t" 00210 "out 0x09,__tmp_reg__" : : "a" (val)); 00211 asm volatile("in __tmp_reg__,0x11" "\n\t" //VPORTE.OUT 00212 "BST %0,7" "\n\t" "BLD __tmp_reg__,1" "\n\t" 00213 "out 0x11,__tmp_reg__" : : "a" (val)); 00214 asm volatile("in __tmp_reg__,0x15" "\n\t" //VPORTF.OUT 00215 "BST %0,5" "\n\t" "BLD __tmp_reg__,6" "\n\t" 00216 "out 0x15,__tmp_reg__" : : "a" (val)); 00217 } 00218 00219 #define read_8() ( ((VPORTA_IN & AMASK) >> 2)\ 00220 | ((VPORTB_IN & (1<<2)) >> 0)\ 00221 | ((VPORTB_IN & (1<<3)) << 3)\ 00222 | ((VPORTC_IN & CMASK) >> 3)\ 00223 | ((VPORTE_IN & EMASK) << 6)\ 00224 | ((VPORTF_IN & FMASK) >> 1)\ 00225 ) 00226 #define setWriteDir() { VPORTA_DIR |= AMASK; VPORTB_DIR |= BMASK; VPORTC_DIR |= CMASK; VPORTE_DIR |= EMASK; VPORTF_DIR |= FMASK; } 00227 #define setReadDir() { VPORTA_DIR &= ~AMASK; VPORTB_DIR &= ~BMASK; VPORTC_DIR &= ~CMASK; VPORTE_DIR &= ~EMASK; VPORTF_DIR &= ~FMASK; } 00228 00229 //#define WRITE_DELAY { WR_ACTIVE; WR_ACTIVE; } //6.47s no_inline 00230 #define WRITE_DELAY { WR_ACTIVE2; WR_ACTIVE; } //-Os=5.43s @20MHz always_inline. (-O1=5.41s, -O3=5.25s) 00231 #define READ_DELAY { RD_ACTIVE4; } //ID=0x7789 00232 #define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; } 00233 #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); } 00234 #define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE; } 00235 #define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); } 00236 00237 #define PIN_LOW(p, b) (p).OUT &= ~(1<<(b)) 00238 #define PIN_HIGH(p, b) (p).OUT |= (1<<(b)) 00239 #define PIN_OUTPUT(p, b) (p).DIR |= (1<<(b)) 00240 00241 #elif defined(__AVR_ATmega328P__) && defined(USE_OPENSMART_SHIELD_PINOUT_UNO) 00242 #define RD_PORT PORTC 00243 #define RD_PIN 0 00244 #define WR_PORT PORTC 00245 #define WR_PIN 1 00246 #define CD_PORT PORTC 00247 #define CD_PIN 2 00248 #define CS_PORT PORTC 00249 #define CS_PIN 3 00250 #define RESET_PORT PORTC 00251 #define RESET_PIN 1 // n/a. so mimic WR_PIN 00252 00253 #define BMASK B00101111 00254 #define DMASK B11010000 00255 00256 #define write_8(x) { \ 00257 PORTD = (PORTD & ~DMASK) | ((x) & DMASK); \ 00258 PORTB = (PORTB & ~BMASK) | ((x) & BMASK);} // STROBEs are defined later 00259 00260 #define read_8() ((PIND & DMASK) | (PINB & BMASK)) 00261 00262 #define setWriteDir() { DDRD |= DMASK; DDRB |= BMASK; } 00263 #define setReadDir() { DDRD &= ~DMASK; DDRB &= ~BMASK; } 00264 00265 00266 #define write8(x) { write_8(x); WR_STROBE; } 00267 #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); } 00268 #define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; } 00269 #define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); } 00270 00271 #define PIN_LOW(p, b) (p) &= ~(1<<(b)) 00272 #define PIN_HIGH(p, b) (p) |= (1<<(b)) 00273 #define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b)) 00274 00275 #elif defined(__AVR_ATmega2560__) && defined(USE_OPENSMART_SHIELD_PINOUT_MEGA) 00276 #define RD_PORT PORTF 00277 #define RD_PIN 0 00278 #define WR_PORT PORTF 00279 #define WR_PIN 1 00280 #define CD_PORT PORTF 00281 #define CD_PIN 2 00282 #define CS_PORT PORTF 00283 #define CS_PIN 3 00284 #define RESET_PORT PORTF 00285 #define RESET_PIN 1 // n/a. so mimic WR_PIN 00286 00287 #define BMASK B10110000 //D13, D11, D10 00288 #define GMASK 0x20 //D4 00289 #define HMASK 0x78 //D6, D7, D8, D9 00290 00291 #if defined(USE_BLD_BST_MEGA2560) 00292 static __attribute((always_inline)) void write_8(uint8_t val) 00293 { 00294 asm volatile("lds __tmp_reg__,0x0102" "\n\t" //PORTH 00295 "BST %0,0" "\n\t" "BLD __tmp_reg__,5" "\n\t" 00296 "BST %0,1" "\n\t" "BLD __tmp_reg__,6" "\n\t" 00297 "BST %0,6" "\n\t" "BLD __tmp_reg__,3" "\n\t" 00298 "BST %0,7" "\n\t" "BLD __tmp_reg__,4" "\n\t" 00299 "sts 0x0102,__tmp_reg__" : : "a" (val)); 00300 asm volatile("in __tmp_reg__,0x05" "\n\t" //PORTB 00301 "BST %0,2" "\n\t" "BLD __tmp_reg__,4" "\n\t" 00302 "BST %0,3" "\n\t" "BLD __tmp_reg__,5" "\n\t" 00303 "BST %0,5" "\n\t" "BLD __tmp_reg__,7" "\n\t" 00304 "out 0x05,__tmp_reg__" : : "a" (val)); 00305 asm volatile("in __tmp_reg__,0x14" "\n\t" //PORTG 00306 "BST %0,4" "\n\t" "BLD __tmp_reg__,5" "\n\t" 00307 "out 0x14,__tmp_reg__" : : "a" (val)); 00308 } 00309 #else 00310 #define write_8(x) { \ 00311 PORTH = (PORTH&~HMASK)|(((x)&B11000000)>>3)|(((x)&B00000011)<<5); \ 00312 PORTB = (PORTB&~BMASK)|(((x)&B00101100)<<2); \ 00313 PORTG = (PORTG&~GMASK)|(((x)&B00010000)<<1); \ 00314 } 00315 #endif 00316 00317 #define read_8()(\ 00318 ((PINH & B00011000) << 3) | ((PINB & BMASK) >> 2) | \ 00319 ((PING & GMASK) >> 1) | ((PINH & B01100000) >> 5) ) 00320 #define setWriteDir() { DDRH |= HMASK; DDRB |= BMASK; DDRG |= GMASK; } 00321 #define setReadDir() { DDRH &= ~HMASK; DDRB &= ~BMASK; DDRG &= ~GMASK; } 00322 00323 #define write8(x) { write_8(x); WR_STROBE; } 00324 #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); } 00325 #define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; } 00326 #define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); } 00327 00328 #define PIN_LOW(p, b) (p) &= ~(1<<(b)) 00329 #define PIN_HIGH(p, b) (p) |= (1<<(b)) 00330 #define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b)) 00331 00332 #elif defined(__SAM3X8E__) && defined(USE_OPENSMART_SHIELD_PINOUT_DUE) //OPENSMART shield on DUE 00333 #warning USE_OPENSMART_SHIELD_PINOUT on DUE 00334 // configure macros for the control pins 00335 #define RD_PORT PIOA 00336 #define RD_PIN 16 00337 #define WR_PORT PIOA 00338 #define WR_PIN 24 00339 #define CD_PORT PIOA 00340 #define CD_PIN 23 00341 #define CS_PORT PIOA 00342 #define CS_PIN 22 00343 #define RESET_PORT PIOA 00344 #define RESET_PIN 24 // n/a. so mimic WR_PIN 00345 // configure macros for data bus 00346 #define BMASK (1<<27) 00347 #define CMASK (0x12F << 21) 00348 #define DMASK (1<<7) 00349 #define write_8(x) { PIOB->PIO_CODR = BMASK; PIOC->PIO_CODR = CMASK; PIOD->PIO_CODR = DMASK; \ 00350 PIOC->PIO_SODR = (((x) & (1<<0)) << 22); \ 00351 PIOC->PIO_SODR = (((x) & (1<<1)) << 20); \ 00352 PIOC->PIO_SODR = (((x) & (1<<2)) << 27); \ 00353 PIOD->PIO_SODR = (((x) & (1<<3)) << 4); \ 00354 PIOC->PIO_SODR = (((x) & (1<<4)) << 22); \ 00355 PIOB->PIO_SODR = (((x) & (1<<5)) << 22); \ 00356 PIOC->PIO_SODR = (((x) & (1<<6)) << 18); \ 00357 PIOC->PIO_SODR = (((x) & (1<<7)) << 16); \ 00358 } 00359 00360 #define read_8() ( ((PIOC->PIO_PDSR & (1<<22)) >> 22)\ 00361 | ((PIOC->PIO_PDSR & (1<<21)) >> 20)\ 00362 | ((PIOC->PIO_PDSR & (1<<29)) >> 27)\ 00363 | ((PIOD->PIO_PDSR & (1<<7)) >> 4)\ 00364 | ((PIOC->PIO_PDSR & (1<<26)) >> 22)\ 00365 | ((PIOB->PIO_PDSR & (1<<27)) >> 22)\ 00366 | ((PIOC->PIO_PDSR & (1<<24)) >> 18)\ 00367 | ((PIOC->PIO_PDSR & (1<<23)) >> 16)\ 00368 ) 00369 #define setWriteDir() { PIOB->PIO_OER = BMASK; PIOC->PIO_OER = CMASK; PIOD->PIO_OER = DMASK; } 00370 #define setReadDir() { \ 00371 PMC->PMC_PCER0 = (1 << ID_PIOB)|(1 << ID_PIOC)|(1 << ID_PIOD);\ 00372 PIOB->PIO_ODR = BMASK; PIOC->PIO_ODR = CMASK; PIOD->PIO_ODR = DMASK;\ 00373 } 00374 #define write8(x) { write_8(x); WR_ACTIVE; WR_STROBE; } 00375 //#define write8(x) { write_8(x); WR_ACTIVE; WR_STROBE; WR_IDLE; } 00376 #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); } 00377 #define READ_8(dst) { RD_STROBE; RD_ACTIVE; dst = read_8(); RD_IDLE; RD_IDLE; } 00378 #define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); } 00379 // Shield Control macros. 00380 #define PIN_LOW(port, pin) (port)->PIO_CODR = (1<<(pin)) 00381 #define PIN_HIGH(port, pin) (port)->PIO_SODR = (1<<(pin)) 00382 #define PIN_OUTPUT(port, pin) (port)->PIO_OER = (1<<(pin)) 00383 00384 #elif defined(__AVR_ATmega2560__) && defined(USE_BLD_BST_MEGA2560) //regular UNO shield on MEGA2560 using BLD/BST 00385 #warning regular UNO shield on MEGA2560 using BLD/BST 00386 #define RD_PORT PORTF 00387 #define RD_PIN 0 00388 #define WR_PORT PORTF 00389 #define WR_PIN 1 00390 #define CD_PORT PORTF 00391 #define CD_PIN 2 00392 #define CS_PORT PORTF 00393 #define CS_PIN 3 00394 #define RESET_PORT PORTF 00395 #define RESET_PIN 4 00396 00397 #define EMASK 0x38 00398 #define GMASK 0x20 00399 #define HMASK 0x78 00400 static __attribute((always_inline)) void write_8(uint8_t val) 00401 { 00402 asm volatile("lds __tmp_reg__,0x0102" "\n\t" 00403 "BST %0,0" "\n\t" "BLD __tmp_reg__,5" "\n\t" 00404 "BST %0,1" "\n\t" "BLD __tmp_reg__,6" "\n\t" 00405 "BST %0,6" "\n\t" "BLD __tmp_reg__,3" "\n\t" 00406 "BST %0,7" "\n\t" "BLD __tmp_reg__,4" "\n\t" 00407 "sts 0x0102,__tmp_reg__" : : "a" (val)); 00408 asm volatile("in __tmp_reg__,0x0E" "\n\t" 00409 "BST %0,2" "\n\t" "BLD __tmp_reg__,4" "\n\t" 00410 "BST %0,3" "\n\t" "BLD __tmp_reg__,5" "\n\t" 00411 "BST %0,5" "\n\t" "BLD __tmp_reg__,3" "\n\t" 00412 "out 0x0E,__tmp_reg__" : : "a" (val)); 00413 asm volatile("in __tmp_reg__,0x14" "\n\t" 00414 "BST %0,4" "\n\t" "BLD __tmp_reg__,5" "\n\t" 00415 "out 0x14,__tmp_reg__" : : "a" (val)); 00416 } 00417 00418 #define read_8() ( ((PINH & (3<<5)) >> 5)\ 00419 | ((PINE & (3<<4)) >> 2)\ 00420 | ((PING & (1<<5)) >> 1)\ 00421 | ((PINE & (1<<3)) << 2)\ 00422 | ((PINH & (3<<3)) << 3)\ 00423 ) 00424 #define setWriteDir() { DDRH |= HMASK; DDRG |= GMASK; DDRE |= EMASK; } 00425 #define setReadDir() { DDRH &= ~HMASK; DDRG &= ~GMASK; DDRE &= ~EMASK; } 00426 #define write8(x) { write_8(x); WR_STROBE; } 00427 #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); } 00428 #define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; } 00429 #define READ_16(dst) { RD_STROBE; dst = read_8(); RD_IDLE; RD_STROBE; dst = (dst<<8) | read_8(); RD_IDLE; } 00430 00431 #define PIN_LOW(p, b) (p) &= ~(1<<(b)) 00432 #define PIN_HIGH(p, b) (p) |= (1<<(b)) 00433 #define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b)) 00434 00435 #elif defined(__AVR_ATmega2560__) && defined(USE_MEGA_16BIT_SHIELD) 00436 #warning USE_MEGA_16BIT_SHIELD 00437 #define USES_16BIT_BUS 00438 #define RD_PORT PORTL 00439 #define RD_PIN 6 //PL6 (D43). Graham has PA15 (D24) on Due Shield 00440 #define WR_PORT PORTG 00441 #define WR_PIN 2 //D39 CTE 00442 #define CD_PORT PORTD 00443 #define CD_PIN 7 //D38 CTE 00444 #define CS_PORT PORTG 00445 #define CS_PIN 1 //D40 CTE 00446 #define RESET_PORT PORTG 00447 #define RESET_PIN 0 //D41 CTE 00448 00449 #define write_8(x) { PORTC = x; } 00450 #define write_16(x) { PORTA = (x) >> 8; PORTC = x; } 00451 00452 #define read_16() ( (PINA<<8) | (PINC) ) 00453 #define setWriteDir() { DDRC = 0xFF; DDRA = 0xff; } 00454 #define setReadDir() { DDRC = 0x00; DDRA = 0x00; } 00455 //#define write8(x) { write_8(x); WR_STROBE; } 00456 #define write8(x) { write16((x) & 0xFF); } 00457 #define write16(x) { write_16(x); WR_ACTIVE; WR_STROBE; } 00458 #define READ_16(dst) { RD_STROBE; dst = read_16(); RD_IDLE; } 00459 #define READ_8(dst) { READ_16(dst); dst &= 0x00FF; } 00460 00461 #define PIN_LOW(p, b) (p) &= ~(1<<(b)) 00462 #define PIN_HIGH(p, b) (p) |= (1<<(b)) 00463 #define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b)) 00464 00465 #elif defined(__AVR_ATmega2560__) && defined(USE_MEGA_8BIT_SHIELD) 00466 #warning USE_MEGA_8BIT_SHIELD for vagos21 00467 #define RD_PORT PORTL 00468 #define RD_PIN 6 //PL6 (D43). Graham has PA15 (D24) on Due Shield 00469 #define WR_PORT PORTG 00470 #define WR_PIN 2 //D39 CTE 00471 #define CD_PORT PORTD 00472 #define CD_PIN 7 //D38 CTE 00473 #define CS_PORT PORTG 00474 #define CS_PIN 1 //D40 CTE 00475 #define RESET_PORT PORTG 00476 #define RESET_PIN 0 //D41 CTE 00477 00478 #define write_8(x) { PORTA = x;} 00479 00480 #define read_8() ( PINA ) 00481 #define setWriteDir() { DDRA = 0xFF; } 00482 #define setReadDir() { DDRA = 0x00; } 00483 #define write8(x) { write_8(x); WR_ACTIVE; WR_STROBE; } // HX8357-D is slower 00484 #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); } 00485 #define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; } 00486 #define READ_16(dst) { RD_STROBE; dst = read_8(); RD_IDLE; RD_STROBE; dst = (dst<<8) | read_8(); RD_IDLE; } 00487 00488 #define PIN_LOW(p, b) (p) &= ~(1<<(b)) 00489 #define PIN_HIGH(p, b) (p) |= (1<<(b)) 00490 #define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b)) 00491 00492 #elif defined(__AVR_ATmega2560__) && defined(USE_MEGA_8BIT_PROTOSHIELD) 00493 #warning USE_MEGA_8BIT_PROTOSHIELD 00494 #define RD_PORT PORTF 00495 #define RD_PIN 0 00496 #define WR_PORT PORTF 00497 #define WR_PIN 1 00498 #define CD_PORT PORTF 00499 #define CD_PIN 2 00500 #define CS_PORT PORTF 00501 #define CS_PIN 3 00502 #define RESET_PORT PORTF 00503 #define RESET_PIN 4 00504 00505 #define write_8(x) { PORTA = x;} 00506 00507 #define read_8() ( PINA ) 00508 #define setWriteDir() { DDRA = 0xFF; } 00509 #define setReadDir() { DDRA = 0x00; } 00510 #define write8(x) { write_8(x); WR_STROBE; } 00511 #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); } 00512 #define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; } 00513 #define READ_16(dst) { RD_STROBE; dst = read_8(); RD_IDLE; RD_STROBE; dst = (dst<<8) | read_8(); RD_IDLE; } 00514 00515 #define PIN_LOW(p, b) (p) &= ~(1<<(b)) 00516 #define PIN_HIGH(p, b) (p) |= (1<<(b)) 00517 #define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b)) 00518 00519 #elif defined(__AVR_ATmega32U4__) && defined(USE_BLD_BST_MEGA32U4) //regular UNO shield on Leonardo using BST/BLD 00520 #warning regular UNO shield on Leonardo using BST/BLD 00521 #define RD_PORT PORTF 00522 #define RD_PIN 7 00523 #define WR_PORT PORTF 00524 #define WR_PIN 6 00525 #define CD_PORT PORTF 00526 #define CD_PIN 5 00527 #define CS_PORT PORTF 00528 #define CS_PIN 4 00529 #define RESET_PORT PORTF 00530 #define RESET_PIN 1 00531 00532 #define BMASK (3<<4) 00533 #define CMASK (1<<6) 00534 #define DMASK ((1<<7)|(1<<4)|(3<<0)) 00535 #define EMASK (1<<6) 00536 static __attribute((always_inline)) void write_8(uint8_t val) 00537 { 00538 asm volatile("in __tmp_reg__,0x05" "\n\t" 00539 "BST %0,0" "\n\t" "BLD __tmp_reg__,4" "\n\t" 00540 "BST %0,1" "\n\t" "BLD __tmp_reg__,5" "\n\t" 00541 "out 0x05,__tmp_reg__" : : "a" (val)); 00542 asm volatile("in __tmp_reg__,0x0B" "\n\t" 00543 "BST %0,2" "\n\t" "BLD __tmp_reg__,1" "\n\t" 00544 "BST %0,3" "\n\t" "BLD __tmp_reg__,0" "\n\t" 00545 "BST %0,4" "\n\t" "BLD __tmp_reg__,4" "\n\t" 00546 "BST %0,6" "\n\t" "BLD __tmp_reg__,7" "\n\t" 00547 "out 0x0B,__tmp_reg__" : : "a" (val)); 00548 asm volatile("in __tmp_reg__,0x08" "\n\t" 00549 "BST %0,5" "\n\t" "BLD __tmp_reg__,6" "\n\t" 00550 "out 0x08,__tmp_reg__" : : "a" (val)); 00551 asm volatile("in __tmp_reg__,0x0E" "\n\t" 00552 "BST %0,7" "\n\t" "BLD __tmp_reg__,6" "\n\t" 00553 "out 0x0E,__tmp_reg__" : : "a" (val)); 00554 } 00555 #define read_8() ( ((PINB & (3<<4)) >> 4)\ 00556 | ((PIND & (1<<1)) << 1)\ 00557 | ((PIND & (1<<0)) << 3)\ 00558 | ((PIND & (1<<4)) >> 0)\ 00559 | ((PINC & (1<<6)) >> 1)\ 00560 | ((PIND & (1<<7)) >> 1)\ 00561 | ((PINE & (1<<6)) << 1)\ 00562 ) 00563 #define setWriteDir() { DDRB |= BMASK; DDRC |= CMASK; DDRD |= DMASK; DDRE |= EMASK; } 00564 #define setReadDir() { DDRB &= ~BMASK; DDRC &= ~CMASK; DDRD &= ~DMASK; DDRE &= ~EMASK; } 00565 #define write8(x) { write_8(x); WR_STROBE; } 00566 #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); } 00567 #define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; } 00568 #define READ_16(dst) { RD_STROBE; dst = read_8(); RD_IDLE; RD_STROBE; dst = (dst<<8) | read_8(); RD_IDLE; } 00569 00570 #define PIN_LOW(p, b) (p) &= ~(1<<(b)) 00571 #define PIN_HIGH(p, b) (p) |= (1<<(b)) 00572 #define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b)) 00573 00574 #elif defined(__SAM3X8E__) && defined(USE_DUE_8BIT_PROTOSHIELD) //regular UNO shield on DUE 00575 #warning USE_DUE_8BIT_PROTOSHIELD 00576 // configure macros for the control pins 00577 #define RD_PORT PIOA 00578 #define RD_PIN 16 //A0 00579 #define WR_PORT PIOA 00580 #define WR_PIN 24 //A1 00581 #define CD_PORT PIOA 00582 #define CD_PIN 23 //A2 00583 #define CS_PORT PIOA 00584 #define CS_PIN 22 //A3 00585 #define RESET_PORT PIOA 00586 #define RESET_PIN 6 //A4 00587 // configure macros for data bus 00588 #define DMASK (0xFF<<0) 00589 #define write_8(x) { PIOD->PIO_CODR = DMASK; PIOD->PIO_SODR = x; } 00590 00591 #define read_8() ( PIOD->PIO_PDSR & DMASK) 00592 #define setWriteDir() { PIOD->PIO_OER = DMASK; PIOD->PIO_PER = DMASK; } 00593 #define setReadDir() { PMC->PMC_PCER0 = (1 << ID_PIOD); PIOD->PIO_ODR = DMASK;} 00594 #define write8(x) { write_8(x); WR_ACTIVE; WR_STROBE; WR_IDLE; WR_IDLE; } 00595 #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); } 00596 #define READ_8(dst) { RD_STROBE; RD_ACTIVE4; dst = read_8(); RD_IDLE; RD_IDLE; RD_IDLE; } 00597 #define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); } 00598 // Shield Control macros. 00599 #define PIN_LOW(port, pin) (port)->PIO_CODR = (1<<(pin)) 00600 #define PIN_HIGH(port, pin) (port)->PIO_SODR = (1<<(pin)) 00601 #define PIN_OUTPUT(port, pin) (port)->PIO_OER = (1<<(pin)) 00602 00603 #elif defined(__SAM3X8E__) && defined(USE_DUE_16BIT_SHIELD) //regular CTE shield on DUE 00604 #warning USE_DUE_16BIT_SHIELD 00605 #define USES_16BIT_BUS 00606 // configure macros for the control pins 00607 #define RD_PORT PIOA 00608 #define RD_PIN 15 //D24 Graham 00609 #define WR_PORT PIOD 00610 #define WR_PIN 1 //D26 00611 #define CD_PORT PIOD 00612 #define CD_PIN 0 //D25 00613 #define CS_PORT PIOD 00614 #define CS_PIN 2 //D27 00615 #define RESET_PORT PIOD 00616 #define RESET_PIN 3 //D28 00617 // configure macros for data bus 00618 // DB0..DB7 on PIOC1..PIOC8, DB8..DB15 on PIOC12..PIOC19 00619 // 00620 #define CMASKH (0xFF00<<4) 00621 #define CMASKL (0x00FF<<1) 00622 #define CMASK (CMASKH | CMASKL) 00623 #define write_8(x) { PIOC->PIO_CODR = CMASKL; PIOC->PIO_SODR = (((x)&0x00FF)<<1); } 00624 #define write_16(x) { PIOC->PIO_CODR = CMASK; \ 00625 PIOC->PIO_SODR = (((x)&0x00FF)<<1)|(((x)&0xFF00)<<4); } 00626 #define read_16() (((PIOC->PIO_PDSR & CMASKH)>>4)|((PIOC->PIO_PDSR & CMASKL)>>1) ) 00627 #define read_8() (read_16() & 0xFF) 00628 #define setWriteDir() { PIOC->PIO_OER = CMASK; PIOC->PIO_PER = CMASK; } 00629 #define setReadDir() { PMC->PMC_PCER0 = (1 << ID_PIOC); PIOC->PIO_ODR = CMASK; } 00630 #define write8(x) { write16(x & 0xFF); } 00631 #define write16(x) { write_16(x); WR_ACTIVE; WR_STROBE; WR_IDLE; WR_IDLE; } 00632 #define READ_16(dst) { RD_STROBE; RD_ACTIVE4; dst = read_16(); RD_IDLE; RD_IDLE; RD_IDLE; } 00633 #define READ_8(dst) { READ_16(dst); dst &= 0xFF; } 00634 00635 // Shield Control macros. 00636 #define PIN_LOW(port, pin) (port)->PIO_CODR = (1<<(pin)) 00637 #define PIN_HIGH(port, pin) (port)->PIO_SODR = (1<<(pin)) 00638 #define PIN_OUTPUT(port, pin) (port)->PIO_OER = (1<<(pin)) 00639 00640 #elif defined(__SAM3X8E__) && defined(USE_ELECHOUSE_DUE_16BIT_SHIELD) //ELECHOUSE_DUE shield on DUE 00641 #warning USE_ELECHOUSE_DUE_16BIT_SHIELD 00642 #define USES_16BIT_BUS 00643 // configure macros for the control pins 00644 #define RD_PORT PIOA 00645 #define RD_PIN 15 //D24 Graham 00646 #define WR_PORT PIOA 00647 #define WR_PIN 14 //D23 00648 #define CD_PORT PIOB 00649 #define CD_PIN 26 //D22 00650 #define CS_PORT PIOA 00651 #define CS_PIN 7 //D31 00652 #define RESET_PORT PIOC 00653 #define RESET_PIN 1 //D33 00654 // configure macros for data bus 00655 // DB0..DB7 on PIOC2..PIOC9, DB8..DB15 on PIOC12..PIOC19 00656 // 00657 #define CMASKH (0xFF00<<4) 00658 #define CMASKL (0x00FF<<2) 00659 #define CMASK (CMASKH | CMASKL) 00660 #define write_8(x) { PIOC->PIO_CODR = CMASKL; PIOC->PIO_SODR = (((x)&0x00FF)<<2); } 00661 #define write_16(x) { PIOC->PIO_CODR = CMASK; \ 00662 PIOC->PIO_SODR = (((x)&0x00FF)<<2)|(((x)&0xFF00)<<4); } 00663 #define read_16() (((PIOC->PIO_PDSR & CMASKH)>>4)|((PIOC->PIO_PDSR & CMASKL)>>2) ) 00664 #define read_8() (read_16() & 0xFF) 00665 #define setWriteDir() { PIOC->PIO_OER = CMASK; PIOC->PIO_PER = CMASK; } 00666 #define setReadDir() { PMC->PMC_PCER0 = (1 << ID_PIOC); PIOC->PIO_ODR = CMASK; } 00667 #define write8(x) { write16(x & 0xFF); } 00668 #define write16(x) { write_16(x); WR_ACTIVE; WR_STROBE; WR_IDLE; WR_IDLE; } 00669 #define READ_16(dst) { RD_STROBE; RD_ACTIVE4; dst = read_16(); RD_IDLE; RD_IDLE; RD_IDLE; } 00670 #define READ_8(dst) { READ_16(dst); dst &= 0xFF; } 00671 00672 // Shield Control macros. 00673 #define PIN_LOW(port, pin) (port)->PIO_CODR = (1<<(pin)) 00674 #define PIN_HIGH(port, pin) (port)->PIO_SODR = (1<<(pin)) 00675 #define PIN_OUTPUT(port, pin) (port)->PIO_OER = (1<<(pin)) 00676 00677 #elif defined(__SAM3X8E__) && defined(USE_MEGA_16BIT_SHIELD) //regular MEGA shield on DUE 00678 #warning USE_MEGA_16BIT_SHIELD 00679 #define USES_16BIT_BUS 00680 // configure macros for the control pins 00681 #define RD_PORT PIOA 00682 #define RD_PIN 20 //D43 00683 #define WR_PORT PIOC 00684 #define WR_PIN 7 //D39 00685 #define CD_PORT PIOC 00686 #define CD_PIN 6 //D38 00687 #define CS_PORT PIOC 00688 #define CS_PIN 8 //D40 00689 #define RESET_PORT PIOC 00690 #define RESET_PIN 9 //D41 00691 // configure macros for data bus 00692 // 00693 #define AMASK ((1<<7)|(3<<14)) //PA7, PA14-PA15 00694 #define BMASK (1<<26) //PB26 00695 #define CMASK (31<<1) //PC1-PC5 00696 #define DMASK ((15<<0)|(1<<6)|(3<<9)) //PD0-PD3, PD6, PD9-PD10 00697 00698 #define write_16(x) { PIOA->PIO_CODR = AMASK; PIOB->PIO_CODR = BMASK; PIOC->PIO_CODR = CMASK; PIOD->PIO_CODR = DMASK; \ 00699 PIOA->PIO_SODR = (((x)&(1<<6))<<1)|(((x)&(3<<9))<<5); \ 00700 PIOB->PIO_SODR = (((x)&(1<<8))<<18); \ 00701 PIOC->PIO_SODR = (((x)&(1<<0))<<5); \ 00702 PIOC->PIO_SODR = (((x)&(1<<1))<<3); \ 00703 PIOC->PIO_SODR = (((x)&(1<<2))<<1); \ 00704 PIOC->PIO_SODR = (((x)&(1<<3))>>1); \ 00705 PIOC->PIO_SODR = (((x)&(1<<4))>>3); \ 00706 PIOD->PIO_SODR = (((x)&(1<<7))<<2)|(((x)&(1<<5))<<5)|(((x)&(15<<11))>>11)|(((x)&(1<<15))>>9); \ 00707 } 00708 00709 /* 00710 #define write_16(VL) { PIOA->PIO_CODR = AMASK; PIOC->PIO_CODR = CMASK; PIOD->PIO_CODR = DMASK; \ 00711 REG_PIOA_SODR=((((VL)>>8) & 0x06)<<13) | ((VL & 0x40)<<1);\ 00712 if ((VL)&(1<<8)) REG_PIOB_SODR=(1<<26); else REG_PIOB_CODR=(1<<26);\ 00713 REG_PIOC_SODR=((VL & 0x01)<<5) | ((VL & 0x02)<<3) | ((VL & 0x04)<<1) | ((VL & 0x08)>>1) | ((VL & 0x10)>>3);\ 00714 REG_PIOD_SODR=((((VL)>>8) & 0x78)>>3) | ((((VL)>>8) & 0x80)>>1) | ((VL & 0x20)<<5) | ((VL & 0x80)<<2);\ 00715 } 00716 */ 00717 #define read_16() ( 0\ 00718 |((PIOC->PIO_PDSR & (1<<5))>>5)\ 00719 |((PIOC->PIO_PDSR & (1<<4))>>3)\ 00720 |((PIOC->PIO_PDSR & (1<<3))>>1)\ 00721 |((PIOC->PIO_PDSR & (1<<2))<<1)\ 00722 |((PIOC->PIO_PDSR & (1<<1))<<3)\ 00723 |((PIOD->PIO_PDSR & (1<<10))>>5)\ 00724 |((PIOA->PIO_PDSR & (1<<7))>>1)\ 00725 |((PIOD->PIO_PDSR & (1<<9))>>2)\ 00726 |((PIOB->PIO_PDSR & (1<<26))>>18)\ 00727 |((PIOA->PIO_PDSR & (3<<14))>>5)\ 00728 |((PIOD->PIO_PDSR & (15<<0))<<11)\ 00729 |((PIOD->PIO_PDSR & (1<<6))<<9)\ 00730 ) 00731 #define read_8() (read_16() & 0xFF) 00732 #define setWriteDir() {\ 00733 PIOA->PIO_OER = AMASK; PIOA->PIO_PER = AMASK; \ 00734 PIOB->PIO_OER = BMASK; PIOB->PIO_PER = BMASK; \ 00735 PIOC->PIO_OER = CMASK; PIOC->PIO_PER = CMASK; \ 00736 PIOD->PIO_OER = DMASK; PIOD->PIO_PER = DMASK; \ 00737 } 00738 #define setReadDir() { \ 00739 PMC->PMC_PCER0 = (1 << ID_PIOA)|(1 << ID_PIOB)|(1 << ID_PIOC)|(1 << ID_PIOD); \ 00740 PIOA->PIO_ODR = AMASK; \ 00741 PIOB->PIO_ODR = BMASK; \ 00742 PIOC->PIO_ODR = CMASK; \ 00743 PIOD->PIO_ODR = DMASK; \ 00744 } 00745 #define write8(x) { write16(x & 0xFF); } 00746 // ILI9486 is slower than ILI9481 00747 #define write16(x) { write_16(x); WR_ACTIVE8; WR_STROBE; WR_IDLE4;} 00748 #define READ_16(dst) { RD_STROBE; RD_ACTIVE4; dst = read_16(); RD_IDLE; RD_IDLE; RD_IDLE; } 00749 #define READ_8(dst) { READ_16(dst); dst &= 0xFF; } 00750 00751 // Shield Control macros. 00752 #define PIN_LOW(port, pin) (port)->PIO_CODR = (1<<(pin)) 00753 #define PIN_HIGH(port, pin) (port)->PIO_SODR = (1<<(pin)) 00754 #define PIN_OUTPUT(port, pin) (port)->PIO_OER = (1<<(pin)) 00755 00756 #elif defined(__SAM3X8E__) && defined(USE_MEGA_8BIT_SHIELD) //regular CTE shield on DUE 00757 #warning USE_MEGA_8BIT_SHIELD for peloxp 00758 // configure macros for the control pins 00759 #define RD_PORT PIOA 00760 #define RD_PIN 20 //D43 00761 #define WR_PORT PIOC 00762 #define WR_PIN 7 //D39 00763 #define CD_PORT PIOC 00764 #define CD_PIN 6 //D38 00765 #define CS_PORT PIOC 00766 #define CS_PIN 8 //D40 00767 #define RESET_PORT PIOC 00768 #define RESET_PIN 9 //D41 00769 // configure macros for data bus 00770 // 00771 #define AMASK ((3<<14)) //PA14-PA15 D23-D24 00772 #define BMASK (1<<26) //PB26 D22 00773 #define DMASK ((15<<0)|(1<<6)) //PD0-PD3, PD6 D25-D28,D29 00774 00775 #define write_8(x) { PIOA->PIO_CODR = AMASK; PIOB->PIO_CODR = BMASK; PIOD->PIO_CODR = DMASK; \ 00776 PIOB->PIO_SODR = (((x)&(1<<0))<<26); \ 00777 PIOA->PIO_SODR = (((x)&(3<<1))<<13); \ 00778 PIOD->PIO_SODR = (((x)&(15<<3))>>3); \ 00779 PIOD->PIO_SODR = (((x)&(1<<7))>>1); \ 00780 } 00781 00782 #define read_8() ( 0\ 00783 |((PIOB->PIO_PDSR & (1<<26))>>26)\ 00784 |((PIOA->PIO_PDSR & (3<<14))>>13)\ 00785 |((PIOD->PIO_PDSR & (15<<0))<<3)\ 00786 |((PIOD->PIO_PDSR & (1<<6))<<1)\ 00787 ) 00788 00789 #define setWriteDir() {\ 00790 PIOA->PIO_OER = AMASK; PIOA->PIO_PER = AMASK; \ 00791 PIOB->PIO_OER = BMASK; PIOB->PIO_PER = BMASK; \ 00792 PIOD->PIO_OER = DMASK; PIOD->PIO_PER = DMASK; \ 00793 } 00794 #define setReadDir() { \ 00795 PMC->PMC_PCER0 = (1 << ID_PIOA)|(1 << ID_PIOB)|(1 << ID_PIOC)|(1 << ID_PIOD); \ 00796 PIOA->PIO_ODR = AMASK; \ 00797 PIOB->PIO_ODR = BMASK; \ 00798 PIOD->PIO_ODR = DMASK; \ 00799 } 00800 00801 // ILI9486 is slower than ILI9481. HX8357-D is slower 00802 #define write8(x) { write_8(x); WR_ACTIVE4; WR_STROBE; WR_IDLE; WR_IDLE; } 00803 #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); } 00804 #define READ_8(dst) { RD_STROBE; RD_ACTIVE4; dst = read_8(); RD_IDLE; RD_IDLE; RD_IDLE; } 00805 #define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); } 00806 00807 // Shield Control macros. 00808 #define PIN_LOW(port, pin) (port)->PIO_CODR = (1<<(pin)) 00809 #define PIN_HIGH(port, pin) (port)->PIO_SODR = (1<<(pin)) 00810 #define PIN_OUTPUT(port, pin) (port)->PIO_OER = (1<<(pin)) 00811 00812 #elif defined(__MK20DX256__) && defined(USE_BOBCACHELOT_TEENSY) // special for BOBCACHEALOT_TEENSY 00813 #warning special for BOBCACHEALOT_TEENSY 00814 #define RD_PORT GPIOD 00815 #define RD_PIN 1 00816 #define WR_PORT GPIOC 00817 #define WR_PIN 0 00818 #define CD_PORT GPIOB 00819 #define CD_PIN 0 00820 #define CS_PORT GPIOB 00821 #define CS_PIN 1 00822 #define RESET_PORT GPIOB 00823 #define RESET_PIN 3 00824 00825 // configure macros for the data pins 00826 #define CMASK ((1<<3)) 00827 #define DMASK ((1<<0)|(1<<2)|(1<<3)|(1<<4)|(1<<5)|(1<<6)|(1<<7)) 00828 00829 #define write_8(d) { \ 00830 GPIOC_PCOR = CMASK; GPIOD_PCOR = DMASK; \ 00831 GPIOC_PSOR = (((d) & (1<<1)) << 2); \ 00832 GPIOD_PSOR = (d) & DMASK; \ 00833 } 00834 #define read_8() ( (GPIOD_PDIR & DMASK) | (GPIOC_PDIR & (1<<3)) >> 2 ) 00835 #define setWriteDir() {GPIOC_PDDR |= CMASK;GPIOD_PDDR |= DMASK; } 00836 #define setReadDir() {GPIOC_PDDR &= ~CMASK;GPIOD_PDDR &= ~DMASK; } 00837 00838 #define write8(x) { write_8(x); WR_STROBE; } 00839 #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); } 00840 #define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; } 00841 #define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); } 00842 00843 #define PASTE(x, y) x ## y 00844 00845 #define PIN_LOW(port, pin) PASTE(port, _PCOR) = (1<<(pin)) 00846 #define PIN_HIGH(port, pin) PASTE(port, _PSOR) = (1<<(pin)) 00847 #define PIN_OUTPUT(port, pin) PASTE(port, _PDDR) |= (1<<(pin)) 00848 00849 #elif defined(USE_MY_BLUEPILL) && (defined(ARDUINO_GENERIC_STM32F103C) || defined(ARDUINO_BLUEPILL_F103C8)) 00850 #warning Uno Shield on MY BLUEPILL 00851 00852 //LCD pins |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 | |RD |WR |RS |CS |RST| |SD_SS|SD_DI|SD_DO|SD_SCK| |SDA|SCL| 00853 //STM32 pin |PA3 |PA2 |PA1|PA0|PB7|PB6|PA10|PA9| |PB1|PB0|PA7|PA6|PA5| |PB12 |PB15 |PB14 |PB13 | |PB9|PB8| 00854 00855 #if defined(ARDUINO_BLUEPILL_F103C8) //regular CMSIS libraries 00856 #define REGS(x) x 00857 #define GPIO_INIT() { RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | RCC_APB2ENR_AFIOEN; \ 00858 AFIO->MAPR |= AFIO_MAPR_SWJ_CFG_1;} 00859 #else //weird Maple libraries 00860 #define REGS(x) regs->x 00861 #endif 00862 00863 #define WRITE_DELAY { } 00864 #define READ_DELAY { RD_ACTIVE; } 00865 #define GROUP_MODE(port, reg, mask, val) {port->REGS(reg) = (port->REGS(reg) & ~(mask)) | ((mask)&(val)); } 00866 #define GP_OUT(port, reg, mask) GROUP_MODE(port, reg, mask, 0x33333333) 00867 #define GP_INP(port, reg, mask) GROUP_MODE(port, reg, mask, 0x44444444) 00868 #define PIN_OUTPUT(port, pin) {\ 00869 if (pin < 8) {GP_OUT(port, CRL, 0xF<<((pin)<<2));} \ 00870 else {GP_OUT(port, CRH, 0xF<<((pin&7)<<2));} \ 00871 } 00872 #define PIN_INPUT(port, pin) { \ 00873 if (pin < 8) { GP_INP(port, CRL, 0xF<<((pin)<<2)); } \ 00874 else { GP_INP(port, CRH, 0xF<<((pin&7)<<2)); } \ 00875 } 00876 #define PIN_HIGH(port, pin) (port)-> REGS(BSRR) = (1<<(pin)) 00877 #define PIN_LOW(port, pin) (port)-> REGS(BSRR) = (1<<((pin)+16)) 00878 00879 #define RD_PORT GPIOB 00880 #define RD_PIN 1 00881 #define WR_PORT GPIOB 00882 #define WR_PIN 0 00883 #define CD_PORT GPIOA 00884 #define CD_PIN 7 00885 #define CS_PORT GPIOA 00886 #define CS_PIN 6 00887 #define RESET_PORT GPIOA 00888 #define RESET_PIN 5 00889 00890 // configure macros for the data pins 00891 #define AMASK 0x060F 00892 #define BMASK 0x00C0 00893 #define write_8(d) { GPIOA->REGS(BSRR) = AMASK << 16; GPIOB->REGS(BSRR) = BMASK << 16; \ 00894 GPIOA->REGS(BSRR) = (((d) & 3) << 9) | (((d) & 0xF0) >> 4); \ 00895 GPIOB->REGS(BSRR) = (((d) & 0x0C) << 4); \ 00896 } 00897 #define read_8() (((GPIOA->REGS(IDR) & (3<<9)) >> 9) | ((GPIOA->REGS(IDR) & (0x0F)) << 4) | ((GPIOB->REGS(IDR) & (3<<6)) >> 4)) 00898 // PA10,PA9 PA3-PA0 PB7,PB6 00899 #define setWriteDir() {GP_OUT(GPIOA, CRH, 0xFF0); GP_OUT(GPIOA, CRL, 0xFFFF); GP_OUT(GPIOB, CRL, 0xFF000000); } 00900 #define setReadDir() {GP_INP(GPIOA, CRH, 0xFF0); GP_INP(GPIOA, CRL, 0xFFFF); GP_INP(GPIOB, CRL, 0xFF000000); } 00901 00902 #define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; } 00903 #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); } 00904 #define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE; } 00905 #define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); } 00906 00907 //####################################### ADIGITALEU_TEENSY ############################ 00908 //UNTESTED 00909 #elif defined(__MK66FX1M0__) && defined(USE_ADIGITALEU_TEENSY) // 16bit on a Teensy 3.6 00910 #warning "Teensy 3.6 16bit port C & D only (for now)" 00911 // Note: Port usage explained in UTFT Teensy edition ...\libraries\UTFT\hardware\arm\HW_Teensy3.h" 00912 00913 #define USES_16BIT_BUS 00914 00915 #define WRITE_DELAY { WR_ACTIVE8; } 00916 #define READ_DELAY { RD_ACTIVE16; } 00917 00918 #define RD_PORT GPIOA 00919 #define RD_PIN 16 //28 RD 00920 #define WR_PORT GPIOA 00921 #define WR_PIN 5 //25 WR 00922 #define CD_PORT GPIOE 00923 #define CD_PIN 26 //24 RS 00924 #define CS_PORT GPIOA 00925 #define CS_PIN 14 //26 CS 00926 #define RESET_PORT GPIOA 00927 #define RESET_PIN 15 //27 Reset 00928 00929 #define write_8(d) { GPIOC_PDOR = d; } 00930 #define write_16(d) { GPIOC_PDOR = d; GPIOD_PDOR = (d >> 8);} 00931 00932 #define read_8() (GPIOC_PDIR) 00933 #define read_16() (GPIOC_PDIR | GPIOD_PDIR << 8) 00934 00935 #define setWriteDir() {GPIOC_PDDR |= 0xFF; GPIOD_PDDR |= 0xFF; } 00936 #define setReadDir() {GPIOC_PDDR &= ~0xFF; GPIOD_PDDR &= ~0xFF; } 00937 00938 #define write8(x) {write_8(x); WRITE_DELAY; WR_STROBE } 00939 #define write16(x) {write_16(x); WRITE_DELAY; WR_STROBE } 00940 00941 #define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE; } 00942 #define READ_16(dst) { RD_STROBE; READ_DELAY; dst = read_16(); RD_IDLE;} 00943 00944 //Data: Teensy pins -> D0-D15 : 00945 // Teensy probably initialises some pins for Analog, Timer, Alternate, ... 00946 // so it is probably wise to use pinMode(n, OUTPUT) for all the control and data lines 00947 #define GPIO_INIT() {pinMode(2, OUTPUT); for (int i = 5; i <= 15; i++) pinMode(i, OUTPUT); for (int i = 20; i <= 28; i++) pinMode(i, OUTPUT);} 00948 00949 #define PASTE(x, y) x ## y 00950 00951 #define PIN_LOW(port, pin) PASTE(port, _PCOR) = (1<<(pin)) 00952 #define PIN_HIGH(port, pin) PASTE(port, _PSOR) = (1<<(pin)) 00953 #define PIN_OUTPUT(port, pin) PASTE(port, _PDDR) |= (1<<(pin)) 00954 00955 #else 00956 #define USE_SPECIAL_FAIL 00957 #endif
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