enc28j60.h

00001 #ifndef ENC28J60_H
00002 #define ENC28J60_H
00003 
00004 #include "mbed.h"
00005 
00006 typedef unsigned char u8;
00007 typedef unsigned short int u16;
00008 //typedef unsigned int u32;
00009 
00010 // ENC28J60 Control Registers
00011 // Control register definitions are a combination of address,
00012 // bank number, and Ethernet/MAC/PHY indicator bits.
00013 // - Register address   (bits 0-4)
00014 // - Bank number        (bits 5-6)
00015 // - MAC/PHY indicator  (bit 7)
00016 #define ADDR_MASK   0x1F
00017 #define BANK_MASK   0x60
00018 #define SPRD_MASK   0x80
00019 // All-bank registers
00020 #define EIE         0x1B
00021 #define EIR         0x1C
00022 #define ESTAT       0x1D
00023 #define ECON2       0x1E
00024 #define ECON1       0x1F
00025 // Bank 0 registers
00026 #define ERDPTL      (0x00|0x00)
00027 #define ERDPTH      (0x01|0x00)
00028 #define EWRPTL      (0x02|0x00)
00029 #define EWRPTH      (0x03|0x00)
00030 #define ETXSTL      (0x04|0x00)
00031 #define ETXSTH      (0x05|0x00)
00032 #define ETXNDL      (0x06|0x00)
00033 #define ETXNDH      (0x07|0x00)
00034 #define ERXSTL      (0x08|0x00)
00035 #define ERXSTH      (0x09|0x00)
00036 #define ERXNDL      (0x0A|0x00)
00037 #define ERXNDH      (0x0B|0x00)
00038 #define ERXRDPTL    (0x0C|0x00)
00039 #define ERXRDPTH    (0x0D|0x00)
00040 #define ERXWRPTL    (0x0E|0x00)
00041 #define ERXWRPTH    (0x0F|0x00)
00042 #define EDMASTL     (0x10|0x00)
00043 #define EDMASTH     (0x11|0x00)
00044 #define EDMANDL     (0x12|0x00)
00045 #define EDMANDH     (0x13|0x00)
00046 #define EDMADSTL    (0x14|0x00)
00047 #define EDMADSTH    (0x15|0x00)
00048 #define EDMACSL     (0x16|0x00)
00049 #define EDMACSH     (0x17|0x00)
00050 // Bank 1 registers
00051 #define EHT0        (0x00|0x20)
00052 #define EHT1        (0x01|0x20)
00053 #define EHT2        (0x02|0x20)
00054 #define EHT3        (0x03|0x20)
00055 #define EHT4        (0x04|0x20)
00056 #define EHT5        (0x05|0x20)
00057 #define EHT6        (0x06|0x20)
00058 #define EHT7        (0x07|0x20)
00059 #define EPMM0       (0x08|0x20)
00060 #define EPMM1       (0x09|0x20)
00061 #define EPMM2       (0x0A|0x20)
00062 #define EPMM3       (0x0B|0x20)
00063 #define EPMM4       (0x0C|0x20)
00064 #define EPMM5       (0x0D|0x20)
00065 #define EPMM6       (0x0E|0x20)
00066 #define EPMM7       (0x0F|0x20)
00067 #define EPMCSL      (0x10|0x20)
00068 #define EPMCSH      (0x11|0x20)
00069 #define EPMOL       (0x14|0x20)
00070 #define EPMOH       (0x15|0x20)
00071 #define EWOLIE      (0x16|0x20)
00072 #define EWOLIR      (0x17|0x20)
00073 #define ERXFCON     (0x18|0x20)
00074 #define EPKTCNT     (0x19|0x20)
00075 // Bank 2 registers
00076 #define MACON1      (0x00|0x40|0x80)
00077 #define MACON2      (0x01|0x40|0x80)
00078 #define MACON3      (0x02|0x40|0x80)
00079 #define MACON4      (0x03|0x40|0x80)
00080 #define MABBIPG     (0x04|0x40|0x80)
00081 #define MAIPGL      (0x06|0x40|0x80)
00082 #define MAIPGH      (0x07|0x40|0x80)
00083 #define MACLCON1    (0x08|0x40|0x80)
00084 #define MACLCON2    (0x09|0x40|0x80)
00085 #define MAMXFLL     (0x0A|0x40|0x80)
00086 #define MAMXFLH     (0x0B|0x40|0x80)
00087 #define MAPHSUP     (0x0D|0x40|0x80)
00088 #define MICON       (0x11|0x40|0x80)
00089 #define MICMD       (0x12|0x40|0x80)
00090 #define MIREGADR    (0x14|0x40|0x80)
00091 #define MIWRL       (0x16|0x40|0x80)
00092 #define MIWRH       (0x17|0x40|0x80)
00093 #define MIRDL       (0x18|0x40|0x80)
00094 #define MIRDH       (0x19|0x40|0x80)
00095 // Bank 3 registers
00096 #define MAADR1      (0x00|0x60|0x80)
00097 #define MAADR0      (0x01|0x60|0x80)
00098 #define MAADR3      (0x02|0x60|0x80)
00099 #define MAADR2      (0x03|0x60|0x80)
00100 #define MAADR5      (0x04|0x60|0x80)
00101 #define MAADR4      (0x05|0x60|0x80)
00102 #define EBSTSD      (0x06|0x60)
00103 #define EBSTCON     (0x07|0x60)
00104 #define EBSTCSL     (0x08|0x60)
00105 #define EBSTCSH     (0x09|0x60)
00106 #define MISTAT      (0x0A|0x60|0x80)
00107 #define EREVID      (0x12|0x60)
00108 #define ECOCON      (0x15|0x60)
00109 #define EFLOCON     (0x17|0x60)
00110 #define EPAUSL      (0x18|0x60)
00111 #define EPAUSH      (0x19|0x60)
00112 // PHY registers
00113 #define PHCON1      0x00
00114 #define PHSTAT1     0x01
00115 #define PHHID1      0x02
00116 #define PHHID2      0x03
00117 #define PHCON2      0x10
00118 #define PHSTAT2     0x11
00119 #define PHIE        0x12
00120 #define PHIR        0x13
00121 #define PHLCON      0x14
00122 
00123 // ENC28J60 EIE Register Bit Definitions
00124 #define EIE_INTIE       0x80
00125 #define EIE_PKTIE       0x40
00126 #define EIE_DMAIE       0x20
00127 #define EIE_LINKIE      0x10
00128 #define EIE_TXIE        0x08
00129 #define EIE_WOLIE       0x04
00130 #define EIE_TXERIE      0x02
00131 #define EIE_RXERIE      0x01
00132 // ENC28J60 EIR Register Bit Definitions
00133 #define EIR_PKTIF       0x40
00134 #define EIR_DMAIF       0x20
00135 #define EIR_LINKIF      0x10
00136 #define EIR_TXIF        0x08
00137 #define EIR_WOLIF       0x04
00138 #define EIR_TXERIF      0x02
00139 #define EIR_RXERIF      0x01
00140 // ENC28J60 ESTAT Register Bit Definitions
00141 #define ESTAT_INT       0x80
00142 #define ESTAT_LATECOL   0x10
00143 #define ESTAT_RXBUSY    0x04
00144 #define ESTAT_TXABRT    0x02
00145 #define ESTAT_CLKRDY    0x01
00146 // ENC28J60 ECON2 Register Bit Definitions
00147 #define ECON2_AUTOINC   0x80
00148 #define ECON2_PKTDEC    0x40
00149 #define ECON2_PWRSV     0x20
00150 #define ECON2_VRPS      0x08
00151 // ENC28J60 ECON1 Register Bit Definitions
00152 #define ECON1_TXRST     0x80
00153 #define ECON1_RXRST     0x40
00154 #define ECON1_DMAST     0x20
00155 #define ECON1_CSUMEN    0x10
00156 #define ECON1_TXRTS     0x08
00157 #define ECON1_RXEN      0x04
00158 #define ECON1_BSEL1     0x02
00159 #define ECON1_BSEL0     0x01
00160 // ENC28J60 MACON1 Register Bit Definitions
00161 #define MACON1_LOOPBK   0x10
00162 #define MACON1_TXPAUS   0x08
00163 #define MACON1_RXPAUS   0x04
00164 #define MACON1_PASSALL  0x02
00165 #define MACON1_MARXEN   0x01
00166 // ENC28J60 MACON2 Register Bit Definitions
00167 #define MACON2_MARST    0x80
00168 #define MACON2_RNDRST   0x40
00169 #define MACON2_MARXRST  0x08
00170 #define MACON2_RFUNRST  0x04
00171 #define MACON2_MATXRST  0x02
00172 #define MACON2_TFUNRST  0x01
00173 // ENC28J60 MACON3 Register Bit Definitions
00174 #define MACON3_PADCFG2  0x80
00175 #define MACON3_PADCFG1  0x40
00176 #define MACON3_PADCFG0  0x20
00177 #define MACON3_TXCRCEN  0x10
00178 #define MACON3_PHDRLEN  0x08
00179 #define MACON3_HFRMLEN  0x04
00180 #define MACON3_FRMLNEN  0x02
00181 #define MACON3_FULDPX   0x01
00182 // ENC28J60 MICMD Register Bit Definitions
00183 #define MICMD_MIISCAN   0x02
00184 #define MICMD_MIIRD     0x01
00185 // ENC28J60 MISTAT Register Bit Definitions
00186 #define MISTAT_NVALID   0x04
00187 #define MISTAT_SCAN     0x02
00188 #define MISTAT_BUSY     0x01
00189 // ENC28J60 PHY PHCON1 Register Bit Definitions
00190 #define PHCON1_PRST     0x8000
00191 #define PHCON1_PLOOPBK  0x4000
00192 #define PHCON1_PPWRSV   0x0800
00193 #define PHCON1_PDPXMD   0x0100
00194 // ENC28J60 PHY PHSTAT1 Register Bit Definitions
00195 #define PHSTAT1_PFDPX   0x1000
00196 #define PHSTAT1_PHDPX   0x0800
00197 #define PHSTAT1_LLSTAT  0x0004
00198 #define PHSTAT1_JBSTAT  0x0002
00199 // ENC28J60 PHY PHCON2 Register Bit Definitions
00200 #define PHCON2_FRCLINK  0x4000
00201 #define PHCON2_TXDIS    0x2000
00202 #define PHCON2_JABBER   0x0400
00203 #define PHCON2_HDLDIS   0x0100
00204 
00205 // ENC28J60 Packet Control Byte Bit Definitions
00206 #define PKTCTRL_PHUGEEN     0x08
00207 #define PKTCTRL_PPADEN      0x04
00208 #define PKTCTRL_PCRCEN      0x02
00209 #define PKTCTRL_POVERRIDE   0x01
00210 
00211 // SPI operation codes
00212 #define ENC28J60_READ_CTRL_REG  0x00
00213 #define ENC28J60_READ_BUF_MEM   0x3A
00214 #define ENC28J60_WRITE_CTRL_REG 0x40
00215 #define ENC28J60_WRITE_BUF_MEM  0x7A
00216 #define ENC28J60_BIT_FIELD_SET  0x80
00217 #define ENC28J60_BIT_FIELD_CLR  0xA0
00218 #define ENC28J60_SOFT_RESET     0xFF
00219 
00220 
00221 // buffer boundaries applied to internal 8K ram
00222 //  entire available packet buffer space is allocated
00223 //#define TXSTART_INIT      0x0000  // start TX buffer at 0
00224 //#define RXSTART_INIT      0x0600  // give TX buffer space for one full ethernet frame (~1500 bytes)
00225 //#define RXSTOP_INIT       0x1FFF  // receive buffer gets the rest
00226 #define TXSTART_INIT    0x1A00  // start TX buffer at 0
00227 #define RXSTART_INIT    0x0000  // give TX buffer space for one full ethernet frame (~1500 bytes)
00228 #define RXSTOP_INIT     0x19FF  // receive buffer gets the rest
00229 
00230 #define MAX_FRAMELEN    1518    // maximum ethernet frame length
00231 
00232 // Ethernet constants
00233 #define ETHERNET_MIN_PACKET_LENGTH  0x3C
00234 //#define ETHERNET_HEADER_LENGTH        0x0E
00235 
00236 #define ENC28J60_CONTROL_PORT   PORTB
00237 #define ENC28J60_CONTROL_DDR    DDRB
00238 #define ENC28J60_CONTROL_CS     0
00239 
00240 class ENC28J60 {
00241 public:
00242 
00243 ENC28J60(SPI* _spi, PinName _cs, PinName _int);
00244 
00245 protected:
00246 
00247 //! do a ENC28J60 read operation
00248 u8 readOp(u8 op, u8 address);
00249 //! do a ENC28J60 write operation
00250 void writeOp(u8 op, u8 address, u8 data);
00251 //! read the packet buffer memory
00252 void readBuffer(u16 len, u8* data);
00253 //! write the packet buffer memory
00254 void writeBuffer(u16 len, u8* data);
00255 //! set the register bank for register at address
00256 void setBank(u8 address);
00257 //! read ax88796 register
00258 u8 read(u8 address);
00259 //! write ax88796 register
00260 void write(u8 address, u8 data);
00261 //! read a PHY register
00262 u16 phyRead(u8 address);
00263 //! write a PHY register
00264 void phyWrite(u8 address, u16 data);
00265 
00266 public:
00267 
00268 //! initialize the ethernet interface for transmit/receive
00269 void init(void);
00270 
00271 //! Packet transmit function.
00272 /// Sends a packet on the network.  It is assumed that the packet is headed by a valid ethernet header.
00273 /// \param len      Length of packet in bytes.
00274 /// \param packet   Pointer to packet data.
00275 void packetSend(unsigned int len, unsigned char* packet);
00276 void packetSend2(unsigned int len1, unsigned char* packet1, unsigned int len2, unsigned char* packet2);
00277 
00278 //! Packet receive function.
00279 /// Gets a packet from the network receive buffer, if one is available.
00280 /// The packet will by headed by an ethernet header.
00281 /// \param  maxlen  The maximum acceptable length of a retrieved packet.
00282 /// \param  packet  Pointer where packet data should be stored.
00283 /// \return Packet length in bytes if a packet was retrieved, zero otherwise.
00284 unsigned int packetReceive(unsigned int maxlen, unsigned char* packet);
00285 
00286 //! execute procedure for recovering from a receive overflow
00287 /// this should be done when the receive memory fills up with packets
00288 void receiveOverflowRecover(void);
00289 
00290 //! formatted print of important ENC28J60 registers
00291 void regDump(void);
00292 
00293 protected:
00294     SPI* spi;
00295     DigitalOut cs_pin;
00296     DigitalIn int_pin;
00297 
00298 };
00299 
00300 #endif