rau cha
fix for mbed lib issue 3 (i2c problem) see also https://mbed.org/users/mbed_official/code/mbed/issues/3 affected implementations: LPC812, LPC11U24, LPC1768, LPC2368, LPC4088
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Core Debug Registers (CoreDebug)
[Defines and Type Definitions]
Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. More...
Data Structures | |
| struct | CoreDebug_Type |
| Structure type to access the Core Debug Register (CoreDebug). More... | |
Detailed Description
Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Type definitions for the Core Debug Registers.
Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M0 header file.
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