不韋 呂
CQエレクトロニクス･セミナ「実習・マイコンを動かしながら学ぶディジタル･フィルタ」で使うプログラムを，入力として STM32F746 の内蔵 ADC を使うように変更したもの． http://seminar.cqpub.co.jp/ccm/ES18-0020
Dependencies: mbed Array_Matrix BSP_DISCO_F746NG LCD_DISCO_F746NG TS_DISCO_F746NG
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F746_ADC.hpp
00001 //---------------------------------------------------------- 00002 // Simultanuous AD Conversion by polling using 00003 // ADC1 and ADC3 on STM32F746 ---- Header 00004 // 00005 // STM32F746 の ADC1, ADC3 を使って同時に AD 変換を開始し， 00006 // ポーリングによりアナログ信号を入力するクラス 00007 // PA_0 (DISCO-F746 の A0) : ADC1 CH0 00008 // PF_10 (DISCO-F746 の A1) : ADC3 CH8 00009 // 00010 // Read() の引数： 00011 // 第一引数：A0 (左)，第二引数：A1 (右) 00012 // 00013 // 2017/08/16, Copyright (c) 2017 MIKAMI, Naoki 00014 //---------------------------------------------------------- 00015 00016 #include "mbed.h" 00017 00018 #ifndef STM32F746xx 00019 #error Target is not STM32F746 00020 #endif 00021 00022 #ifndef F746_ADC_DUAL_HPP 00023 #define F746_ADC_DUAL_HPP 00024 00025 namespace Mikami 00026 { 00027 class AdcDual 00028 { 00029 public: 00030 // Constructor 00031 // frequency: 標本化周波数 00032 explicit AdcDual(int frequency); 00033 00034 virtual ~AdcDual() {} 00035 00036 // -1.0f <= ad1, ad2 <= 1.0f 00037 // ad1: left, ad2: right 00038 virtual void Read(float &ad1, float &ad2); 00039 00040 // 0 <= ad1, ad2 <= 4095 00041 // ad1: left, ad2: right 00042 virtual void Read(uint16_t &ad1, uint16_t &ad2); 00043 00044 protected: 00045 float ToFloat(uint16_t x) 00046 { return AMP_*(x - 2048); } 00047 00048 private: 00049 static const float AMP_ = 1.0f/2048.0f; 00050 static const uint32_t EOC13_ = ADC_CSR_EOC1 | ADC_CSR_EOC3; 00051 00052 // AD 変換が完了するまで待つ 00053 void WaitDone() 00054 { while((ADC->CSR & EOC13_) != EOC13_); } 00055 00056 // AD 変換器の外部トリガに使うタイマ (TIM6) の設定 00057 void SetTim6(int frequency); 00058 00059 // for inhibition of copy constructor 00060 AdcDual(const AdcDual&); 00061 // for inhibition of substitute operator 00062 AdcDual& operator=(const AdcDual&); 00063 }; 00064 } 00065 #endif // F746_ADC_DUAL_HPP 00066 00067 /* 00068 typedef struct 00069 { 00070 __IO uint32_t SR; //!< ADC status register, Address offset: 0x00 // 00071 __IO uint32_t CR1; //!< ADC control register 1, Address offset: 0x04 // 00072 __IO uint32_t CR2; //!< ADC control register 2, Address offset: 0x08 // 00073 __IO uint32_t SMPR1; //!< ADC sample time register 1, Address offset: 0x0C // 00074 __IO uint32_t SMPR2; //!< ADC sample time register 2, Address offset: 0x10 // 00075 __IO uint32_t JOFR1; //!< ADC injected channel data offset register 1, Address offset: 0x14 // 00076 __IO uint32_t JOFR2; //!< ADC injected channel data offset register 2, Address offset: 0x18 // 00077 __IO uint32_t JOFR3; //!< ADC injected channel data offset register 3, Address offset: 0x1C // 00078 __IO uint32_t JOFR4; //!< ADC injected channel data offset register 4, Address offset: 0x20 // 00079 __IO uint32_t HTR; //!< ADC watchdog higher threshold register, Address offset: 0x24 // 00080 __IO uint32_t LTR; //!< ADC watchdog lower threshold register, Address offset: 0x28 // 00081 __IO uint32_t SQR1; //!< ADC regular sequence register 1, Address offset: 0x2C // 00082 __IO uint32_t SQR2; //!< ADC regular sequence register 2, Address offset: 0x30 // 00083 __IO uint32_t SQR3; //!< ADC regular sequence register 3, Address offset: 0x34 // 00084 __IO uint32_t JSQR; //!< ADC injected sequence register, Address offset: 0x38 // 00085 __IO uint32_t JDR1; //!< ADC injected data register 1, Address offset: 0x3C // 00086 __IO uint32_t JDR2; //!< ADC injected data register 2, Address offset: 0x40 // 00087 __IO uint32_t JDR3; //!< ADC injected data register 3, Address offset: 0x44 // 00088 __IO uint32_t JDR4; //!< ADC injected data register 4, Address offset: 0x48 // 00089 __IO uint32_t DR; //!< ADC regular data register, Address offset: 0x4C // 00090 } ADC_TypeDef; 00091 00092 typedef struct 00093 { 00094 __IO uint32_t CSR; //!< ADC Common status register, Address offset: ADC1 base address + 0x300 // 00095 __IO uint32_t CCR; //!< ADC common control register, Address offset: ADC1 base address + 0x304 // 00096 __IO uint32_t CDR; //!< ADC common regular data register for dual 00097 AND triple modes, Address offset: ADC1 base address + 0x308 // 00098 } ADC_Common_TypeDef; 00099 */
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