Dmitry Kovalev
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el_lin.c
00001 00002 /**--------------File Info--------------------------------------------------------------------------------- 00003 ** File name: el_lin.c 00004 ** Last modified Date: 2011-08-22 00005 ** Last Version: V1.00 00006 **-------------------------------------------------------------------------------------------------------- 00007 ** Created by: Electrooptica Incor. 00008 ** Created date: 2011-08-22 00009 ** Version: V1.00 00010 **-------------------------------------------------------------------------------------------------------- 00011 *********************************************************************************************************/ 00012 00013 #include "Global.h" 00014 00015 00016 #define UART1TEST 00017 #define UART1REC 00018 /* 00019 struct { 00020 uint32_t rcv_num_byt; 00021 uint32_t rcv_num_byt_old; 00022 uint32_t rcv_Rdy; 00023 char rcv_copy[64]; 00024 char rcv_buf[64]; 00025 int32_t rx_buf_copy; 00026 int32_t rcv_byt_copy; 00027 }RECIEVER; 00028 00029 struct { 00030 uint32_t trm_num_byt; 00031 uint32_t trm_rate; 00032 uint32_t trm_cycl; 00033 uint32_t num_of_par; 00034 char trm_buf[64]; 00035 void* addr_param[16]; 00036 uint32_t size_param[16]; 00037 uint32_t trm_ena; 00038 }TRANSMITTER; 00039 */ 00040 uint32_t rcv_num_byt; 00041 uint32_t rcv_num_byt_old; 00042 uint32_t rcv_Rdy; 00043 char rcv_copy[64]; 00044 char rcv_buf[64]; 00045 int32_t rx_buf_copy; 00046 int32_t rcv_byt_copy; 00047 00048 uint32_t trm_num_byt; 00049 uint32_t trm_rate; 00050 uint32_t num_of_par; 00051 char trm_buf[64]; 00052 void* addr_param[16]; 00053 uint32_t size_param[16]; 00054 uint32_t trm_ena; 00055 00056 uint32_t line_err; 00057 uint32_t line_sts; 00058 00059 uint32_t EnablLength = 12; 00060 uint32_t LLI0_TypeDef[4]; 00061 uint32_t LLI1_TypeDef[4]; 00062 uint32_t EnablTx = 0x80; 00063 uint32_t EnablDMA = 0; 00064 /****************************************************************************** 00065 ** Function name: DMA_IRQHandler 00066 ** 00067 ** Descriptions: DMA interrupt handler 00068 ** 00069 ** parameters: None 00070 ** Returned value: None 00071 ** 00072 ******************************************************************************/ 00073 int check_lcc(void) //e. CRC checking //r.проверка контрольной суммы 00074 { 00075 int iCRC_calc, CRC_calc = 0, CRC_real; 00076 00077 for (iCRC_calc = 1; iCRC_calc < (rcv_num_byt-2); iCRC_calc++) 00078 CRC_calc += rcv_buf[iCRC_calc]; 00079 00080 CRC_real = (rcv_buf[rcv_num_byt-2] << 8) | rcv_buf[rcv_num_byt-1]; 00081 00082 return (CRC_real - CRC_calc); 00083 } 00084 void PacketSafing(void) 00085 { 00086 /* int j; static char rcv_buf_copy[16]; 00087 for (j=2; j<rcv_num_byt; j++) 00088 { 00089 if (rcv_buf[j] == 0xCC); 00090 rcv_buf_copy[0] = 0xCC; 00091 // if ((rcv_buf[j] < 3) || (rcv_buf[j] == 0x1F)) 00092 } */ 00093 } 00094 00095 /****************************************************************************** 00096 ** Function name: Line_1_Rcv 00097 ** 00098 ** Descriptions: receive process preparation 00099 ** 00100 ** parameters: None 00101 ** Returned value: None 00102 ** 00103 ******************************************************************************/ 00104 void Line_1_Rcv(void) 00105 { 00106 static int ToWaitEnd, ErrReg ; 00107 00108 00109 00110 00111 while ((LPC_UART1->LSR & RecievBufEmpty) != 0) //e. reciever contain some information 00112 rcv_buf[rcv_num_byt++] = LPC_UART1->RBR;//чтение информации из буфера. 00113 00114 00115 00116 00117 if (( ToWaitEnd > 25000)) { //e. end part of packet is absent //r. не дождались конца пакета 00118 do 00119 rcv_buf[--rcv_num_byt] = 0; 00120 while(rcv_num_byt); 00121 rcv_num_byt_old = rcv_num_byt; 00122 #if defined UART1REC 00123 LPC_UART1->FCR |= RX_FIFO_Reset; 00124 #else 00125 LPC_UART0->FCR |= RX_FIFO_Reset; 00126 #endif 00127 // L1_Rc_err (TIMEOUT_ERR); 00128 ToWaitEnd = 0; 00129 return; 00130 } 00131 if (rcv_num_byt_old == rcv_num_byt) { //e. we have not received any new bytes 00132 if (ToWaitEnd) ToWaitEnd++; 00133 return; 00134 } 00135 rcv_num_byt_old = rcv_num_byt; 00136 00137 if ((rcv_num_byt < 6) || ((rcv_num_byt & 0x0001) == 1)) { 00138 ToWaitEnd++; 00139 return; 00140 } 00141 00142 if ((!ToWaitEnd) && (rcv_num_byt > 1)) //e. the header of packet has not recieved //r. ожидаем начало пакета 00143 if ((rcv_buf[0] != 0xCC) || (( rcv_buf[1] > 2) && ( rcv_buf[1] != 0x1F))) { 00144 // L1_Rc_err (HEADER_ERR); 00145 ErrReg |= 5; 00146 ToWaitEnd++; 00147 return; 00148 } 00149 // if (ErrReg != 0) //e. trying of recovering of packet //r. спасение следующего пакета 00150 // PacketSafing(); 00151 00152 00153 if (rcv_num_byt == 6) { 00154 if ((rcv_buf[2] == 0x0A) || (rcv_buf[2] == 0xE0) || (rcv_buf[2] == 0xE4) || (rcv_buf[2] == 0xE6) || (rcv_buf[2] == 0xE8)) { 00155 //e. packet length is not valid, so we have the error //r. ошибка размера пакета 00156 ToWaitEnd++; 00157 return; 00158 } 00159 00160 } else if (rcv_num_byt == 8) { 00161 if ((rcv_buf[2] == 0xE0) || (rcv_buf[2] == 0xE4)) { 00162 ToWaitEnd++; 00163 return; 00164 } 00165 } 00166 if (check_lcc() != 0) { //e. checksum is bad //r.контрольные суммы не равны 00167 00168 return; 00169 } else { //e. cheksum is not bad //r.контрольные суммы равны 00170 rcv_Rdy = 1; 00171 } 00172 ToWaitEnd = 0; 00173 00174 return; 00175 00176 } 00177 /* 00178 void L1_Rc_err (int Error) //e. error fixing and reciever restart //r. модуль фиксации ошибки и перезапуска приемника 00179 { 00180 int temp; 00181 line_sts |= Error; 00182 temp = Copy_SRgR & (~Rcv_Rdy); 00183 io_space_write(Sys_RgR, temp); 00184 temp |= Rcv_Rdy; 00185 asm("nop;"); 00186 io_space_write(Sys_RgR, temp); 00187 return; 00188 } 00189 */ 00190 00191 /****************************************************************************** 00192 ** Function name: transm_DAT 00193 ** 00194 ** Descriptions: transmit process preparation 00195 ** 00196 ** parameters: None 00197 ** Returned value: None 00198 ** 00199 ******************************************************************************/ 00200 00201 00202 void transm_DAT(void) 00203 { 00204 uint32_t param, param_byte, CRC; 00205 int32_t *trans_param; 00206 00207 if ((LPC_UART1->LSR & TRANS_SHIFT_BUF_EMPTY)) //r. передающий буфер пуст 00208 if (!( LPC_GPDMACH1->CConfig & (1<<17))) 00209 LPC_GPIO2->FIOCLR |= 8; //switch off UART1 driver 00210 00211 if (trm_ena == 0) { 00212 // LPC_GPIO1->FIOCLR = (0x01<<30); //r.передача требуется? 00213 return; //r. если нет, возврат 00214 } 00215 00216 if (!(LPC_UART1->LSR & TRANS_SHIFT_BUF_EMPTY)) //r. передающий буфер пуст 00217 return; 00218 00219 if ( LPC_GPDMACH1->CConfig & (1<<17)) //r. если канал передачи занят, ждать 00220 return; 00221 00222 //#if defined UART1TEST 00223 // if (LPC_SC->DMAREQSEL == 0x8) //e. DMA request from UART 00224 // LPC_GPIO2->FIOSET |= (1<<3); //e. set enable UART bit 00225 //#endif 00226 00227 trm_ena = 0; //r. сбросить флаг разрешения передачи 00228 00229 trm_num_byt = 2; 00230 00231 trm_buf[0] = 0x00dd; //r. заголовок пакета 00232 trm_buf[1] = Device_blk.Str.My_Addres; //r. адрес прибора 00233 00234 CRC = trm_buf[1]; //r.инициализация счетчика контрольной суммы 00235 for ( param = 0; param < num_of_par; param++) { //r.цикл формирования блока данных пакета 00236 trans_param = (int32_t *)addr_param[param]; //r. чтение адреса одного из выдаваемых в пакете параметров 00237 00238 for (param_byte = 0; param_byte < size_param[param]; param_byte++) { 00239 if ( (param_byte & 0x0001) == 0 ) //r. считываем старший байт 00240 trm_buf[trm_num_byt] = (*trans_param >> (8/**(size_param[param]-param_byte-1)*/)) & 0x00ff; //r.размещение передаваемого параметра в пакете 00241 else { 00242 trm_buf[trm_num_byt] = *trans_param & 0x00ff; 00243 trans_param ++; //r.переходим к следующей ячейке памяти 00244 } 00245 CRC += trm_buf[trm_num_byt]; //r. вычисление текущей контрольной суммы 00246 trm_num_byt++; //r. количество бит, отправленных в пакет 00247 } 00248 } 00249 trm_buf[trm_num_byt] = CRC >> 8; //r. запись контрольной суммы в пакет 00250 trm_buf[trm_num_byt+1] = CRC & 0x00ff; 00251 00252 trm_num_byt += 2; 00253 00254 LPC_GPDMACH1->CSrcAddr = (uint32_t)&trm_buf; 00255 00256 LPC_GPDMACH1->CControl &= ~0xFFF; //e. reset of numer bytes for transmitting 00257 LPC_GPDMACH2->CControl &= ~0xFFF; //e. reset of numer bytes for transmitting 00258 00259 LPC_GPDMACH1->CLLI = 0; //e. linked list is empty 00260 00261 if (trm_num_byt > 16) { //e. a packet is too long for FIFO 00262 LPC_GPDMACH1->CControl |= 16; //e. set length of first packet part 00263 LPC_GPDMACH1->CLLI = (uint32_t)&LLI0_TypeDef; //e. initialize chain for other parts transmitting 00264 } else 00265 LPC_GPDMACH1->CControl |= trm_num_byt; 00266 00267 LPC_GPDMACH2->CControl |= 1; //e. set 1 transfert for enable signal 00268 #if defined UART1TEST 00269 LPC_UART1->TER = 0; //e. disable data output to UART1 00270 #endif 00271 if (Device_Mode < 4) { //e. work with internal latch 00272 LPC_TIM0->TCR = 1; //e. start timer 00273 //-------------------debug----------------------------------------- 00274 LPC_GPIO2->FIOSET |= 8; //turn on RS-422 driver 00275 //-------------------debug----------------------------------------- 00276 00277 LPC_GPDMACH1->CConfig |= DMAChannelEn; //e. DMA for UART transmition 00278 //LPC_GPIO1->FIOSET = (0x1<<30); 00279 00280 } 00281 00282 LPC_GPDMACH2->CConfig |= DMAChannelEn; //e. DMA for enable signal 00283 return; 00284 } 00285 /****************************************************************************** 00286 ** Function name: DMA_Init 00287 ** 00288 ** Descriptions: 00289 ** 00290 ** parameters: 00291 ** Returned value: 00292 ** 00293 ******************************************************************************/ 00294 void DMA_Init( void ) 00295 { 00296 /* Enable CLOCK into GPDMA controller */ 00297 LPC_SC->PCONP |= GPDMA_POWER_ON; 00298 00299 /* Select primary function(UART0/1/2/3) in DMA channels, 00300 secondary is timer 0/1/2/3. */ 00301 #if defined UART1TEST 00302 LPC_SC->DMAREQSEL = 3; 00303 #endif 00304 //LPC_GPDMA->Sync = (0x1<<DMA_UART0_RX)|(0x1<<DMA_UART1_TX); //synchronization logic is enabled by default 00305 LPC_GPDMA->Config = DMA_ControllerEn | DMA_AHB_Little; 00306 while ( !(LPC_GPDMA->Config & DMA_ControllerEn) ); //wait until DMA_Controller switched on 00307 00308 NVIC_DisableIRQ(DMA_IRQn ); 00309 return; 00310 } 00311 00312 /****************************************************************************** 00313 ** Function name: UARTInit 00314 ** 00315 ** Descriptions: Initialisation of UART on 38400 baud 00316 ** 00317 ** parameters: None 00318 ** Returned value: None 00319 ** 00320 ******************************************************************************/ 00321 void UARTInit(void) 00322 { 00323 uint32_t Fdiv; 00324 uint32_t pclk; 00325 #if !defined UART1TEST 00326 uint32_t baudrate = 38400; 00327 #else 00328 uint32_t baudrate = 38400; 00329 #endif 00330 LPC_SC->PCONP |= (1<<3); 00331 00332 LPC_PINCON->PINSEL0 |= 0x00000050; 00333 00334 pclk = SystemCoreClock/4; 00335 00336 LPC_UART0->LCR = word_length_8 |one_stop_bit |no_parity |back_trans_dis |DLAB_access; 00337 Fdiv = (pclk / 16) / baudrate; 00338 LPC_UART0->DLM = Fdiv / 256; 00339 LPC_UART0->DLL = Fdiv % 256; 00340 LPC_UART0->LCR &= ~DLAB_access; 00341 LPC_UART0->FCR = TX_FIFO_Reset |RX_FIFO_Reset |FIFOs_En |RX_TrigLvl_14; //0x06; 00342 LPC_UART0->IER = 0;//RBR_IntEnabl; 00343 00344 LPC_UART0->FCR |= 0x08; //e. DMA mode select 00345 //+++++++++++++++++++++++enable signal initialization++++++++++++++++++++++++++ 00346 LPC_PINCON->PINSEL1 &= ~0x0000C000; //e. select P0.23 as general purpose 00347 LPC_GPIO0->FIODIR |= 0x00800000; //e. P0.23 is output 00348 // LPC_GPIO0->FIOMASK |= 0x007F0000; //e. P0.16..P0.22 is not changed by FIOSET writing 00349 LPC_GPIO0->FIOCLR |= 0x00800000; // e. clear P0.23 00350 00351 return; 00352 } 00353 00354 void UART1_Init(void) 00355 { 00356 uint32_t Fdiv; 00357 uint32_t pclk; 00358 #if !defined UART1TEST 00359 uint32_t baudrate = 256000; 00360 #else 00361 uint32_t baudrate = 38400; 00362 #endif 00363 LPC_SC->PCONP |= (1<<4); //switch on UART1 00364 00365 LPC_PINCON->PINSEL4 |= (2<<0)|(2<<2)|(2<<10)|(2<<14); //P2.0, P2.1, P2.5, P2.7 00366 00367 pclk = SystemCoreClock/4; 00368 00369 LPC_UART1->LCR = word_length_8 |one_stop_bit |no_parity |back_trans_dis |DLAB_access; 00370 Fdiv = (pclk / 16) / baudrate; 00371 LPC_UART1->DLM = Fdiv / 256; 00372 LPC_UART1->DLL = Fdiv % 256; 00373 LPC_UART1->LCR &= ~DLAB_access; 00374 LPC_UART1->FCR = TX_FIFO_Reset |RX_FIFO_Reset |FIFOs_En |RX_TrigLvl_14; //0x06; 00375 00376 LPC_UART1->RS485CTRL = (1<<5); //(1<<4); 00377 00378 LPC_UART1->IER = 0;//RBR_IntEnabl; 00379 00380 LPC_UART1->FCR |= 0x08; //e. DMA mode select 00381 return; 00382 } 00383 //----------------------temp---------------------------- 00384 /*int UART0_SendByte (int ucData) 00385 { 00386 // while (!(LPC_UART1->LSR & 0x20)); 00387 return (LPC_UART0->THR = ucData); 00388 }*/ 00389 //----------------------temp---------------------------- 00390 int UART1_SendByte (int ucData) 00391 { 00392 // while (!(LPC_UART1->LSR & 0x20)); 00393 return (LPC_UART1->THR = ucData); 00394 } 00395 /****************************************************************************** 00396 ** Function name: UART_SwitchSpeed 00397 ** 00398 ** Descriptions: Change UART speed 00399 ** 00400 ** parameters: Demanded speed 00401 ** Returned value: None 00402 ** 00403 ******************************************************************************/ 00404 void UART_SwitchSpeed(unsigned Speed) 00405 { 00406 uint32_t Fdiv; 00407 uint32_t pclk; 00408 00409 pclk = SystemCoreClock/4; 00410 #if defined UART1REC 00411 LPC_UART1->LCR |= DLAB_access; 00412 #else 00413 LPC_UART0->LCR |= DLAB_access; 00414 #endif 00415 switch (Speed) { 00416 case Sp38400: 00417 Fdiv = (pclk / 16) / 38400; 00418 EnablLength = 3240; 00419 break; 00420 00421 case Sp115200: 00422 Fdiv = (pclk / 16) /115200; 00423 EnablLength = 1090; 00424 break; 00425 00426 case Sp460800: 00427 Fdiv = (pclk / 16) / 460800; 00428 break; 00429 00430 case Sp921600: 00431 Fdiv = (pclk / 16) / 921600; 00432 EnablLength = 140; 00433 break; 00434 00435 } 00436 #if defined UART1REC 00437 LPC_UART1->DLM = Fdiv / 256; 00438 LPC_UART1->DLL = Fdiv % 256; 00439 LPC_UART1->LCR &= ~DLAB_access; 00440 #else 00441 LPC_UART0->DLM = Fdiv / 256; 00442 LPC_UART0->DLL = Fdiv % 256; 00443 LPC_UART0->LCR &= ~DLAB_access; 00444 #endif 00445 } 00446 /****************************************************************************** 00447 ** Function name: UART_DMA_Init 00448 ** 00449 ** Descriptions: Initialisation of DMA channel for UART transmitter 00450 ** 00451 ** parameters: None 00452 ** Returned value: None 00453 ** 00454 ******************************************************************************/ 00455 void UART_DMA_Init() 00456 { 00457 //+++++++++++++++++config channel for UART0+++++++++++++++++++++++++++++++++++++++++++++++ 00458 LPC_GPDMACH1->CConfig &= ~DMAChannelEn; 00459 00460 LPC_GPDMA->IntTCClear = DMA1_IntTCClear; 00461 LPC_GPDMA->IntErrClr = DMA1_IntErrClear; 00462 00463 LPC_GPDMACH1->CSrcAddr = (uint32_t)&trm_buf; 00464 LPC_GPDMACH1->CDestAddr = UART1_DMA_TX_DST; 00465 LPC_GPDMACH1->CControl = SrcBSize_1 | DstBSize_1 | SrcWidth_8b | DstWidth_8b | SrcInc | DstFixed | TCIntDisabl; 00466 #if defined UART1TEST 00467 LPC_GPDMACH1->CConfig |= MaskTCInt | MaskErrInt | DMA_MEMORY | DstDMA_UART1_TX |(M2P << 11); 00468 #else 00469 g LPC_GPDMACH1->CConfig |= MaskTCInt | MaskErrInt | DMA_MEMORY | DstDMA_UART0_TX |(M2P << 11); 00470 #endif 00471 00472 EnablDMA = (LPC_GPDMACH1->CConfig)|DMAChannelEn; //save register content for DMA starting in multidrop mode 00473 //**********for Rate mode output***************************** 00474 #if defined UART1TEST 00475 LLI1_TypeDef[0] = (uint32_t)&trm_buf[32]; 00476 LLI1_TypeDef[1] = UART1_DMA_TX_DST; 00477 LLI1_TypeDef[2] = 0; 00478 LLI1_TypeDef[3] = (12 & 0x0FFF) | SrcBSize_1 | DstBSize_1 | SrcWidth_8b | DstWidth_8b | SrcInc | DstFixed | TCIntDisabl; 00479 00480 LLI0_TypeDef[0] = (uint32_t)&trm_buf[16]; 00481 LLI0_TypeDef[1] = UART1_DMA_TX_DST; 00482 LLI0_TypeDef[2] = (uint32_t)&LLI1_TypeDef; 00483 LLI0_TypeDef[3] = (16 & 0x0FFF) | SrcBSize_1 | DstBSize_1 | SrcWidth_8b | DstWidth_8b | SrcInc | DstFixed | TCIntDisabl; 00484 #else 00485 LLI1_TypeDef[0] = (uint32_t)&trm_buf[32]; 00486 LLI1_TypeDef[1] = UART0_DMA_TX_DST; 00487 LLI1_TypeDef[2] = 0; 00488 LLI1_TypeDef[3] = (12 & 0x0FFF) | SrcBSize_1 | DstBSize_1 | SrcWidth_8b | DstWidth_8b | SrcInc | DstFixed | TCIntDisabl; 00489 00490 LLI0_TypeDef[0] = (uint32_t)&trm_buf[16]; 00491 LLI0_TypeDef[1] = UART0_DMA_TX_DST; 00492 LLI0_TypeDef[2] = (uint32_t)&LLI1_TypeDef; 00493 LLI0_TypeDef[3] = (16 & 0x0FFF)|SrcBSize_1 |DstBSize_1 |SrcWidth_8b 00494 |DstWidth_8b|SrcInc |DstFixed |TCIntDisabl; 00495 #endif 00496 //++++++++++++++++++++++++++config channel for transmit enable signal+++++++++++++++++++ 00497 LPC_GPDMACH2->CConfig &= ~DMAChannelEn; 00498 00499 LPC_GPDMA->IntTCClear = DMA2_IntTCClear; 00500 LPC_GPDMA->IntErrClr = DMA2_IntErrClear; 00501 00502 LPC_GPDMACH2->CSrcAddr = (uint32_t)&EnablTx; //e. content of TX UART1 enable register 00503 LPC_GPDMACH2->CDestAddr = 0x40010030; //e. address of TX UART1 enable register (U1TER) 00504 00505 LPC_GPDMACH2->CControl = SrcBSize_4 |DstBSize_4 00506 |SrcWidth_8b |DstWidth_8b|SrcFixed |DstFixed |TCIntEnabl; 00507 00508 LPC_GPDMACH2->CConfig |= MaskTCInt |MaskErrInt 00509 |SrcDMA_UART0_RX |DstDMA_UART0_RX|(M2P << 11); 00510 LPC_GPDMACH2->CLLI = 0; //e. linked list is empty 00511 00512 //++++++++++++++++++++++++++config channel for DMA1 enable signal+++++++++++++++++++ 00513 #if defined UART1TEST 00514 LPC_GPDMACH4->CConfig &= ~DMAChannelEn; 00515 00516 LPC_GPDMA->IntTCClear = DMA4_IntTCClear; 00517 LPC_GPDMA->IntErrClr = DMA4_IntErrClear; 00518 00519 LPC_GPDMACH4->CSrcAddr = (uint32_t)&EnablDMA; //e. content of TX UART1 enable register 00520 LPC_GPDMACH4->CDestAddr = 0x50004130; //e. address of DMA1CConfig register 00521 00522 LPC_GPDMACH4->CControl = SrcBSize_4 |DstBSize_4 00523 |SrcWidth_8b |DstWidth_8b|SrcFixed |DstFixed |TCIntEnabl; 00524 00525 LPC_GPDMACH4->CConfig |= MaskTCInt |MaskErrInt 00526 |SrcDMA_UART0_TX |DstDMA_UART0_TX|(M2P << 11); 00527 LPC_GPDMACH4->CLLI = 0; //e. linked list is empty 00528 #endif 00529 } 00530 /****************************************************************************** 00531 ** End Of File 00532 ******************************************************************************/ 00533 00534
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