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core_armv8mbl.h
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00001 /**************************************************************************//** 00002 * @file core_armv8mbl.h 00003 * @brief CMSIS ARMv8MBL Core Peripheral Access Layer Header File 00004 * @version V5.0.2 00005 * @date 13. February 2017 00006 ******************************************************************************/ 00007 /* 00008 * Copyright (c) 2009-2017 ARM Limited. All rights reserved. 00009 * 00010 * SPDX-License-Identifier: Apache-2.0 00011 * 00012 * Licensed under the Apache License, Version 2.0 (the License); you may 00013 * not use this file except in compliance with the License. 00014 * You may obtain a copy of the License at 00015 * 00016 * www.apache.org/licenses/LICENSE-2.0 00017 * 00018 * Unless required by applicable law or agreed to in writing, software 00019 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 00020 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 00021 * See the License for the specific language governing permissions and 00022 * limitations under the License. 00023 */ 00024 00025 #if defined ( __ICCARM__ ) 00026 #pragma system_include /* treat file as system include file for MISRA check */ 00027 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 00028 #pragma clang system_header /* treat file as system include file */ 00029 #endif 00030 00031 #ifndef __CORE_ARMV8MBL_H_GENERIC 00032 #define __CORE_ARMV8MBL_H_GENERIC 00033 00034 #include <stdint.h> 00035 00036 #ifdef __cplusplus 00037 extern "C" { 00038 #endif 00039 00040 /** 00041 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 00042 CMSIS violates the following MISRA-C:2004 rules: 00043 00044 \li Required Rule 8.5, object/function definition in header file.<br> 00045 Function definitions in header files are used to allow 'inlining'. 00046 00047 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 00048 Unions are used for effective representation of core registers. 00049 00050 \li Advisory Rule 19.7, Function-like macro defined.<br> 00051 Function-like macros are used to allow more efficient code. 00052 */ 00053 00054 00055 /******************************************************************************* 00056 * CMSIS definitions 00057 ******************************************************************************/ 00058 /** 00059 \ingroup Cortex_ARMv8MBL 00060 @{ 00061 */ 00062 00063 /* CMSIS cmGrebe definitions */ 00064 #define __ARMv8MBL_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ 00065 #define __ARMv8MBL_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ 00066 #define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ 00067 __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ 00068 00069 #define __CORTEX_M ( 2U) /*!< Cortex-M Core */ 00070 00071 /** __FPU_USED indicates whether an FPU is used or not. 00072 This core does not support an FPU at all 00073 */ 00074 #define __FPU_USED 0U 00075 00076 #if defined ( __CC_ARM ) 00077 #if defined __TARGET_FPU_VFP 00078 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00079 #endif 00080 00081 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 00082 #if defined __ARM_PCS_VFP 00083 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00084 #endif 00085 00086 #elif defined ( __GNUC__ ) 00087 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 00088 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00089 #endif 00090 00091 #elif defined ( __ICCARM__ ) 00092 #if defined __ARMVFP__ 00093 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00094 #endif 00095 00096 #elif defined ( __TI_ARM__ ) 00097 #if defined __TI_VFP_SUPPORT__ 00098 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00099 #endif 00100 00101 #elif defined ( __TASKING__ ) 00102 #if defined __FPU_VFP__ 00103 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00104 #endif 00105 00106 #elif defined ( __CSMC__ ) 00107 #if ( __CSMC__ & 0x400U) 00108 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00109 #endif 00110 00111 #endif 00112 00113 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ 00114 00115 00116 #ifdef __cplusplus 00117 } 00118 #endif 00119 00120 #endif /* __CORE_ARMV8MBL_H_GENERIC */ 00121 00122 #ifndef __CMSIS_GENERIC 00123 00124 #ifndef __CORE_ARMV8MBL_H_DEPENDANT 00125 #define __CORE_ARMV8MBL_H_DEPENDANT 00126 00127 #ifdef __cplusplus 00128 extern "C" { 00129 #endif 00130 00131 /* check device defines and use defaults */ 00132 #if defined __CHECK_DEVICE_DEFINES 00133 #ifndef __ARMv8MBL_REV 00134 #define __ARMv8MBL_REV 0x0000U 00135 #warning "__ARMv8MBL_REV not defined in device header file; using default!" 00136 #endif 00137 00138 #ifndef __FPU_PRESENT 00139 #define __FPU_PRESENT 0U 00140 #warning "__FPU_PRESENT not defined in device header file; using default!" 00141 #endif 00142 00143 #ifndef __MPU_PRESENT 00144 #define __MPU_PRESENT 0U 00145 #warning "__MPU_PRESENT not defined in device header file; using default!" 00146 #endif 00147 00148 #ifndef __SAUREGION_PRESENT 00149 #define __SAUREGION_PRESENT 0U 00150 #warning "__SAUREGION_PRESENT not defined in device header file; using default!" 00151 #endif 00152 00153 #ifndef __VTOR_PRESENT 00154 #define __VTOR_PRESENT 0U 00155 #warning "__VTOR_PRESENT not defined in device header file; using default!" 00156 #endif 00157 00158 #ifndef __NVIC_PRIO_BITS 00159 #define __NVIC_PRIO_BITS 2U 00160 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 00161 #endif 00162 00163 #ifndef __Vendor_SysTickConfig 00164 #define __Vendor_SysTickConfig 0U 00165 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 00166 #endif 00167 00168 #ifndef __ETM_PRESENT 00169 #define __ETM_PRESENT 0U 00170 #warning "__ETM_PRESENT not defined in device header file; using default!" 00171 #endif 00172 00173 #ifndef __MTB_PRESENT 00174 #define __MTB_PRESENT 0U 00175 #warning "__MTB_PRESENT not defined in device header file; using default!" 00176 #endif 00177 00178 #endif 00179 00180 /* IO definitions (access restrictions to peripheral registers) */ 00181 /** 00182 \defgroup CMSIS_glob_defs CMSIS Global Defines 00183 00184 <strong>IO Type Qualifiers</strong> are used 00185 \li to specify the access to peripheral variables. 00186 \li for automatic generation of peripheral register debug information. 00187 */ 00188 #ifdef __cplusplus 00189 #define __I volatile /*!< Defines 'read only' permissions */ 00190 #else 00191 #define __I volatile const /*!< Defines 'read only' permissions */ 00192 #endif 00193 #define __O volatile /*!< Defines 'write only' permissions */ 00194 #define __IO volatile /*!< Defines 'read / write' permissions */ 00195 00196 /* following defines should be used for structure members */ 00197 #define __IM volatile const /*! Defines 'read only' structure member permissions */ 00198 #define __OM volatile /*! Defines 'write only' structure member permissions */ 00199 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ 00200 00201 /*@} end of group ARMv8MBL */ 00202 00203 00204 00205 /******************************************************************************* 00206 * Register Abstraction 00207 Core Register contain: 00208 - Core Register 00209 - Core NVIC Register 00210 - Core SCB Register 00211 - Core SysTick Register 00212 - Core Debug Register 00213 - Core MPU Register 00214 - Core SAU Register 00215 ******************************************************************************/ 00216 /** 00217 \defgroup CMSIS_core_register Defines and Type Definitions 00218 \brief Type definitions and defines for Cortex-M processor based devices. 00219 */ 00220 00221 /** 00222 \ingroup CMSIS_core_register 00223 \defgroup CMSIS_CORE Status and Control Registers 00224 \brief Core Register type definitions. 00225 @{ 00226 */ 00227 00228 /** 00229 \brief Union type to access the Application Program Status Register (APSR). 00230 */ 00231 typedef union 00232 { 00233 struct 00234 { 00235 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ 00236 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00237 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00238 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00239 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00240 } b; /*!< Structure used for bit access */ 00241 uint32_t w; /*!< Type used for word access */ 00242 } APSR_Type; 00243 00244 /* APSR Register Definitions */ 00245 #define APSR_N_Pos 31U /*!< APSR: N Position */ 00246 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ 00247 00248 #define APSR_Z_Pos 30U /*!< APSR: Z Position */ 00249 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ 00250 00251 #define APSR_C_Pos 29U /*!< APSR: C Position */ 00252 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ 00253 00254 #define APSR_V_Pos 28U /*!< APSR: V Position */ 00255 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ 00256 00257 00258 /** 00259 \brief Union type to access the Interrupt Program Status Register (IPSR). 00260 */ 00261 typedef union 00262 { 00263 struct 00264 { 00265 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00266 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 00267 } b; /*!< Structure used for bit access */ 00268 uint32_t w; /*!< Type used for word access */ 00269 } IPSR_Type; 00270 00271 /* IPSR Register Definitions */ 00272 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ 00273 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ 00274 00275 00276 /** 00277 \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 00278 */ 00279 typedef union 00280 { 00281 struct 00282 { 00283 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00284 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ 00285 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ 00286 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ 00287 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00288 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00289 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00290 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00291 } b; /*!< Structure used for bit access */ 00292 uint32_t w; /*!< Type used for word access */ 00293 } xPSR_Type; 00294 00295 /* xPSR Register Definitions */ 00296 #define xPSR_N_Pos 31U /*!< xPSR: N Position */ 00297 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ 00298 00299 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ 00300 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ 00301 00302 #define xPSR_C_Pos 29U /*!< xPSR: C Position */ 00303 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ 00304 00305 #define xPSR_V_Pos 28U /*!< xPSR: V Position */ 00306 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ 00307 00308 #define xPSR_T_Pos 24U /*!< xPSR: T Position */ 00309 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ 00310 00311 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ 00312 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ 00313 00314 00315 /** 00316 \brief Union type to access the Control Registers (CONTROL). 00317 */ 00318 typedef union 00319 { 00320 struct 00321 { 00322 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ 00323 uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ 00324 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ 00325 } b; /*!< Structure used for bit access */ 00326 uint32_t w; /*!< Type used for word access */ 00327 } CONTROL_Type; 00328 00329 /* CONTROL Register Definitions */ 00330 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ 00331 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ 00332 00333 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ 00334 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ 00335 00336 /*@} end of group CMSIS_CORE */ 00337 00338 00339 /** 00340 \ingroup CMSIS_core_register 00341 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 00342 \brief Type definitions for the NVIC Registers 00343 @{ 00344 */ 00345 00346 /** 00347 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 00348 */ 00349 typedef struct 00350 { 00351 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 00352 uint32_t RESERVED0[16U]; 00353 __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 00354 uint32_t RSERVED1[16U]; 00355 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 00356 uint32_t RESERVED2[16U]; 00357 __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 00358 uint32_t RESERVED3[16U]; 00359 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ 00360 uint32_t RESERVED4[16U]; 00361 __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ 00362 uint32_t RESERVED5[16U]; 00363 __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ 00364 } NVIC_Type; 00365 00366 /*@} end of group CMSIS_NVIC */ 00367 00368 00369 /** 00370 \ingroup CMSIS_core_register 00371 \defgroup CMSIS_SCB System Control Block (SCB) 00372 \brief Type definitions for the System Control Block Registers 00373 @{ 00374 */ 00375 00376 /** 00377 \brief Structure type to access the System Control Block (SCB). 00378 */ 00379 typedef struct 00380 { 00381 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 00382 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 00383 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 00384 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ 00385 #else 00386 uint32_t RESERVED0; 00387 #endif 00388 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 00389 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 00390 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 00391 uint32_t RESERVED1; 00392 __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ 00393 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 00394 } SCB_Type; 00395 00396 /* SCB CPUID Register Definitions */ 00397 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ 00398 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 00399 00400 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ 00401 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 00402 00403 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ 00404 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 00405 00406 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ 00407 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 00408 00409 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ 00410 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ 00411 00412 /* SCB Interrupt Control State Register Definitions */ 00413 #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ 00414 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ 00415 00416 #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ 00417 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ 00418 00419 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ 00420 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 00421 00422 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ 00423 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 00424 00425 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ 00426 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 00427 00428 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ 00429 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 00430 00431 #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ 00432 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ 00433 00434 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ 00435 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 00436 00437 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ 00438 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 00439 00440 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ 00441 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 00442 00443 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ 00444 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ 00445 00446 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ 00447 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ 00448 00449 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 00450 /* SCB Vector Table Offset Register Definitions */ 00451 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ 00452 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 00453 #endif 00454 00455 /* SCB Application Interrupt and Reset Control Register Definitions */ 00456 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ 00457 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 00458 00459 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ 00460 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 00461 00462 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ 00463 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 00464 00465 #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ 00466 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ 00467 00468 #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ 00469 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ 00470 00471 #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ 00472 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ 00473 00474 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ 00475 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 00476 00477 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ 00478 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 00479 00480 /* SCB System Control Register Definitions */ 00481 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ 00482 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 00483 00484 #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ 00485 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ 00486 00487 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ 00488 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 00489 00490 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ 00491 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 00492 00493 /* SCB Configuration Control Register Definitions */ 00494 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ 00495 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ 00496 00497 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ 00498 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ 00499 00500 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ 00501 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ 00502 00503 #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ 00504 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ 00505 00506 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ 00507 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ 00508 00509 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ 00510 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ 00511 00512 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ 00513 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 00514 00515 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ 00516 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ 00517 00518 /* SCB System Handler Control and State Register Definitions */ 00519 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ 00520 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ 00521 00522 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ 00523 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 00524 00525 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ 00526 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ 00527 00528 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ 00529 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ 00530 00531 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ 00532 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ 00533 00534 #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ 00535 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ 00536 00537 #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ 00538 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ 00539 00540 /*@} end of group CMSIS_SCB */ 00541 00542 00543 /** 00544 \ingroup CMSIS_core_register 00545 \defgroup CMSIS_SysTick System Tick Timer (SysTick) 00546 \brief Type definitions for the System Timer Registers. 00547 @{ 00548 */ 00549 00550 /** 00551 \brief Structure type to access the System Timer (SysTick). 00552 */ 00553 typedef struct 00554 { 00555 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 00556 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 00557 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 00558 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 00559 } SysTick_Type; 00560 00561 /* SysTick Control / Status Register Definitions */ 00562 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ 00563 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 00564 00565 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ 00566 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 00567 00568 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ 00569 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 00570 00571 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ 00572 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ 00573 00574 /* SysTick Reload Register Definitions */ 00575 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ 00576 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ 00577 00578 /* SysTick Current Register Definitions */ 00579 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ 00580 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ 00581 00582 /* SysTick Calibration Register Definitions */ 00583 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ 00584 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 00585 00586 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ 00587 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 00588 00589 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ 00590 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ 00591 00592 /*@} end of group CMSIS_SysTick */ 00593 00594 00595 /** 00596 \ingroup CMSIS_core_register 00597 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) 00598 \brief Type definitions for the Data Watchpoint and Trace (DWT) 00599 @{ 00600 */ 00601 00602 /** 00603 \brief Structure type to access the Data Watchpoint and Trace Register (DWT). 00604 */ 00605 typedef struct 00606 { 00607 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ 00608 uint32_t RESERVED0[6U]; 00609 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ 00610 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ 00611 uint32_t RESERVED1[1U]; 00612 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ 00613 uint32_t RESERVED2[1U]; 00614 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ 00615 uint32_t RESERVED3[1U]; 00616 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ 00617 uint32_t RESERVED4[1U]; 00618 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ 00619 uint32_t RESERVED5[1U]; 00620 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ 00621 uint32_t RESERVED6[1U]; 00622 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ 00623 uint32_t RESERVED7[1U]; 00624 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ 00625 uint32_t RESERVED8[1U]; 00626 __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ 00627 uint32_t RESERVED9[1U]; 00628 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ 00629 uint32_t RESERVED10[1U]; 00630 __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ 00631 uint32_t RESERVED11[1U]; 00632 __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ 00633 uint32_t RESERVED12[1U]; 00634 __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ 00635 uint32_t RESERVED13[1U]; 00636 __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ 00637 uint32_t RESERVED14[1U]; 00638 __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ 00639 uint32_t RESERVED15[1U]; 00640 __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ 00641 uint32_t RESERVED16[1U]; 00642 __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ 00643 uint32_t RESERVED17[1U]; 00644 __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ 00645 uint32_t RESERVED18[1U]; 00646 __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ 00647 uint32_t RESERVED19[1U]; 00648 __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ 00649 uint32_t RESERVED20[1U]; 00650 __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ 00651 uint32_t RESERVED21[1U]; 00652 __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ 00653 uint32_t RESERVED22[1U]; 00654 __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ 00655 uint32_t RESERVED23[1U]; 00656 __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ 00657 uint32_t RESERVED24[1U]; 00658 __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ 00659 uint32_t RESERVED25[1U]; 00660 __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ 00661 uint32_t RESERVED26[1U]; 00662 __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ 00663 uint32_t RESERVED27[1U]; 00664 __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ 00665 uint32_t RESERVED28[1U]; 00666 __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ 00667 uint32_t RESERVED29[1U]; 00668 __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ 00669 uint32_t RESERVED30[1U]; 00670 __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ 00671 uint32_t RESERVED31[1U]; 00672 __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ 00673 } DWT_Type; 00674 00675 /* DWT Control Register Definitions */ 00676 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ 00677 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ 00678 00679 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ 00680 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ 00681 00682 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ 00683 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ 00684 00685 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ 00686 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ 00687 00688 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ 00689 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ 00690 00691 /* DWT Comparator Function Register Definitions */ 00692 #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ 00693 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ 00694 00695 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ 00696 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ 00697 00698 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ 00699 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ 00700 00701 #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ 00702 #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ 00703 00704 #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ 00705 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ 00706 00707 /*@}*/ /* end of group CMSIS_DWT */ 00708 00709 00710 /** 00711 \ingroup CMSIS_core_register 00712 \defgroup CMSIS_TPI Trace Port Interface (TPI) 00713 \brief Type definitions for the Trace Port Interface (TPI) 00714 @{ 00715 */ 00716 00717 /** 00718 \brief Structure type to access the Trace Port Interface Register (TPI). 00719 */ 00720 typedef struct 00721 { 00722 __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ 00723 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ 00724 uint32_t RESERVED0[2U]; 00725 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ 00726 uint32_t RESERVED1[55U]; 00727 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ 00728 uint32_t RESERVED2[131U]; 00729 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ 00730 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ 00731 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ 00732 uint32_t RESERVED3[759U]; 00733 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ 00734 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ 00735 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ 00736 uint32_t RESERVED4[1U]; 00737 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ 00738 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ 00739 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ 00740 uint32_t RESERVED5[39U]; 00741 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ 00742 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ 00743 uint32_t RESERVED7[8U]; 00744 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ 00745 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ 00746 } TPI_Type; 00747 00748 /* TPI Asynchronous Clock Prescaler Register Definitions */ 00749 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ 00750 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ 00751 00752 /* TPI Selected Pin Protocol Register Definitions */ 00753 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ 00754 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ 00755 00756 /* TPI Formatter and Flush Status Register Definitions */ 00757 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ 00758 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ 00759 00760 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ 00761 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ 00762 00763 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ 00764 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ 00765 00766 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ 00767 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ 00768 00769 /* TPI Formatter and Flush Control Register Definitions */ 00770 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ 00771 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ 00772 00773 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ 00774 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ 00775 00776 /* TPI TRIGGER Register Definitions */ 00777 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ 00778 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ 00779 00780 /* TPI Integration ETM Data Register Definitions (FIFO0) */ 00781 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ 00782 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ 00783 00784 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ 00785 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ 00786 00787 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ 00788 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ 00789 00790 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ 00791 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ 00792 00793 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ 00794 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ 00795 00796 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ 00797 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ 00798 00799 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ 00800 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ 00801 00802 /* TPI ITATBCTR2 Register Definitions */ 00803 #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ 00804 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ 00805 00806 /* TPI Integration ITM Data Register Definitions (FIFO1) */ 00807 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ 00808 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ 00809 00810 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ 00811 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ 00812 00813 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ 00814 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ 00815 00816 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ 00817 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ 00818 00819 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ 00820 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ 00821 00822 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ 00823 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ 00824 00825 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ 00826 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ 00827 00828 /* TPI ITATBCTR0 Register Definitions */ 00829 #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ 00830 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ 00831 00832 /* TPI Integration Mode Control Register Definitions */ 00833 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ 00834 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ 00835 00836 /* TPI DEVID Register Definitions */ 00837 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ 00838 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ 00839 00840 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ 00841 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ 00842 00843 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ 00844 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ 00845 00846 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ 00847 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ 00848 00849 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ 00850 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ 00851 00852 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ 00853 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ 00854 00855 /* TPI DEVTYPE Register Definitions */ 00856 #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ 00857 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ 00858 00859 #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ 00860 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ 00861 00862 /*@}*/ /* end of group CMSIS_TPI */ 00863 00864 00865 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 00866 /** 00867 \ingroup CMSIS_core_register 00868 \defgroup CMSIS_MPU Memory Protection Unit (MPU) 00869 \brief Type definitions for the Memory Protection Unit (MPU) 00870 @{ 00871 */ 00872 00873 /** 00874 \brief Structure type to access the Memory Protection Unit (MPU). 00875 */ 00876 typedef struct 00877 { 00878 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ 00879 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ 00880 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ 00881 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ 00882 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ 00883 uint32_t RESERVED0[7U]; 00884 __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ 00885 __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ 00886 } MPU_Type; 00887 00888 /* MPU Type Register Definitions */ 00889 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ 00890 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ 00891 00892 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ 00893 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ 00894 00895 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ 00896 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ 00897 00898 /* MPU Control Register Definitions */ 00899 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ 00900 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ 00901 00902 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ 00903 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ 00904 00905 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ 00906 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ 00907 00908 /* MPU Region Number Register Definitions */ 00909 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ 00910 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ 00911 00912 /* MPU Region Base Address Register Definitions */ 00913 #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ 00914 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ 00915 00916 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ 00917 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ 00918 00919 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ 00920 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ 00921 00922 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ 00923 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ 00924 00925 /* MPU Region Limit Address Register Definitions */ 00926 #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ 00927 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ 00928 00929 #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ 00930 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ 00931 00932 #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ 00933 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ 00934 00935 /* MPU Memory Attribute Indirection Register 0 Definitions */ 00936 #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ 00937 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ 00938 00939 #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ 00940 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ 00941 00942 #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ 00943 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ 00944 00945 #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ 00946 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ 00947 00948 /* MPU Memory Attribute Indirection Register 1 Definitions */ 00949 #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ 00950 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ 00951 00952 #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ 00953 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ 00954 00955 #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ 00956 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ 00957 00958 #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ 00959 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ 00960 00961 /*@} end of group CMSIS_MPU */ 00962 #endif 00963 00964 00965 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 00966 /** 00967 \ingroup CMSIS_core_register 00968 \defgroup CMSIS_SAU Security Attribution Unit (SAU) 00969 \brief Type definitions for the Security Attribution Unit (SAU) 00970 @{ 00971 */ 00972 00973 /** 00974 \brief Structure type to access the Security Attribution Unit (SAU). 00975 */ 00976 typedef struct 00977 { 00978 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ 00979 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ 00980 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) 00981 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ 00982 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ 00983 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ 00984 #endif 00985 } SAU_Type; 00986 00987 /* SAU Control Register Definitions */ 00988 #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ 00989 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ 00990 00991 #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ 00992 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ 00993 00994 /* SAU Type Register Definitions */ 00995 #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ 00996 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ 00997 00998 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) 00999 /* SAU Region Number Register Definitions */ 01000 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ 01001 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ 01002 01003 /* SAU Region Base Address Register Definitions */ 01004 #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ 01005 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ 01006 01007 /* SAU Region Limit Address Register Definitions */ 01008 #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ 01009 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ 01010 01011 #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ 01012 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ 01013 01014 #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ 01015 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ 01016 01017 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ 01018 01019 /*@} end of group CMSIS_SAU */ 01020 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 01021 01022 01023 /** 01024 \ingroup CMSIS_core_register 01025 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 01026 \brief Type definitions for the Core Debug Registers 01027 @{ 01028 */ 01029 01030 /** 01031 \brief Structure type to access the Core Debug Register (CoreDebug). 01032 */ 01033 typedef struct 01034 { 01035 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ 01036 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ 01037 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ 01038 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ 01039 uint32_t RESERVED4[1U]; 01040 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ 01041 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ 01042 } CoreDebug_Type; 01043 01044 /* Debug Halting Control and Status Register Definitions */ 01045 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ 01046 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ 01047 01048 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ 01049 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ 01050 01051 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ 01052 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ 01053 01054 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ 01055 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ 01056 01057 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ 01058 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ 01059 01060 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ 01061 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ 01062 01063 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ 01064 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ 01065 01066 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ 01067 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ 01068 01069 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ 01070 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ 01071 01072 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ 01073 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ 01074 01075 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ 01076 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ 01077 01078 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ 01079 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ 01080 01081 /* Debug Core Register Selector Register Definitions */ 01082 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ 01083 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ 01084 01085 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ 01086 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ 01087 01088 /* Debug Exception and Monitor Control Register */ 01089 #define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ 01090 #define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ 01091 01092 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ 01093 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ 01094 01095 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ 01096 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ 01097 01098 /* Debug Authentication Control Register Definitions */ 01099 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ 01100 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ 01101 01102 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ 01103 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ 01104 01105 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ 01106 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ 01107 01108 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ 01109 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ 01110 01111 /* Debug Security Control and Status Register Definitions */ 01112 #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ 01113 #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ 01114 01115 #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ 01116 #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ 01117 01118 #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ 01119 #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ 01120 01121 /*@} end of group CMSIS_CoreDebug */ 01122 01123 01124 /** 01125 \ingroup CMSIS_core_register 01126 \defgroup CMSIS_core_bitfield Core register bit field macros 01127 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). 01128 @{ 01129 */ 01130 01131 /** 01132 \brief Mask and shift a bit field value for use in a register bit range. 01133 \param[in] field Name of the register bit field. 01134 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. 01135 \return Masked and shifted value. 01136 */ 01137 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) 01138 01139 /** 01140 \brief Mask and shift a register value to extract a bit filed value. 01141 \param[in] field Name of the register bit field. 01142 \param[in] value Value of register. This parameter is interpreted as an uint32_t type. 01143 \return Masked and shifted bit field value. 01144 */ 01145 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) 01146 01147 /*@} end of group CMSIS_core_bitfield */ 01148 01149 01150 /** 01151 \ingroup CMSIS_core_register 01152 \defgroup CMSIS_core_base Core Definitions 01153 \brief Definitions for base addresses, unions, and structures. 01154 @{ 01155 */ 01156 01157 /* Memory mapping of Core Hardware */ 01158 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 01159 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ 01160 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ 01161 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ 01162 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 01163 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 01164 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 01165 01166 01167 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 01168 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 01169 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 01170 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ 01171 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ 01172 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ 01173 01174 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 01175 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ 01176 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ 01177 #endif 01178 01179 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 01180 #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ 01181 #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ 01182 #endif 01183 01184 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 01185 #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ 01186 #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ 01187 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ 01188 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ 01189 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ 01190 01191 #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ 01192 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ 01193 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ 01194 #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ 01195 01196 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 01197 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ 01198 #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ 01199 #endif 01200 01201 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 01202 /*@} */ 01203 01204 01205 01206 /******************************************************************************* 01207 * Hardware Abstraction Layer 01208 Core Function Interface contains: 01209 - Core NVIC Functions 01210 - Core SysTick Functions 01211 - Core Register Access Functions 01212 ******************************************************************************/ 01213 /** 01214 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 01215 */ 01216 01217 01218 01219 /* ########################## NVIC functions #################################### */ 01220 /** 01221 \ingroup CMSIS_Core_FunctionInterface 01222 \defgroup CMSIS_Core_NVICFunctions NVIC Functions 01223 \brief Functions that manage interrupts and exceptions via the NVIC. 01224 @{ 01225 */ 01226 01227 #ifdef CMSIS_NVIC_VIRTUAL 01228 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE 01229 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" 01230 #endif 01231 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE 01232 #else 01233 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for ARMv8-M Baseline */ 01234 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for ARMv8-M Baseline */ 01235 #define NVIC_EnableIRQ __NVIC_EnableIRQ 01236 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ 01237 #define NVIC_DisableIRQ __NVIC_DisableIRQ 01238 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ 01239 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ 01240 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ 01241 #define NVIC_GetActive __NVIC_GetActive 01242 #define NVIC_SetPriority __NVIC_SetPriority 01243 #define NVIC_GetPriority __NVIC_GetPriority 01244 #define NVIC_SystemReset __NVIC_SystemReset 01245 #endif /* CMSIS_NVIC_VIRTUAL */ 01246 01247 #ifdef CMSIS_VECTAB_VIRTUAL 01248 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE 01249 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" 01250 #endif 01251 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE 01252 #else 01253 #define NVIC_SetVector __NVIC_SetVector 01254 #define NVIC_GetVector __NVIC_GetVector 01255 #endif /* (CMSIS_VECTAB_VIRTUAL) */ 01256 01257 #define NVIC_USER_IRQ_OFFSET 16 01258 01259 01260 /* Interrupt Priorities are WORD accessible only under ARMv6M */ 01261 /* The following MACROS handle generation of the register offset and byte masks */ 01262 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) 01263 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) 01264 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) 01265 01266 01267 /** 01268 \brief Enable Interrupt 01269 \details Enables a device specific interrupt in the NVIC interrupt controller. 01270 \param [in] IRQn Device specific interrupt number. 01271 \note IRQn must not be negative. 01272 */ 01273 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) 01274 { 01275 if ((int32_t)(IRQn) >= 0) 01276 { 01277 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); 01278 } 01279 } 01280 01281 01282 /** 01283 \brief Get Interrupt Enable status 01284 \details Returns a device specific interrupt enable status from the NVIC interrupt controller. 01285 \param [in] IRQn Device specific interrupt number. 01286 \return 0 Interrupt is not enabled. 01287 \return 1 Interrupt is enabled. 01288 \note IRQn must not be negative. 01289 */ 01290 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) 01291 { 01292 if ((int32_t)(IRQn) >= 0) 01293 { 01294 return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01295 } 01296 else 01297 { 01298 return(0U); 01299 } 01300 } 01301 01302 01303 /** 01304 \brief Disable Interrupt 01305 \details Disables a device specific interrupt in the NVIC interrupt controller. 01306 \param [in] IRQn Device specific interrupt number. 01307 \note IRQn must not be negative. 01308 */ 01309 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) 01310 { 01311 if ((int32_t)(IRQn) >= 0) 01312 { 01313 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); 01314 __DSB(); 01315 __ISB(); 01316 } 01317 } 01318 01319 01320 /** 01321 \brief Get Pending Interrupt 01322 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. 01323 \param [in] IRQn Device specific interrupt number. 01324 \return 0 Interrupt status is not pending. 01325 \return 1 Interrupt status is pending. 01326 \note IRQn must not be negative. 01327 */ 01328 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) 01329 { 01330 if ((int32_t)(IRQn) >= 0) 01331 { 01332 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01333 } 01334 else 01335 { 01336 return(0U); 01337 } 01338 } 01339 01340 01341 /** 01342 \brief Set Pending Interrupt 01343 \details Sets the pending bit of a device specific interrupt in the NVIC pending register. 01344 \param [in] IRQn Device specific interrupt number. 01345 \note IRQn must not be negative. 01346 */ 01347 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) 01348 { 01349 if ((int32_t)(IRQn) >= 0) 01350 { 01351 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); 01352 } 01353 } 01354 01355 01356 /** 01357 \brief Clear Pending Interrupt 01358 \details Clears the pending bit of a device specific interrupt in the NVIC pending register. 01359 \param [in] IRQn Device specific interrupt number. 01360 \note IRQn must not be negative. 01361 */ 01362 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) 01363 { 01364 if ((int32_t)(IRQn) >= 0) 01365 { 01366 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); 01367 } 01368 } 01369 01370 01371 /** 01372 \brief Get Active Interrupt 01373 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. 01374 \param [in] IRQn Device specific interrupt number. 01375 \return 0 Interrupt status is not active. 01376 \return 1 Interrupt status is active. 01377 \note IRQn must not be negative. 01378 */ 01379 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) 01380 { 01381 if ((int32_t)(IRQn) >= 0) 01382 { 01383 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01384 } 01385 else 01386 { 01387 return(0U); 01388 } 01389 } 01390 01391 01392 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 01393 /** 01394 \brief Get Interrupt Target State 01395 \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. 01396 \param [in] IRQn Device specific interrupt number. 01397 \return 0 if interrupt is assigned to Secure 01398 \return 1 if interrupt is assigned to Non Secure 01399 \note IRQn must not be negative. 01400 */ 01401 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) 01402 { 01403 if ((int32_t)(IRQn) >= 0) 01404 { 01405 return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01406 } 01407 else 01408 { 01409 return(0U); 01410 } 01411 } 01412 01413 01414 /** 01415 \brief Set Interrupt Target State 01416 \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. 01417 \param [in] IRQn Device specific interrupt number. 01418 \return 0 if interrupt is assigned to Secure 01419 1 if interrupt is assigned to Non Secure 01420 \note IRQn must not be negative. 01421 */ 01422 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) 01423 { 01424 if ((int32_t)(IRQn) >= 0) 01425 { 01426 NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); 01427 return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01428 } 01429 else 01430 { 01431 return(0U); 01432 } 01433 } 01434 01435 01436 /** 01437 \brief Clear Interrupt Target State 01438 \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. 01439 \param [in] IRQn Device specific interrupt number. 01440 \return 0 if interrupt is assigned to Secure 01441 1 if interrupt is assigned to Non Secure 01442 \note IRQn must not be negative. 01443 */ 01444 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) 01445 { 01446 if ((int32_t)(IRQn) >= 0) 01447 { 01448 NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); 01449 return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01450 } 01451 else 01452 { 01453 return(0U); 01454 } 01455 } 01456 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 01457 01458 01459 /** 01460 \brief Set Interrupt Priority 01461 \details Sets the priority of a device specific interrupt or a processor exception. 01462 The interrupt number can be positive to specify a device specific interrupt, 01463 or negative to specify a processor exception. 01464 \param [in] IRQn Interrupt number. 01465 \param [in] priority Priority to set. 01466 \note The priority cannot be set for every processor exception. 01467 */ 01468 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 01469 { 01470 if ((int32_t)(IRQn) >= 0) 01471 { 01472 NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 01473 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 01474 } 01475 else 01476 { 01477 SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 01478 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 01479 } 01480 } 01481 01482 01483 /** 01484 \brief Get Interrupt Priority 01485 \details Reads the priority of a device specific interrupt or a processor exception. 01486 The interrupt number can be positive to specify a device specific interrupt, 01487 or negative to specify a processor exception. 01488 \param [in] IRQn Interrupt number. 01489 \return Interrupt Priority. 01490 Value is aligned automatically to the implemented priority bits of the microcontroller. 01491 */ 01492 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) 01493 { 01494 01495 if ((int32_t)(IRQn) >= 0) 01496 { 01497 return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); 01498 } 01499 else 01500 { 01501 return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); 01502 } 01503 } 01504 01505 01506 /** 01507 \brief Set Interrupt Vector 01508 \details Sets an interrupt vector in SRAM based interrupt vector table. 01509 The interrupt number can be positive to specify a device specific interrupt, 01510 or negative to specify a processor exception. 01511 VTOR must been relocated to SRAM before. 01512 If VTOR is not present address 0 must be mapped to SRAM. 01513 \param [in] IRQn Interrupt number 01514 \param [in] vector Address of interrupt handler function 01515 */ 01516 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) 01517 { 01518 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 01519 uint32_t *vectors = (uint32_t *)SCB->VTOR; 01520 #else 01521 uint32_t *vectors = (uint32_t *)0x0U; 01522 #endif 01523 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; 01524 } 01525 01526 01527 /** 01528 \brief Get Interrupt Vector 01529 \details Reads an interrupt vector from interrupt vector table. 01530 The interrupt number can be positive to specify a device specific interrupt, 01531 or negative to specify a processor exception. 01532 \param [in] IRQn Interrupt number. 01533 \return Address of interrupt handler function 01534 */ 01535 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) 01536 { 01537 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 01538 uint32_t *vectors = (uint32_t *)SCB->VTOR; 01539 #else 01540 uint32_t *vectors = (uint32_t *)0x0U; 01541 #endif 01542 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; 01543 } 01544 01545 01546 /** 01547 \brief System Reset 01548 \details Initiates a system reset request to reset the MCU. 01549 */ 01550 __STATIC_INLINE void __NVIC_SystemReset(void) 01551 { 01552 __DSB(); /* Ensure all outstanding memory accesses included 01553 buffered write are completed before reset */ 01554 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 01555 SCB_AIRCR_SYSRESETREQ_Msk); 01556 __DSB(); /* Ensure completion of memory access */ 01557 01558 for(;;) /* wait until reset */ 01559 { 01560 __NOP(); 01561 } 01562 } 01563 01564 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 01565 /** 01566 \brief Enable Interrupt (non-secure) 01567 \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. 01568 \param [in] IRQn Device specific interrupt number. 01569 \note IRQn must not be negative. 01570 */ 01571 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) 01572 { 01573 if ((int32_t)(IRQn) >= 0) 01574 { 01575 NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); 01576 } 01577 } 01578 01579 01580 /** 01581 \brief Get Interrupt Enable status (non-secure) 01582 \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. 01583 \param [in] IRQn Device specific interrupt number. 01584 \return 0 Interrupt is not enabled. 01585 \return 1 Interrupt is enabled. 01586 \note IRQn must not be negative. 01587 */ 01588 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) 01589 { 01590 if ((int32_t)(IRQn) >= 0) 01591 { 01592 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01593 } 01594 else 01595 { 01596 return(0U); 01597 } 01598 } 01599 01600 01601 /** 01602 \brief Disable Interrupt (non-secure) 01603 \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. 01604 \param [in] IRQn Device specific interrupt number. 01605 \note IRQn must not be negative. 01606 */ 01607 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) 01608 { 01609 if ((int32_t)(IRQn) >= 0) 01610 { 01611 NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); 01612 } 01613 } 01614 01615 01616 /** 01617 \brief Get Pending Interrupt (non-secure) 01618 \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. 01619 \param [in] IRQn Device specific interrupt number. 01620 \return 0 Interrupt status is not pending. 01621 \return 1 Interrupt status is pending. 01622 \note IRQn must not be negative. 01623 */ 01624 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) 01625 { 01626 if ((int32_t)(IRQn) >= 0) 01627 { 01628 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01629 } 01630 } 01631 01632 01633 /** 01634 \brief Set Pending Interrupt (non-secure) 01635 \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. 01636 \param [in] IRQn Device specific interrupt number. 01637 \note IRQn must not be negative. 01638 */ 01639 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) 01640 { 01641 if ((int32_t)(IRQn) >= 0) 01642 { 01643 NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); 01644 } 01645 } 01646 01647 01648 /** 01649 \brief Clear Pending Interrupt (non-secure) 01650 \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. 01651 \param [in] IRQn Device specific interrupt number. 01652 \note IRQn must not be negative. 01653 */ 01654 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) 01655 { 01656 if ((int32_t)(IRQn) >= 0) 01657 { 01658 NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); 01659 } 01660 } 01661 01662 01663 /** 01664 \brief Get Active Interrupt (non-secure) 01665 \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. 01666 \param [in] IRQn Device specific interrupt number. 01667 \return 0 Interrupt status is not active. 01668 \return 1 Interrupt status is active. 01669 \note IRQn must not be negative. 01670 */ 01671 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) 01672 { 01673 if ((int32_t)(IRQn) >= 0) 01674 { 01675 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01676 } 01677 else 01678 { 01679 return(0U); 01680 } 01681 } 01682 01683 01684 /** 01685 \brief Set Interrupt Priority (non-secure) 01686 \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. 01687 The interrupt number can be positive to specify a device specific interrupt, 01688 or negative to specify a processor exception. 01689 \param [in] IRQn Interrupt number. 01690 \param [in] priority Priority to set. 01691 \note The priority cannot be set for every non-secure processor exception. 01692 */ 01693 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) 01694 { 01695 if ((int32_t)(IRQn) >= 0) 01696 { 01697 NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 01698 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 01699 } 01700 else 01701 { 01702 SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 01703 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 01704 } 01705 } 01706 01707 01708 /** 01709 \brief Get Interrupt Priority (non-secure) 01710 \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. 01711 The interrupt number can be positive to specify a device specific interrupt, 01712 or negative to specify a processor exception. 01713 \param [in] IRQn Interrupt number. 01714 \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. 01715 */ 01716 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) 01717 { 01718 01719 if ((int32_t)(IRQn) >= 0) 01720 { 01721 return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); 01722 } 01723 else 01724 { 01725 return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); 01726 } 01727 } 01728 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ 01729 01730 /*@} end of CMSIS_Core_NVICFunctions */ 01731 01732 01733 /* ########################## FPU functions #################################### */ 01734 /** 01735 \ingroup CMSIS_Core_FunctionInterface 01736 \defgroup CMSIS_Core_FpuFunctions FPU Functions 01737 \brief Function that provides FPU type. 01738 @{ 01739 */ 01740 01741 /** 01742 \brief get FPU type 01743 \details returns the FPU type 01744 \returns 01745 - \b 0: No FPU 01746 - \b 1: Single precision FPU 01747 - \b 2: Double + Single precision FPU 01748 */ 01749 __STATIC_INLINE uint32_t SCB_GetFPUType(void) 01750 { 01751 return 0U; /* No FPU */ 01752 } 01753 01754 01755 /*@} end of CMSIS_Core_FpuFunctions */ 01756 01757 01758 01759 /* ########################## SAU functions #################################### */ 01760 /** 01761 \ingroup CMSIS_Core_FunctionInterface 01762 \defgroup CMSIS_Core_SAUFunctions SAU Functions 01763 \brief Functions that configure the SAU. 01764 @{ 01765 */ 01766 01767 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 01768 01769 /** 01770 \brief Enable SAU 01771 \details Enables the Security Attribution Unit (SAU). 01772 */ 01773 __STATIC_INLINE void TZ_SAU_Enable(void) 01774 { 01775 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); 01776 } 01777 01778 01779 01780 /** 01781 \brief Disable SAU 01782 \details Disables the Security Attribution Unit (SAU). 01783 */ 01784 __STATIC_INLINE void TZ_SAU_Disable(void) 01785 { 01786 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); 01787 } 01788 01789 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 01790 01791 /*@} end of CMSIS_Core_SAUFunctions */ 01792 01793 01794 01795 01796 /* ################################## SysTick function ############################################ */ 01797 /** 01798 \ingroup CMSIS_Core_FunctionInterface 01799 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 01800 \brief Functions that configure the System. 01801 @{ 01802 */ 01803 01804 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) 01805 01806 /** 01807 \brief System Tick Configuration 01808 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. 01809 Counter is in free running mode to generate periodic interrupts. 01810 \param [in] ticks Number of ticks between two interrupts. 01811 \return 0 Function succeeded. 01812 \return 1 Function failed. 01813 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 01814 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 01815 must contain a vendor-specific implementation of this function. 01816 */ 01817 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 01818 { 01819 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 01820 { 01821 return (1UL); /* Reload value impossible */ 01822 } 01823 01824 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 01825 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 01826 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 01827 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 01828 SysTick_CTRL_TICKINT_Msk | 01829 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 01830 return (0UL); /* Function successful */ 01831 } 01832 01833 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 01834 /** 01835 \brief System Tick Configuration (non-secure) 01836 \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. 01837 Counter is in free running mode to generate periodic interrupts. 01838 \param [in] ticks Number of ticks between two interrupts. 01839 \return 0 Function succeeded. 01840 \return 1 Function failed. 01841 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 01842 function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b> 01843 must contain a vendor-specific implementation of this function. 01844 01845 */ 01846 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) 01847 { 01848 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 01849 { 01850 return (1UL); /* Reload value impossible */ 01851 } 01852 01853 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 01854 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 01855 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ 01856 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 01857 SysTick_CTRL_TICKINT_Msk | 01858 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 01859 return (0UL); /* Function successful */ 01860 } 01861 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 01862 01863 #endif 01864 01865 /*@} end of CMSIS_Core_SysTickFunctions */ 01866 01867 01868 01869 01870 #ifdef __cplusplus 01871 } 01872 #endif 01873 01874 #endif /* __CORE_ARMV8MBL_H_DEPENDANT */ 01875 01876 #endif /* __CMSIS_GENERIC */
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