MCUGearBaseALPC1114.h

00001 /* MCU Gear Library, only for testing MCUGear without any circuit you connected.
00002  * Copyright (c) 2013, NestEgg Inc., http://www.mcugear.com/
00003  *
00004  * Permission is hereby granted, free of charge, to any person obtaining a copy
00005  * of this software and associated documentation files (the "Software"), to deal
00006  * in the Software without restriction, including without limitation the rights
00007  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
00008  * copies of the Software, and to permit persons to whom the Software is
00009  * furnished to do so, subject to the following conditions:
00010  *
00011  * The above copyright notice and this permission notice shall be included in
00012  * all copies or substantial portions of the Software.
00013  *
00014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
00015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
00016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
00017  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
00018  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
00019  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
00020  * THE SOFTWARE.
00021  */
00022 
00023 #include "commonALPC1114.h"
00024 
00025 
00026 #define FPGA_SYSINFO_0 0x00
00027 #define FPGA_SYSINFO_1 0x04
00028 #define FPGA_ENABLE    0x08
00029 #define FPGA_DETECT    0x14
00030 
00031 void fpga_write(int dev_adr,unsigned char adr, unsigned char data);
00032 unsigned char fpga_read(int dev_adr,unsigned char adr);
00033 void initBase(void);
00034 //void startReg(uint8_t bank);
00035 //void endReg(uint8_t bank);
00036 void deleteBank(uint8_t bank);
00037 void changeBank(uint8_t bank);
00038 
00039 
00040 // FGPGA CPU I/O
00041 typedef enum {
00042 
00043     IOMOSI = 0x80,//P0_9
00044     IOSCK,//P0_6
00045     IOMISO,//P0_8
00046     IOout4,//P1_0
00047     NC1,//NC1
00048     IOout5,//P1_1
00049     IOout2,//P0_7
00050     IORX,//P1_6
00051     NC2,//NC2
00052     IOin2,//P1_9
00053     IOTX,//P1_7
00054     IOin1,//P1_8
00055     IOout7,//P1_5
00056     IOout8,//P1_4
00057     IOout6,//P1_2
00058     IOout3,//P0_11
00059     IOout1,//P0_3
00060     IOCS,//P0_2
00061     IOSDA,//P0_5
00062     IOSCL//0_4
00063             
00064 /*  IOP0_9 = 0x80,//P0_9
00065     IOP0_6,//P0_6
00066     IOP0_8,//P0_8
00067     IOP1_0,//P1_0
00068     NC1,//NC1
00069     IOP1_1,//P1_1
00070     IOP0_7,//P0_7
00071     IOP1_6,//P1_6
00072     NC2,//NC2
00073     IOP1_9,//P1_9
00074     IOP1_7,//P1_7
00075     IOP1_8,//P1_8
00076     IOP1_5,//P1_5
00077     IOP1_4,//P1_4
00078     IOP1_2,//P1_2
00079     IOP0_11,//P0_11
00080     IOP0_3,//P0_3
00081     IOP0_2,//P0_2
00082     IOP0_5,//P0_5
00083     IO0_4//0_4
00084 */
00085 } en_cpu_io;
00086 
00087 // FPGA EXT I/O
00088 typedef enum {
00089   IO_CON1_1 = 0,
00090   IO_CON1_2,
00091   IO_CON1_3,
00092   IO_CON1_4,
00093   IO_CON2_1,
00094   IO_CON2_2,
00095   IO_CON2_3,
00096   IO_CON2_4,
00097   IO_CON3_1,
00098   IO_CON3_2,
00099   IO_CON3_3,
00100   IO_CON3_4,
00101   IO_CON4_1,
00102   IO_CON4_2,
00103   IO_CON4_3,
00104   IO_CON4_4,
00105   IO_CON5_1,
00106   IO_CON5_2,
00107   IO_CON5_3,
00108   IO_CON5_4,
00109   IO_CON6_1,
00110   IO_CON6_2,
00111   IO_CON6_3,
00112   IO_CON6_4,
00113   IO_CON7_1,
00114   IO_CON7_2,
00115   IO_CON7_3,
00116   IO_CON7_4,
00117   IO_CON8_1,
00118   IO_CON8_2,
00119   IO_CON8_3,
00120   IO_CON8_4,
00121   IO_CON9_1,
00122   IO_CON9_2,
00123   IO_CON9_3,
00124   IO_CON9_4,
00125   IO_CON10_1,
00126   IO_CON10_2,
00127   IO_CON10_3,
00128   IO_CON10_4,
00129   IO_CON11_1,
00130   IO_CON11_2,
00131   IO_CON11_3,
00132   IO_CON11_4,
00133   IO_CON12_1,
00134   IO_CON12_2,
00135   IO_CON12_3,
00136   IO_CON12_4
00137 } en_fpga_io;
00138 
00139 typedef enum {
00140   IO_REG_EN = 0x80,
00141   IO_REG_OUT_DIR = 0x40,
00142   IO_REG_IN_DIR  = 0x00,
00143   IO_REG_DISABLE = 0x3f
00144 } en_fpga_io_reg;
00145 
00146