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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_flash.c
00004   * @author  MCD Application Team
00005   * @version V1.7.1
00006   * @date    20-May-2016
00007   * @brief   This file provides firmware functions to manage the following 
00008   *          functionalities of the FLASH peripheral:
00009   *            + FLASH Interface configuration
00010   *            + FLASH Memory Programming
00011   *            + Option Bytes Programming
00012   *            + Interrupts and flags management
00013   *  
00014  @verbatim    
00015  ===============================================================================
00016                         ##### How to use this driver #####
00017  ===============================================================================
00018     [..]                             
00019       This driver provides functions to configure and program the FLASH memory 
00020       of all STM32F4xx devices. These functions are split in 4 groups:
00021    
00022       (#) FLASH Interface configuration functions: this group includes the
00023           management of the following features:
00024         (++) Set the latency
00025         (++) Enable/Disable the prefetch buffer
00026         (++) Enable/Disable the Instruction cache and the Data cache
00027         (++) Reset the Instruction cache and the Data cache
00028     
00029       (#) FLASH Memory Programming functions: this group includes all needed
00030           functions to erase and program the main memory:
00031         (++) Lock and Unlock the FLASH interface
00032         (++) Erase function: Erase sector, erase all sectors
00033         (++) Program functions: byte, half word, word and double word
00034     
00035       (#) Option Bytes Programming functions: this group includes all needed
00036           functions to manage the Option Bytes:
00037         (++) Set/Reset the write protection
00038         (++) Set the Read protection Level
00039         (++) Set the BOR level
00040         (++) Program the user Option Bytes
00041         (++) Launch the Option Bytes loader
00042     
00043       (#) Interrupts and flags management functions: this group 
00044           includes all needed functions to:
00045         (++) Enable/Disable the FLASH interrupt sources
00046         (++) Get flags status
00047         (++) Clear flags
00048         (++) Get FLASH operation status
00049         (++) Wait for last FLASH operation   
00050  @endverbatim
00051   ******************************************************************************
00052   * @attention
00053   *
00054   * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
00055   *
00056   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00057   * You may not use this file except in compliance with the License.
00058   * You may obtain a copy of the License at:
00059   *
00060   *        http://www.st.com/software_license_agreement_liberty_v2
00061   *
00062   * Unless required by applicable law or agreed to in writing, software 
00063   * distributed under the License is distributed on an "AS IS" BASIS, 
00064   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00065   * See the License for the specific language governing permissions and
00066   * limitations under the License.
00067   *
00068   ******************************************************************************
00069   */
00070  
00071 /* Includes ------------------------------------------------------------------*/
00072 #include "stm32f4xx_flash.h"
00073  
00074 /** @addtogroup STM32F4xx_StdPeriph_Driver
00075   * @{
00076   */
00077  
00078 /** @defgroup FLASH 
00079   * @brief FLASH driver modules
00080   * @{
00081   */ 
00082  
00083 /* Private typedef -----------------------------------------------------------*/
00084 /* Private define ------------------------------------------------------------*/ 
00085 #define SECTOR_MASK               ((uint32_t)0xFFFFFF07)
00086  
00087 /* Private macro -------------------------------------------------------------*/
00088 /* Private variables ---------------------------------------------------------*/
00089 /* Private function prototypes -----------------------------------------------*/
00090 /* Private functions ---------------------------------------------------------*/
00091  
00092 /** @defgroup FLASH_Private_Functions
00093   * @{
00094   */ 
00095  
00096 /** @defgroup FLASH_Group1 FLASH Interface configuration functions
00097   *  @brief   FLASH Interface configuration functions 
00098  *
00099  
00100 @verbatim   
00101  ===============================================================================
00102               ##### FLASH Interface configuration functions #####
00103  ===============================================================================
00104     [..]
00105       This group includes the following functions:
00106       (+) void FLASH_SetLatency(uint32_t FLASH_Latency)
00107           To correctly read data from FLASH memory, the number of wait states (LATENCY) 
00108           must be correctly programmed according to the frequency of the CPU clock 
00109           (HCLK) and the supply voltage of the device.
00110     [..]      
00111       For STM32F405xx/07xx and STM32F415xx/17xx devices
00112  +-------------------------------------------------------------------------------------+
00113  | Latency       |                HCLK clock frequency (MHz)                           |
00114  |               |---------------------------------------------------------------------|
00115  |               | voltage range  | voltage range  | voltage range   | voltage range   |
00116  |               | 2.7 V - 3.6 V  | 2.4 V - 2.7 V  | 2.1 V - 2.4 V   | 1.8 V - 2.1 V   |
00117  |---------------|----------------|----------------|-----------------|-----------------|
00118  |0WS(1CPU cycle)|0 < HCLK <= 30  |0 < HCLK <= 24  |0 < HCLK <= 22   |0 < HCLK <= 20   |
00119  |---------------|----------------|----------------|-----------------|-----------------|
00120  |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44  |20 < HCLK <= 40  |
00121  |---------------|----------------|----------------|-----------------|-----------------|
00122  |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66  |40 < HCLK <= 60  |
00123  |---------------|----------------|----------------|-----------------|-----------------|
00124  |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88  |60 < HCLK <= 80  |
00125  |---------------|----------------|----------------|-----------------|-----------------|
00126  |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 |
00127  |---------------|----------------|----------------|-----------------|-----------------|
00128  |5WS(6CPU cycle)|150< HCLK <= 168|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120|
00129  |---------------|----------------|----------------|-----------------|-----------------|
00130  |6WS(7CPU cycle)|      NA        |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140|
00131  |---------------|----------------|----------------|-----------------|-----------------|
00132  |7WS(8CPU cycle)|      NA        |      NA        |154 < HCLK <= 168|140 < HCLK <= 160|
00133  +---------------|----------------|----------------|-----------------|-----------------+
00134  
00135     [..]      
00136       For STM32F42xxx/43xxx devices
00137  +-------------------------------------------------------------------------------------+
00138  | Latency       |                HCLK clock frequency (MHz)                           |
00139  |               |---------------------------------------------------------------------|
00140  |               | voltage range  | voltage range  | voltage range   | voltage range   |
00141  |               | 2.7 V - 3.6 V  | 2.4 V - 2.7 V  | 2.1 V - 2.4 V   | 1.8 V - 2.1 V   |
00142  |---------------|----------------|----------------|-----------------|-----------------|
00143  |0WS(1CPU cycle)|0 < HCLK <= 30  |0 < HCLK <= 24  |0 < HCLK <= 22   |0 < HCLK <= 20   |
00144  |---------------|----------------|----------------|-----------------|-----------------|
00145  |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44  |20 < HCLK <= 40  |
00146  |---------------|----------------|----------------|-----------------|-----------------|
00147  |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66  |40 < HCLK <= 60  |
00148  |---------------|----------------|----------------|-----------------|-----------------|
00149  |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88  |60 < HCLK <= 80  |
00150  |---------------|----------------|----------------|-----------------|-----------------|
00151  |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 |
00152  |---------------|----------------|----------------|-----------------|-----------------|
00153  |5WS(6CPU cycle)|120< HCLK <= 180|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120|
00154  |---------------|----------------|----------------|-----------------|-----------------|
00155  |6WS(7CPU cycle)|      NA        |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140|
00156  |---------------|----------------|----------------|-----------------|-----------------|
00157  |7WS(8CPU cycle)|      NA        |168< HCLK <= 180|154 < HCLK <= 176|140 < HCLK <= 160|
00158  |---------------|----------------|----------------|-----------------|-----------------|
00159  |8WS(9CPU cycle)|      NA        |      NA        |176 < HCLK <= 180|160 < HCLK <= 168|
00160  +-------------------------------------------------------------------------------------+
00161    
00162     [..]
00163     For STM32F401x devices
00164  +-------------------------------------------------------------------------------------+
00165  | Latency       |                HCLK clock frequency (MHz)                           |
00166  |               |---------------------------------------------------------------------|
00167  |               | voltage range  | voltage range  | voltage range   | voltage range   |
00168  |               | 2.7 V - 3.6 V  | 2.4 V - 2.7 V  | 2.1 V - 2.4 V   | 1.8 V - 2.1 V   |
00169  |---------------|----------------|----------------|-----------------|-----------------|
00170  |0WS(1CPU cycle)|0 < HCLK <= 30  |0 < HCLK <= 24  |0 < HCLK <= 22   |0 < HCLK <= 20   |
00171  |---------------|----------------|----------------|-----------------|-----------------|
00172  |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44  |20 < HCLK <= 40  |
00173  |---------------|----------------|----------------|-----------------|-----------------|
00174  |2WS(3CPU cycle)|60 < HCLK <= 84 |48 < HCLK <= 72 |44 < HCLK <= 66  |40 < HCLK <= 60  |
00175  |---------------|----------------|----------------|-----------------|-----------------|
00176  |3WS(4CPU cycle)|      NA        |72 < HCLK <= 84 |66 < HCLK <= 84  |60 < HCLK <= 80  |
00177  |---------------|----------------|----------------|-----------------|-----------------|
00178  |4WS(5CPU cycle)|      NA        |      NA        |      NA         |80 < HCLK <= 84  |
00179  +-------------------------------------------------------------------------------------+
00180  
00181     [..]
00182     For STM32F410xx/STM32F411xE devices
00183  +-------------------------------------------------------------------------------------+
00184  | Latency       |                HCLK clock frequency (MHz)                           |
00185  |               |---------------------------------------------------------------------|
00186  |               | voltage range  | voltage range  | voltage range   | voltage range   |
00187  |               | 2.7 V - 3.6 V  | 2.4 V - 2.7 V  | 2.1 V - 2.4 V   | 1.8 V - 2.1 V   |
00188  |---------------|----------------|----------------|-----------------|-----------------|
00189  |0WS(1CPU cycle)|0 < HCLK <= 30  |0 < HCLK <= 24  |0 < HCLK <= 18   |0 < HCLK <= 16   |
00190  |---------------|----------------|----------------|-----------------|-----------------|
00191  |1WS(2CPU cycle)|30 < HCLK <= 64 |24 < HCLK <= 48 |18 < HCLK <= 36  |16 < HCLK <= 32  |
00192  |---------------|----------------|----------------|-----------------|-----------------|
00193  |2WS(3CPU cycle)|64 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54  |32 < HCLK <= 48  |
00194  |---------------|----------------|----------------|-----------------|-----------------|
00195  |3WS(4CPU cycle)|90 < HCLK <= 100|72 < HCLK <= 96 |54 < HCLK <= 72  |48 < HCLK <= 64  |
00196  |---------------|----------------|----------------|-----------------|-----------------|
00197  |4WS(5CPU cycle)|      NA        |96 < HCLK <= 100|72 < HCLK <= 90  |64 < HCLK <= 80  |
00198  |---------------|----------------|----------------|-----------------|-----------------|
00199  |5WS(6CPU cycle)|      NA        |       NA       |90 < HCLK <= 100 |80 < HCLK <= 96  |
00200  |---------------|----------------|----------------|-----------------|-----------------|
00201  |6WS(7CPU cycle)|      NA        |       NA       |        NA       |96 < HCLK <= 100 |
00202  +-------------------------------------------------------------------------------------+
00203  
00204  [..]
00205  +-------------------------------------------------------------------------------------------------------------------+
00206  |               | voltage range  | voltage range  | voltage range   | voltage range   | voltage range 2.7 V - 3.6 V |
00207  |               | 2.7 V - 3.6 V  | 2.4 V - 2.7 V  | 2.1 V - 2.4 V   | 1.8 V - 2.1 V   | with External Vpp = 9V      |
00208  |---------------|----------------|----------------|-----------------|-----------------|-----------------------------|
00209  |Max Parallelism|      x32       |               x16                |       x8        |          x64                |
00210  |---------------|----------------|----------------|-----------------|-----------------|-----------------------------|
00211  |PSIZE[1:0]     |      10        |               01                 |       00        |           11                |
00212  +-------------------------------------------------------------------------------------------------------------------+
00213  
00214       -@- On STM32F405xx/407xx and STM32F415xx/417xx devices: 
00215            (++) when VOS = '0' Scale 2 mode, the maximum value of fHCLK = 144MHz. 
00216            (++) when VOS = '1' Scale 1 mode, the maximum value of fHCLK = 168MHz. 
00217           [..] 
00218           On STM32F42xxx/43xxx devices:
00219            (++) when VOS[1:0] = '0x01' Scale 3 mode, the maximum value of fHCLK is 120MHz.
00220            (++) when VOS[1:0] = '0x10' Scale 2 mode, the maximum value of fHCLK is 144MHz if OverDrive OFF and 168MHz if OverDrive ON.
00221            (++) when VOS[1:0] = '0x11' Scale 1 mode, the maximum value of fHCLK is 168MHz if OverDrive OFF and 180MHz if OverDrive ON. 
00222           [..]
00223           On STM32F401x devices:
00224            (++) when VOS[1:0] = '0x01' Scale 3 mode, the maximum value of fHCLK is 60MHz.
00225            (++) when VOS[1:0] = '0x10' Scale 2 mode, the maximum value of fHCLK is 84MHz.
00226           [..]  
00227           On STM32F410xx/STM32F411xE devices:
00228            (++) when VOS[1:0] = '0x01' Scale 3 mode, the maximum value of fHCLK is 64MHz.
00229            (++) when VOS[1:0] = '0x10' Scale 2 mode, the maximum value of fHCLK is 84MHz.
00230            (++) when VOS[1:0] = '0x11' Scale 1 mode, the maximum value of fHCLK is 100MHz.
00231  
00232         For more details please refer product DataSheet 
00233            You can use PWR_MainRegulatorModeConfig() function to control VOS bits.
00234  
00235       (+) void FLASH_PrefetchBufferCmd(FunctionalState NewState)
00236       (+) void FLASH_InstructionCacheCmd(FunctionalState NewState)
00237       (+) void FLASH_DataCacheCmd(FunctionalState NewState)
00238       (+) void FLASH_InstructionCacheReset(void)
00239       (+) void FLASH_DataCacheReset(void)
00240       
00241     [..]   
00242       The unlock sequence is not needed for these functions.
00243  
00244 @endverbatim
00245   * @{
00246   */
00247  
00248 /**
00249   * @brief  Sets the code latency value.  
00250   * @param  FLASH_Latency: specifies the FLASH Latency value.
00251   *          This parameter can be one of the following values:
00252   *            @arg FLASH_Latency_0: FLASH Zero Latency cycle
00253   *            @arg FLASH_Latency_1: FLASH One Latency cycle
00254   *            @arg FLASH_Latency_2: FLASH Two Latency cycles
00255   *            @arg FLASH_Latency_3: FLASH Three Latency cycles
00256   *            @arg FLASH_Latency_4: FLASH Four Latency cycles 
00257   *            @arg FLASH_Latency_5: FLASH Five Latency cycles 
00258   *            @arg FLASH_Latency_6: FLASH Six Latency cycles
00259   *            @arg FLASH_Latency_7: FLASH Seven Latency cycles 
00260   *            @arg FLASH_Latency_8: FLASH Eight Latency cycles
00261   *            @arg FLASH_Latency_9: FLASH Nine Latency cycles
00262   *            @arg FLASH_Latency_10: FLASH Teen Latency cycles 
00263   *            @arg FLASH_Latency_11: FLASH Eleven Latency cycles 
00264   *            @arg FLASH_Latency_12: FLASH Twelve Latency cycles
00265   *            @arg FLASH_Latency_13: FLASH Thirteen Latency cycles
00266   *            @arg FLASH_Latency_14: FLASH Fourteen Latency cycles
00267   *            @arg FLASH_Latency_15: FLASH Fifteen Latency cycles 
00268   *              
00269   * @note For STM32F405xx/407xx, STM32F415xx/417xx, STM32F401xx/411xE and STM32F412xG devices
00270   *       this parameter can be a value between FLASH_Latency_0 and FLASH_Latency_7.
00271   *
00272   * @note For STM32F42xxx/43xxx devices this parameter can be a value between 
00273   *       FLASH_Latency_0 and FLASH_Latency_15. 
00274   *         
00275   * @retval None
00276   */
00277 void FLASH_SetLatency(uint32_t FLASH_Latency)
00278 {
00279   /* Check the parameters */
00280   assert_param(IS_FLASH_LATENCY(FLASH_Latency));
00281   
00282   /* Perform Byte access to FLASH_ACR[8:0] to set the Latency value */
00283   *(__IO uint8_t *)ACR_BYTE0_ADDRESS = (uint8_t)FLASH_Latency;
00284 }
00285  
00286 /**
00287   * @brief  Enables or disables the Prefetch Buffer.
00288   * @param  NewState: new state of the Prefetch Buffer.
00289   *          This parameter  can be: ENABLE or DISABLE.
00290   * @retval None
00291   */
00292 void FLASH_PrefetchBufferCmd(FunctionalState NewState)
00293 {
00294   /* Check the parameters */
00295   assert_param(IS_FUNCTIONAL_STATE(NewState));
00296   
00297   /* Enable or disable the Prefetch Buffer */
00298   if(NewState != DISABLE)
00299   {
00300     FLASH->ACR |= FLASH_ACR_PRFTEN;
00301   }
00302   else
00303   {
00304     FLASH->ACR &= (~FLASH_ACR_PRFTEN);
00305   }
00306 }
00307  
00308 /**
00309   * @brief  Enables or disables the Instruction Cache feature.
00310   * @param  NewState: new state of the Instruction Cache.
00311   *          This parameter  can be: ENABLE or DISABLE.
00312   * @retval None
00313   */
00314 void FLASH_InstructionCacheCmd(FunctionalState NewState)
00315 {
00316   /* Check the parameters */
00317   assert_param(IS_FUNCTIONAL_STATE(NewState));
00318   
00319   if(NewState != DISABLE)
00320   {
00321     FLASH->ACR |= FLASH_ACR_ICEN;
00322   }
00323   else
00324   {
00325     FLASH->ACR &= (~FLASH_ACR_ICEN);
00326   }
00327 }
00328  
00329 /**
00330   * @brief  Enables or disables the Data Cache feature.
00331   * @param  NewState: new state of the Data Cache.
00332   *          This parameter  can be: ENABLE or DISABLE.
00333   * @retval None
00334   */
00335 void FLASH_DataCacheCmd(FunctionalState NewState)
00336 {
00337   /* Check the parameters */
00338   assert_param(IS_FUNCTIONAL_STATE(NewState));
00339   
00340   if(NewState != DISABLE)
00341   {
00342     FLASH->ACR |= FLASH_ACR_DCEN;
00343   }
00344   else
00345   {
00346     FLASH->ACR &= (~FLASH_ACR_DCEN);
00347   }
00348 }
00349  
00350 /**
00351   * @brief  Resets the Instruction Cache.
00352   * @note   This function must be used only when the Instruction Cache is disabled.  
00353   * @param  None
00354   * @retval None
00355   */
00356 void FLASH_InstructionCacheReset(void)
00357 {
00358   FLASH->ACR |= FLASH_ACR_ICRST;
00359 }
00360  
00361 /**
00362   * @brief  Resets the Data Cache.
00363   * @note   This function must be used only when the Data Cache is disabled.  
00364   * @param  None
00365   * @retval None
00366   */
00367 void FLASH_DataCacheReset(void)
00368 {
00369   FLASH->ACR |= FLASH_ACR_DCRST;
00370 }
00371  
00372 /**
00373   * @}
00374   */
00375  
00376 /** @defgroup FLASH_Group2 FLASH Memory Programming functions
00377  *  @brief   FLASH Memory Programming functions
00378  *
00379 @verbatim   
00380  ===============================================================================
00381                 ##### FLASH Memory Programming functions #####
00382  ===============================================================================   
00383     [..]
00384       This group includes the following functions:
00385       (+) void FLASH_Unlock(void)
00386       (+) void FLASH_Lock(void)
00387       (+) FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange)
00388       (+) FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange)       
00389       (+) FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data)
00390       (+) FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
00391       (+) FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
00392       (+) FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data)
00393           The following functions can be used only for STM32F42xxx/43xxx devices. 
00394       (+) FLASH_Status FLASH_EraseAllBank1Sectors(uint8_t VoltageRange)
00395       (+) FLASH_Status FLASH_EraseAllBank2Sectors(uint8_t VoltageRange)    
00396     [..]   
00397       Any operation of erase or program should follow these steps:
00398       (#) Call the FLASH_Unlock() function to enable the FLASH control register access
00399  
00400       (#) Call the desired function to erase sector(s) or program data
00401  
00402       (#) Call the FLASH_Lock() function to disable the FLASH control register access
00403           (recommended to protect the FLASH memory against possible unwanted operation)
00404     
00405 @endverbatim
00406   * @{
00407   */
00408  
00409 /**
00410   * @brief  Unlocks the FLASH control register access
00411   * @param  None
00412   * @retval None
00413   */
00414 void FLASH_Unlock(void)
00415 {
00416   if((FLASH->CR & FLASH_CR_LOCK) != RESET)
00417   {
00418     /* Authorize the FLASH Registers access */
00419     FLASH->KEYR = FLASH_KEY1;
00420     FLASH->KEYR = FLASH_KEY2;
00421   }  
00422 }
00423  
00424 /**
00425   * @brief  Locks the FLASH control register access
00426   * @param  None
00427   * @retval None
00428   */
00429 void FLASH_Lock(void)
00430 {
00431   /* Set the LOCK Bit to lock the FLASH Registers access */
00432   FLASH->CR |= FLASH_CR_LOCK;
00433 }
00434  
00435 /**
00436   * @brief  Erases a specified FLASH Sector.
00437   *
00438   * @note   If an erase and a program operations are requested simultaneously,    
00439   *         the erase operation is performed before the program one.
00440   *
00441   * @param  FLASH_Sector: The Sector number to be erased.
00442   *
00443   *  @note  For STM32F405xx/407xx and STM32F415xx/417xx devices this parameter can 
00444   *         be a value between FLASH_Sector_0 and FLASH_Sector_11.
00445   *
00446   *         For STM32F42xxx/43xxx devices this parameter can be a value between 
00447   *         FLASH_Sector_0 and FLASH_Sector_23.
00448   *
00449   *         For STM32F401xx devices this parameter can be a value between 
00450   *         FLASH_Sector_0 and FLASH_Sector_5.
00451   *
00452   *         For STM32F411xE and STM32F412xG devices this parameter can be a value between 
00453   *         FLASH_Sector_0 and FLASH_Sector_7.
00454   *
00455   *         For STM32F410xx devices this parameter can be a value between 
00456   *         FLASH_Sector_0 and FLASH_Sector_4.
00457   *
00458   * @param  VoltageRange: The device voltage range which defines the erase parallelism.  
00459   *          This parameter can be one of the following values:
00460   *            @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V, 
00461   *                                  the operation will be done by byte (8-bit) 
00462   *            @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V,
00463   *                                  the operation will be done by half word (16-bit)
00464   *            @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V,
00465   *                                  the operation will be done by word (32-bit)
00466   *            @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, 
00467   *                                  the operation will be done by double word (64-bit)
00468   *       
00469   * @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
00470   *                       FLASH_ERROR_WRP2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
00471   */
00472 FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange)
00473 {
00474   uint32_t tmp_psize = 0x0;
00475   FLASH_Status status = FLASH_COMPLETE2;
00476  
00477   /* Check the parameters */
00478   assert_param(IS_FLASH_SECTOR(FLASH_Sector));
00479   assert_param(IS_VOLTAGERANGE(VoltageRange));
00480   
00481   if(VoltageRange == VoltageRange_1)
00482   {
00483      tmp_psize = FLASH_PSIZE_BYTE;
00484   }
00485   else if(VoltageRange == VoltageRange_2)
00486   {
00487     tmp_psize = FLASH_PSIZE_HALF_WORD;
00488   }
00489   else if(VoltageRange == VoltageRange_3)
00490   {
00491     tmp_psize = FLASH_PSIZE_WORD;
00492   }
00493   else
00494   {
00495     tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
00496   }
00497   /* Wait for last operation to be completed */
00498   status = FLASH_WaitForLastOperation2();
00499   
00500   if(status == FLASH_COMPLETE2)
00501   { 
00502     /* if the previous operation is completed, proceed to erase the sector */
00503     FLASH->CR &= CR_PSIZE_MASK;
00504     FLASH->CR |= tmp_psize;
00505     FLASH->CR &= SECTOR_MASK;
00506     FLASH->CR |= FLASH_CR_SER | FLASH_Sector;
00507     FLASH->CR |= FLASH_CR_STRT;
00508     
00509     /* Wait for last operation to be completed */
00510     status = FLASH_WaitForLastOperation2();
00511     
00512     /* if the erase operation is completed, disable the SER Bit */
00513     FLASH->CR &= (~FLASH_CR_SER);
00514     FLASH->CR &= SECTOR_MASK; 
00515   }
00516   /* Return the Erase Status */
00517   return status;
00518 }
00519  
00520 /**
00521   * @brief  Erases all FLASH Sectors.
00522   *
00523   * @note   If an erase and a program operations are requested simultaneously,    
00524   *         the erase operation is performed before the program one.
00525   *  
00526   * @param  VoltageRange: The device voltage range which defines the erase parallelism.  
00527   *          This parameter can be one of the following values:
00528   *            @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V, 
00529   *                                  the operation will be done by byte (8-bit) 
00530   *            @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V,
00531   *                                  the operation will be done by half word (16-bit)
00532   *            @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V,
00533   *                                  the operation will be done by word (32-bit)
00534   *            @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, 
00535   *                                  the operation will be done by double word (64-bit)
00536   *       
00537   * @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
00538   *                       FLASH_ERROR_WRP2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
00539   */
00540 FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange)
00541 {
00542   uint32_t tmp_psize = 0x0;
00543   FLASH_Status status = FLASH_COMPLETE2;
00544   
00545   /* Wait for last operation to be completed */
00546   status = FLASH_WaitForLastOperation2();
00547   assert_param(IS_VOLTAGERANGE(VoltageRange));
00548   
00549   if(VoltageRange == VoltageRange_1)
00550   {
00551      tmp_psize = FLASH_PSIZE_BYTE;
00552   }
00553   else if(VoltageRange == VoltageRange_2)
00554   {
00555     tmp_psize = FLASH_PSIZE_HALF_WORD;
00556   }
00557   else if(VoltageRange == VoltageRange_3)
00558   {
00559     tmp_psize = FLASH_PSIZE_WORD;
00560   }
00561   else
00562   {
00563     tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
00564   }  
00565   if(status == FLASH_COMPLETE2)
00566   {
00567     /* if the previous operation is completed, proceed to erase all sectors */
00568 #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
00569     FLASH->CR &= CR_PSIZE_MASK;
00570     FLASH->CR |= tmp_psize;
00571     FLASH->CR |= (FLASH_CR_MER1 | FLASH_CR_MER2);
00572     FLASH->CR |= FLASH_CR_STRT;
00573     
00574     /* Wait for last operation to be completed */
00575     status = FLASH_WaitForLastOperation2();
00576  
00577     /* if the erase operation is completed, disable the MER Bit */
00578     FLASH->CR &= ~(FLASH_CR_MER1 | FLASH_CR_MER2);
00579 #endif /* STM32F427_437xx ||  STM32F429_439xx ||  STM32F469_479xx */
00580  
00581 #if defined(STM32F40_41xxx) || defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F412xG) || defined(STM32F446xx)
00582     FLASH->CR &= CR_PSIZE_MASK;
00583     FLASH->CR |= tmp_psize;
00584     FLASH->CR |= FLASH_CR_MER;
00585     FLASH->CR |= FLASH_CR_STRT;
00586     
00587     /* Wait for last operation to be completed */
00588     status = FLASH_WaitForLastOperation2();
00589  
00590     /* if the erase operation is completed, disable the MER Bit */
00591     FLASH->CR &= (~FLASH_CR_MER);
00592 #endif /* STM32F40_41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F412xG || STM32F446xx */
00593  
00594   }   
00595   /* Return the Erase Status */
00596   return status;
00597 }
00598  
00599 /**
00600   * @brief  Erases all FLASH Sectors in Bank 1.
00601   *
00602   * @note   This function can be used only for STM32F42xxx/43xxx devices.
00603   *      
00604   * @note   If an erase and a program operations are requested simultaneously,    
00605   *         the erase operation is performed before the program one. 
00606   *  
00607   * @param  VoltageRange: The device voltage range which defines the erase parallelism.  
00608   *          This parameter can be one of the following values:
00609   *            @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V, 
00610   *                                  the operation will be done by byte (8-bit) 
00611   *            @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V,
00612   *                                  the operation will be done by half word (16-bit)
00613   *            @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V,
00614   *                                  the operation will be done by word (32-bit)
00615   *            @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, 
00616   *                                  the operation will be done by double word (64-bit)
00617   *       
00618   * @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
00619   *                       FLASH_ERROR_WRP2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
00620   */
00621 FLASH_Status FLASH_EraseAllBank1Sectors(uint8_t VoltageRange)
00622 {
00623   uint32_t tmp_psize = 0x0;
00624   FLASH_Status status = FLASH_COMPLETE2;
00625   
00626   /* Wait for last operation to be completed */
00627   status = FLASH_WaitForLastOperation2();
00628   assert_param(IS_VOLTAGERANGE(VoltageRange));
00629   
00630   if(VoltageRange == VoltageRange_1)
00631   {
00632      tmp_psize = FLASH_PSIZE_BYTE;
00633   }
00634   else if(VoltageRange == VoltageRange_2)
00635   {
00636     tmp_psize = FLASH_PSIZE_HALF_WORD;
00637   }
00638   else if(VoltageRange == VoltageRange_3)
00639   {
00640     tmp_psize = FLASH_PSIZE_WORD;
00641   }
00642   else
00643   {
00644     tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
00645   }  
00646   if(status == FLASH_COMPLETE2)
00647   {
00648     /* if the previous operation is completed, proceed to erase all sectors */
00649      FLASH->CR &= CR_PSIZE_MASK;
00650      FLASH->CR |= tmp_psize;
00651      FLASH->CR |= FLASH_CR_MER1;
00652      FLASH->CR |= FLASH_CR_STRT;
00653     
00654     /* Wait for last operation to be completed */
00655     status = FLASH_WaitForLastOperation2();
00656  
00657     /* if the erase operation is completed, disable the MER Bit */
00658     FLASH->CR &= (~FLASH_CR_MER1);
00659  
00660   }   
00661   /* Return the Erase Status */
00662   return status;
00663 }
00664  
00665  
00666 /**
00667   * @brief  Erases all FLASH Sectors in Bank 2.
00668   *
00669   * @note   This function can be used only for STM32F42xxx/43xxx devices.
00670   *     
00671   * @note   If an erase and a program operations are requested simultaneously,    
00672   *         the erase operation is performed before the program one.
00673   *     
00674   * @param  VoltageRange: The device voltage range which defines the erase parallelism.  
00675   *          This parameter can be one of the following values:
00676   *            @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V, 
00677   *                                  the operation will be done by byte (8-bit) 
00678   *            @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V,
00679   *                                  the operation will be done by half word (16-bit)
00680   *            @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V,
00681   *                                  the operation will be done by word (32-bit)
00682   *            @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, 
00683   *                                  the operation will be done by double word (64-bit)
00684   *       
00685   * @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
00686   *                       FLASH_ERROR_WRP2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
00687   */
00688 FLASH_Status FLASH_EraseAllBank2Sectors(uint8_t VoltageRange)
00689 {
00690   uint32_t tmp_psize = 0x0;
00691   FLASH_Status status = FLASH_COMPLETE2;
00692   
00693   /* Wait for last operation to be completed */
00694   status = FLASH_WaitForLastOperation2();
00695   assert_param(IS_VOLTAGERANGE(VoltageRange));
00696   
00697   if(VoltageRange == VoltageRange_1)
00698   {
00699      tmp_psize = FLASH_PSIZE_BYTE;
00700   }
00701   else if(VoltageRange == VoltageRange_2)
00702   {
00703     tmp_psize = FLASH_PSIZE_HALF_WORD;
00704   }
00705   else if(VoltageRange == VoltageRange_3)
00706   {
00707     tmp_psize = FLASH_PSIZE_WORD;
00708   }
00709   else
00710   {
00711     tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
00712   }  
00713   if(status == FLASH_COMPLETE2)
00714   {
00715     /* if the previous operation is completed, proceed to erase all sectors */
00716      FLASH->CR &= CR_PSIZE_MASK;
00717      FLASH->CR |= tmp_psize;
00718      FLASH->CR |= FLASH_CR_MER2;
00719      FLASH->CR |= FLASH_CR_STRT;
00720     
00721     /* Wait for last operation to be completed */
00722     status = FLASH_WaitForLastOperation2();
00723  
00724     /* if the erase operation is completed, disable the MER Bit */
00725     FLASH->CR &= (~FLASH_CR_MER2);
00726  
00727   }   
00728   /* Return the Erase Status */
00729   return status;
00730 }
00731  
00732 /**
00733   * @brief  Programs a double word (64-bit) at a specified address.
00734   * @note   This function must be used when the device voltage range is from
00735   *         2.7V to 3.6V and an External Vpp is present.
00736   *
00737   * @note   If an erase and a program operations are requested simultaneously,    
00738   *         the erase operation is performed before the program one.
00739   *  
00740   * @param  Address: specifies the address to be programmed.
00741   * @param  Data: specifies the data to be programmed.
00742   * @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
00743   *                       FLASH_ERROR_WRP2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
00744   */
00745 FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data)
00746 {
00747   FLASH_Status status = FLASH_COMPLETE2;
00748  
00749   /* Check the parameters */
00750   assert_param(IS_FLASH_ADDRESS(Address));
00751  
00752   /* Wait for last operation to be completed */
00753   status = FLASH_WaitForLastOperation2();
00754   
00755   if(status == FLASH_COMPLETE2)
00756   {
00757     /* if the previous operation is completed, proceed to program the new data */
00758     FLASH->CR &= CR_PSIZE_MASK;
00759     FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD;
00760     FLASH->CR |= FLASH_CR_PG;
00761   
00762     *(__IO uint64_t*)Address = Data;
00763         
00764     /* Wait for last operation to be completed */
00765     status = FLASH_WaitForLastOperation2();
00766  
00767     /* if the program operation is completed, disable the PG Bit */
00768     FLASH->CR &= (~FLASH_CR_PG);
00769   } 
00770   /* Return the Program Status */
00771   return status;
00772 }
00773  
00774 /**
00775   * @brief  Programs a word (32-bit) at a specified address.
00776   *
00777   * @note   This function must be used when the device voltage range is from 2.7V to 3.6V. 
00778   *
00779   * @note   If an erase and a program operations are requested simultaneously,    
00780   *         the erase operation is performed before the program one.
00781   *  
00782   * @param  Address: specifies the address to be programmed.
00783   *         This parameter can be any address in Program memory zone or in OTP zone.  
00784   * @param  Data: specifies the data to be programmed.
00785   * @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
00786   *                       FLASH_ERROR_WRP2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
00787   */
00788 FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
00789 {
00790   FLASH_Status status = FLASH_COMPLETE2;
00791  
00792   /* Check the parameters */
00793   assert_param(IS_FLASH_ADDRESS(Address));
00794  
00795   /* Wait for last operation to be completed */
00796   status = FLASH_WaitForLastOperation2();
00797   
00798   if(status == FLASH_COMPLETE2)
00799   {
00800     /* if the previous operation is completed, proceed to program the new data */
00801     FLASH->CR &= CR_PSIZE_MASK;
00802     FLASH->CR |= FLASH_PSIZE_WORD;
00803     FLASH->CR |= FLASH_CR_PG;
00804   
00805     *(__IO uint32_t*)Address = Data;
00806         
00807     /* Wait for last operation to be completed */
00808     status = FLASH_WaitForLastOperation2();
00809  
00810     /* if the program operation is completed, disable the PG Bit */
00811     FLASH->CR &= (~FLASH_CR_PG);
00812   } 
00813   /* Return the Program Status */
00814   return status;
00815 }
00816  
00817 /**
00818   * @brief  Programs a half word (16-bit) at a specified address. 
00819   * @note   This function must be used when the device voltage range is from 2.1V to 3.6V. 
00820   *
00821   * @note   If an erase and a program operations are requested simultaneously,    
00822   *         the erase operation is performed before the program one.
00823   * 
00824   * @param  Address: specifies the address to be programmed.
00825   *         This parameter can be any address in Program memory zone or in OTP zone.  
00826   * @param  Data: specifies the data to be programmed.
00827   * @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
00828   *                       FLASH_ERROR_WRP2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
00829   */
00830 FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
00831 {
00832   FLASH_Status status = FLASH_COMPLETE2;
00833  
00834   /* Check the parameters */
00835   assert_param(IS_FLASH_ADDRESS(Address));
00836  
00837   /* Wait for last operation to be completed */
00838   status = FLASH_WaitForLastOperation2();
00839   
00840   if(status == FLASH_COMPLETE2)
00841   {
00842     /* if the previous operation is completed, proceed to program the new data */
00843     FLASH->CR &= CR_PSIZE_MASK;
00844     FLASH->CR |= FLASH_PSIZE_HALF_WORD;
00845     FLASH->CR |= FLASH_CR_PG;
00846   
00847     *(__IO uint16_t*)Address = Data;
00848         
00849     /* Wait for last operation to be completed */
00850     status = FLASH_WaitForLastOperation2();
00851  
00852     /* if the program operation is completed, disable the PG Bit */
00853     FLASH->CR &= (~FLASH_CR_PG);
00854   } 
00855   /* Return the Program Status */
00856   return status;
00857 }
00858  
00859 /**
00860   * @brief  Programs a byte (8-bit) at a specified address.
00861   * @note   This function can be used within all the device supply voltage ranges.  
00862   *
00863   * @note   If an erase and a program operations are requested simultaneously,    
00864   *         the erase operation is performed before the program one.
00865   * 
00866   * @param  Address: specifies the address to be programmed.
00867   *         This parameter can be any address in Program memory zone or in OTP zone.  
00868   * @param  Data: specifies the data to be programmed.
00869   * @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
00870   *                       FLASH_ERROR_WRP2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
00871   */
00872 FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data)
00873 {
00874   FLASH_Status status = FLASH_COMPLETE2;
00875  
00876   /* Check the parameters */
00877   assert_param(IS_FLASH_ADDRESS(Address));
00878  
00879   /* Wait for last operation to be completed */
00880   status = FLASH_WaitForLastOperation2();
00881   
00882   if(status == FLASH_COMPLETE2)
00883   {
00884     /* if the previous operation is completed, proceed to program the new data */
00885     FLASH->CR &= CR_PSIZE_MASK;
00886     FLASH->CR |= FLASH_PSIZE_BYTE;
00887     FLASH->CR |= FLASH_CR_PG;
00888   
00889     *(__IO uint8_t*)Address = Data;
00890         
00891     /* Wait for last operation to be completed */
00892     status = FLASH_WaitForLastOperation2();
00893  
00894     /* if the program operation is completed, disable the PG Bit */
00895     FLASH->CR &= (~FLASH_CR_PG);
00896   } 
00897  
00898   /* Return the Program Status */
00899   return status;
00900 }
00901  
00902 /**
00903   * @}
00904   */
00905  
00906 /** @defgroup FLASH_Group3 Option Bytes Programming functions
00907  *  @brief   Option Bytes Programming functions 
00908  *
00909 @verbatim   
00910  ===============================================================================
00911                 ##### Option Bytes Programming functions #####
00912  ===============================================================================  
00913     [..]
00914       This group includes the following functions:
00915       (+) void FLASH_OB_Unlock(void)
00916       (+) void FLASH_OB_Lock(void)
00917       (+) void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)
00918       (+) void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState)  
00919       (+) void FLASH_OB_PCROPSelectionConfig(uint8_t OB_PCROPSelect)
00920       (+) void FLASH_OB_PCROPConfig(uint32_t OB_PCROP, FunctionalState NewState)
00921       (+) void FLASH_OB_PCROP1Config(uint32_t OB_PCROP, FunctionalState NewState) 
00922       (+) void FLASH_OB_RDPConfig(uint8_t OB_RDP)
00923       (+) void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
00924       (+) void FLASH_OB_BORConfig(uint8_t OB_BOR)
00925       (+) FLASH_Status FLASH_ProgramOTP(uint32_t Address, uint32_t Data)
00926       (+) FLASH_Status FLASH_OB_Launch(void)
00927       (+) uint32_t FLASH_OB_GetUser(void)
00928       (+) uint8_t FLASH_OB_GetWRP(void)
00929       (+) uint8_t FLASH_OB_GetWRP1(void)
00930       (+) uint8_t FLASH_OB_GetPCROP(void)
00931       (+) uint8_t FLASH_OB_GetPCROP1(void)
00932       (+) uint8_t FLASH_OB_GetRDP(void)
00933       (+) uint8_t FLASH_OB_GetBOR(void)
00934     [..]  
00935       The following function can be used only for STM32F42xxx/43xxx devices. 
00936       (+) void FLASH_OB_BootConfig(uint8_t OB_BOOT)
00937     [..]   
00938      Any operation of erase or program should follow these steps:
00939       (#) Call the FLASH_OB_Unlock() function to enable the FLASH option control 
00940           register access
00941  
00942       (#) Call one or several functions to program the desired Option Bytes:
00943         (++) void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) 
00944              => to Enable/Disable the desired sector write protection
00945         (++) void FLASH_OB_RDPConfig(uint8_t OB_RDP) => to set the desired read 
00946              Protection Level
00947         (++) void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) 
00948              => to configure the user Option Bytes.
00949         (++) void FLASH_OB_BORConfig(uint8_t OB_BOR) => to set the BOR Level             
00950  
00951       (#) Once all needed Option Bytes to be programmed are correctly written, 
00952           call the FLASH_OB_Launch() function to launch the Option Bytes 
00953           programming process.
00954      
00955       -@- When changing the IWDG mode from HW to SW or from SW to HW, a system 
00956           reset is needed to make the change effective.  
00957  
00958       (#) Call the FLASH_OB_Lock() function to disable the FLASH option control 
00959           register access (recommended to protect the Option Bytes against 
00960           possible unwanted operations)
00961     
00962 @endverbatim
00963   * @{
00964   */
00965  
00966 /**
00967   * @brief  Unlocks the FLASH Option Control Registers access.
00968   * @param  None
00969   * @retval None
00970   */
00971 void FLASH_OB_Unlock(void)
00972 {
00973   if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET)
00974   {
00975     /* Authorizes the Option Byte register programming */
00976     FLASH->OPTKEYR = FLASH_OPT_KEY1;
00977     FLASH->OPTKEYR = FLASH_OPT_KEY2;
00978   }  
00979 }
00980  
00981 /**
00982   * @brief  Locks the FLASH Option Control Registers access.
00983   * @param  None
00984   * @retval None
00985   */
00986 void FLASH_OB_Lock(void)
00987 {
00988   /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
00989   FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK;
00990 }
00991  
00992 /**
00993   * @brief  Enables or disables the write protection of the desired sectors, for the first
00994   *         1 Mb of the Flash  
00995   *
00996   * @note   When the memory read protection level is selected (RDP level = 1), 
00997   *         it is not possible to program or erase the flash sector i if CortexM4  
00998   *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1 
00999   * @note   Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).   
01000   * 
01001   * @param  OB_WRP: specifies the sector(s) to be write protected or unprotected.
01002   *          This parameter can be one of the following values:
01003   *            @arg OB_WRP: A value between OB_WRP_Sector0 and OB_WRP_Sector11                      
01004   *            @arg OB_WRP_Sector_All
01005   * @param  Newstate: new state of the Write Protection.
01006   *          This parameter can be: ENABLE or DISABLE.
01007   * @retval None  
01008   */
01009 void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)
01010 { 
01011   FLASH_Status status = FLASH_COMPLETE2;
01012   
01013   /* Check the parameters */
01014   assert_param(IS_OB_WRP(OB_WRP));
01015   assert_param(IS_FUNCTIONAL_STATE(NewState));
01016     
01017   status = FLASH_WaitForLastOperation2();
01018  
01019   if(status == FLASH_COMPLETE2)
01020   { 
01021     if(NewState != DISABLE)
01022     {
01023       *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~OB_WRP);
01024     }
01025     else
01026     {
01027       *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)OB_WRP;
01028     }
01029   }
01030 }
01031  
01032 /**
01033   * @brief  Enables or disables the write protection of the desired sectors, for the second
01034   *         1 Mb of the Flash  
01035   *           
01036   * @note   This function can be used only for STM32F42xxx/43xxx devices.
01037   *   
01038   * @note   When the memory read out protection is selected (RDP level = 1), 
01039   *         it is not possible to program or erase the flash sector i if CortexM4  
01040   *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1 
01041   * @note   Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).      
01042   * 
01043   * @param  OB_WRP: specifies the sector(s) to be write protected or unprotected.
01044   *          This parameter can be one of the following values:
01045   *            @arg OB_WRP: A value between OB_WRP_Sector12 and OB_WRP_Sector23
01046   *            @arg OB_WRP_Sector_All                        
01047   * @param  Newstate: new state of the Write Protection.
01048   *          This parameter can be: ENABLE or DISABLE.
01049   * @retval None  
01050   */
01051 void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState)
01052 { 
01053   FLASH_Status status = FLASH_COMPLETE2;
01054   
01055   /* Check the parameters */
01056   assert_param(IS_OB_WRP(OB_WRP));
01057   assert_param(IS_FUNCTIONAL_STATE(NewState));
01058     
01059   status = FLASH_WaitForLastOperation2();
01060  
01061   if(status == FLASH_COMPLETE2)
01062   { 
01063     if(NewState != DISABLE)
01064     {
01065       *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~OB_WRP);
01066     }
01067     else
01068     {
01069       *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)OB_WRP;
01070     }
01071   }
01072 }
01073  
01074 /**
01075   * @brief  Select the Protection Mode (SPRMOD). 
01076   * 
01077   * @note   This function can be used only for STM32F42xxx/43xxx and STM32F401xx/411xE devices.       
01078   * 
01079   * @note   After PCROP activation, Option Byte modification is not possible. 
01080   *         Exception made for the global Read Out Protection modification level (level1 to level0) 
01081   * @note   Once SPRMOD bit is active unprotection of a protected sector is not possible 
01082   *   
01083   * @note   Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag
01084   *   
01085   * @note   Some Precautions should be taken when activating the PCROP feature :
01086   *         The active value of nWRPi bits is inverted when PCROP mode is active, this means if SPRMOD = 1
01087   *         and WRPi = 1 (default value), then the user sector i is read/write protected.
01088   *         In order to avoid activation of PCROP Mode for undesired sectors, please follow the
01089   *         below safety sequence :       
01090   *         - Disable PCROP for all Sectors using FLASH_OB_PCROPConfig(OB_PCROP_Sector_All, DISABLE) function 
01091   *           for Bank1 or FLASH_OB_PCROP1Config(OB_PCROP_Sector_All, DISABLE) function for Bank2   
01092   *         - Enable PCROP for the desired Sector i using FLASH_OB_PCROPConfig(Sector i, ENABLE) function
01093   *         - Activate the PCROP Mode FLASH_OB_PCROPSelectionConfig() function. 
01094   * 
01095   * @param  OB_PCROP:  Select the Protection Mode of nWPRi bits 
01096   *          This parameter can be one of the following values:
01097   *            @arg OB_PcROP_Disable: nWRPi control the write protection of respective user sectors.
01098   *            @arg OB_PcROP_Enable: nWRPi control the  read&write protection (PCROP) of respective user sectors.
01099   * @retval None
01100   */
01101 void FLASH_OB_PCROPSelectionConfig(uint8_t OB_PcROP)
01102 {  
01103   uint8_t optiontmp = 0xFF;
01104       
01105   /* Check the parameters */
01106   assert_param(IS_OB_PCROP_SELECT(OB_PcROP));
01107   
01108   /* Mask SPRMOD bit */
01109   optiontmp =  (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7F); 
01110   /* Update Option Byte */
01111   *(__IO uint8_t *)OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PcROP | optiontmp); 
01112     
01113 }
01114  
01115 /**
01116   * @brief  Enables or disables the read/write protection (PCROP) of the desired 
01117   *         sectors, for the first 1 MB of the Flash.
01118   *           
01119   * @note   This function can be used only for STM32F42xxx/43xxx , STM32F401xx/411xE 
01120   *         and STM32F412xG devices.
01121   *   
01122   * @param  OB_PCROP: specifies the sector(s) to be read/write protected or unprotected.
01123   *          This parameter can be one of the following values:
01124   *            @arg OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector11 for 
01125   *                           STM32F42xxx/43xxx devices and between OB_PCROP_Sector0 and 
01126   *                           OB_PCROP_Sector5 for STM32F401xx/411xE devices.
01127   *            @arg OB_PCROP_Sector_All
01128   * @param  Newstate: new state of the Write Protection.
01129   *          This parameter can be: ENABLE or DISABLE.
01130   * @retval None  
01131   */
01132 void FLASH_OB_PCROPConfig(uint32_t OB_PCROP, FunctionalState NewState)
01133 { 
01134   FLASH_Status status = FLASH_COMPLETE2;
01135   
01136   /* Check the parameters */
01137   assert_param(IS_OB_PCROP(OB_PCROP));
01138   assert_param(IS_FUNCTIONAL_STATE(NewState));
01139     
01140   status = FLASH_WaitForLastOperation2();
01141  
01142   if(status == FLASH_COMPLETE2)
01143   { 
01144     if(NewState != DISABLE)
01145     {
01146       *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)OB_PCROP;    
01147     }
01148     else
01149     {
01150       *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~OB_PCROP);
01151     }
01152   }
01153 }
01154  
01155 /**
01156    * @brief Enables or disables the read/write protection (PCROP) of the desired 
01157   *         sectors
01158   *           
01159   * @note   This function can be used only for STM32F42xxx/43xxx devices.
01160   *   
01161   * @param  OB_PCROP: specifies the sector(s) to be read/write protected or unprotected.
01162   *          This parameter can be one of the following values:
01163   *            @arg OB_PCROP: A value between OB_PCROP_Sector12 and OB_PCROP_Sector23 
01164   *            @arg OB_PCROP_Sector_All
01165   * @param  Newstate: new state of the Write Protection.
01166   *          This parameter can be: ENABLE or DISABLE.
01167   * @retval None  
01168   */
01169 void FLASH_OB_PCROP1Config(uint32_t OB_PCROP, FunctionalState NewState)
01170 { 
01171   FLASH_Status status = FLASH_COMPLETE2;
01172   
01173   /* Check the parameters */
01174   assert_param(IS_OB_PCROP(OB_PCROP));
01175   assert_param(IS_FUNCTIONAL_STATE(NewState));
01176     
01177   status = FLASH_WaitForLastOperation2();
01178  
01179   if(status == FLASH_COMPLETE2)
01180   { 
01181     if(NewState != DISABLE)
01182     {
01183       *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)OB_PCROP;
01184     }
01185     else
01186     {
01187       *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~OB_PCROP);
01188     }
01189   }
01190 }
01191  
01192  
01193 /**
01194   * @brief  Sets the read protection level.
01195   * @param  OB_RDP: specifies the read protection level.
01196   *          This parameter can be one of the following values:
01197   *            @arg OB_RDP_Level_0: No protection
01198   *            @arg OB_RDP_Level_1: Read protection of the memory
01199   *            @arg OB_RDP_Level_2: Full chip protection
01200   *   
01201   * /!\ Warning /!\ When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
01202   *    
01203   * @retval None
01204   */
01205 void FLASH_OB_RDPConfig(uint8_t OB_RDP)
01206 {
01207   FLASH_Status status = FLASH_COMPLETE2;
01208  
01209   /* Check the parameters */
01210   assert_param(IS_OB_RDP(OB_RDP));
01211  
01212   status = FLASH_WaitForLastOperation2();
01213  
01214   if(status == FLASH_COMPLETE2)
01215   {
01216     *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = OB_RDP;
01217  
01218   }
01219 }
01220  
01221 /**
01222   * @brief  Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.    
01223   * @param  OB_IWDG: Selects the IWDG mode
01224   *          This parameter can be one of the following values:
01225   *            @arg OB_IWDG_SW: Software IWDG selected
01226   *            @arg OB_IWDG_HW: Hardware IWDG selected
01227   * @param  OB_STOP: Reset event when entering STOP mode.
01228   *          This parameter  can be one of the following values:
01229   *            @arg OB_STOP_NoRST: No reset generated when entering in STOP
01230   *            @arg OB_STOP_RST: Reset generated when entering in STOP
01231   * @param  OB_STDBY: Reset event when entering Standby mode.
01232   *          This parameter  can be one of the following values:
01233   *            @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY
01234   *            @arg OB_STDBY_RST: Reset generated when entering in STANDBY
01235   * @retval None
01236   */
01237 void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
01238 {
01239   uint8_t optiontmp = 0xFF;
01240   FLASH_Status status = FLASH_COMPLETE2; 
01241  
01242   /* Check the parameters */
01243   assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
01244   assert_param(IS_OB_STOP_SOURCE(OB_STOP));
01245   assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
01246  
01247   /* Wait for last operation to be completed */
01248   status = FLASH_WaitForLastOperation2();
01249   
01250   if(status == FLASH_COMPLETE2)
01251   { 
01252 #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
01253     /* Mask OPTLOCK, OPTSTRT, BOR_LEV and BFB2 bits */
01254     optiontmp =  (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x1F);
01255 #endif /* STM32F427_437xx ||  STM32F429_439xx ||  STM32F469_479xx */
01256  
01257 #if defined(STM32F40_41xxx) || defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F446xx)
01258     /* Mask OPTLOCK, OPTSTRT and BOR_LEV bits */
01259     optiontmp =  (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0F); 
01260 #endif /* STM32F40_41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F446xx */ 
01261  
01262     /* Update User Option Byte */
01263     *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS = OB_IWDG | (uint8_t)(OB_STDBY | (uint8_t)(OB_STOP | ((uint8_t)optiontmp))); 
01264   }  
01265 }
01266  
01267 /**
01268   * @brief  Configure the Dual Bank Boot.
01269   *   
01270   * @note   This function can be used only for STM32F42xxx/43xxx devices.
01271   *      
01272   * @param  OB_BOOT: specifies the Dual Bank Boot Option byte.
01273   *          This parameter can be one of the following values:
01274   *            @arg OB_Dual_BootEnabled: Dual Bank Boot Enable
01275   *            @arg OB_Dual_BootDisabled: Dual Bank Boot Disabled
01276   * @retval None
01277   */
01278 void FLASH_OB_BootConfig(uint8_t OB_BOOT)
01279 {
01280   /* Check the parameters */
01281   assert_param(IS_OB_BOOT(OB_BOOT));
01282  
01283   /* Set Dual Bank Boot */
01284   *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BFB2);
01285   *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= OB_BOOT;
01286  
01287 }
01288  
01289 /**
01290   * @brief  Sets the BOR Level. 
01291   * @param  OB_BOR: specifies the Option Bytes BOR Reset Level.
01292   *          This parameter can be one of the following values:
01293   *            @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
01294   *            @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
01295   *            @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
01296   *            @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V
01297   * @retval None
01298   */
01299 void FLASH_OB_BORConfig(uint8_t OB_BOR)
01300 {
01301   /* Check the parameters */
01302   assert_param(IS_OB_BOR(OB_BOR));
01303  
01304   /* Set the BOR Level */
01305   *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BOR_LEV);
01306   *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= OB_BOR;
01307  
01308 }
01309  
01310 /**
01311   * @brief  Launch the option byte loading.
01312   * @param  None
01313   * @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
01314   *                       FLASH_ERROR_WRP2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
01315   */
01316 FLASH_Status FLASH_OB_Launch(void)
01317 {
01318   FLASH_Status status = FLASH_COMPLETE2;
01319  
01320   /* Set the OPTSTRT bit in OPTCR register */
01321   *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= FLASH_OPTCR_OPTSTRT;
01322  
01323   /* Wait for last operation to be completed */
01324   status = FLASH_WaitForLastOperation2();
01325  
01326   return status;
01327 }
01328  
01329 /**
01330   * @brief  Returns the FLASH User Option Bytes values.
01331   * @param  None
01332   * @retval The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1)
01333   *         and RST_STDBY(Bit2).
01334   */
01335 uint8_t FLASH_OB_GetUser(void)
01336 {
01337   /* Return the User Option Byte */
01338   return (uint8_t)(FLASH->OPTCR >> 5);
01339 }
01340  
01341 /**
01342   * @brief  Returns the FLASH Write Protection Option Bytes value.
01343   * @param  None
01344   * @retval The FLASH Write Protection  Option Bytes value
01345   */
01346 uint16_t FLASH_OB_GetWRP(void)
01347 {
01348   /* Return the FLASH write protection Register value */
01349   return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));
01350 }
01351  
01352 /**
01353   * @brief  Returns the FLASH Write Protection Option Bytes value.
01354   *   
01355   * @note   This function can be used only for STM32F42xxx/43xxx devices.
01356   *   
01357   * @param  None
01358   * @retval The FLASH Write Protection  Option Bytes value
01359   */
01360 uint16_t FLASH_OB_GetWRP1(void)
01361 {
01362   /* Return the FLASH write protection Register value */
01363   return (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS));
01364 }
01365  
01366 /**
01367   * @brief  Returns the FLASH PC Read/Write Protection Option Bytes value.
01368   *   
01369   * @note   This function can be used only for STM32F42xxx/43xxx devices and STM32F401xx/411xE devices.
01370   *   
01371   * @param  None
01372   * @retval The FLASH PC Read/Write Protection Option Bytes value
01373   */
01374 uint16_t FLASH_OB_GetPCROP(void)
01375 {
01376   /* Return the FLASH PC Read/write protection Register value */
01377   return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));
01378 }
01379  
01380 /**
01381   * @brief  Returns the FLASH PC Read/Write Protection Option Bytes value.
01382   *   
01383   * @note   This function can be used only for STM32F42xxx/43xxx devices. 
01384   *     
01385   * @param  None
01386   * @retval The FLASH PC Read/Write Protection Option Bytes value
01387   */
01388 uint16_t FLASH_OB_GetPCROP1(void)
01389 {
01390   /* Return the FLASH write protection Register value */
01391   return (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS));
01392 }
01393  
01394 /**
01395   * @brief  Returns the FLASH Read Protection level.
01396   * @param  None
01397   * @retval FLASH ReadOut Protection Status:
01398   *           - SET, when OB_RDP_Level_1 or OB_RDP_Level_2 is set
01399   *           - RESET, when OB_RDP_Level_0 is set
01400   */
01401 FlagStatus FLASH_OB_GetRDP(void)
01402 {
01403   FlagStatus readstatus = RESET;
01404  
01405   if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) != (uint8_t)OB_RDP_Level_0))
01406   {
01407     readstatus = SET;
01408   }
01409   else
01410   {
01411     readstatus = RESET;
01412   }
01413   return readstatus;
01414 }
01415  
01416 /**
01417   * @brief  Returns the FLASH BOR level.
01418   * @param  None
01419   * @retval The FLASH BOR level:
01420   *           - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
01421   *           - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
01422   *           - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
01423   *           - OB_BOR_OFF   : Supply voltage ranges from 1.62 to 2.1 V  
01424   */
01425 uint8_t FLASH_OB_GetBOR(void)
01426 {
01427   /* Return the FLASH BOR level */
01428   return (uint8_t)(*(__IO uint8_t *)(OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0C);
01429 }
01430  
01431 /**
01432   * @}
01433   */
01434  
01435 /** @defgroup FLASH_Group4 Interrupts and flags management functions
01436  *  @brief   Interrupts and flags management functions
01437  *
01438 @verbatim   
01439  ===============================================================================
01440               ##### Interrupts and flags management functions #####
01441  ===============================================================================  
01442 @endverbatim
01443   * @{
01444   */
01445  
01446 /**
01447   * @brief  Enables or disables the specified FLASH interrupts.
01448   * @param  FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled.
01449   *          This parameter can be any combination of the following values:
01450   *            @arg FLASH_IT_ERR: FLASH Error Interrupt
01451   *            @arg FLASH_IT_EOP: FLASH end of operation Interrupt
01452   * @retval None 
01453   */
01454 void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)
01455 {
01456   /* Check the parameters */
01457   assert_param(IS_FLASH_IT(FLASH_IT)); 
01458   assert_param(IS_FUNCTIONAL_STATE(NewState));
01459  
01460   if(NewState != DISABLE)
01461   {
01462     /* Enable the interrupt sources */
01463     FLASH->CR |= FLASH_IT;
01464   }
01465   else
01466   {
01467     /* Disable the interrupt sources */
01468     FLASH->CR &= ~(uint32_t)FLASH_IT;
01469   }
01470 }
01471  
01472 /**
01473   * @brief  Checks whether the specified FLASH flag is set or not.
01474   * @param  FLASH_FLAG: specifies the FLASH flag to check.
01475   *          This parameter can be one of the following values:
01476   *            @arg FLASH_FLAG_EOP: FLASH End of Operation flag 
01477   *            @arg FLASH_FLAG_OPERR: FLASH operation Error flag 
01478   *            @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag 
01479   *            @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
01480   *            @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
01481   *            @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
01482   *            @arg FLASH_FLAG_RDERR: FLASH (PCROP) Read Protection error flag (STM32F42xx/43xxx and STM32F401xx/411xE devices) 
01483   *            @arg FLASH_FLAG_BSY: FLASH Busy flag
01484   * @retval The new state of FLASH_FLAG (SET or RESET).
01485   */
01486 FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
01487 {
01488   FlagStatus bitstatus = RESET;
01489   /* Check the parameters */
01490   assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG));
01491  
01492   if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)
01493   {
01494     bitstatus = SET;
01495   }
01496   else
01497   {
01498     bitstatus = RESET;
01499   }
01500   /* Return the new state of FLASH_FLAG (SET or RESET) */
01501   return bitstatus; 
01502 }
01503  
01504 /**
01505   * @brief  Clears the FLASH's pending flags.
01506   * @param  FLASH_FLAG: specifies the FLASH flags to clear.
01507   *          This parameter can be any combination of the following values:
01508   *            @arg FLASH_FLAG_EOP: FLASH End of Operation flag 
01509   *            @arg FLASH_FLAG_OPERR: FLASH operation Error flag 
01510   *            @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag 
01511   *            @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag 
01512   *            @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
01513   *            @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
01514   *            @arg FLASH_FLAG_RDERR: FLASH Read Protection error flag (STM32F42xx/43xxx and STM32F401xx/411xE devices)   
01515   * @retval None
01516   */
01517 void FLASH_ClearFlag(uint32_t FLASH_FLAG)
01518 {
01519   /* Check the parameters */
01520   assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG));
01521   
01522   /* Clear the flags */
01523   FLASH->SR = FLASH_FLAG;
01524 }
01525  
01526 /**
01527   * @brief  Returns the FLASH Status.
01528   * @param  None
01529   * @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
01530   *                       FLASH_ERROR_WRP2, FLASH_ERROR_RD2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
01531   */
01532 FLASH_Status FLASH_GetStatus(void)
01533 {
01534   FLASH_Status flashstatus = FLASH_COMPLETE2;
01535   
01536   if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) 
01537   {
01538     flashstatus = FLASH_BUSY2;
01539   }
01540   else 
01541   {  
01542     if((FLASH->SR & FLASH_FLAG_WRPERR) != (uint32_t)0x00)
01543     { 
01544       flashstatus = FLASH_ERROR_WRP2;
01545     }
01546     else
01547     {
01548       if((FLASH->SR & FLASH_FLAG_RDERR) != (uint32_t)0x00)
01549       { 
01550         flashstatus = FLASH_ERROR_RD2;
01551       } 
01552       else 
01553       {
01554         if((FLASH->SR & (uint32_t)0xE0) != (uint32_t)0x00)
01555         {
01556           flashstatus = FLASH_ERROR_PROGRAM2; 
01557         }
01558         else
01559         {
01560           if((FLASH->SR & FLASH_FLAG_OPERR) != (uint32_t)0x00)
01561           {
01562             flashstatus = FLASH_ERROR_OPERATION2;
01563           }
01564           else
01565           {
01566             flashstatus = FLASH_COMPLETE2;
01567           }
01568         }
01569       }
01570     }
01571   }
01572   /* Return the FLASH Status */
01573   return flashstatus;
01574 }
01575  
01576 /**
01577   * @brief  Waits for a FLASH operation to complete.
01578   * @param  None
01579   * @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
01580   *                       FLASH_ERROR_WRP2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
01581   */
01582 FLASH_Status FLASH_WaitForLastOperation2(void)
01583 { 
01584   __IO FLASH_Status status = FLASH_COMPLETE2;
01585    
01586   /* Check for the FLASH Status */
01587   status = FLASH_GetStatus();
01588  
01589   /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
01590      Even if the FLASH operation fails, the BUSY flag will be reset and an error
01591      flag will be set */
01592   while(status == FLASH_BUSY2)
01593   {
01594     status = FLASH_GetStatus();
01595   }
01596   /* Return the operation status */
01597   return status;
01598 }
01599  
01600 /**
01601   * @}
01602   */ 
01603  
01604 /**
01605   * @}
01606   */ 
01607  
01608 /**
01609   * @}
01610   */ 
01611  
01612 /**
01613   * @}
01614   */
01615  
01616 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/