Eric Lewiston
Hal Drivers for L4
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stm32l4xx_ll_system.h
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_ll_system.h 00004 * @author MCD Application Team 00005 * @version V1.1.0 00006 * @date 16-September-2015 00007 * @brief Header file of SYSTEM LL module. 00008 @verbatim 00009 ============================================================================== 00010 ##### How to use this driver ##### 00011 ============================================================================== 00012 [..] 00013 The LL SYSTEM driver contains a set of generic APIs that can be 00014 used by user: 00015 (+) Some of the FLASH features need to be handled in the SYSTEM file. 00016 (+) Access to DBGCMU registers 00017 (+) Access to SYSCFG registers 00018 (+) Access to VREFBUF registers 00019 00020 @endverbatim 00021 ****************************************************************************** 00022 * @attention 00023 * 00024 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> 00025 * 00026 * Redistribution and use in source and binary forms, with or without modification, 00027 * are permitted provided that the following conditions are met: 00028 * 1. Redistributions of source code must retain the above copyright notice, 00029 * this list of conditions and the following disclaimer. 00030 * 2. Redistributions in binary form must reproduce the above copyright notice, 00031 * this list of conditions and the following disclaimer in the documentation 00032 * and/or other materials provided with the distribution. 00033 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00034 * may be used to endorse or promote products derived from this software 00035 * without specific prior written permission. 00036 * 00037 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00038 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00039 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00040 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00041 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00042 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00043 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00044 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00045 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00046 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00047 * 00048 ****************************************************************************** 00049 */ 00050 00051 /* Define to prevent recursive inclusion -------------------------------------*/ 00052 #ifndef __STM32L4xx_LL_SYSTEM_H 00053 #define __STM32L4xx_LL_SYSTEM_H 00054 00055 #ifdef __cplusplus 00056 extern "C" { 00057 #endif 00058 00059 /* Includes ------------------------------------------------------------------*/ 00060 #include "stm32l4xx.h" 00061 00062 /** @addtogroup STM32L4xx_LL_Driver 00063 * @{ 00064 */ 00065 00066 #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF) 00067 00068 /** @defgroup SYSTEM_LL SYSTEM 00069 * @{ 00070 */ 00071 00072 /* Private types -------------------------------------------------------------*/ 00073 /* Private variables ---------------------------------------------------------*/ 00074 00075 /* Private constants ---------------------------------------------------------*/ 00076 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants 00077 * @{ 00078 */ 00079 00080 /* Defines used for position in the register */ 00081 #define DBGMCU_REVID_POSITION (uint32_t)POSITION_VAL(DBGMCU_IDCODE_REV_ID) 00082 00083 /** 00084 * @brief Power-down in Run mode Flash key 00085 */ 00086 #define FLASH_PDKEY1 ((uint32_t)0x04152637) /*!< Flash power down key1 */ 00087 #define FLASH_PDKEY2 ((uint32_t)0xFAFBFCFD) /*!< Flash power down key2: used with FLASH_PDKEY1 00088 to unlock the RUN_PD bit in FLASH_ACR */ 00089 00090 /** 00091 * @} 00092 */ 00093 00094 /* Private macros ------------------------------------------------------------*/ 00095 00096 /* Exported types ------------------------------------------------------------*/ 00097 /* Exported constants --------------------------------------------------------*/ 00098 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants 00099 * @{ 00100 */ 00101 00102 /** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP 00103 * @{ 00104 */ 00105 #define LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000 /*!< Main Flash memory mapped at 0x00000000 */ 00106 #define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 /*!< System Flash memory mapped at 0x00000000 */ 00107 #define LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) /*!< FMC bank 1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 */ 00108 #define LL_SYSCFG_REMAP_FMC SYSCFG_MEMRMP_MEM_MODE_1 /*!< SRAM1 mapped at 0x00000000 */ 00109 #define LL_SYSCFG_REMAP_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1) /*!< QUADSPI memory mapped at 0x00000000 */ 00110 /** 00111 * @} 00112 */ 00113 00114 /** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG BANK MODE 00115 * @{ 00116 */ 00117 #define LL_SYSCFG_BANKMODE_BANK1 (uint32_t)0x00000000 /*!< Flash Bank1 mapped at 0x08000000 (and aliased @0x00000000) 00118 and Flash Bank2 mapped at 0x08080000 (and aliased at 0x00080000) */ 00119 #define LL_SYSCFG_BANKMODE_BANK2 SYSCFG_MEMRMP_FB_MODE /*!< Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000) 00120 and Flash Bank1 mapped at 0x08080000 (and aliased at 0x00080000) */ 00121 /** 00122 * @} 00123 */ 00124 00125 /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS 00126 * @{ 00127 */ 00128 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ 00129 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ 00130 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */ 00131 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ 00132 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */ 00133 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */ 00134 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */ 00135 /** 00136 * @} 00137 */ 00138 00139 /** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT 00140 * @{ 00141 */ 00142 #define LL_SYSCFG_EXTI_PORTA (uint32_t)0 /*!< EXTI PORT A */ 00143 #define LL_SYSCFG_EXTI_PORTB (uint32_t)1 /*!< EXTI PORT B */ 00144 #define LL_SYSCFG_EXTI_PORTC (uint32_t)2 /*!< EXTI PORT C */ 00145 #define LL_SYSCFG_EXTI_PORTD (uint32_t)3 /*!< EXTI PORT D */ 00146 #define LL_SYSCFG_EXTI_PORTE (uint32_t)4 /*!< EXTI PORT E */ 00147 #define LL_SYSCFG_EXTI_PORTF (uint32_t)5 /*!< EXTI PORT F */ 00148 #define LL_SYSCFG_EXTI_PORTG (uint32_t)6 /*!< EXTI PORT G */ 00149 #define LL_SYSCFG_EXTI_PORTH (uint32_t)7 /*!< EXTI PORT H */ 00150 /** 00151 * @} 00152 */ 00153 00154 /** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE 00155 * @{ 00156 */ 00157 #define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0x000FU << 16 | 0) /* !< EXTI_POSITION_0 | EXTICR[0] */ 00158 #define LL_SYSCFG_EXTI_LINE1 (uint32_t)(0x00F0U << 16 | 0) /* !< EXTI_POSITION_4 | EXTICR[0] */ 00159 #define LL_SYSCFG_EXTI_LINE2 (uint32_t)(0x0F00U << 16 | 0) /* !< EXTI_POSITION_8 | EXTICR[0] */ 00160 #define LL_SYSCFG_EXTI_LINE3 (uint32_t)(0xF000U << 16 | 0) /* !< EXTI_POSITION_12 | EXTICR[0] */ 00161 #define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0x000FU << 16 | 1) /* !< EXTI_POSITION_0 | EXTICR[1] */ 00162 #define LL_SYSCFG_EXTI_LINE5 (uint32_t)(0x00F0U << 16 | 1) /* !< EXTI_POSITION_4 | EXTICR[1] */ 00163 #define LL_SYSCFG_EXTI_LINE6 (uint32_t)(0x0F00U << 16 | 1) /* !< EXTI_POSITION_8 | EXTICR[1] */ 00164 #define LL_SYSCFG_EXTI_LINE7 (uint32_t)(0xF000U << 16 | 1) /* !< EXTI_POSITION_12 | EXTICR[1] */ 00165 #define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0x000FU << 16 | 2) /* !< EXTI_POSITION_0 | EXTICR[2] */ 00166 #define LL_SYSCFG_EXTI_LINE9 (uint32_t)(0x00F0U << 16 | 2) /* !< EXTI_POSITION_4 | EXTICR[2] */ 00167 #define LL_SYSCFG_EXTI_LINE10 (uint32_t)(0x0F00U << 16 | 2) /* !< EXTI_POSITION_8 | EXTICR[2] */ 00168 #define LL_SYSCFG_EXTI_LINE11 (uint32_t)(0xF000U << 16 | 2) /* !< EXTI_POSITION_12 | EXTICR[2] */ 00169 #define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0x000FU << 16 | 3) /* !< EXTI_POSITION_0 | EXTICR[3] */ 00170 #define LL_SYSCFG_EXTI_LINE13 (uint32_t)(0x00F0U << 16 | 3) /* !< EXTI_POSITION_4 | EXTICR[3] */ 00171 #define LL_SYSCFG_EXTI_LINE14 (uint32_t)(0x0F00U << 16 | 3) /* !< EXTI_POSITION_8 | EXTICR[3] */ 00172 #define LL_SYSCFG_EXTI_LINE15 (uint32_t)(0xF000U << 16 | 3) /* !< EXTI_POSITION_12 | EXTICR[3] */ 00173 /** 00174 * @} 00175 */ 00176 00177 /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK 00178 * @{ 00179 */ 00180 #define LL_SYSCFG_TIMBREAK_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal 00181 with Break Input of TIM1/8/15/16/17 */ 00182 #define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection 00183 with TIM1/8/15/16/17 Break Input 00184 and also the PVDE and PLS bits of the Power Control Interface */ 00185 #define LL_SYSCFG_TIMBREAK_SRAM2_PARITY SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM2_PARITY error signal 00186 with Break Input of TIM1/8/15/16/17 */ 00187 #define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 00188 with Break Input of TIM1/15/16/17 */ 00189 /** 00190 * @} 00191 */ 00192 00193 /** @defgroup SYSTEM_LL_EC_SRAM2WRP SYSCFG SRAM2 WRP 00194 * @{ 00195 */ 00196 #define LL_SYSCFG_SRAM2WRP_PAGE0 SYSCFG_SWPR_PAGE0 /*!< SRAM2 Write protection page 0 */ 00197 #define LL_SYSCFG_SRAM2WRP_PAGE1 SYSCFG_SWPR_PAGE1 /*!< SRAM2 Write protection page 1 */ 00198 #define LL_SYSCFG_SRAM2WRP_PAGE2 SYSCFG_SWPR_PAGE2 /*!< SRAM2 Write protection page 2 */ 00199 #define LL_SYSCFG_SRAM2WRP_PAGE3 SYSCFG_SWPR_PAGE3 /*!< SRAM2 Write protection page 3 */ 00200 #define LL_SYSCFG_SRAM2WRP_PAGE4 SYSCFG_SWPR_PAGE4 /*!< SRAM2 Write protection page 4 */ 00201 #define LL_SYSCFG_SRAM2WRP_PAGE5 SYSCFG_SWPR_PAGE5 /*!< SRAM2 Write protection page 5 */ 00202 #define LL_SYSCFG_SRAM2WRP_PAGE6 SYSCFG_SWPR_PAGE6 /*!< SRAM2 Write protection page 6 */ 00203 #define LL_SYSCFG_SRAM2WRP_PAGE7 SYSCFG_SWPR_PAGE7 /*!< SRAM2 Write protection page 7 */ 00204 #define LL_SYSCFG_SRAM2WRP_PAGE8 SYSCFG_SWPR_PAGE8 /*!< SRAM2 Write protection page 8 */ 00205 #define LL_SYSCFG_SRAM2WRP_PAGE9 SYSCFG_SWPR_PAGE9 /*!< SRAM2 Write protection page 9 */ 00206 #define LL_SYSCFG_SRAM2WRP_PAGE10 SYSCFG_SWPR_PAGE10 /*!< SRAM2 Write protection page 10 */ 00207 #define LL_SYSCFG_SRAM2WRP_PAGE11 SYSCFG_SWPR_PAGE11 /*!< SRAM2 Write protection page 11 */ 00208 #define LL_SYSCFG_SRAM2WRP_PAGE12 SYSCFG_SWPR_PAGE12 /*!< SRAM2 Write protection page 12 */ 00209 #define LL_SYSCFG_SRAM2WRP_PAGE13 SYSCFG_SWPR_PAGE13 /*!< SRAM2 Write protection page 13 */ 00210 #define LL_SYSCFG_SRAM2WRP_PAGE14 SYSCFG_SWPR_PAGE14 /*!< SRAM2 Write protection page 14 */ 00211 #define LL_SYSCFG_SRAM2WRP_PAGE15 SYSCFG_SWPR_PAGE15 /*!< SRAM2 Write protection page 15 */ 00212 #define LL_SYSCFG_SRAM2WRP_PAGE16 SYSCFG_SWPR_PAGE16 /*!< SRAM2 Write protection page 16 */ 00213 #define LL_SYSCFG_SRAM2WRP_PAGE17 SYSCFG_SWPR_PAGE17 /*!< SRAM2 Write protection page 17 */ 00214 #define LL_SYSCFG_SRAM2WRP_PAGE18 SYSCFG_SWPR_PAGE18 /*!< SRAM2 Write protection page 18 */ 00215 #define LL_SYSCFG_SRAM2WRP_PAGE19 SYSCFG_SWPR_PAGE19 /*!< SRAM2 Write protection page 19 */ 00216 #define LL_SYSCFG_SRAM2WRP_PAGE20 SYSCFG_SWPR_PAGE20 /*!< SRAM2 Write protection page 20 */ 00217 #define LL_SYSCFG_SRAM2WRP_PAGE21 SYSCFG_SWPR_PAGE21 /*!< SRAM2 Write protection page 21 */ 00218 #define LL_SYSCFG_SRAM2WRP_PAGE22 SYSCFG_SWPR_PAGE22 /*!< SRAM2 Write protection page 22 */ 00219 #define LL_SYSCFG_SRAM2WRP_PAGE23 SYSCFG_SWPR_PAGE23 /*!< SRAM2 Write protection page 23 */ 00220 #define LL_SYSCFG_SRAM2WRP_PAGE24 SYSCFG_SWPR_PAGE24 /*!< SRAM2 Write protection page 24 */ 00221 #define LL_SYSCFG_SRAM2WRP_PAGE25 SYSCFG_SWPR_PAGE25 /*!< SRAM2 Write protection page 25 */ 00222 #define LL_SYSCFG_SRAM2WRP_PAGE26 SYSCFG_SWPR_PAGE26 /*!< SRAM2 Write protection page 26 */ 00223 #define LL_SYSCFG_SRAM2WRP_PAGE27 SYSCFG_SWPR_PAGE27 /*!< SRAM2 Write protection page 27 */ 00224 #define LL_SYSCFG_SRAM2WRP_PAGE28 SYSCFG_SWPR_PAGE28 /*!< SRAM2 Write protection page 28 */ 00225 #define LL_SYSCFG_SRAM2WRP_PAGE29 SYSCFG_SWPR_PAGE29 /*!< SRAM2 Write protection page 29 */ 00226 #define LL_SYSCFG_SRAM2WRP_PAGE30 SYSCFG_SWPR_PAGE30 /*!< SRAM2 Write protection page 30 */ 00227 #define LL_SYSCFG_SRAM2WRP_PAGE31 SYSCFG_SWPR_PAGE31 /*!< SRAM2 Write protection page 31 */ 00228 /** 00229 * @} 00230 */ 00231 00232 /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment 00233 * @{ 00234 */ 00235 #define LL_DBGMCU_TRACE_NONE (uint32_t)0x00000000 /*!< TRACE pins not assigned (default state) */ 00236 #define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */ 00237 #define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */ 00238 #define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */ 00239 #define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */ 00240 /** 00241 * @} 00242 */ 00243 00244 /** @defgroup SYSTEM_LL_EC_ABP1_GRP1_STOP_IP DBGMCU ABP1 GRP1 STOP IP 00245 * @{ 00246 */ 00247 #define LL_DBGMCU_ABP1_GRP1_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP /*!< The counter clock of TIM2 is stopped when the core is halted*/ 00248 #define LL_DBGMCU_ABP1_GRP1_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP /*!< The counter clock of TIM3 is stopped when the core is halted*/ 00249 #define LL_DBGMCU_ABP1_GRP1_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP /*!< The counter clock of TIM4 is stopped when the core is halted*/ 00250 #define LL_DBGMCU_ABP1_GRP1_TIM5_STOP DBGMCU_APB1FZR1_DBG_TIM5_STOP /*!< The counter clock of TIM5 is stopped when the core is halted*/ 00251 #define LL_DBGMCU_ABP1_GRP1_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP /*!< The counter clock of TIM6 is stopped when the core is halted*/ 00252 #define LL_DBGMCU_ABP1_GRP1_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP /*!< The counter clock of TIM7 is stopped when the core is halted*/ 00253 #define LL_DBGMCU_ABP1_GRP1_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP /*!< The clock of the RTC counter is stopped when the core is halted*/ 00254 #define LL_DBGMCU_ABP1_GRP1_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP /*!< The window watchdog counter clock is stopped when the core is halted*/ 00255 #define LL_DBGMCU_ABP1_GRP1_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP /*!< The independent watchdog counter clock is stopped when the core is halted*/ 00256 #define LL_DBGMCU_ABP1_GRP1_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP /*!< The I2C1 SMBus timeout is frozen*/ 00257 #define LL_DBGMCU_ABP1_GRP1_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP /*!< The I2C2 SMBus timeout is frozen*/ 00258 #define LL_DBGMCU_ABP1_GRP1_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP /*!< The I2C3 SMBus timeout is frozen*/ 00259 #define LL_DBGMCU_ABP1_GRP1_CAN_STOP DBGMCU_APB1FZR1_DBG_CAN_STOP /*!< The bxCAN receive registers are frozen*/ 00260 #define LL_DBGMCU_ABP1_GRP1_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP /*!< The counter clock of LPTIM1 is stopped when the core is halted*/ 00261 /** 00262 * @} 00263 */ 00264 00265 /** @defgroup SYSTEM_LL_EC_ABP1_GRP2_STOP_IP DBGMCU ABP1 GRP2 STOP IP 00266 * @{ 00267 */ 00268 #define LL_DBGMCU_ABP1_GRP2_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP /*!< The counter clock of LPTIM2 is stopped when the core is halted*/ 00269 /** 00270 * @} 00271 */ 00272 00273 /** @defgroup SYSTEM_LL_EC_ABP2_GRP1_STOP_IP DBGMCU ABP2 GRP1 STOP IP 00274 * @{ 00275 */ 00276 #define LL_DBGMCU_ABP2_GRP1_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP /*!< The counter clock of TIM1 is stopped when the core is halted*/ 00277 #define LL_DBGMCU_ABP2_GRP1_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP /*!< The counter clock of TIM8 is stopped when the core is halted*/ 00278 #define LL_DBGMCU_ABP2_GRP1_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP /*!< The counter clock of TIM15 is stopped when the core is halted*/ 00279 #define LL_DBGMCU_ABP2_GRP1_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP /*!< The counter clock of TIM16 is stopped when the core is halted*/ 00280 #define LL_DBGMCU_ABP2_GRP1_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP /*!< The counter clock of TIM17 is stopped when the core is halted*/ 00281 /** 00282 * @} 00283 */ 00284 00285 /** @defgroup SYSTEM_LL_EC_VOLTAGE VREFBUF VOLTAGE 00286 * @{ 00287 */ 00288 #define LL_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */ 00289 #define LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /*!< Voltage reference scale 1 (VREF_OUT2) */ 00290 /** 00291 * @} 00292 */ 00293 00294 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY 00295 * @{ 00296 */ 00297 #define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */ 00298 #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */ 00299 #define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */ 00300 #define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */ 00301 #define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */ 00302 /** 00303 * @} 00304 */ 00305 00306 /** 00307 * @} 00308 */ 00309 00310 /* Exported macro ------------------------------------------------------------*/ 00311 00312 /* Exported functions --------------------------------------------------------*/ 00313 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions 00314 * @{ 00315 */ 00316 00317 /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG 00318 * @{ 00319 */ 00320 00321 /** 00322 * @brief Set memory mapping at address 0x00000000 00323 * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_SetRemapMemory 00324 * @param Memory This parameter can be one of the following values: 00325 * @arg @ref LL_SYSCFG_REMAP_FLASH 00326 * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH 00327 * @arg @ref LL_SYSCFG_REMAP_SRAM 00328 * @arg @ref LL_SYSCFG_REMAP_FMC 00329 * @arg @ref LL_SYSCFG_REMAP_QUADSPI 00330 * @retval None 00331 */ 00332 __STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory) 00333 { 00334 MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory); 00335 } 00336 00337 /** 00338 * @brief Get memory mapping at address 0x00000000 00339 * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_GetRemapMemory 00340 * @retval Returned value can be one of the following values: 00341 * @arg @ref LL_SYSCFG_REMAP_FLASH 00342 * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH 00343 * @arg @ref LL_SYSCFG_REMAP_SRAM 00344 * @arg @ref LL_SYSCFG_REMAP_FMC 00345 * @arg @ref LL_SYSCFG_REMAP_QUADSPI 00346 */ 00347 __STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void) 00348 { 00349 return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)); 00350 } 00351 00352 /** 00353 * @brief Select Flash bank mode (Bank flashed at 0x08000000) 00354 * @rmtoll SYSCFG_MEMRMP FB_MODE LL_SYSCFG_SetFlashBankMode 00355 * @param Bank This parameter can be one of the following values: 00356 * @arg @ref LL_SYSCFG_BANKMODE_BANK1 00357 * @arg @ref LL_SYSCFG_BANKMODE_BANK2 00358 * @retval None 00359 */ 00360 __STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank) 00361 { 00362 MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE, Bank); 00363 } 00364 00365 /** 00366 * @brief Get Flash bank mode (Bank flashed at 0x08000000) 00367 * @rmtoll SYSCFG_MEMRMP FB_MODE LL_SYSCFG_GetFlashBankMode 00368 * @retval Returned value can be one of the following values: 00369 * @arg @ref LL_SYSCFG_BANKMODE_BANK1 00370 * @arg @ref LL_SYSCFG_BANKMODE_BANK2 00371 */ 00372 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void) 00373 { 00374 return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE)); 00375 } 00376 00377 /** 00378 * @brief Firewall protection enabled 00379 * @rmtoll SYSCFG_CFGR1 FWDIS LL_SYSCFG_EnableFirewall 00380 * @retval None 00381 */ 00382 __STATIC_INLINE void LL_SYSCFG_EnableFirewall(void) 00383 { 00384 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FWDIS); 00385 } 00386 00387 /** 00388 * @brief Check if Firewall protection is enabled or not 00389 * @rmtoll SYSCFG_CFGR1 FWDIS LL_SYSCFG_IsEnabledFirewall 00390 * @retval State of bit (1 or 0). 00391 */ 00392 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledFirewall(void) 00393 { 00394 return !(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FWDIS) == SYSCFG_CFGR1_FWDIS); 00395 } 00396 00397 /** 00398 * @brief Enable I/O analog switch voltage booster (I/O analog switches are supplied by a dedicated voltage booster (supplied by VDD). This is 00399 * the recommended configuration when using the ADC in low VDDAvoltage operation) 00400 * @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_EnableAnalogBooster 00401 * @retval None 00402 */ 00403 __STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void) 00404 { 00405 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); 00406 } 00407 00408 /** 00409 * @brief Disable I/O analog switch voltage booster (I/O analog switches are supplied by VDDAvoltage. This is the recommended configuration 00410 * when using the ADC in high VDDAvoltage operation) 00411 * @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_DisableAnalogBooster 00412 * @retval None 00413 */ 00414 __STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void) 00415 { 00416 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); 00417 } 00418 00419 /** 00420 * @brief Enable the I2C fast mode plus driving capability. 00421 * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_EnableFastModePlus\n 00422 * SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_EnableFastModePlus 00423 * @param ConfigFastModePlus This parameter can be a combination of the following values: 00424 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 00425 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 00426 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 00427 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 00428 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 00429 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 00430 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 00431 * @retval None 00432 */ 00433 __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus) 00434 { 00435 SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus); 00436 } 00437 00438 /** 00439 * @brief Disable the I2C fast mode plus driving capability. 00440 * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus\n 00441 * SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_DisableFastModePlus 00442 * @param ConfigFastModePlus This parameter can be a combination of the following values: 00443 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 00444 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 00445 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 00446 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 00447 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 00448 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 00449 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 00450 * @retval None 00451 */ 00452 __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus) 00453 { 00454 CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus); 00455 } 00456 00457 /** 00458 * @brief Enable Floating Point Unit Invalid operation Interrupt 00459 * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_EnableIT_FPU_IOC 00460 * @retval None 00461 */ 00462 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void) 00463 { 00464 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0); 00465 } 00466 00467 /** 00468 * @brief Enable Floating Point Unit Divide-by-zero Interrupt 00469 * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_EnableIT_FPU_DZC 00470 * @retval None 00471 */ 00472 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void) 00473 { 00474 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1); 00475 } 00476 00477 /** 00478 * @brief Enable Floating Point Unit Underflow Interrupt 00479 * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_EnableIT_FPU_UFC 00480 * @retval None 00481 */ 00482 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void) 00483 { 00484 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2); 00485 } 00486 00487 /** 00488 * @brief Enable Floating Point Unit Overflow Interrupt 00489 * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_EnableIT_FPU_OFC 00490 * @retval None 00491 */ 00492 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void) 00493 { 00494 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3); 00495 } 00496 00497 /** 00498 * @brief Enable Floating Point Unit Input denormal Interrupt 00499 * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_EnableIT_FPU_IDC 00500 * @retval None 00501 */ 00502 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void) 00503 { 00504 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4); 00505 } 00506 00507 /** 00508 * @brief Enable Floating Point Unit Inexact Interrupt 00509 * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_EnableIT_FPU_IXC 00510 * @retval None 00511 */ 00512 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void) 00513 { 00514 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5); 00515 } 00516 00517 /** 00518 * @brief Disable Floating Point Unit Invalid operation Interrupt 00519 * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_DisableIT_FPU_IOC 00520 * @retval None 00521 */ 00522 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void) 00523 { 00524 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0); 00525 } 00526 00527 /** 00528 * @brief Disable Floating Point Unit Divide-by-zero Interrupt 00529 * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_DisableIT_FPU_DZC 00530 * @retval None 00531 */ 00532 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void) 00533 { 00534 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1); 00535 } 00536 00537 /** 00538 * @brief Disable Floating Point Unit Underflow Interrupt 00539 * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_DisableIT_FPU_UFC 00540 * @retval None 00541 */ 00542 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void) 00543 { 00544 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2); 00545 } 00546 00547 /** 00548 * @brief Disable Floating Point Unit Overflow Interrupt 00549 * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_DisableIT_FPU_OFC 00550 * @retval None 00551 */ 00552 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void) 00553 { 00554 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3); 00555 } 00556 00557 /** 00558 * @brief Disable Floating Point Unit Input denormal Interrupt 00559 * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_DisableIT_FPU_IDC 00560 * @retval None 00561 */ 00562 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void) 00563 { 00564 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4); 00565 } 00566 00567 /** 00568 * @brief Disable Floating Point Unit Inexact Interrupt 00569 * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_DisableIT_FPU_IXC 00570 * @retval None 00571 */ 00572 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC(void) 00573 { 00574 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5); 00575 } 00576 00577 /** 00578 * @brief Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled. 00579 * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_IsEnabledIT_FPU_IOC 00580 * @retval State of bit (1 or 0). 00581 */ 00582 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void) 00583 { 00584 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0) == (SYSCFG_CFGR1_FPU_IE_0)); 00585 } 00586 00587 /** 00588 * @brief Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled. 00589 * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_IsEnabledIT_FPU_DZC 00590 * @retval State of bit (1 or 0). 00591 */ 00592 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void) 00593 { 00594 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1) == (SYSCFG_CFGR1_FPU_IE_1)); 00595 } 00596 00597 /** 00598 * @brief Check if Floating Point Unit Underflow Interrupt source is enabled or disabled. 00599 * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_IsEnabledIT_FPU_UFC 00600 * @retval State of bit (1 or 0). 00601 */ 00602 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void) 00603 { 00604 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2) == (SYSCFG_CFGR1_FPU_IE_2)); 00605 } 00606 00607 /** 00608 * @brief Check if Floating Point Unit Overflow Interrupt source is enabled or disabled. 00609 * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_IsEnabledIT_FPU_OFC 00610 * @retval State of bit (1 or 0). 00611 */ 00612 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void) 00613 { 00614 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3) == (SYSCFG_CFGR1_FPU_IE_3)); 00615 } 00616 00617 /** 00618 * @brief Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled. 00619 * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_IsEnabledIT_FPU_IDC 00620 * @retval State of bit (1 or 0). 00621 */ 00622 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void) 00623 { 00624 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4) == (SYSCFG_CFGR1_FPU_IE_4)); 00625 } 00626 00627 /** 00628 * @brief Check if Floating Point Unit Inexact Interrupt source is enabled or disabled. 00629 * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_IsEnabledIT_FPU_IXC 00630 * @retval State of bit (1 or 0). 00631 */ 00632 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void) 00633 { 00634 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5) == (SYSCFG_CFGR1_FPU_IE_5)); 00635 } 00636 00637 /** 00638 * @brief Configure source input for the EXTI external interrupt. 00639 * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n 00640 * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n 00641 * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n 00642 * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource 00643 * @param Port This parameter can be one of the following values: 00644 * @arg @ref LL_SYSCFG_EXTI_PORTA 00645 * @arg @ref LL_SYSCFG_EXTI_PORTB 00646 * @arg @ref LL_SYSCFG_EXTI_PORTC 00647 * @arg @ref LL_SYSCFG_EXTI_PORTD 00648 * @arg @ref LL_SYSCFG_EXTI_PORTE 00649 * @arg @ref LL_SYSCFG_EXTI_PORTF 00650 * @arg @ref LL_SYSCFG_EXTI_PORTG 00651 * @arg @ref LL_SYSCFG_EXTI_PORTH 00652 * @param Line This parameter can be one of the following values: 00653 * @arg @ref LL_SYSCFG_EXTI_LINE0 00654 * @arg @ref LL_SYSCFG_EXTI_LINE1 00655 * @arg @ref LL_SYSCFG_EXTI_LINE2 00656 * @arg @ref LL_SYSCFG_EXTI_LINE3 00657 * @arg @ref LL_SYSCFG_EXTI_LINE4 00658 * @arg @ref LL_SYSCFG_EXTI_LINE5 00659 * @arg @ref LL_SYSCFG_EXTI_LINE6 00660 * @arg @ref LL_SYSCFG_EXTI_LINE7 00661 * @arg @ref LL_SYSCFG_EXTI_LINE8 00662 * @arg @ref LL_SYSCFG_EXTI_LINE9 00663 * @arg @ref LL_SYSCFG_EXTI_LINE10 00664 * @arg @ref LL_SYSCFG_EXTI_LINE11 00665 * @arg @ref LL_SYSCFG_EXTI_LINE12 00666 * @arg @ref LL_SYSCFG_EXTI_LINE13 00667 * @arg @ref LL_SYSCFG_EXTI_LINE14 00668 * @arg @ref LL_SYSCFG_EXTI_LINE15 00669 * @retval None 00670 */ 00671 __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line) 00672 { 00673 MODIFY_REG(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16), Port << POSITION_VAL((Line >> 16))); 00674 } 00675 00676 /** 00677 * @brief Get the configured defined for specific EXTI Line 00678 * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n 00679 * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n 00680 * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n 00681 * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource 00682 * @param Line This parameter can be one of the following values: 00683 * @arg @ref LL_SYSCFG_EXTI_LINE0 00684 * @arg @ref LL_SYSCFG_EXTI_LINE1 00685 * @arg @ref LL_SYSCFG_EXTI_LINE2 00686 * @arg @ref LL_SYSCFG_EXTI_LINE3 00687 * @arg @ref LL_SYSCFG_EXTI_LINE4 00688 * @arg @ref LL_SYSCFG_EXTI_LINE5 00689 * @arg @ref LL_SYSCFG_EXTI_LINE6 00690 * @arg @ref LL_SYSCFG_EXTI_LINE7 00691 * @arg @ref LL_SYSCFG_EXTI_LINE8 00692 * @arg @ref LL_SYSCFG_EXTI_LINE9 00693 * @arg @ref LL_SYSCFG_EXTI_LINE10 00694 * @arg @ref LL_SYSCFG_EXTI_LINE11 00695 * @arg @ref LL_SYSCFG_EXTI_LINE12 00696 * @arg @ref LL_SYSCFG_EXTI_LINE13 00697 * @arg @ref LL_SYSCFG_EXTI_LINE14 00698 * @arg @ref LL_SYSCFG_EXTI_LINE15 00699 * @retval Returned value can be one of the following values: 00700 * @arg @ref LL_SYSCFG_EXTI_PORTA 00701 * @arg @ref LL_SYSCFG_EXTI_PORTB 00702 * @arg @ref LL_SYSCFG_EXTI_PORTC 00703 * @arg @ref LL_SYSCFG_EXTI_PORTD 00704 * @arg @ref LL_SYSCFG_EXTI_PORTE 00705 * @arg @ref LL_SYSCFG_EXTI_PORTF 00706 * @arg @ref LL_SYSCFG_EXTI_PORTG 00707 * @arg @ref LL_SYSCFG_EXTI_PORTH 00708 */ 00709 __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line) 00710 { 00711 return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16)) >> POSITION_VAL(Line >> 16)); 00712 } 00713 00714 /** 00715 * @brief Enable SRAM2 Erase (starts a hardware SRAM2 erase operation. This bit is 00716 * automatically cleared at the end of the SRAM2 erase operation.) 00717 * @note This bit is write-protected: setting this bit is possible only after the 00718 * correct key sequence is written in the SYSCFG_SKR register. 00719 * @rmtoll SYSCFG_SCSR SRAM2ER LL_SYSCFG_EnableSRAM2Erase 00720 * @retval None 00721 */ 00722 __STATIC_INLINE void LL_SYSCFG_EnableSRAM2Erase(void) 00723 { 00724 /* unlock the write protection of the SRAM2ER bit */ 00725 WRITE_REG(SYSCFG->SKR, 0xCA); 00726 WRITE_REG(SYSCFG->SKR, 0x53); 00727 00728 /* Starts a hardware SRAM2 erase operation*/ 00729 SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER); 00730 } 00731 00732 /** 00733 * @brief Check if SRAM2 erase operation is on going 00734 * @rmtoll SYSCFG_SCSR SRAM2BSY LL_SYSCFG_IsSRAM2EraseOngoing 00735 * @retval State of bit (1 or 0). 00736 */ 00737 __STATIC_INLINE uint32_t LL_SYSCFG_IsSRAM2EraseOngoing(void) 00738 { 00739 return (READ_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2BSY) == (SYSCFG_SCSR_SRAM2BSY)); 00740 } 00741 00742 /** 00743 * @brief Set connections to TIM1/8/15/16/17 Break inputs 00744 * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_SetTIMBreakInputs\n 00745 * SYSCFG_CFGR2 SPL LL_SYSCFG_SetTIMBreakInputs\n 00746 * SYSCFG_CFGR2 PVDL LL_SYSCFG_SetTIMBreakInputs\n 00747 * SYSCFG_CFGR2 ECCL LL_SYSCFG_SetTIMBreakInputs 00748 * @param Break This parameter can be a combination of the following values: 00749 * @arg @ref LL_SYSCFG_TIMBREAK_ECC 00750 * @arg @ref LL_SYSCFG_TIMBREAK_PVD 00751 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_PARITY 00752 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP 00753 * @retval None 00754 */ 00755 __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break) 00756 { 00757 MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL, Break); 00758 } 00759 00760 /** 00761 * @brief Get connections to TIM1/8/15/16/17 Break inputs 00762 * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_GetTIMBreakInputs\n 00763 * SYSCFG_CFGR2 SPL LL_SYSCFG_GetTIMBreakInputs\n 00764 * SYSCFG_CFGR2 PVDL LL_SYSCFG_GetTIMBreakInputs\n 00765 * SYSCFG_CFGR2 ECCL LL_SYSCFG_GetTIMBreakInputs 00766 * @retval Returned value can be can be a combination of the following values: 00767 * @arg @ref LL_SYSCFG_TIMBREAK_ECC 00768 * @arg @ref LL_SYSCFG_TIMBREAK_PVD 00769 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_PARITY 00770 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP 00771 */ 00772 __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void) 00773 { 00774 return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL)); 00775 } 00776 00777 /** 00778 * @brief Check if SRAM2 parity error detected 00779 * @rmtoll SYSCFG_CFGR2 SPF LL_SYSCFG_IsActiveFlag_SP 00780 * @retval State of bit (1 or 0). 00781 */ 00782 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void) 00783 { 00784 return (READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) == (SYSCFG_CFGR2_SPF)); 00785 } 00786 00787 /** 00788 * @brief Clear SRAM2 parity error flag 00789 * @rmtoll SYSCFG_CFGR2 SPF LL_SYSCFG_ClearFlag_SP 00790 * @retval None 00791 */ 00792 __STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void) 00793 { 00794 SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF); 00795 } 00796 00797 /** 00798 * @brief Enable SRAM2 page write protection 00799 * @note Write protection is cleared only by a system reset 00800 * @rmtoll SYSCFG_SWPR PAGEx LL_SYSCFG_EnableSRAM2PageWRP 00801 * @param SRAM2WRP This parameter can be a combination of the following values: 00802 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE0 00803 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE1 00804 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE2 00805 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE3 00806 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE4 00807 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE5 00808 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE6 00809 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE7 00810 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE8 00811 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE9 00812 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE10 00813 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE11 00814 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE12 00815 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE13 00816 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE14 00817 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE15 00818 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE16 00819 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE17 00820 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE18 00821 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE19 00822 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE20 00823 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE21 00824 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE22 00825 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE23 00826 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE24 00827 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE25 00828 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE26 00829 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE27 00830 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE28 00831 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE29 00832 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE30 00833 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE31 00834 * @retval None 00835 */ 00836 __STATIC_INLINE void LL_SYSCFG_EnableSRAM2PageWRP(uint32_t SRAM2WRP) 00837 { 00838 SET_BIT(SYSCFG->SWPR, SRAM2WRP); 00839 } 00840 00841 /** 00842 * @brief SRAM2 page write protection lock prior to erase 00843 * @rmtoll SYSCFG_SKR KEY LL_SYSCFG_LockSRAM2WRP 00844 * @retval None 00845 */ 00846 __STATIC_INLINE void LL_SYSCFG_LockSRAM2WRP(void) 00847 { 00848 /* Writing a wrong key reactivates the write protection */ 00849 WRITE_REG(SYSCFG->SKR, 0x00); 00850 } 00851 00852 /** 00853 * @brief SRAM2 page write protection unlock prior to erase 00854 * @rmtoll SYSCFG_SKR KEY LL_SYSCFG_UnlockSRAM2WRP 00855 * @retval None 00856 */ 00857 __STATIC_INLINE void LL_SYSCFG_UnlockSRAM2WRP(void) 00858 { 00859 /* unlock the write protection of the SRAM2ER bit */ 00860 WRITE_REG(SYSCFG->SKR, 0xCA); 00861 WRITE_REG(SYSCFG->SKR, 0x53); 00862 } 00863 00864 /** 00865 * @} 00866 */ 00867 00868 00869 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU 00870 * @{ 00871 */ 00872 00873 /** 00874 * @brief Returns the device identifier 00875 * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID 00876 * @retval Values between 0x00 and 0xFFFF (ex: device ID is 0x6415) 00877 */ 00878 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) 00879 { 00880 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); 00881 } 00882 00883 /** 00884 * @brief Returns the device revision identifier 00885 * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID 00886 * @retval Values between 0x00 and 0xFFFF (ex: This field indicates the revision of the device. 00887 */ 00888 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) 00889 { 00890 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_REVID_POSITION); 00891 } 00892 00893 /** 00894 * @brief Enable the Debug Module during SLEEP mode 00895 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode 00896 * @retval None 00897 */ 00898 __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void) 00899 { 00900 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); 00901 } 00902 00903 /** 00904 * @brief Disable the Debug Module during SLEEP mode 00905 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode 00906 * @retval None 00907 */ 00908 __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void) 00909 { 00910 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); 00911 } 00912 00913 /** 00914 * @brief Enable the Debug Module during STOP mode 00915 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode 00916 * @retval None 00917 */ 00918 __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) 00919 { 00920 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); 00921 } 00922 00923 /** 00924 * @brief Disable the Debug Module during STOP mode 00925 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode 00926 * @retval None 00927 */ 00928 __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void) 00929 { 00930 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); 00931 } 00932 00933 /** 00934 * @brief Enable the Debug Module during STANDBY mode 00935 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode 00936 * @retval None 00937 */ 00938 __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) 00939 { 00940 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); 00941 } 00942 00943 /** 00944 * @brief Disable the Debug Module during STANDBY mode 00945 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode 00946 * @retval None 00947 */ 00948 __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) 00949 { 00950 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); 00951 } 00952 00953 /** 00954 * @brief Set Trace pin assignment control 00955 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n 00956 * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment 00957 * @param PinAssignment This parameter can be one of the following values: 00958 * @arg @ref LL_DBGMCU_TRACE_NONE 00959 * @arg @ref LL_DBGMCU_TRACE_ASYNCH 00960 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 00961 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 00962 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 00963 * @retval None 00964 */ 00965 __STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment) 00966 { 00967 MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment); 00968 } 00969 00970 /** 00971 * @brief Get Trace pin assignment control 00972 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n 00973 * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment 00974 * @retval Returned value can be one of the following values: 00975 * @arg @ref LL_DBGMCU_TRACE_NONE 00976 * @arg @ref LL_DBGMCU_TRACE_ASYNCH 00977 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 00978 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 00979 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 00980 */ 00981 __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void) 00982 { 00983 return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)); 00984 } 00985 00986 /** 00987 * @brief Freeze APB1 peripherals (group1 peripherals) 00988 * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_ABP1_GRP1_FreezePeriph 00989 * @param Periphs This parameter can be a combination of the following values: 00990 * @arg @ref LL_DBGMCU_ABP1_GRP1_TIM2_STOP 00991 * @arg @ref LL_DBGMCU_ABP1_GRP1_TIM3_STOP 00992 * @arg @ref LL_DBGMCU_ABP1_GRP1_TIM4_STOP 00993 * @arg @ref LL_DBGMCU_ABP1_GRP1_TIM5_STOP 00994 * @arg @ref LL_DBGMCU_ABP1_GRP1_TIM6_STOP 00995 * @arg @ref LL_DBGMCU_ABP1_GRP1_TIM7_STOP 00996 * @arg @ref LL_DBGMCU_ABP1_GRP1_RTC_STOP 00997 * @arg @ref LL_DBGMCU_ABP1_GRP1_WWDG_STOP 00998 * @arg @ref LL_DBGMCU_ABP1_GRP1_IWDG_STOP 00999 * @arg @ref LL_DBGMCU_ABP1_GRP1_I2C1_STOP 01000 * @arg @ref LL_DBGMCU_ABP1_GRP1_I2C2_STOP 01001 * @arg @ref LL_DBGMCU_ABP1_GRP1_I2C3_STOP 01002 * @arg @ref LL_DBGMCU_ABP1_GRP1_CAN_STOP 01003 * @arg @ref LL_DBGMCU_ABP1_GRP1_LPTIM1_STOP 01004 * @retval None 01005 */ 01006 __STATIC_INLINE void LL_DBGMCU_ABP1_GRP1_FreezePeriph(uint32_t Periphs) 01007 { 01008 SET_BIT(DBGMCU->APB1FZR1, Periphs); 01009 } 01010 01011 /** 01012 * @brief Freeze APB1 peripherals (group2 peripherals) 01013 * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_ABP1_GRP2_FreezePeriph 01014 * @param Periphs This parameter can be a combination of the following values: 01015 * @arg @ref LL_DBGMCU_ABP1_GRP2_LPTIM2_STOP 01016 * @retval None 01017 */ 01018 __STATIC_INLINE void LL_DBGMCU_ABP1_GRP2_FreezePeriph(uint32_t Periphs) 01019 { 01020 SET_BIT(DBGMCU->APB1FZR2, Periphs); 01021 } 01022 01023 /** 01024 * @brief Unfreeze APB1 peripherals (group1 peripherals) 01025 * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_ABP1_GRP1_UnFreezePeriph 01026 * @param Periphs This parameter can be a combination of the following values: 01027 * @arg @ref LL_DBGMCU_ABP1_GRP1_TIM2_STOP 01028 * @arg @ref LL_DBGMCU_ABP1_GRP1_TIM3_STOP 01029 * @arg @ref LL_DBGMCU_ABP1_GRP1_TIM4_STOP 01030 * @arg @ref LL_DBGMCU_ABP1_GRP1_TIM5_STOP 01031 * @arg @ref LL_DBGMCU_ABP1_GRP1_TIM6_STOP 01032 * @arg @ref LL_DBGMCU_ABP1_GRP1_TIM7_STOP 01033 * @arg @ref LL_DBGMCU_ABP1_GRP1_RTC_STOP 01034 * @arg @ref LL_DBGMCU_ABP1_GRP1_WWDG_STOP 01035 * @arg @ref LL_DBGMCU_ABP1_GRP1_IWDG_STOP 01036 * @arg @ref LL_DBGMCU_ABP1_GRP1_I2C1_STOP 01037 * @arg @ref LL_DBGMCU_ABP1_GRP1_I2C2_STOP 01038 * @arg @ref LL_DBGMCU_ABP1_GRP1_I2C3_STOP 01039 * @arg @ref LL_DBGMCU_ABP1_GRP1_CAN_STOP 01040 * @arg @ref LL_DBGMCU_ABP1_GRP1_LPTIM1_STOP 01041 * @retval None 01042 */ 01043 __STATIC_INLINE void LL_DBGMCU_ABP1_GRP1_UnFreezePeriph(uint32_t Periphs) 01044 { 01045 CLEAR_BIT(DBGMCU->APB1FZR1, Periphs); 01046 } 01047 01048 /** 01049 * @brief Unfreeze APB1 peripherals (group2 peripherals) 01050 * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_ABP1_GRP2_UnFreezePeriph 01051 * @param Periphs This parameter can be a combination of the following values: 01052 * @arg @ref LL_DBGMCU_ABP1_GRP2_LPTIM2_STOP 01053 * @retval None 01054 */ 01055 __STATIC_INLINE void LL_DBGMCU_ABP1_GRP2_UnFreezePeriph(uint32_t Periphs) 01056 { 01057 CLEAR_BIT(DBGMCU->APB1FZR2, Periphs); 01058 } 01059 01060 /** 01061 * @brief Freeze APB2 peripherals 01062 * @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP LL_DBGMCU_ABP2_GRP1_FreezePeriph 01063 * @param Periphs This parameter can be a combination of the following values: 01064 * @arg @ref LL_DBGMCU_ABP2_GRP1_TIM1_STOP 01065 * @arg @ref LL_DBGMCU_ABP2_GRP1_TIM8_STOP 01066 * @arg @ref LL_DBGMCU_ABP2_GRP1_TIM15_STOP 01067 * @arg @ref LL_DBGMCU_ABP2_GRP1_TIM16_STOP 01068 * @arg @ref LL_DBGMCU_ABP2_GRP1_TIM17_STOP 01069 * @retval None 01070 */ 01071 __STATIC_INLINE void LL_DBGMCU_ABP2_GRP1_FreezePeriph(uint32_t Periphs) 01072 { 01073 SET_BIT(DBGMCU->APB2FZ, Periphs); 01074 } 01075 01076 /** 01077 * @brief Unfreeze APB2 peripherals 01078 * @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP LL_DBGMCU_ABP2_GRP1_UnFreezePeriph 01079 * @param Periphs This parameter can be a combination of the following values: 01080 * @arg @ref LL_DBGMCU_ABP2_GRP1_TIM1_STOP 01081 * @arg @ref LL_DBGMCU_ABP2_GRP1_TIM8_STOP 01082 * @arg @ref LL_DBGMCU_ABP2_GRP1_TIM15_STOP 01083 * @arg @ref LL_DBGMCU_ABP2_GRP1_TIM16_STOP 01084 * @arg @ref LL_DBGMCU_ABP2_GRP1_TIM17_STOP 01085 * @retval None 01086 */ 01087 __STATIC_INLINE void LL_DBGMCU_ABP2_GRP1_UnFreezePeriph(uint32_t Periphs) 01088 { 01089 CLEAR_BIT(DBGMCU->APB2FZ, Periphs); 01090 } 01091 01092 /** 01093 * @} 01094 */ 01095 01096 01097 /** @defgroup SYSTEM_LL_EF_VREFBUF VREFBUF 01098 * @{ 01099 */ 01100 01101 /** 01102 * @brief Enable Internal voltage reference 01103 * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Enable 01104 * @retval None 01105 */ 01106 __STATIC_INLINE void LL_VREFBUF_Enable(void) 01107 { 01108 SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); 01109 } 01110 01111 /** 01112 * @brief Disable Internal voltage reference 01113 * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Disable 01114 * @retval None 01115 */ 01116 __STATIC_INLINE void LL_VREFBUF_Disable(void) 01117 { 01118 CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); 01119 } 01120 01121 /** 01122 * @brief Enable high impedance (VREF+pin is high impedance) 01123 * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_EnableHIZ 01124 * @retval None 01125 */ 01126 __STATIC_INLINE void LL_VREFBUF_EnableHIZ(void) 01127 { 01128 SET_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ); 01129 } 01130 01131 /** 01132 * @brief Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output) 01133 * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_DisableHIZ 01134 * @retval None 01135 */ 01136 __STATIC_INLINE void LL_VREFBUF_DisableHIZ(void) 01137 { 01138 CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ); 01139 } 01140 01141 /** 01142 * @brief Set the Voltage reference scale 01143 * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_SetVoltageScaling 01144 * @param Scale This parameter can be one of the following values: 01145 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0 01146 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1 01147 * @retval None 01148 */ 01149 __STATIC_INLINE void LL_VREFBUF_SetVoltageScaling(uint32_t Scale) 01150 { 01151 MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, Scale); 01152 } 01153 01154 /** 01155 * @brief Get the Voltage reference scale 01156 * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_GetVoltageScaling 01157 * @retval Returned value can be one of the following values: 01158 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0 01159 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1 01160 */ 01161 __STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling(void) 01162 { 01163 return (uint32_t)(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRS)); 01164 } 01165 01166 /** 01167 * @brief Check if Voltage reference buffer is ready 01168 * @rmtoll VREFBUF_CSR VRR LL_VREFBUF_IsVREFReady 01169 * @retval State of bit (1 or 0). 01170 */ 01171 __STATIC_INLINE uint32_t LL_VREFBUF_IsVREFReady(void) 01172 { 01173 return (READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == (VREFBUF_CSR_VRR)); 01174 } 01175 01176 /** 01177 * @brief Get the trimming code for VREFBUF calibration 01178 * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_GetTrimming 01179 * @retval Between 0 and 0x3F 01180 */ 01181 __STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming(void) 01182 { 01183 return (uint32_t)(READ_BIT(VREFBUF->CCR, VREFBUF_CCR_TRIM)); 01184 } 01185 01186 /** 01187 * @brief Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage) 01188 * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_SetTrimming 01189 * @param Value Between 0 and 0x3F 01190 * @retval None 01191 */ 01192 __STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value) 01193 { 01194 WRITE_REG(VREFBUF->CCR, Value); 01195 } 01196 01197 /** 01198 * @} 01199 */ 01200 01201 01202 /** @defgroup SYSTEM_LL_EF_FLASH FLASH 01203 * @{ 01204 */ 01205 01206 /** 01207 * @brief Set FLASH Latency 01208 * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency 01209 * @param Latency This parameter can be one of the following values: 01210 * @arg @ref LL_FLASH_LATENCY_0 01211 * @arg @ref LL_FLASH_LATENCY_1 01212 * @arg @ref LL_FLASH_LATENCY_2 01213 * @arg @ref LL_FLASH_LATENCY_3 01214 * @arg @ref LL_FLASH_LATENCY_4 01215 * @retval None 01216 */ 01217 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) 01218 { 01219 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); 01220 } 01221 01222 /** 01223 * @brief Get FLASH Latency 01224 * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency 01225 * @retval Returned value can be one of the following values: 01226 * @arg @ref LL_FLASH_LATENCY_0 01227 * @arg @ref LL_FLASH_LATENCY_1 01228 * @arg @ref LL_FLASH_LATENCY_2 01229 * @arg @ref LL_FLASH_LATENCY_3 01230 * @arg @ref LL_FLASH_LATENCY_4 01231 */ 01232 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) 01233 { 01234 return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); 01235 } 01236 01237 /** 01238 * @brief Enable Prefetch 01239 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch 01240 * @retval None 01241 */ 01242 __STATIC_INLINE void LL_FLASH_EnablePrefetch(void) 01243 { 01244 SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN); 01245 } 01246 01247 /** 01248 * @brief Disable Prefetch 01249 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch 01250 * @retval None 01251 */ 01252 __STATIC_INLINE void LL_FLASH_DisablePrefetch(void) 01253 { 01254 CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN); 01255 } 01256 01257 /** 01258 * @brief Enable Instruction cache 01259 * @rmtoll FLASH_ACR ICEN LL_FLASH_EnableInstCache 01260 * @retval None 01261 */ 01262 __STATIC_INLINE void LL_FLASH_EnableInstCache(void) 01263 { 01264 SET_BIT(FLASH->ACR, FLASH_ACR_ICEN); 01265 } 01266 01267 /** 01268 * @brief Disable Instruction cache 01269 * @rmtoll FLASH_ACR ICEN LL_FLASH_DisableInstCache 01270 * @retval None 01271 */ 01272 __STATIC_INLINE void LL_FLASH_DisableInstCache(void) 01273 { 01274 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN); 01275 } 01276 01277 /** 01278 * @brief Enable Data cache 01279 * @rmtoll FLASH_ACR DCEN LL_FLASH_EnableDataCache 01280 * @retval None 01281 */ 01282 __STATIC_INLINE void LL_FLASH_EnableDataCache(void) 01283 { 01284 SET_BIT(FLASH->ACR, FLASH_ACR_DCEN); 01285 } 01286 01287 /** 01288 * @brief Disable Data cache 01289 * @rmtoll FLASH_ACR DCEN LL_FLASH_DisableDataCache 01290 * @retval None 01291 */ 01292 __STATIC_INLINE void LL_FLASH_DisableDataCache(void) 01293 { 01294 CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN); 01295 } 01296 01297 /** 01298 * @brief Enable Instruction cache reset 01299 * @note bit can be written only when the instruction cache is disabled 01300 * @rmtoll FLASH_ACR ICRST LL_FLASH_EnableInstCacheReset 01301 * @retval None 01302 */ 01303 __STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void) 01304 { 01305 SET_BIT(FLASH->ACR, FLASH_ACR_ICRST); 01306 } 01307 01308 /** 01309 * @brief Disable Instruction cache reset 01310 * @rmtoll FLASH_ACR ICRST LL_FLASH_DisableInstCacheReset 01311 * @retval None 01312 */ 01313 __STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void) 01314 { 01315 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); 01316 } 01317 01318 /** 01319 * @brief Enable Data cache reset 01320 * @note bit can be written only when the data cache is disabled 01321 * @rmtoll FLASH_ACR DCRST LL_FLASH_EnableDataCacheReset 01322 * @retval None 01323 */ 01324 __STATIC_INLINE void LL_FLASH_EnableDataCacheReset(void) 01325 { 01326 SET_BIT(FLASH->ACR, FLASH_ACR_DCRST); 01327 } 01328 01329 /** 01330 * @brief Disable Data cache reset 01331 * @rmtoll FLASH_ACR DCRST LL_FLASH_DisableDataCacheReset 01332 * @retval None 01333 */ 01334 __STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void) 01335 { 01336 CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST); 01337 } 01338 01339 /** 01340 * @brief Enable Flash Power-down mode during run mode or Low-power run mode 01341 * @note Flash memory can be put in power-down mode only when the code is executed 01342 * from RAM 01343 * @note Flash must not be accessed when power down is enabled 01344 * @note Flash must not be put in power-down while a program or an erase operation 01345 * is on-going 01346 * @rmtoll FLASH_ACR RUN_PD LL_FLASH_EnableRunPowerDown\n 01347 * FLASH_PDKEYR PDKEY1 LL_FLASH_EnableRunPowerDown\n 01348 * FLASH_PDKEYR PDKEY2 LL_FLASH_EnableRunPowerDown 01349 * @retval None 01350 */ 01351 __STATIC_INLINE void LL_FLASH_EnableRunPowerDown(void) 01352 { 01353 /* Following values must be written consecutively to unlock the RUN_PD bit in 01354 FLASH_ACR */ 01355 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); 01356 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); 01357 SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); 01358 } 01359 01360 /** 01361 * @brief Disable Flash Power-down mode during run mode or Low-power run mode 01362 * @rmtoll FLASH_ACR RUN_PD LL_FLASH_DisableRunPowerDown\n 01363 * FLASH_PDKEYR PDKEY1 LL_FLASH_DisableRunPowerDown\n 01364 * FLASH_PDKEYR PDKEY2 LL_FLASH_DisableRunPowerDown 01365 * @retval None 01366 */ 01367 __STATIC_INLINE void LL_FLASH_DisableRunPowerDown(void) 01368 { 01369 /* Following values must be written consecutively to unlock the RUN_PD bit in 01370 FLASH_ACR */ 01371 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); 01372 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); 01373 CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); 01374 } 01375 01376 /** 01377 * @brief Enable Flash Power-down mode during Sleep or Low-power sleep mode 01378 * @note Flash must not be put in power-down while a program or an erase operation 01379 * is on-going 01380 * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_EnableSleepPowerDown 01381 * @retval None 01382 */ 01383 __STATIC_INLINE void LL_FLASH_EnableSleepPowerDown(void) 01384 { 01385 SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD); 01386 } 01387 01388 /** 01389 * @brief Disable Flash Power-down mode during Sleep or Low-power sleep mode 01390 * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_DisableSleepPowerDown 01391 * @retval None 01392 */ 01393 __STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void) 01394 { 01395 CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD); 01396 } 01397 01398 /** 01399 * @} 01400 */ 01401 01402 /** 01403 * @} 01404 */ 01405 01406 /** 01407 * @} 01408 */ 01409 01410 #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF) */ 01411 01412 /** 01413 * @} 01414 */ 01415 01416 #ifdef __cplusplus 01417 } 01418 #endif 01419 01420 #endif /* __STM32L4xx_LL_SYSTEM_H */ 01421 01422 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 01423
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