stm32l4xx_ll_swpmi.h

00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_swpmi.h
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    16-September-2015
00007   * @brief   Header file of SWPMI LL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037 
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_LL_SWPMI_H
00040 #define __STM32L4xx_LL_SWPMI_H
00041 
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045 
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx.h"
00048 
00049 /** @addtogroup STM32L4xx_LL_Driver
00050   * @{
00051   */
00052 
00053 #if defined (SWPMI1)
00054 
00055 /** @defgroup SWPMI_LL SWPMI
00056   * @{
00057   */
00058 
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061 
00062 /* Private constants ---------------------------------------------------------*/
00063 
00064 /* Private macros ------------------------------------------------------------*/
00065 
00066 /* Exported types ------------------------------------------------------------*/
00067 /* Exported constants --------------------------------------------------------*/
00068 /** @defgroup SWPMI_LL_Exported_Constants SWPMI Exported Constants
00069   * @{
00070   */
00071 
00072 /** @defgroup SWPMI_LL_EC_CLEAR_FLAG Clear Flags Defines
00073   * @brief    Flags defines which can be used with LL_SWPMI_WriteReg function
00074   * @{
00075   */
00076 #define LL_SWPMI_ICR_CRXBFF          SWPMI_ICR_CRXBFF
00077 #define LL_SWPMI_ICR_CTXBEF          SWPMI_ICR_CTXBEF
00078 #define LL_SWPMI_ICR_CRXBERF         SWPMI_ICR_CRXBERF
00079 #define LL_SWPMI_ICR_CRXOVRF         SWPMI_ICR_CRXOVRF
00080 #define LL_SWPMI_ICR_CTXUNRF         SWPMI_ICR_CTXUNRF
00081 #define LL_SWPMI_ICR_CTCF            SWPMI_ICR_CTCF
00082 #define LL_SWPMI_ICR_CSRF            SWPMI_ICR_CSRF
00083 /**
00084   * @}
00085   */
00086 
00087 /** @defgroup SWPMI_LL_EC_GET_FLAG Get Flags Defines
00088   * @brief    Flags defines which can be used with LL_SWPMI_ReadReg function
00089   * @{
00090   */
00091 #define LL_SWPMI_ISR_RXBFF           SWPMI_ISR_RXBFF
00092 #define LL_SWPMI_ISR_TXBEF           SWPMI_ISR_TXBEF
00093 #define LL_SWPMI_ISR_RXBERF          SWPMI_ISR_RXBERF
00094 #define LL_SWPMI_ISR_RXOVRF          SWPMI_ISR_RXOVRF
00095 #define LL_SWPMI_ISR_TXUNRF          SWPMI_ISR_TXUNRF
00096 #define LL_SWPMI_ISR_RXNE            SWPMI_ISR_RXNE
00097 #define LL_SWPMI_ISR_TXE             SWPMI_ISR_TXE
00098 #define LL_SWPMI_ISR_TCF             SWPMI_ISR_TCF
00099 #define LL_SWPMI_ISR_SRF             SWPMI_ISR_SRF
00100 #define LL_SWPMI_ISR_SUSP            SWPMI_ISR_SUSP
00101 #define LL_SWPMI_ISR_DEACTF          SWPMI_ISR_DEACTF
00102 /**
00103   * @}
00104   */
00105 
00106 /** @defgroup SWPMI_LL_EC_IT IT Defines
00107   * @brief    IT defines which can be used with LL_SWPMI_ReadReg and  LL_SWPMI_WriteReg functions
00108   * @{
00109   */
00110 #define LL_SWPMI_IER_SRIE            SWPMI_IER_SRIE
00111 #define LL_SWPMI_IER_TCIE            SWPMI_IER_TCIE
00112 #define LL_SWPMI_IER_TIE             SWPMI_IER_TIE
00113 #define LL_SWPMI_IER_RIE             SWPMI_IER_RIE
00114 #define LL_SWPMI_IER_TXUNRIE         SWPMI_IER_TXUNRIE
00115 #define LL_SWPMI_IER_RXOVRIE         SWPMI_IER_RXOVRIE
00116 #define LL_SWPMI_IER_RXBERIE         SWPMI_IER_RXBERIE
00117 #define LL_SWPMI_IER_TXBEIE          SWPMI_IER_TXBEIE
00118 #define LL_SWPMI_IER_RXBFIE          SWPMI_IER_RXBFIE
00119 /**
00120   * @}
00121   */
00122 
00123 /** @defgroup SWPMI_LL_EC_SW_BUFFER_RX SW BUFFER RX
00124   * @{
00125   */
00126 #define LL_SWPMI_SW_BUFFER_RX_SINGLE ((uint32_t)0x00000000) /* Single software buffer mode for reception */
00127 #define LL_SWPMI_SW_BUFFER_RX_MULTI  SWPMI_CR_RXMODE        /* Multi software buffermode for reception */
00128 /**
00129   * @}
00130   */
00131 
00132 /** @defgroup SWPMI_LL_EC_SW_BUFFER_TX SW BUFFER TX
00133   * @{
00134   */
00135 #define LL_SWPMI_SW_BUFFER_TX_SINGLE ((uint32_t)0x00000000) /* Single software buffer mode for transmission */
00136 #define LL_SWPMI_SW_BUFFER_TX_MULTI  SWPMI_CR_TXMODE        /* Multi software buffermode for transmission */
00137 /**
00138   * @}
00139   */
00140 
00141 /** @defgroup SWPMI_LL_EC_VOLTAGE_CLASS VOLTAGE CLASS
00142   * @{
00143   */
00144 #define LL_SWPMI_VOLTAGE_CLASS_C     ((uint32_t)0x00000000) /* SWPMI_IO uses directly VDD voltage to operate in class C */
00145 #define LL_SWPMI_VOLTAGE_CLASS_B     SWPMI_OR_CLASS         /* SWPMI_IO uses an internal voltage regulator to operate in class B */
00146 /**
00147   * @}
00148   */
00149 
00150 /** @defgroup SWPMI_LL_EC_DMA_REG_DATA DMA register data
00151   * @{
00152   */
00153 #define LL_SWPMI_DMA_REG_DATA_TRANSMIT     (uint32_t)0  /*!< Get address of data register used for transmission */
00154 #define LL_SWPMI_DMA_REG_DATA_RECEIVE      (uint32_t)1  /*!< Get address of data register used for reception */
00155 /**
00156   * @}
00157   */
00158 
00159 /**
00160   * @}
00161   */
00162 
00163 /* Exported macro ------------------------------------------------------------*/
00164 /** @defgroup SWPMI_LL_Exported_Macros SWPMI Exported Macros
00165   * @{
00166   */
00167 
00168 /** @defgroup SWPMI_LL_EM_WRITE_READ Common Write and read registers Macros
00169   * @{
00170   */
00171 
00172 /**
00173   * @brief  Write a value in SWPMI register
00174   * @param  __INSTANCE__ SWPMI Instance
00175   * @param  __REG__ Register to be written
00176   * @param  __VALUE__ Value to be written in the register
00177   * @retval None
00178   */
00179 #define LL_SWPMI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00180 
00181 /**
00182   * @brief  Read a value in SWPMI register
00183   * @param  __INSTANCE__ SWPMI Instance
00184   * @param  __REG__ Register to be read
00185   * @retval Register value
00186   */
00187 #define LL_SWPMI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00188 /**
00189   * @}
00190   */
00191 
00192 /** @defgroup SWPMI_LL_EM_BitRate Bit rate calculation helper Macros
00193   * @{
00194   */
00195 
00196 /**
00197   * @brief  Helper macro to calculate bit rate value to set in BRR register (LL_SWPMI_SetBitRatePrescaler function)
00198   * @note ex: __LL_SWPMI_CALC_BITRATE_PRESCALER(2000000, 80000000);
00199   * @param  __FSWP__ Within the following range: from 100 kbit/s up to 2Mbit/s (in bit/s)
00200   * @param  __FSWPCLK__ PCLK or HSI frequency (in hz)
00201   * @retval Bitrate prescaler (BRR register)
00202   */
00203 #define __LL_SWPMI_CALC_BITRATE_PRESCALER(__FSWP__, __FSWPCLK__)   ((uint32_t)(((__FSWPCLK__) / ((__FSWP__) * 4)) - 1))
00204 
00205 /**
00206   * @}
00207   */
00208 
00209 /**
00210   * @}
00211   */
00212 
00213 /* Exported functions --------------------------------------------------------*/
00214 /** @defgroup SWPMI_LL_Exported_Functions SWPMI Exported Functions
00215   * @{
00216   */
00217 
00218 /** @defgroup SWPMI_LL_EF_Configuration Configuration
00219   * @{
00220   */
00221 
00222 /**
00223   * @brief  Set Reception buffering mode
00224   * @note If Multi software buffer mode is chosen, RXDMA bits must also be set.
00225   * @rmtoll CR           RXMODE        LL_SWPMI_SetReceptionMode
00226   * @param  SWPMIx SWPMI Instance
00227   * @param  Mode This parameter can be one of the following values:
00228   *         @arg @ref LL_SWPMI_SW_BUFFER_RX_SINGLE
00229   *         @arg @ref LL_SWPMI_SW_BUFFER_RX_MULTI
00230   * @retval None
00231   */
00232 __STATIC_INLINE void LL_SWPMI_SetReceptionMode(SWPMI_TypeDef *SWPMIx, uint32_t Mode)
00233 {
00234   MODIFY_REG(SWPMIx->CR, SWPMI_CR_RXMODE, Mode);
00235 }
00236 
00237 /**
00238   * @brief  Get Reception buffering mode
00239   * @rmtoll CR           RXMODE        LL_SWPMI_GetReceptionMode
00240   * @param  SWPMIx SWPMI Instance
00241   * @retval Returned value can be one of the following values:
00242   *         @arg @ref LL_SWPMI_SW_BUFFER_RX_SINGLE
00243   *         @arg @ref LL_SWPMI_SW_BUFFER_RX_MULTI
00244   */
00245 __STATIC_INLINE uint32_t LL_SWPMI_GetReceptionMode(SWPMI_TypeDef *SWPMIx)
00246 {
00247   return (uint32_t)(READ_BIT(SWPMIx->CR, SWPMI_CR_RXMODE));
00248 }
00249 
00250 /**
00251   * @brief  Set Transmission buffering mode
00252   * @note If Multi software buffer mode is chosen, TXDMA bits must also be set.
00253   * @rmtoll CR           TXMODE        LL_SWPMI_SetTransmissionMode
00254   * @param  SWPMIx SWPMI Instance
00255   * @param  Mode This parameter can be one of the following values:
00256   *         @arg @ref LL_SWPMI_SW_BUFFER_TX_SINGLE
00257   *         @arg @ref LL_SWPMI_SW_BUFFER_TX_MULTI
00258   * @retval None
00259   */
00260 __STATIC_INLINE void LL_SWPMI_SetTransmissionMode(SWPMI_TypeDef *SWPMIx, uint32_t Mode)
00261 {
00262   MODIFY_REG(SWPMIx->CR, SWPMI_CR_TXMODE, Mode);
00263 }
00264 
00265 /**
00266   * @brief  Get Transmission buffering mode
00267   * @rmtoll CR           TXMODE        LL_SWPMI_GetTransmissionMode
00268   * @param  SWPMIx SWPMI Instance
00269   * @retval Returned value can be one of the following values:
00270   *         @arg @ref LL_SWPMI_SW_BUFFER_TX_SINGLE
00271   *         @arg @ref LL_SWPMI_SW_BUFFER_TX_MULTI
00272   */
00273 __STATIC_INLINE uint32_t LL_SWPMI_GetTransmissionMode(SWPMI_TypeDef *SWPMIx)
00274 {
00275   return (uint32_t)(READ_BIT(SWPMIx->CR, SWPMI_CR_TXMODE));
00276 }
00277 
00278 /**
00279   * @brief  Enable Loopback mode
00280   * @rmtoll CR           LPBK          LL_SWPMI_EnableLoopback
00281   * @param  SWPMIx SWPMI Instance
00282   * @retval None
00283   */
00284 __STATIC_INLINE void LL_SWPMI_EnableLoopback(SWPMI_TypeDef *SWPMIx)
00285 {
00286   SET_BIT(SWPMIx->CR, SWPMI_CR_LPBK);
00287 }
00288 
00289 /**
00290   * @brief  Disable Loopback mode
00291   * @rmtoll CR           LPBK          LL_SWPMI_DisableLoopback
00292   * @param  SWPMIx SWPMI Instance
00293   * @retval None
00294   */
00295 __STATIC_INLINE void LL_SWPMI_DisableLoopback(SWPMI_TypeDef *SWPMIx)
00296 {
00297   CLEAR_BIT(SWPMIx->CR, SWPMI_CR_LPBK);
00298 }
00299 
00300 /**
00301   * @brief  Activate Single wire protocol bus (SUSPENDED or ACTIVATED state)
00302   * @note SWP bus stays in the ACTIVATED state as long as there is a communication
00303   * with the slave, either in transmission or in reception. The SWP bus switches back
00304   * to the SUSPENDED state as soon as there is no more transmission or reception
00305   * activity, after 7 idle bits.
00306   * @rmtoll CR           SWPACT        LL_SWPMI_Activate
00307   * @param  SWPMIx SWPMI Instance
00308   * @retval None
00309   */
00310 __STATIC_INLINE void LL_SWPMI_Activate(SWPMI_TypeDef *SWPMIx)
00311 {
00312   /* In order to activate SWP again, the software must clear DEACT bit*/
00313   CLEAR_BIT(SWPMIx->CR, SWPMI_CR_DEACT);
00314 
00315   /* Set SWACT bit */
00316   SET_BIT(SWPMIx->CR, SWPMI_CR_SWPACT);
00317 }
00318 
00319 /**
00320   * @brief  Deactivate immediately Single wire protocol bus (immediate transition to
00321   * DEACTIVATED state)
00322   * @rmtoll CR           SWPACT        LL_SWPMI_Deactivate
00323   * @param  SWPMIx SWPMI Instance
00324   * @retval None
00325   */
00326 __STATIC_INLINE void LL_SWPMI_Deactivate(SWPMI_TypeDef *SWPMIx)
00327 {
00328   CLEAR_BIT(SWPMIx->CR, SWPMI_CR_SWPACT);
00329 }
00330 
00331 /**
00332   * @brief  Request a deactivation of Single wire protocol bus (request to go in DEACTIVATED
00333   * state if no resume from slave)
00334   * @rmtoll CR           DEACT         LL_SWPMI_RequestDeactivation
00335   * @param  SWPMIx SWPMI Instance
00336   * @retval None
00337   */
00338 __STATIC_INLINE void LL_SWPMI_RequestDeactivation(SWPMI_TypeDef *SWPMIx)
00339 {
00340   SET_BIT(SWPMIx->CR, SWPMI_CR_DEACT);
00341 }
00342 
00343 /**
00344   * @brief  Set Bitrate prescaler SWPMI_freq = SWPMI_clk / (((BitRate) + 1)  * 4)
00345   * @rmtoll BRR          BR            LL_SWPMI_SetBitRatePrescaler
00346   * @param  SWPMIx SWPMI Instance
00347   * @param  Prescaler A number between 0 and 63
00348   * @retval None
00349   */
00350 __STATIC_INLINE void LL_SWPMI_SetBitRatePrescaler(SWPMI_TypeDef *SWPMIx, uint32_t Prescaler)
00351 {
00352   WRITE_REG(SWPMIx->BRR, Prescaler);
00353 }
00354 
00355 /**
00356   * @brief  Get Bitrate prescaler
00357   * @rmtoll BRR          BR            LL_SWPMI_GetBitRatePrescaler
00358   * @param  SWPMIx SWPMI Instance
00359   * @retval A number between 0 and 63
00360   */
00361 __STATIC_INLINE uint32_t LL_SWPMI_GetBitRatePrescaler(SWPMI_TypeDef *SWPMIx)
00362 {
00363   return (uint32_t)(READ_BIT(SWPMIx->BRR, SWPMI_BRR_BR));
00364 }
00365 
00366 /**
00367   * @brief  Set SWP Voltage Class
00368   * @rmtoll OR           CLASS         LL_SWPMI_SetVoltageClass
00369   * @param  SWPMIx SWPMI Instance
00370   * @param  Class This parameter can be one of the following values:
00371   *         @arg @ref LL_SWPMI_VOLTAGE_CLASS_C
00372   *         @arg @ref LL_SWPMI_VOLTAGE_CLASS_B
00373   * @retval None
00374   */
00375 __STATIC_INLINE void LL_SWPMI_SetVoltageClass(SWPMI_TypeDef *SWPMIx, uint32_t Class)
00376 {
00377   MODIFY_REG(SWPMIx->OR, SWPMI_OR_CLASS, Class);
00378 }
00379 
00380 /**
00381   * @brief  Get SWP Voltage Class
00382   * @rmtoll OR           CLASS         LL_SWPMI_GetVoltageClass
00383   * @param  SWPMIx SWPMI Instance
00384   * @retval Returned value can be one of the following values:
00385   *         @arg @ref LL_SWPMI_VOLTAGE_CLASS_C
00386   *         @arg @ref LL_SWPMI_VOLTAGE_CLASS_B
00387   */
00388 __STATIC_INLINE uint32_t LL_SWPMI_GetVoltageClass(SWPMI_TypeDef *SWPMIx)
00389 {
00390   return (uint32_t)(READ_BIT(SWPMIx->OR, SWPMI_OR_CLASS));
00391 }
00392 
00393 /**
00394   * @}
00395   */
00396 
00397 /** @defgroup SWPMI_LL_EF_FLAG_Management FLAG_Management
00398   * @{
00399   */
00400 
00401 /**
00402   * @brief  Check if the last word of the frame underreception has arrived in SWPMI_RDR.
00403   * @rmtoll ISR          RXBFF         LL_SWPMI_IsActiveFlag_RXBF
00404   * @param  SWPMIx SWPMI Instance
00405   * @retval State of bit (1 or 0).
00406   */
00407 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBF(SWPMI_TypeDef *SWPMIx)
00408 {
00409   return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXBFF) == (SWPMI_ISR_RXBFF));
00410 }
00411 
00412 /**
00413   * @brief  Check if Frame transmission buffer has been emptied
00414   * @rmtoll ISR          TXBEF         LL_SWPMI_IsActiveFlag_TXBE
00415   * @param  SWPMIx SWPMI Instance
00416   * @retval State of bit (1 or 0).
00417   */
00418 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXBE(SWPMI_TypeDef *SWPMIx)
00419 {
00420   return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXBEF) == (SWPMI_ISR_TXBEF));
00421 }
00422 
00423 /**
00424   * @brief  Check if CRC error in reception has been detected
00425   * @rmtoll ISR          RXBERF        LL_SWPMI_IsActiveFlag_RXBER
00426   * @param  SWPMIx SWPMI Instance
00427   * @retval State of bit (1 or 0).
00428   */
00429 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBER(SWPMI_TypeDef *SWPMIx)
00430 {
00431   return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXBERF) == (SWPMI_ISR_RXBERF));
00432 }
00433 
00434 /**
00435   * @brief  Check if Overrun in reception has been detected
00436   * @rmtoll ISR          RXOVRF        LL_SWPMI_IsActiveFlag_RXOVR
00437   * @param  SWPMIx SWPMI Instance
00438   * @retval State of bit (1 or 0).
00439   */
00440 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXOVR(SWPMI_TypeDef *SWPMIx)
00441 {
00442   return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXOVRF) == (SWPMI_ISR_RXOVRF));
00443 }
00444 
00445 /**
00446   * @brief  Check if Underrun error in transmission has been detected
00447   * @rmtoll ISR          TXUNRF        LL_SWPMI_IsActiveFlag_TXUNR
00448   * @param  SWPMIx SWPMI Instance
00449   * @retval State of bit (1 or 0).
00450   */
00451 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXUNR(SWPMI_TypeDef *SWPMIx)
00452 {
00453   return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXUNRF) == (SWPMI_ISR_TXUNRF));
00454 }
00455 
00456 /**
00457   * @brief  Check if Receive data register not empty (it means that Received data is ready
00458   * to be read in the SWPMI_RDR register)
00459   * @rmtoll ISR          RXNE          LL_SWPMI_IsActiveFlag_RXNE
00460   * @param  SWPMIx SWPMI Instance
00461   * @retval State of bit (1 or 0).
00462   */
00463 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXNE(SWPMI_TypeDef *SWPMIx)
00464 {
00465   return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXNE) == (SWPMI_ISR_RXNE));
00466 }
00467 
00468 /**
00469   * @brief  Check if Transmit data register is empty (it means that Data written in transmit
00470   * data register SWPMI_TDR has been transmitted and SWPMI_TDR can be written to again)
00471   * @rmtoll ISR          TXE           LL_SWPMI_IsActiveFlag_TXE
00472   * @param  SWPMIx SWPMI Instance
00473   * @retval State of bit (1 or 0).
00474   */
00475 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXE(SWPMI_TypeDef *SWPMIx)
00476 {
00477   return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXE) == (SWPMI_ISR_TXE));
00478 }
00479 
00480 /**
00481   * @brief  Check if Both transmission and reception are completed and SWP is switched to
00482   * the SUSPENDED state
00483   * @rmtoll ISR          TCF           LL_SWPMI_IsActiveFlag_TC
00484   * @param  SWPMIx SWPMI Instance
00485   * @retval State of bit (1 or 0).
00486   */
00487 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TC(SWPMI_TypeDef *SWPMIx)
00488 {
00489   return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_TCF) == (SWPMI_ISR_TCF));
00490 }
00491 
00492 /**
00493   * @brief  Check if a Resume by slave state has been detected during the SWP bus SUSPENDED
00494   * state
00495   * @rmtoll ISR          SRF           LL_SWPMI_IsActiveFlag_SR
00496   * @param  SWPMIx SWPMI Instance
00497   * @retval State of bit (1 or 0).
00498   */
00499 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SR(SWPMI_TypeDef *SWPMIx)
00500 {
00501   return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_SRF) == (SWPMI_ISR_SRF));
00502 }
00503 
00504 /**
00505   * @brief  Check if SWP bus is in SUSPENDED or DEACTIVATED state
00506   * @rmtoll ISR          SUSP          LL_SWPMI_IsActiveFlag_SUSP
00507   * @param  SWPMIx SWPMI Instance
00508   * @retval State of bit (1 or 0).
00509   */
00510 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SUSP(SWPMI_TypeDef *SWPMIx)
00511 {
00512   return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_SUSP) == (SWPMI_ISR_SUSP));
00513 }
00514 
00515 /**
00516   * @brief  Check if SWP bus is in DEACTIVATED state
00517   * @rmtoll ISR          DEACTF        LL_SWPMI_IsActiveFlag_DEACT
00518   * @param  SWPMIx SWPMI Instance
00519   * @retval State of bit (1 or 0).
00520   */
00521 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_DEACT(SWPMI_TypeDef *SWPMIx)
00522 {
00523   return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_DEACTF) == (SWPMI_ISR_DEACTF));
00524 }
00525 
00526 /**
00527   * @brief  Clear receive buffer full flag
00528   * @rmtoll ICR          CRXBFF        LL_SWPMI_ClearFlag_RXBF
00529   * @param  SWPMIx SWPMI Instance
00530   * @retval None
00531   */
00532 __STATIC_INLINE void LL_SWPMI_ClearFlag_RXBF(SWPMI_TypeDef *SWPMIx)
00533 {
00534   WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRXBFF);
00535 }
00536 
00537 /**
00538   * @brief  Clear transmit buffer empty flag
00539   * @rmtoll ICR          CTXBEF        LL_SWPMI_ClearFlag_TXBE
00540   * @param  SWPMIx SWPMI Instance
00541   * @retval None
00542   */
00543 __STATIC_INLINE void LL_SWPMI_ClearFlag_TXBE(SWPMI_TypeDef *SWPMIx)
00544 {
00545   WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CTXBEF);
00546 }
00547 
00548 /**
00549   * @brief  Clear receive CRC error flag
00550   * @rmtoll ICR          CRXBERF       LL_SWPMI_ClearFlag_RXBER
00551   * @param  SWPMIx SWPMI Instance
00552   * @retval None
00553   */
00554 __STATIC_INLINE void LL_SWPMI_ClearFlag_RXBER(SWPMI_TypeDef *SWPMIx)
00555 {
00556   WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRXBERF);
00557 }
00558 
00559 /**
00560   * @brief  Clear receive overrun error flag
00561   * @rmtoll ICR          CRXOVRF       LL_SWPMI_ClearFlag_RXOVR
00562   * @param  SWPMIx SWPMI Instance
00563   * @retval None
00564   */
00565 __STATIC_INLINE void LL_SWPMI_ClearFlag_RXOVR(SWPMI_TypeDef *SWPMIx)
00566 {
00567   WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRXOVRF);
00568 }
00569 
00570 /**
00571   * @brief  Clear transmit underrun error flag
00572   * @rmtoll ICR          CTXUNRF       LL_SWPMI_ClearFlag_TXUNR
00573   * @param  SWPMIx SWPMI Instance
00574   * @retval None
00575   */
00576 __STATIC_INLINE void LL_SWPMI_ClearFlag_TXUNR(SWPMI_TypeDef *SWPMIx)
00577 {
00578   WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CTXUNRF);
00579 }
00580 
00581 /**
00582   * @brief  Clear transfer complete flag
00583   * @rmtoll ICR          CTCF          LL_SWPMI_ClearFlag_TC
00584   * @param  SWPMIx SWPMI Instance
00585   * @retval None
00586   */
00587 __STATIC_INLINE void LL_SWPMI_ClearFlag_TC(SWPMI_TypeDef *SWPMIx)
00588 {
00589   WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CTCF);
00590 }
00591 
00592 /**
00593   * @brief  Clear slave resume flag
00594   * @rmtoll ICR          CSRF          LL_SWPMI_ClearFlag_SR
00595   * @param  SWPMIx SWPMI Instance
00596   * @retval None
00597   */
00598 __STATIC_INLINE void LL_SWPMI_ClearFlag_SR(SWPMI_TypeDef *SWPMIx)
00599 {
00600   WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CSRF);
00601 }
00602 
00603 /**
00604   * @}
00605   */
00606 
00607 /** @defgroup SWPMI_LL_EF_IT_Management IT_Management
00608   * @{
00609   */
00610 
00611 /**
00612   * @brief  Enable Slave resume interrupt
00613   * @rmtoll IER          SRIE          LL_SWPMI_EnableIT_SR
00614   * @param  SWPMIx SWPMI Instance
00615   * @retval None
00616   */
00617 __STATIC_INLINE void LL_SWPMI_EnableIT_SR(SWPMI_TypeDef *SWPMIx)
00618 {
00619   SET_BIT(SWPMIx->IER, SWPMI_IER_SRIE);
00620 }
00621 
00622 /**
00623   * @brief  Enable Transmit complete interrupt
00624   * @rmtoll IER          TCIE          LL_SWPMI_EnableIT_TC
00625   * @param  SWPMIx SWPMI Instance
00626   * @retval None
00627   */
00628 __STATIC_INLINE void LL_SWPMI_EnableIT_TC(SWPMI_TypeDef *SWPMIx)
00629 {
00630   SET_BIT(SWPMIx->IER, SWPMI_IER_TCIE);
00631 }
00632 
00633 /**
00634   * @brief  Enable Transmit interrupt
00635   * @rmtoll IER          TIE           LL_SWPMI_EnableIT_TX
00636   * @param  SWPMIx SWPMI Instance
00637   * @retval None
00638   */
00639 __STATIC_INLINE void LL_SWPMI_EnableIT_TX(SWPMI_TypeDef *SWPMIx)
00640 {
00641   SET_BIT(SWPMIx->IER, SWPMI_IER_TIE);
00642 }
00643 
00644 /**
00645   * @brief  Enable Receive interrupt
00646   * @rmtoll IER          RIE           LL_SWPMI_EnableIT_RX
00647   * @param  SWPMIx SWPMI Instance
00648   * @retval None
00649   */
00650 __STATIC_INLINE void LL_SWPMI_EnableIT_RX(SWPMI_TypeDef *SWPMIx)
00651 {
00652   SET_BIT(SWPMIx->IER, SWPMI_IER_RIE);
00653 }
00654 
00655 /**
00656   * @brief  Enable Transmit underrun error interrupt
00657   * @rmtoll IER          TXUNRIE       LL_SWPMI_EnableIT_TXUNR
00658   * @param  SWPMIx SWPMI Instance
00659   * @retval None
00660   */
00661 __STATIC_INLINE void LL_SWPMI_EnableIT_TXUNR(SWPMI_TypeDef *SWPMIx)
00662 {
00663   SET_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE);
00664 }
00665 
00666 /**
00667   * @brief  Enable Receive overrun error interrupt
00668   * @rmtoll IER          RXOVRIE       LL_SWPMI_EnableIT_RXOVR
00669   * @param  SWPMIx SWPMI Instance
00670   * @retval None
00671   */
00672 __STATIC_INLINE void LL_SWPMI_EnableIT_RXOVR(SWPMI_TypeDef *SWPMIx)
00673 {
00674   SET_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE);
00675 }
00676 
00677 /**
00678   * @brief  Enable Receive CRC error interrupt
00679   * @rmtoll IER          RXBERIE       LL_SWPMI_EnableIT_RXBER
00680   * @param  SWPMIx SWPMI Instance
00681   * @retval None
00682   */
00683 __STATIC_INLINE void LL_SWPMI_EnableIT_RXBER(SWPMI_TypeDef *SWPMIx)
00684 {
00685   SET_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE);
00686 }
00687 
00688 /**
00689   * @brief  Enable Transmit buffer empty interrupt
00690   * @rmtoll IER          TXBEIE        LL_SWPMI_EnableIT_TXBE
00691   * @param  SWPMIx SWPMI Instance
00692   * @retval None
00693   */
00694 __STATIC_INLINE void LL_SWPMI_EnableIT_TXBE(SWPMI_TypeDef *SWPMIx)
00695 {
00696   SET_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE);
00697 }
00698 
00699 /**
00700   * @brief  Enable Receive buffer full interrupt
00701   * @rmtoll IER          RXBFIE        LL_SWPMI_EnableIT_RXBF
00702   * @param  SWPMIx SWPMI Instance
00703   * @retval None
00704   */
00705 __STATIC_INLINE void LL_SWPMI_EnableIT_RXBF(SWPMI_TypeDef *SWPMIx)
00706 {
00707   SET_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE);
00708 }
00709 
00710 /**
00711   * @brief  Disable Slave resume interrupt
00712   * @rmtoll IER          SRIE          LL_SWPMI_DisableIT_SR
00713   * @param  SWPMIx SWPMI Instance
00714   * @retval None
00715   */
00716 __STATIC_INLINE void LL_SWPMI_DisableIT_SR(SWPMI_TypeDef *SWPMIx)
00717 {
00718   CLEAR_BIT(SWPMIx->IER, SWPMI_IER_SRIE);
00719 }
00720 
00721 /**
00722   * @brief  Disable Transmit complete interrupt
00723   * @rmtoll IER          TCIE          LL_SWPMI_DisableIT_TC
00724   * @param  SWPMIx SWPMI Instance
00725   * @retval None
00726   */
00727 __STATIC_INLINE void LL_SWPMI_DisableIT_TC(SWPMI_TypeDef *SWPMIx)
00728 {
00729   CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TCIE);
00730 }
00731 
00732 /**
00733   * @brief  Disable Transmit interrupt
00734   * @rmtoll IER          TIE           LL_SWPMI_DisableIT_TX
00735   * @param  SWPMIx SWPMI Instance
00736   * @retval None
00737   */
00738 __STATIC_INLINE void LL_SWPMI_DisableIT_TX(SWPMI_TypeDef *SWPMIx)
00739 {
00740   CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TIE);
00741 }
00742 
00743 /**
00744   * @brief  Disable Receive interrupt
00745   * @rmtoll IER          RIE           LL_SWPMI_DisableIT_RX
00746   * @param  SWPMIx SWPMI Instance
00747   * @retval None
00748   */
00749 __STATIC_INLINE void LL_SWPMI_DisableIT_RX(SWPMI_TypeDef *SWPMIx)
00750 {
00751   CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RIE);
00752 }
00753 
00754 /**
00755   * @brief  Disable Transmit underrun error interrupt
00756   * @rmtoll IER          TXUNRIE       LL_SWPMI_DisableIT_TXUNR
00757   * @param  SWPMIx SWPMI Instance
00758   * @retval None
00759   */
00760 __STATIC_INLINE void LL_SWPMI_DisableIT_TXUNR(SWPMI_TypeDef *SWPMIx)
00761 {
00762   CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE);
00763 }
00764 
00765 /**
00766   * @brief  Disable Receive overrun error interrupt
00767   * @rmtoll IER          RXOVRIE       LL_SWPMI_DisableIT_RXOVR
00768   * @param  SWPMIx SWPMI Instance
00769   * @retval None
00770   */
00771 __STATIC_INLINE void LL_SWPMI_DisableIT_RXOVR(SWPMI_TypeDef *SWPMIx)
00772 {
00773   CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE);
00774 }
00775 
00776 /**
00777   * @brief  Disable Receive CRC error interrupt
00778   * @rmtoll IER          RXBERIE       LL_SWPMI_DisableIT_RXBER
00779   * @param  SWPMIx SWPMI Instance
00780   * @retval None
00781   */
00782 __STATIC_INLINE void LL_SWPMI_DisableIT_RXBER(SWPMI_TypeDef *SWPMIx)
00783 {
00784   CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE);
00785 }
00786 
00787 /**
00788   * @brief  Disable Transmit buffer empty interrupt
00789   * @rmtoll IER          TXBEIE        LL_SWPMI_DisableIT_TXBE
00790   * @param  SWPMIx SWPMI Instance
00791   * @retval None
00792   */
00793 __STATIC_INLINE void LL_SWPMI_DisableIT_TXBE(SWPMI_TypeDef *SWPMIx)
00794 {
00795   CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE);
00796 }
00797 
00798 /**
00799   * @brief  Disable Receive buffer full interrupt
00800   * @rmtoll IER          RXBFIE        LL_SWPMI_DisableIT_RXBF
00801   * @param  SWPMIx SWPMI Instance
00802   * @retval None
00803   */
00804 __STATIC_INLINE void LL_SWPMI_DisableIT_RXBF(SWPMI_TypeDef *SWPMIx)
00805 {
00806   CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE);
00807 }
00808 
00809 /**
00810   * @brief  Check if Slave resume interrupt is enabled
00811   * @rmtoll IER          SRIE          LL_SWPMI_IsEnabledIT_SR
00812   * @param  SWPMIx SWPMI Instance
00813   * @retval State of bit (1 or 0).
00814   */
00815 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_SR(SWPMI_TypeDef *SWPMIx)
00816 {
00817   return (READ_BIT(SWPMIx->IER, SWPMI_IER_SRIE) == (SWPMI_IER_SRIE));
00818 }
00819 
00820 /**
00821   * @brief  Check if Transmit complete interrupt is enabled
00822   * @rmtoll IER          TCIE          LL_SWPMI_IsEnabledIT_TC
00823   * @param  SWPMIx SWPMI Instance
00824   * @retval State of bit (1 or 0).
00825   */
00826 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TC(SWPMI_TypeDef *SWPMIx)
00827 {
00828   return (READ_BIT(SWPMIx->IER, SWPMI_IER_TCIE) == (SWPMI_IER_TCIE));
00829 }
00830 
00831 /**
00832   * @brief  Check if Transmit interrupt is enabled
00833   * @rmtoll IER          TIE           LL_SWPMI_IsEnabledIT_TX
00834   * @param  SWPMIx SWPMI Instance
00835   * @retval State of bit (1 or 0).
00836   */
00837 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TX(SWPMI_TypeDef *SWPMIx)
00838 {
00839   return (READ_BIT(SWPMIx->IER, SWPMI_IER_TIE) == (SWPMI_IER_TIE));
00840 }
00841 
00842 /**
00843   * @brief  Check if Receive interrupt is enabled
00844   * @rmtoll IER          RIE           LL_SWPMI_IsEnabledIT_RX
00845   * @param  SWPMIx SWPMI Instance
00846   * @retval State of bit (1 or 0).
00847   */
00848 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RX(SWPMI_TypeDef *SWPMIx)
00849 {
00850   return (READ_BIT(SWPMIx->IER, SWPMI_IER_RIE) == (SWPMI_IER_RIE));
00851 }
00852 
00853 /**
00854   * @brief  Check if Transmit underrun error interrupt is enabled
00855   * @rmtoll IER          TXUNRIE       LL_SWPMI_IsEnabledIT_TXUNR
00856   * @param  SWPMIx SWPMI Instance
00857   * @retval State of bit (1 or 0).
00858   */
00859 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXUNR(SWPMI_TypeDef *SWPMIx)
00860 {
00861   return (READ_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE) == (SWPMI_IER_TXUNRIE));
00862 }
00863 
00864 /**
00865   * @brief  Check if Receive overrun error interrupt is enabled
00866   * @rmtoll IER          RXOVRIE       LL_SWPMI_IsEnabledIT_RXOVR
00867   * @param  SWPMIx SWPMI Instance
00868   * @retval State of bit (1 or 0).
00869   */
00870 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXOVR(SWPMI_TypeDef *SWPMIx)
00871 {
00872   return (READ_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE) == (SWPMI_IER_RXOVRIE));
00873 }
00874 
00875 /**
00876   * @brief  Check if Receive CRC error interrupt is enabled
00877   * @rmtoll IER          RXBERIE       LL_SWPMI_IsEnabledIT_RXBER
00878   * @param  SWPMIx SWPMI Instance
00879   * @retval State of bit (1 or 0).
00880   */
00881 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBER(SWPMI_TypeDef *SWPMIx)
00882 {
00883   return (READ_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE) == (SWPMI_IER_RXBERIE));
00884 }
00885 
00886 /**
00887   * @brief  Check if Transmit buffer empty interrupt is enabled
00888   * @rmtoll IER          TXBEIE        LL_SWPMI_IsEnabledIT_TXBE
00889   * @param  SWPMIx SWPMI Instance
00890   * @retval State of bit (1 or 0).
00891   */
00892 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXBE(SWPMI_TypeDef *SWPMIx)
00893 {
00894   return (READ_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE) == (SWPMI_IER_TXBEIE));
00895 }
00896 
00897 /**
00898   * @brief  Check if Receive buffer full interrupt is enabled
00899   * @rmtoll IER          RXBFIE        LL_SWPMI_IsEnabledIT_RXBF
00900   * @param  SWPMIx SWPMI Instance
00901   * @retval State of bit (1 or 0).
00902   */
00903 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBF(SWPMI_TypeDef *SWPMIx)
00904 {
00905   return (READ_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE) == (SWPMI_IER_RXBFIE));
00906 }
00907 
00908 /**
00909   * @}
00910   */
00911 
00912 /** @defgroup SWPMI_LL_EF_DMA_Management DMA_Management
00913   * @{
00914   */
00915 
00916 /**
00917   * @brief  Enable DMA mode for reception
00918   * @rmtoll CR           RXDMA         LL_SWPMI_EnableDMAReq_RX
00919   * @param  SWPMIx SWPMI Instance
00920   * @retval None
00921   */
00922 __STATIC_INLINE void LL_SWPMI_EnableDMAReq_RX(SWPMI_TypeDef *SWPMIx)
00923 {
00924   SET_BIT(SWPMIx->CR, SWPMI_CR_RXDMA);
00925 }
00926 
00927 /**
00928   * @brief  Disable DMA mode for reception
00929   * @rmtoll CR           RXDMA         LL_SWPMI_DisableDMAReq_RX
00930   * @param  SWPMIx SWPMI Instance
00931   * @retval None
00932   */
00933 __STATIC_INLINE void LL_SWPMI_DisableDMAReq_RX(SWPMI_TypeDef *SWPMIx)
00934 {
00935   CLEAR_BIT(SWPMIx->CR, SWPMI_CR_RXDMA);
00936 }
00937 
00938 /**
00939   * @brief  Check if DMA mode for reception is enabled
00940   * @rmtoll CR           RXDMA         LL_SWPMI_IsEnabledDMAReq_RX
00941   * @param  SWPMIx SWPMI Instance
00942   * @retval State of bit (1 or 0).
00943   */
00944 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_RX(SWPMI_TypeDef *SWPMIx)
00945 {
00946   return (READ_BIT(SWPMIx->CR, SWPMI_CR_RXDMA) == (SWPMI_CR_RXDMA));
00947 }
00948 
00949 /**
00950   * @brief  Enable DMA mode for transmission
00951   * @rmtoll CR           TXDMA         LL_SWPMI_EnableDMAReq_TX
00952   * @param  SWPMIx SWPMI Instance
00953   * @retval None
00954   */
00955 __STATIC_INLINE void LL_SWPMI_EnableDMAReq_TX(SWPMI_TypeDef *SWPMIx)
00956 {
00957   SET_BIT(SWPMIx->CR, SWPMI_CR_TXDMA);
00958 }
00959 
00960 /**
00961   * @brief  Disable DMA mode for transmission
00962   * @rmtoll CR           TXDMA         LL_SWPMI_DisableDMAReq_TX
00963   * @param  SWPMIx SWPMI Instance
00964   * @retval None
00965   */
00966 __STATIC_INLINE void LL_SWPMI_DisableDMAReq_TX(SWPMI_TypeDef *SWPMIx)
00967 {
00968   CLEAR_BIT(SWPMIx->CR, SWPMI_CR_TXDMA);
00969 }
00970 
00971 /**
00972   * @brief  Check if DMA mode for transmission is enabled
00973   * @rmtoll CR           TXDMA         LL_SWPMI_IsEnabledDMAReq_TX
00974   * @param  SWPMIx SWPMI Instance
00975   * @retval State of bit (1 or 0).
00976   */
00977 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_TX(SWPMI_TypeDef *SWPMIx)
00978 {
00979   return (READ_BIT(SWPMIx->CR, SWPMI_CR_TXDMA) == (SWPMI_CR_TXDMA));
00980 }
00981 
00982 /**
00983   * @brief  Get the data register address used for DMA transfer
00984   * @rmtoll TDR          TD            LL_SWPMI_DMA_GetRegAddr\n
00985   *         RDR          RD            LL_SWPMI_DMA_GetRegAddr
00986   * @param  SWPMIx SWPMI Instance
00987   * @param  Direction This parameter can be one of the following values:
00988   *         @arg @ref LL_SWPMI_DMA_REG_DATA_TRANSMIT
00989   *         @arg @ref LL_SWPMI_DMA_REG_DATA_RECEIVE
00990   * @retval Address of data register
00991   */
00992 __STATIC_INLINE uint32_t LL_SWPMI_DMA_GetRegAddr(SWPMI_TypeDef * SWPMIx, uint32_t Direction)
00993 {
00994   register uint32_t data_reg_addr = 0;
00995 
00996   if (Direction == LL_SWPMI_DMA_REG_DATA_TRANSMIT)
00997   {
00998     /* return address of TDR register */
00999     data_reg_addr = (uint32_t)&(SWPMIx->TDR);
01000   }
01001   else
01002   {
01003     /* return address of RDR register */
01004     data_reg_addr = (uint32_t)&(SWPMIx->RDR);
01005   }
01006 
01007   return data_reg_addr;
01008 }
01009 
01010 /**
01011   * @}
01012   */
01013 
01014 /** @defgroup SWPMI_LL_EF_Data_Management Data_Management
01015   * @{
01016   */
01017 
01018 /**
01019   * @brief  Retrieve number of data bytes present in payload of received frame
01020   * @rmtoll RFL          RFL           LL_SWPMI_GetReceiveFrameLength
01021   * @param  SWPMIx SWPMI Instance
01022   * @retval Between 0 and 0x1F
01023   */
01024 __STATIC_INLINE uint32_t LL_SWPMI_GetReceiveFrameLength(SWPMI_TypeDef *SWPMIx)
01025 {
01026   return (uint32_t)(READ_BIT(SWPMIx->RFL, SWPMI_RFL_RFL));
01027 }
01028 
01029 /**
01030   * @brief  Transmit Data Register
01031   * @rmtoll TDR          TD            LL_SWPMI_TransmitData32
01032   * @param  SWPMIx SWPMI Instance
01033   * @param  TxData Between 0 and 0xFFFFFFFF
01034   * @retval None
01035   */
01036 __STATIC_INLINE void LL_SWPMI_TransmitData32(SWPMI_TypeDef *SWPMIx, uint32_t TxData)
01037 {
01038   WRITE_REG(SWPMIx->TDR, TxData);
01039 }
01040 
01041 /**
01042   * @brief  Receive Data Register
01043   * @rmtoll RDR          RD            LL_SWPMI_ReceiveData32
01044   * @param  SWPMIx SWPMI Instance
01045   * @retval Between 0 and 0xFFFFFFFF
01046   */
01047 __STATIC_INLINE uint32_t LL_SWPMI_ReceiveData32(SWPMI_TypeDef *SWPMIx)
01048 {
01049   return (uint32_t)(READ_BIT(SWPMIx->RDR, SWPMI_RDR_RD));
01050 }
01051 
01052 /**
01053   * @brief  Enable SWP Transceiver Bypass
01054   * @note The external interface for SWPMI is SWPMI_IO
01055   *       (SWPMI_RX, SWPMI_TX and SWPMI_SUSPEND signals are not available on GPIOs)
01056   * @rmtoll OR           TBYP          LL_SWPMI_EnableTXBypass
01057   * @param  SWPMIx SWPMI Instance
01058   * @retval None
01059   */
01060 __STATIC_INLINE void LL_SWPMI_EnableTXBypass(SWPMI_TypeDef *SWPMIx)
01061 {
01062   CLEAR_BIT(SWPMIx->OR, SWPMI_OR_TBYP);
01063 }
01064 
01065 /**
01066   * @brief  Disable SWP Transceiver Bypass
01067   * @note SWPMI_RX, SWPMI_TX and SWPMI_SUSPEND signals are available as alternate
01068   *       function on GPIOs. This configuration is selected to connect an external transceiver
01069   * @rmtoll OR           TBYP          LL_SWPMI_DisableTXBypass
01070   * @param  SWPMIx SWPMI Instance
01071   * @retval None
01072   */
01073 __STATIC_INLINE void LL_SWPMI_DisableTXBypass(SWPMI_TypeDef *SWPMIx)
01074 {
01075   SET_BIT(SWPMIx->OR, SWPMI_OR_TBYP);
01076 }
01077 
01078 /**
01079   * @}
01080   */
01081 
01082 
01083 /**
01084   * @}
01085   */
01086 
01087 /**
01088   * @}
01089   */
01090 
01091 #endif /* defined (SWPMI1) */
01092 
01093 /**
01094   * @}
01095   */
01096 
01097 #ifdef __cplusplus
01098 }
01099 #endif
01100 
01101 #endif /* __STM32L4xx_LL_SWPMI_H */
01102 
01103 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
01104