Eric Lewiston
Hal Drivers for L4
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stm32l4xx_hal_pwr_ex.h
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_pwr_ex.h 00004 * @author MCD Application Team 00005 * @version V1.1.0 00006 * @date 16-September-2015 00007 * @brief Header file of PWR HAL Extended module. 00008 ****************************************************************************** 00009 * @attention 00010 * 00011 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> 00012 * 00013 * Redistribution and use in source and binary forms, with or without modification, 00014 * are permitted provided that the following conditions are met: 00015 * 1. Redistributions of source code must retain the above copyright notice, 00016 * this list of conditions and the following disclaimer. 00017 * 2. Redistributions in binary form must reproduce the above copyright notice, 00018 * this list of conditions and the following disclaimer in the documentation 00019 * and/or other materials provided with the distribution. 00020 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00021 * may be used to endorse or promote products derived from this software 00022 * without specific prior written permission. 00023 * 00024 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00025 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00026 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00027 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00028 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00029 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00030 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00031 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00032 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00033 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00034 * 00035 ****************************************************************************** 00036 */ 00037 00038 /* Define to prevent recursive inclusion -------------------------------------*/ 00039 #ifndef __STM32L4xx_HAL_PWR_EX_H 00040 #define __STM32L4xx_HAL_PWR_EX_H 00041 00042 #ifdef __cplusplus 00043 extern "C" { 00044 #endif 00045 00046 /* Includes ------------------------------------------------------------------*/ 00047 #include "stm32l4xx_hal_def.h" 00048 00049 /** @addtogroup STM32L4xx_HAL_Driver 00050 * @{ 00051 */ 00052 00053 /** @addtogroup PWREx 00054 * @{ 00055 */ 00056 00057 00058 /* Exported types ------------------------------------------------------------*/ 00059 00060 /** @defgroup PWREx_Exported_Types PWR Extended Exported Types 00061 * @{ 00062 */ 00063 00064 00065 /** 00066 * @brief PWR PVM configuration structure definition 00067 */ 00068 typedef struct 00069 { 00070 uint32_t PVMType; /*!< PVMType: Specifies which voltage is monitored and against which threshold. 00071 This parameter can be a value of @ref PWREx_PVM_Type. 00072 @arg PWR_PVM_1: Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported). 00073 @arg PWR_PVM_2: Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device). 00074 @arg PWR_PVM_3: Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V. 00075 @arg PWR_PVM_4: Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V. */ 00076 00077 uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. 00078 This parameter can be a value of @ref PWREx_PVM_Mode. */ 00079 }PWR_PVMTypeDef; 00080 00081 /** 00082 * @} 00083 */ 00084 00085 /* Exported constants --------------------------------------------------------*/ 00086 00087 /** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants 00088 * @{ 00089 */ 00090 00091 /** @defgroup PWREx_WUP_Polarity Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants 00092 * @{ 00093 */ 00094 #define PWR_WUP_POLARITY_SHIFT 0x05 /*!< Internal constant used to retrieve wakeup pin polariry */ 00095 /** 00096 * @} 00097 */ 00098 00099 00100 /** @defgroup PWREx_WakeUp_Pins PWR wake-up pins 00101 * @{ 00102 */ 00103 #define PWR_WAKEUP_PIN1 PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */ 00104 #define PWR_WAKEUP_PIN2 PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */ 00105 #define PWR_WAKEUP_PIN3 PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */ 00106 #define PWR_WAKEUP_PIN4 PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */ 00107 #define PWR_WAKEUP_PIN5 PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */ 00108 #define PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */ 00109 #define PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */ 00110 #define PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */ 00111 #define PWR_WAKEUP_PIN4_HIGH PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */ 00112 #define PWR_WAKEUP_PIN5_HIGH PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */ 00113 #define PWR_WAKEUP_PIN1_LOW (uint32_t)((PWR_CR4_WP1<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1) /*!< Wakeup pin 1 (with low level polarity) */ 00114 #define PWR_WAKEUP_PIN2_LOW (uint32_t)((PWR_CR4_WP2<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2) /*!< Wakeup pin 2 (with low level polarity) */ 00115 #define PWR_WAKEUP_PIN3_LOW (uint32_t)((PWR_CR4_WP3<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3) /*!< Wakeup pin 3 (with low level polarity) */ 00116 #define PWR_WAKEUP_PIN4_LOW (uint32_t)((PWR_CR4_WP4<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4) /*!< Wakeup pin 4 (with low level polarity) */ 00117 #define PWR_WAKEUP_PIN5_LOW (uint32_t)((PWR_CR4_WP5<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5) /*!< Wakeup pin 5 (with low level polarity) */ 00118 /** 00119 * @} 00120 */ 00121 00122 /** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type 00123 * @{ 00124 */ 00125 #if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 00126 #define PWR_PVM_1 PWR_CR2_PVME1 /*!< Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported) */ 00127 #endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ 00128 #define PWR_PVM_2 PWR_CR2_PVME2 /*!< Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device) */ 00129 #define PWR_PVM_3 PWR_CR2_PVME3 /*!< Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V */ 00130 #define PWR_PVM_4 PWR_CR2_PVME4 /*!< Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V */ 00131 /** 00132 * @} 00133 */ 00134 00135 /** @defgroup PWREx_PVM_Mode PWR PVM interrupt and event mode 00136 * @{ 00137 */ 00138 #define PWR_PVM_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */ 00139 #define PWR_PVM_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */ 00140 #define PWR_PVM_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */ 00141 #define PWR_PVM_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ 00142 #define PWR_PVM_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */ 00143 #define PWR_PVM_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */ 00144 #define PWR_PVM_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */ 00145 /** 00146 * @} 00147 */ 00148 00149 00150 00151 /** @defgroup PWREx_Regulator_Voltage_Scale PWR Regulator voltage scale 00152 * @{ 00153 */ 00154 #define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS_0 /*!< Voltage scaling range 1 */ 00155 #define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1 /*!< Voltage scaling range 2 */ 00156 /** 00157 * @} 00158 */ 00159 00160 00161 /** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR battery charging resistor selection 00162 * @{ 00163 */ 00164 #define PWR_BATTERY_CHARGING_RESISTOR_5 ((uint32_t)0x00000000) /*!< VBAT charging through a 5 kOhms resistor */ 00165 #define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR4_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */ 00166 /** 00167 * @} 00168 */ 00169 00170 /** @defgroup PWREx_VBAT_Battery_Charging PWR battery charging 00171 * @{ 00172 */ 00173 #define PWR_BATTERY_CHARGING_DISABLE ((uint32_t)0x00000000) 00174 #define PWR_BATTERY_CHARGING_ENABLE PWR_CR4_VBE 00175 /** 00176 * @} 00177 */ 00178 00179 /** @defgroup PWREx_GPIO_Bit_Number GPIO bit number for I/O setting in standby/shutdown mode 00180 * @{ 00181 */ 00182 #define PWR_GPIO_BIT_0 PWR_PUCRB_PB0 /*!< GPIO port I/O pin 0 */ 00183 #define PWR_GPIO_BIT_1 PWR_PUCRB_PB1 /*!< GPIO port I/O pin 1 */ 00184 #define PWR_GPIO_BIT_2 PWR_PUCRB_PB2 /*!< GPIO port I/O pin 2 */ 00185 #define PWR_GPIO_BIT_3 PWR_PUCRB_PB3 /*!< GPIO port I/O pin 3 */ 00186 #define PWR_GPIO_BIT_4 PWR_PUCRB_PB4 /*!< GPIO port I/O pin 4 */ 00187 #define PWR_GPIO_BIT_5 PWR_PUCRB_PB5 /*!< GPIO port I/O pin 5 */ 00188 #define PWR_GPIO_BIT_6 PWR_PUCRB_PB6 /*!< GPIO port I/O pin 6 */ 00189 #define PWR_GPIO_BIT_7 PWR_PUCRB_PB7 /*!< GPIO port I/O pin 7 */ 00190 #define PWR_GPIO_BIT_8 PWR_PUCRB_PB8 /*!< GPIO port I/O pin 8 */ 00191 #define PWR_GPIO_BIT_9 PWR_PUCRB_PB9 /*!< GPIO port I/O pin 9 */ 00192 #define PWR_GPIO_BIT_10 PWR_PUCRB_PB10 /*!< GPIO port I/O pin 10 */ 00193 #define PWR_GPIO_BIT_11 PWR_PUCRB_PB11 /*!< GPIO port I/O pin 11 */ 00194 #define PWR_GPIO_BIT_12 PWR_PUCRB_PB12 /*!< GPIO port I/O pin 12 */ 00195 #define PWR_GPIO_BIT_13 PWR_PUCRB_PB13 /*!< GPIO port I/O pin 13 */ 00196 #define PWR_GPIO_BIT_14 PWR_PUCRB_PB14 /*!< GPIO port I/O pin 14 */ 00197 #define PWR_GPIO_BIT_15 PWR_PUCRB_PB15 /*!< GPIO port I/O pin15 */ 00198 /** 00199 * @} 00200 */ 00201 00202 /** @defgroup PWREx_GPIO GPIO port 00203 * @{ 00204 */ 00205 #define PWR_GPIO_A 0x00000000 /*!< GPIO port A */ 00206 #define PWR_GPIO_B 0x00000001 /*!< GPIO port B */ 00207 #define PWR_GPIO_C 0x00000002 /*!< GPIO port C */ 00208 #define PWR_GPIO_D 0x00000003 /*!< GPIO port D */ 00209 #define PWR_GPIO_E 0x00000004 /*!< GPIO port E */ 00210 #define PWR_GPIO_F 0x00000005 /*!< GPIO port F */ 00211 #define PWR_GPIO_G 0x00000006 /*!< GPIO port G */ 00212 #define PWR_GPIO_H 0x00000007 /*!< GPIO port H */ 00213 /** 00214 * @} 00215 */ 00216 00217 /** @defgroup PWREx_PVM_EXTI_LINE PWR PVM external interrupts lines 00218 * @{ 00219 */ 00220 #if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 00221 #define PWR_EXTI_LINE_PVM1 ((uint32_t)0x00000008) /*!< External interrupt line 35 Connected to the PVM1 EXTI Line */ 00222 #endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ 00223 00224 #define PWR_EXTI_LINE_PVM2 ((uint32_t)0x00000010) /*!< External interrupt line 36 Connected to the PVM2 EXTI Line */ 00225 #define PWR_EXTI_LINE_PVM3 ((uint32_t)0x00000020) /*!< External interrupt line 37 Connected to the PVM3 EXTI Line */ 00226 #define PWR_EXTI_LINE_PVM4 ((uint32_t)0x00000040) /*!< External interrupt line 38 Connected to the PVM4 EXTI Line */ 00227 /** 00228 * @} 00229 */ 00230 00231 /** @defgroup PWREx_PVM_EVENT_LINE PWR PVM event lines 00232 * @{ 00233 */ 00234 #if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 00235 #define PWR_EVENT_LINE_PVM1 ((uint32_t)0x00000008) /*!< Event line 35 Connected to the PVM1 EXTI Line */ 00236 #endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ 00237 #define PWR_EVENT_LINE_PVM2 ((uint32_t)0x00000010) /*!< Event line 36 Connected to the PVM2 EXTI Line */ 00238 #define PWR_EVENT_LINE_PVM3 ((uint32_t)0x00000020) /*!< Event line 37 Connected to the PVM3 EXTI Line */ 00239 #define PWR_EVENT_LINE_PVM4 ((uint32_t)0x00000040) /*!< Event line 38 Connected to the PVM4 EXTI Line */ 00240 /** 00241 * @} 00242 */ 00243 00244 /** @defgroup PWREx_Flag PWR Status Flags 00245 * Elements values convention: 0000 0000 0XXY YYYYb 00246 * - Y YYYY : Flag position in the XX register (5 bits) 00247 * - XX : Status register (2 bits) 00248 * - 01: SR1 register 00249 * - 10: SR2 register 00250 * The only exception is PWR_FLAG_WU, encompassing all 00251 * wake-up flags and set to PWR_SR1_WUF. 00252 * @{ 00253 */ 00254 #define PWR_FLAG_WUF1 ((uint32_t)0x0020) /*!< Wakeup event on wakeup pin 1 */ 00255 #define PWR_FLAG_WUF2 ((uint32_t)0x0021) /*!< Wakeup event on wakeup pin 2 */ 00256 #define PWR_FLAG_WUF3 ((uint32_t)0x0022) /*!< Wakeup event on wakeup pin 3 */ 00257 #define PWR_FLAG_WUF4 ((uint32_t)0x0023) /*!< Wakeup event on wakeup pin 4 */ 00258 #define PWR_FLAG_WUF5 ((uint32_t)0x0024) /*!< Wakeup event on wakeup pin 5 */ 00259 #define PWR_FLAG_WU PWR_SR1_WUF /*!< Encompass wakeup event on all wakeup pins */ 00260 #define PWR_FLAG_SB ((uint32_t)0x0028) /*!< Standby flag */ 00261 #define PWR_FLAG_WUFI ((uint32_t)0x002F) /*!< Wakeup on internal wakeup line */ 00262 00263 #define PWR_FLAG_REGLPS ((uint32_t)0x0048) /*!< Low-power regulator start flag */ 00264 #define PWR_FLAG_REGLPF ((uint32_t)0x0049) /*!< Low-power regulator flag */ 00265 #define PWR_FLAG_VOSF ((uint32_t)0x004A) /*!< Voltage scaling flag */ 00266 #define PWR_FLAG_PVDO ((uint32_t)0x004B) /*!< Power Voltage Detector output flag */ 00267 #if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 00268 #define PWR_FLAG_PVMO1 ((uint32_t)0x004C) /*!< Power Voltage Monitoring 1 output flag */ 00269 #endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ 00270 #define PWR_FLAG_PVMO2 ((uint32_t)0x004D) /*!< Power Voltage Monitoring 2 output flag */ 00271 #define PWR_FLAG_PVMO3 ((uint32_t)0x004E) /*!< Power Voltage Monitoring 3 output flag */ 00272 #define PWR_FLAG_PVMO4 ((uint32_t)0x004F) /*!< Power Voltage Monitoring 4 output flag */ 00273 /** 00274 * @} 00275 */ 00276 00277 /** 00278 * @} 00279 */ 00280 00281 /* Exported macros -----------------------------------------------------------*/ 00282 /** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros 00283 * @{ 00284 */ 00285 00286 #if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 00287 /** 00288 * @brief Enable the PVM1 Extended Interrupt Line. 00289 * @retval None 00290 */ 00291 #define __HAL_PWR_PVM1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1) 00292 00293 /** 00294 * @brief Disable the PVM1 Extended Interrupt Line. 00295 * @retval None 00296 */ 00297 #define __HAL_PWR_PVM1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1) 00298 00299 /** 00300 * @brief Enable the PVM1 Event Line. 00301 * @retval None 00302 */ 00303 #define __HAL_PWR_PVM1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1) 00304 00305 /** 00306 * @brief Disable the PVM1 Event Line. 00307 * @retval None 00308 */ 00309 #define __HAL_PWR_PVM1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1) 00310 00311 /** 00312 * @brief Enable the PVM1 Extended Interrupt Rising Trigger. 00313 * @retval None 00314 */ 00315 #define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1) 00316 00317 /** 00318 * @brief Disable the PVM1 Extended Interrupt Rising Trigger. 00319 * @retval None 00320 */ 00321 #define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1) 00322 00323 /** 00324 * @brief Enable the PVM1 Extended Interrupt Falling Trigger. 00325 * @retval None 00326 */ 00327 #define __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1) 00328 00329 00330 /** 00331 * @brief Disable the PVM1 Extended Interrupt Falling Trigger. 00332 * @retval None 00333 */ 00334 #define __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1) 00335 00336 00337 /** 00338 * @brief PVM1 EXTI line configuration: set rising & falling edge trigger. 00339 * @retval None 00340 */ 00341 #define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE() \ 00342 do { \ 00343 __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE(); \ 00344 __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE(); \ 00345 } while(0) 00346 00347 /** 00348 * @brief Disable the PVM1 Extended Interrupt Rising & Falling Trigger. 00349 * @retval None 00350 */ 00351 #define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE() \ 00352 do { \ 00353 __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE(); \ 00354 __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE(); \ 00355 } while(0) 00356 00357 /** 00358 * @brief Generate a Software interrupt on selected EXTI line. 00359 * @retval None 00360 */ 00361 #define __HAL_PWR_PVM1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM1) 00362 00363 /** 00364 * @brief Check whether the specified PVM1 EXTI interrupt flag is set or not. 00365 * @retval EXTI PVM1 Line Status. 00366 */ 00367 #define __HAL_PWR_PVM1_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM1) 00368 00369 /** 00370 * @brief Clear the PVM1 EXTI flag. 00371 * @retval None 00372 */ 00373 #define __HAL_PWR_PVM1_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM1) 00374 00375 #endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ 00376 00377 00378 /** 00379 * @brief Enable the PVM2 Extended Interrupt Line. 00380 * @retval None 00381 */ 00382 #define __HAL_PWR_PVM2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2) 00383 00384 /** 00385 * @brief Disable the PVM2 Extended Interrupt Line. 00386 * @retval None 00387 */ 00388 #define __HAL_PWR_PVM2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2) 00389 00390 /** 00391 * @brief Enable the PVM2 Event Line. 00392 * @retval None 00393 */ 00394 #define __HAL_PWR_PVM2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2) 00395 00396 /** 00397 * @brief Disable the PVM2 Event Line. 00398 * @retval None 00399 */ 00400 #define __HAL_PWR_PVM2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2) 00401 00402 /** 00403 * @brief Enable the PVM2 Extended Interrupt Rising Trigger. 00404 * @retval None 00405 */ 00406 #define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2) 00407 00408 /** 00409 * @brief Disable the PVM2 Extended Interrupt Rising Trigger. 00410 * @retval None 00411 */ 00412 #define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2) 00413 00414 /** 00415 * @brief Enable the PVM2 Extended Interrupt Falling Trigger. 00416 * @retval None 00417 */ 00418 #define __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2) 00419 00420 00421 /** 00422 * @brief Disable the PVM2 Extended Interrupt Falling Trigger. 00423 * @retval None 00424 */ 00425 #define __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2) 00426 00427 00428 /** 00429 * @brief PVM2 EXTI line configuration: set rising & falling edge trigger. 00430 * @retval None 00431 */ 00432 #define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_FALLING_EDGE() \ 00433 do { \ 00434 __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE(); \ 00435 __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE(); \ 00436 } while(0) 00437 00438 /** 00439 * @brief Disable the PVM2 Extended Interrupt Rising & Falling Trigger. 00440 * @retval None 00441 */ 00442 #define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_FALLING_EDGE() \ 00443 do { \ 00444 __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE(); \ 00445 __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE(); \ 00446 } while(0) 00447 00448 /** 00449 * @brief Generate a Software interrupt on selected EXTI line. 00450 * @retval None 00451 */ 00452 #define __HAL_PWR_PVM2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM2) 00453 00454 /** 00455 * @brief Check whether the specified PVM2 EXTI interrupt flag is set or not. 00456 * @retval EXTI PVM2 Line Status. 00457 */ 00458 #define __HAL_PWR_PVM2_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM2) 00459 00460 /** 00461 * @brief Clear the PVM2 EXTI flag. 00462 * @retval None 00463 */ 00464 #define __HAL_PWR_PVM2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM2) 00465 00466 /** 00467 * @brief Enable the PVM3 Extended Interrupt Line. 00468 * @retval None 00469 */ 00470 #define __HAL_PWR_PVM3_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3) 00471 00472 /** 00473 * @brief Disable the PVM3 Extended Interrupt Line. 00474 * @retval None 00475 */ 00476 #define __HAL_PWR_PVM3_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3) 00477 00478 /** 00479 * @brief Enable the PVM3 Event Line. 00480 * @retval None 00481 */ 00482 #define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3) 00483 00484 /** 00485 * @brief Disable the PVM3 Event Line. 00486 * @retval None 00487 */ 00488 #define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3) 00489 00490 /** 00491 * @brief Enable the PVM3 Extended Interrupt Rising Trigger. 00492 * @retval None 00493 */ 00494 #define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3) 00495 00496 /** 00497 * @brief Disable the PVM3 Extended Interrupt Rising Trigger. 00498 * @retval None 00499 */ 00500 #define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3) 00501 00502 /** 00503 * @brief Enable the PVM3 Extended Interrupt Falling Trigger. 00504 * @retval None 00505 */ 00506 #define __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3) 00507 00508 00509 /** 00510 * @brief Disable the PVM3 Extended Interrupt Falling Trigger. 00511 * @retval None 00512 */ 00513 #define __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3) 00514 00515 00516 /** 00517 * @brief PVM3 EXTI line configuration: set rising & falling edge trigger. 00518 * @retval None 00519 */ 00520 #define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE() \ 00521 do { \ 00522 __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE(); \ 00523 __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE(); \ 00524 } while(0) 00525 00526 /** 00527 * @brief Disable the PVM3 Extended Interrupt Rising & Falling Trigger. 00528 * @retval None 00529 */ 00530 #define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE() \ 00531 do { \ 00532 __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE(); \ 00533 __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); \ 00534 } while(0) 00535 00536 /** 00537 * @brief Generate a Software interrupt on selected EXTI line. 00538 * @retval None 00539 */ 00540 #define __HAL_PWR_PVM3_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM3) 00541 00542 /** 00543 * @brief Check whether the specified PVM3 EXTI interrupt flag is set or not. 00544 * @retval EXTI PVM3 Line Status. 00545 */ 00546 #define __HAL_PWR_PVM3_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM3) 00547 00548 /** 00549 * @brief Clear the PVM3 EXTI flag. 00550 * @retval None 00551 */ 00552 #define __HAL_PWR_PVM3_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM3) 00553 00554 00555 00556 00557 /** 00558 * @brief Enable the PVM4 Extended Interrupt Line. 00559 * @retval None 00560 */ 00561 #define __HAL_PWR_PVM4_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4) 00562 00563 /** 00564 * @brief Disable the PVM4 Extended Interrupt Line. 00565 * @retval None 00566 */ 00567 #define __HAL_PWR_PVM4_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4) 00568 00569 /** 00570 * @brief Enable the PVM4 Event Line. 00571 * @retval None 00572 */ 00573 #define __HAL_PWR_PVM4_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4) 00574 00575 /** 00576 * @brief Disable the PVM4 Event Line. 00577 * @retval None 00578 */ 00579 #define __HAL_PWR_PVM4_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4) 00580 00581 /** 00582 * @brief Enable the PVM4 Extended Interrupt Rising Trigger. 00583 * @retval None 00584 */ 00585 #define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4) 00586 00587 /** 00588 * @brief Disable the PVM4 Extended Interrupt Rising Trigger. 00589 * @retval None 00590 */ 00591 #define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4) 00592 00593 /** 00594 * @brief Enable the PVM4 Extended Interrupt Falling Trigger. 00595 * @retval None 00596 */ 00597 #define __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4) 00598 00599 00600 /** 00601 * @brief Disable the PVM4 Extended Interrupt Falling Trigger. 00602 * @retval None 00603 */ 00604 #define __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4) 00605 00606 00607 /** 00608 * @brief PVM4 EXTI line configuration: set rising & falling edge trigger. 00609 * @retval None 00610 */ 00611 #define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_FALLING_EDGE() \ 00612 do { \ 00613 __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE(); \ 00614 __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE(); \ 00615 } while(0) 00616 00617 /** 00618 * @brief Disable the PVM4 Extended Interrupt Rising & Falling Trigger. 00619 * @retval None 00620 */ 00621 #define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_FALLING_EDGE() \ 00622 do { \ 00623 __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE(); \ 00624 __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE(); \ 00625 } while(0) 00626 00627 /** 00628 * @brief Generate a Software interrupt on selected EXTI line. 00629 * @retval None 00630 */ 00631 #define __HAL_PWR_PVM4_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM4) 00632 00633 /** 00634 * @brief Check whether or not the specified PVM4 EXTI interrupt flag is set. 00635 * @retval EXTI PVM4 Line Status. 00636 */ 00637 #define __HAL_PWR_PVM4_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM4) 00638 00639 /** 00640 * @brief Clear the PVM4 EXTI flag. 00641 * @retval None 00642 */ 00643 #define __HAL_PWR_PVM4_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM4) 00644 00645 00646 /** 00647 * @brief Configure the main internal regulator output voltage. 00648 * @param __REGULATOR__: specifies the regulator output voltage to achieve 00649 * a tradeoff between performance and power consumption. 00650 * This parameter can be one of the following values: 00651 * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode, 00652 * typical output voltage at 1.2 V, 00653 * system frequency up to 80 MHz. 00654 * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode, 00655 * typical output voltage at 1.0 V, 00656 * system frequency up to 26 MHz. 00657 * @note This macro is similar to HAL_PWREx_ControlVoltageScaling() API but doesn't check 00658 * whether or not VOSF flag is cleared when moving from range 2 to range 1. User 00659 * may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting. 00660 * @retval None 00661 */ 00662 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \ 00663 __IO uint32_t tmpreg; \ 00664 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \ 00665 /* Delay after an RCC peripheral clock enabling */ \ 00666 tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \ 00667 UNUSED(tmpreg); \ 00668 } while(0) 00669 00670 /** 00671 * @} 00672 */ 00673 00674 /* Private macros --------------------------------------------------------*/ 00675 /** @addtogroup PWREx_Private_Macros PWR Extended Private Macros 00676 * @{ 00677 */ 00678 00679 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ 00680 ((PIN) == PWR_WAKEUP_PIN2) || \ 00681 ((PIN) == PWR_WAKEUP_PIN3) || \ 00682 ((PIN) == PWR_WAKEUP_PIN4) || \ 00683 ((PIN) == PWR_WAKEUP_PIN5) || \ 00684 ((PIN) == PWR_WAKEUP_PIN1_HIGH) || \ 00685 ((PIN) == PWR_WAKEUP_PIN2_HIGH) || \ 00686 ((PIN) == PWR_WAKEUP_PIN3_HIGH) || \ 00687 ((PIN) == PWR_WAKEUP_PIN4_HIGH) || \ 00688 ((PIN) == PWR_WAKEUP_PIN5_HIGH) || \ 00689 ((PIN) == PWR_WAKEUP_PIN1_LOW) || \ 00690 ((PIN) == PWR_WAKEUP_PIN2_LOW) || \ 00691 ((PIN) == PWR_WAKEUP_PIN3_LOW) || \ 00692 ((PIN) == PWR_WAKEUP_PIN4_LOW) || \ 00693 ((PIN) == PWR_WAKEUP_PIN5_LOW)) 00694 00695 #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) & PWR_CR2_PVME) != RESET) 00696 00697 #define IS_PWR_PVM_MODE(MODE) (((MODE) == PWR_PVM_MODE_NORMAL) ||\ 00698 ((MODE) == PWR_PVM_MODE_IT_RISING) ||\ 00699 ((MODE) == PWR_PVM_MODE_IT_FALLING) ||\ 00700 ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING) ||\ 00701 ((MODE) == PWR_PVM_MODE_EVENT_RISING) ||\ 00702 ((MODE) == PWR_PVM_MODE_EVENT_FALLING) ||\ 00703 ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING)) 00704 00705 #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ 00706 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2)) 00707 00708 #define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\ 00709 ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5)) 00710 00711 #define IS_PWR_BATTERY_CHARGING(CHARGING) (((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) ||\ 00712 ((CHARGING) == PWR_BATTERY_CHARGING_ENABLE)) 00713 00714 #define IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00) 00715 00716 00717 #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\ 00718 ((GPIO) == PWR_GPIO_B) ||\ 00719 ((GPIO) == PWR_GPIO_C) ||\ 00720 ((GPIO) == PWR_GPIO_D) ||\ 00721 ((GPIO) == PWR_GPIO_E) ||\ 00722 ((GPIO) == PWR_GPIO_F) ||\ 00723 ((GPIO) == PWR_GPIO_G) ||\ 00724 ((GPIO) == PWR_GPIO_H)) 00725 00726 00727 /** 00728 * @} 00729 */ 00730 00731 00732 /** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions 00733 * @{ 00734 */ 00735 00736 /** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions 00737 * @{ 00738 */ 00739 00740 00741 /* Peripheral Control functions **********************************************/ 00742 uint32_t HAL_PWREx_GetVoltageRange(void); 00743 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling); 00744 void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection); 00745 void HAL_PWREx_DisableBatteryCharging(void); 00746 #if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 00747 void HAL_PWREx_EnableVddUSB(void); 00748 void HAL_PWREx_DisableVddUSB(void); 00749 #endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ 00750 void HAL_PWREx_EnableVddIO2(void); 00751 void HAL_PWREx_DisableVddIO2(void); 00752 void HAL_PWREx_EnableInternalWakeUpLine(void); 00753 void HAL_PWREx_DisableInternalWakeUpLine(void); 00754 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber); 00755 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber); 00756 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber); 00757 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber); 00758 void HAL_PWREx_EnablePullUpPullDownConfig(void); 00759 void HAL_PWREx_DisablePullUpPullDownConfig(void); 00760 void HAL_PWREx_EnableSRAM2ContentRetention(void); 00761 void HAL_PWREx_DisableSRAM2ContentRetention(void); 00762 #if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 00763 void HAL_PWREx_EnablePVM1(void); 00764 void HAL_PWREx_DisablePVM1(void); 00765 #endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ 00766 void HAL_PWREx_EnablePVM2(void); 00767 void HAL_PWREx_DisablePVM2(void); 00768 void HAL_PWREx_EnablePVM3(void); 00769 void HAL_PWREx_DisablePVM3(void); 00770 void HAL_PWREx_EnablePVM4(void); 00771 void HAL_PWREx_DisablePVM4(void); 00772 HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM); 00773 00774 00775 /* Low Power modes configuration functions ************************************/ 00776 void HAL_PWREx_EnableLowPowerRunMode(void); 00777 HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void); 00778 void HAL_PWREx_EnterSTOP1Mode(uint32_t Regulator, uint8_t STOPEntry); 00779 void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry); 00780 void HAL_PWREx_EnterSHUTDOWNMode(void); 00781 00782 void HAL_PWREx_PVD_PVM_IRQHandler(void); 00783 #if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 00784 void HAL_PWREx_PVM1Callback(void); 00785 #endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ 00786 void HAL_PWREx_PVM2Callback(void); 00787 void HAL_PWREx_PVM3Callback(void); 00788 void HAL_PWREx_PVM4Callback(void); 00789 00790 00791 /** 00792 * @} 00793 */ 00794 00795 /** 00796 * @} 00797 */ 00798 00799 /** 00800 * @} 00801 */ 00802 00803 /** 00804 * @} 00805 */ 00806 00807 #ifdef __cplusplus 00808 } 00809 #endif 00810 00811 00812 #endif /* __STM32L4xx_HAL_PWR_EX_H */ 00813 00814 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 00815
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